Synchronous serial communication system and method

Abstract

The invention discloses a synchronous serial communication system and method, and relates to the technical field of communication. The system comprises a master device and a slave device, the master device and the slave device are connected through a clock signal line and a data signal line, and the data signal line is connected with a pull-up resistor; the data frame of the write command sent by the master device to the slave device comprises a start bit, a read-write command bit, an address field, a first parity check bit, a write data field, a second parity check bit and an end bit; a data frame of a read command sent by the master device to the slave device comprises a start bit, a read-write command bit, an address field, a first parity check bit and an end bit; the data signal line is at a low level when at the start bit, and the data signal line is at a high level when at the end bit. The method can improve the communication speed and reduce the cost.

Description

Synchronous Serial Communication Systems and Methods Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a synchronous serial communication system and method. Background Technology

[0002] In the field of integrated circuits, especially in a complete system-on-a-chip (SoC) solution, there are scenarios where several chips work together to form a complete electronic system. Communication between SoCs typically uses serial data sequences. With the continuous development of chip technology, there are generally requirements to continuously increase the communication speed between chips, continuously reduce the interconnections between chips, and continuously decrease the power consumption of chips.

[0003] In current serial digital communication systems, numerous protocols are employed for serial communication. Among them, the Serial Peripheral Interface (SPI) and Inter-Integrated Circuit (IIC) protocols are widely used in master-slave communication scenarios for configuration, control, and data transfer between chips. The Universal Asynchronous Receiver / Transmitter (UART), as an asynchronous serial communication interface, is widely used in embedded systems, industrial control, and communication equipment. Universal Serial Bus (USB) technology, jointly developed by Intel and other companies, has become one of the world's most widely used peripheral connection standards.

[0004] There are two types of serial communication: asynchronous serial communication and synchronous serial communication. Asynchronous serial communication typically does not carry a clock signal. The master and slave devices use independent local clocks of a specific frequency to perform data sampling, clock recovery, and other operations on the interface signals. Synchronous serial communication requires a clock signal. The master device drives the clock signal, and the slave device samples the data according to the received clock signal. Synchronous serial communication can be further divided into half-duplex serial communication and full-duplex serial communication according to the transmission direction. Existing communication methods have the following disadvantages: 1. For UART, it is asynchronous serial communication, which has a limited communication speed, with a maximum of 3Mbps, and has a bit error rate; 2. For USB, it is asynchronous serial communication, which requires a local high-frequency clock, resulting in high implementation costs; 3. For SPI, it is synchronous serial communication, with a 4-wire interface, requiring a large number of I / O pins; 4. For IIC, it is synchronous serial communication, with a slow transmission speed of only 400Kbps.

[0005] Therefore, it is necessary to propose an improved communication method to address the shortcomings of existing methods. Summary of the Invention

[0006] This invention aims to solve at least one of the technical problems existing in the prior art. To this end, this invention proposes a synchronous serial communication system and method that can improve communication speed and reduce costs.

[0007] In a first aspect, a synchronous serial communication system according to an embodiment of the present invention includes a master device and a slave device, the master device and the slave device being connected via a clock signal line and a data signal line, the data signal line being connected to a pull-up resistor; the data frame of a write command sent by the master device to the slave device includes: a start bit, a read / write command bit, an address field, a first parity bit, a write data field, a second parity bit, and an end bit; the data frame of a read command sent by the master device to the slave device includes a start bit, a read / write command bit, an address field, a first parity bit, and an end bit; when the start bit is present, the data signal line is at a low level, and when the end bit is present, the data signal line is at a high level; the slave device transmits a level signal to the master device via the data signal line during a data frame idle time slot.

[0008] According to some embodiments of the present invention, when the master device sends the write command to the slave device, the response data frame of the slave device includes a start bit, a write command response field, and an end bit; when the master device sends the read command to the slave device, the response data frame of the slave device includes a start bit, a read data field, a third parity bit, and an end bit.

[0009] According to some embodiments of the present invention, the master device includes a master control module, a clock generation module, a parallel-to-serial conversion module, and an interrupt status check module. The master control module is connected to the clock generation module, the parallel-to-serial conversion module, and the interrupt status check module, respectively. The clock generation module is used to generate a clock signal on the clock signal line. The parallel-to-serial conversion module is used to perform parallel-to-serial conversion when transmitting data and serial-to-parallel conversion when receiving data. The interrupt status check module is used to detect the interrupt signal of the slave device.

[0010] According to some embodiments of the present invention, the main control module includes a main state machine and a main counter. The main counter is used to count when the main state machine is in a corresponding state, and to trigger the main state machine to perform a state transition when the count value meets the maximum count value of the corresponding state. The main state machine is used to control the working state of the main device.

[0011] According to some embodiments of the present invention, the clock generation module includes a clock divider circuit and a clock gating unit. The clock divider circuit is configured with a preset divider factor and is used to divide the original clock signal according to the divider factor. The gating enable signal of the clock gating unit is controlled by the main control module. The clock gating unit is used to output the divided clock signal in the communication state.

[0012] According to some embodiments of the present invention, the slave device includes a slave control module, a reset command counting module, a serial-to-parallel conversion module, an interrupt status output module, and an SDA signal multiplexing module; the slave control module is connected to the reset command counting module, the serial-to-parallel conversion module, and the interrupt status output module respectively; the SDA signal multiplexing module is electrically connected to the serial-to-parallel conversion module and the interrupt status output module respectively; the reset command counting module is used to monitor the reset command of the master device to reset the slave device; the serial-to-parallel conversion module is used to perform parallel-to-serial conversion when transmitting data and serial-to-parallel conversion when receiving data; the interrupt status output module is used to generate an interrupt signal; and the SDA signal multiplexing module is used to multiplex data signals and interrupt signals.

[0013] In a second aspect, according to an embodiment of the present invention, a synchronous serial communication method is applied to the master device of the synchronous serial communication system described in the first aspect embodiment. The master device includes a master control module, a clock generation module, a parallel-to-serial conversion module, and an interrupt status check module. The master control module includes a master state machine and a master counter. The method includes: during communication, causing the master state machine to enter a first state, outputting a one-cycle clock on the clock signal line through the clock generation module, and outputting a start bit on the data signal line through the parallel-to-serial conversion module; after completing the transmission of the start bit, causing the master state machine to enter a second state, outputting a one-cycle clock on the clock signal line through the clock generation module, and outputting a start bit on the data signal line through the parallel-to-serial conversion module. The system outputs read / write command bits online; this causes the main state machine to enter the third state, whereby the clock generation module outputs eight clock cycles on the clock signal line and the parallel-to-serial conversion module outputs the address field on the data signal line; this causes the main state machine to enter the fourth state, whereby the clock generation module outputs one clock cycle on the clock signal line and the parallel-to-serial conversion module outputs the first parity bit on the data signal line; based on the read / write command bits, it determines whether to perform a read or write operation; when a read operation is performed, the main state machine enters the fifth state, whereby the clock generation module outputs one clock cycle on the clock signal line and the parallel-to-serial conversion module outputs the end bit on the data signal line.

[0014] According to some embodiments of the present invention, after the step of determining whether to perform a read operation or a write operation based on the read / write command bit, the method further includes: when performing a write operation, causing the main state machine to enter a sixth state, outputting eight-cycle clocks on the clock signal line through the clock generation module, and outputting a write data field on the data signal line through the parallel-to-serial conversion module; causing the main state machine to enter a seventh state, outputting one-cycle clocks on the clock signal line through the clock generation module, and outputting a second parity bit on the data signal line through the parallel-to-serial conversion module; causing the main state machine to enter an eighth state, outputting one-cycle clocks on the clock signal line through the clock generation module, and outputting an end bit on the data signal line through the parallel-to-serial conversion module.

[0015] Thirdly, according to an embodiment of the present invention, a synchronous serial communication method is applied to a slave device in a synchronous serial communication system described in the first aspect embodiment. The slave device includes a slave control module, a reset command counting module, a serial-to-parallel conversion module, an interrupt status output module, and an SDA signal multiplexing module. The slave control module further includes a slave state machine and a slave state counter. The method includes: detecting a start bit on a data signal line through the serial-to-parallel conversion module; when the start bit is detected, causing the slave state machine to enter a ninth state; sampling read / write command bits through the serial-to-parallel conversion module; and determining, based on the read / write command bits, that the master device is sending a read command. The system executes a command or write command; it causes the slave state machine to enter the tenth state, and obtains the read / write address by sampling the address field through the serial-to-parallel conversion module; it causes the slave state machine to enter the eleventh state, and samples the first parity bit through the serial-to-parallel conversion module and performs parity checking; after the parity check passes, if the master device sends a read command, the slave state machine enters the twelfth state, and samples the end bit through the serial-to-parallel conversion module; it causes the slave state machine to enter the thirteenth state, and the slave device performs a read operation according to the read / write address to obtain read data; it causes the slave state machine to enter the fourteenth state, and sends the read data to the master device.

[0016] According to some embodiments of the present invention, after the step of causing the slave state machine to enter the eleventh state, sampling the first parity bit through the serial-to-parallel conversion module, and performing parity checking, the method further includes: when the parity check passes, if the master device sends a write command, causing the slave state machine to enter the fifteenth state, sampling the write data field through the serial-to-parallel conversion module to obtain the write data; causing the slave state machine to enter the sixteenth state, sampling the second parity bit through the serial-to-parallel conversion module, and performing parity checking; when the parity check passes, causing the slave state machine to enter the seventeenth state, sampling the end bit through the serial-to-parallel conversion module; causing the slave state machine to enter the eighteenth state, causing the slave device to perform a write operation according to the read / write address and the write data; when a write response is received, causing the slave state machine to enter the nineteenth state, sending a response value to the master device through the serial-to-parallel conversion module.

[0017] The synchronous serial communication system and method according to embodiments of the present invention have at least the following advantages: It provides a fully synchronous serial communication method where the transmission format of the start bit, end bit, and data bits is consistent; it defines a unique command structure, eliminates device addresses, and ensures the shortest possible communication frame time. The communication speed of this system depends on the speed of the digital circuit implementation, which can expand the application scenarios of the communication interface. All stages of the communication frame in the communication method use synchronous driving and sampling, resulting in a simple implementation structure and communication speed independent of a third-party clock on the device side.

[0018] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0019] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments in conjunction with the following drawings, in which: FIG1 is a schematic diagram of the structure of a synchronous serial communication system according to an embodiment of the present invention; FIG2 is a timing diagram of data sampling according to an embodiment of the present invention; FIG3 is a schematic diagram of the format of a write command frame according to an embodiment of the present invention; FIG4 is a schematic diagram of the format of a read command frame according to an embodiment of the present invention; FIG5 is a timing diagram of a reset command according to an embodiment of the present invention; FIG6 is a timing diagram of the communication process between the master device and the slave device according to an embodiment of the present invention; FIG7 is a schematic diagram of the specific structure of the synchronous serial communication system according to an embodiment of the present invention; FIG8 is a schematic diagram of the state changes of the master state machine according to an embodiment of the present invention; FIG9 is a schematic diagram of the clock generation module according to an embodiment of the present invention. Figure 10 is a circuit diagram of the parallel-to-serial conversion circuit according to an embodiment of the present invention; Figure 11 is a circuit diagram of the serial-to-parallel conversion circuit according to an embodiment of the present invention; Figure 12 is a schematic diagram of the state changes of the slave state machine according to an embodiment of the present invention; Figure 13 is a circuit diagram of the interrupt state output module according to an embodiment of the present invention; Figure 14 is a driving schematic diagram of the master device and slave device according to an embodiment of the present invention; Figure 15 is a flowchart of the steps of a synchronous serial communication method according to an embodiment of the present invention; Figure 16 is a flowchart of some steps of a synchronous serial communication method according to an embodiment of the present invention; Figure 17 is a flowchart of the steps of a synchronous serial communication method according to another embodiment of the present invention; Figure 18 is a flowchart of some steps of a synchronous serial communication method according to another embodiment of the present invention. Detailed Implementation

[0020] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0021] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0022] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0023] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0024] This invention provides a synchronous serial communication system and method, comprising a master device and a slave device connected via a clock signal line and a data signal line, the data signal line being connected to a pull-up resistor. The data frame for a write command sent by the master device to the slave device includes: a start bit, a read / write command bit, an address field, a first parity bit, a write data field, a second parity bit, and an end bit. The data frame for a read command sent by the master device to the slave device includes a start bit, a read / write command bit, an address field, a first parity bit, and an end bit. When the start bit is active, the data signal line is low; when the end bit is active, the data signal line is high. The slave device transmits a level signal to the master device via the data signal line during idle time slots in the data frame. This system defines a unique command structure, eliminates the device address, and ensures the shortest communication frame time. This application provides a fully synchronous serial communication method where the start bit, end bit, and data bits are transmitted in a consistent manner; it defines a unique command structure, eliminates the device address, and ensures the shortest communication frame time. The communication speed of this system depends on the speed of the digital circuit implementation, which can expand the application scenarios of the communication interface. The signals in all stages of the communication frame of the communication method used are synchronously driven and sampled, resulting in a simple structure and communication speed that does not depend on a third-party clock on the device side.

[0025] The synchronous serial communication system and method of the present invention will now be described in detail with reference to the accompanying drawings.

[0026] In a first aspect, embodiments of the present invention propose a synchronous serial communication system, as shown in FIG1. ​​The system includes: a master device 100 and a slave device 200, which are connected via a clock signal line (SCK) and a data signal line (SDA). The data signal line is connected to a pull-up resistor. The data frame of a write command sent by the master device 100 to the slave device 200 includes: a start bit, a read / write command bit, an address field, a first parity bit, a write data field, a second parity bit, and an end bit. The data frame of a read command sent by the master device 100 to the slave device 200 includes a start bit, a read / write command bit, an address field, a first parity bit, and an end bit. When the start bit is active, the data signal line is at a low level; when the end bit is active, the data signal line is at a high level. The slave device 200 transmits a level signal to the master device via the data signal line during idle time slots in the data frame.

[0027] Specifically, as shown in Figure 1, in this application, serial communication between the master device 100 and the slave device 200 requires two signals: SCK and SDA. SCK is a clock signal, driven by the master device 100 and received by the slave device 200. SDA is a data signal, a bidirectional signal, which, depending on the protocol, can be driven by the master device 100 and received by the slave device 200; or, driven by the slave device 200 and received by the master device 100. The SDA signal has a pull-up resistor. As shown in Figure 2, this serial communication method uses a synchronous clock for data sampling, and the communication data is transmitted through the level state of SDA at the rising edge of the SCK clock.

[0028] As shown in Figure 3, in this application, serial data communication data is transmitted in the form of frames. For the write command, the fields of the data frame sent by the master device 100 include the start bit (ST), read / write command bit (WR), address field (ADDR), first parity bit (PAR0), write data field (WDAT), second parity bit (PAR1), and end bit (END). The meanings of each character in Figure 3 are shown in Table 1:

[0029] As shown in Figure 3, for slave device 200, when master device 100 sends a write command, the response data frame of slave device 200 includes a start bit (ST), a write command response field (WACK), and an end bit (END).

[0030] As shown in Figure 4, for a read command, the data frame sent by the master device 100 includes a start bit (ST), a read / write command bit (RD), an address field (ADDR), a first parity bit (PAR0), and an end bit (END). For the slave device 200, when the master device 100 sends a read command, the response data frame of the slave device 200 includes a start bit (ST), a read data field (RDAT), a third parity bit (PAR2), and an end bit (END). As shown in Table 1, when the start bit is active, the data signal line is low; when the end bit is active, the data signal line is high.

[0031] It should be noted that in this application, read / write data frames are divided into write command frames and read command frames, and the frame format and data length are fixed. The length of all data fields has been specified in the protocol. During the slave device 200's command waiting phase or the master device 100's response waiting phase, the waiting party waits for a low level on SDA (the start bit) on the bus. After receiving the specified data length, the receiving party confirms the completion of frame data reception by receiving a high level on SDA (the end bit) and proceeds to the next state. This serial communication method is generally only used for interconnection between two devices and is not applicable to serial communication scenarios between a master device and multiple slave devices. Therefore, the serial communication protocol of this method does not include device addresses, saving communication time.

[0032] In special circumstances, such as abnormal power outages or software malfunctions during product development, communication frames may be suddenly interrupted, failing to complete a full frame of data according to the protocol. This can cause the slave device 200 to remain in a state somewhere in the middle of the previous frame when the master device 100 initiates a new frame of communication, making it unable to correctly identify the start bit of the current frame. To address this issue and improve communication robustness, this application also specifies a communication reset command to reset the communication state of the slave device 200. The reset command format is 64 bits in length, with the first 63 bits being low and the last bit being high, as shown in Figure 5.

[0033] This application introduces a serial communication method for master and slave devices, applied to communication between two devices, one of which is a master device 100 and the other is a slave device 200. Generally, in addition to data exchange, master and slave devices also need to transmit other electrical levels. This application introduces a technique that allows the drive level signal from slave device 200 to master device 100 to be multiplexed in the SDA signal during the idle state of serial communication. This multiplexing method further reduces the signal wiring between master and slave devices. This multiplexing method can be applied to the slave device 200 to transmit interrupt signals to master device 100. Specifically, when the serial communication bus is idle, SCK is a low level driven by master device 100, while SDA is not driven by either master or slave device, but only pulled up to a high level by a resistor. If the level signal to be transmitted by slave device 200 is low, slave device 200 drives a low level on the SDA signal line; if the level signal to be transmitted by slave device 200 is high, slave device 200 remains undriven on the SDA signal line, and the SDA signal line remains high. The main device 100 detects the level status on the SDA signal line in the IDLE state.

[0034] Since the master device 100 controls the serial communication process, during the command phase, the master device 100 drives SCK to generate a clock and drives SDA to generate a start bit. At this time, SDA is driven low by both the master and slave devices, so no conflict occurs. The slave device receives the SCK clock signal and recognizes that SDA is low at the rising edge of the SCK clock, thus determining that the serial communication command start bit is valid. It then releases the low-level state driven on SDA to ensure that the master device can send serial communication commands normally. This method can complete the transmission of slave device level signals without affecting the transmission of serial communication commands, as shown in Figure 6. Based on the serial communication and level signal multiplexing method described above, the following describes an interface implementation scheme for multiplexing master-slave device serial communication and interrupt signals.

[0035] As shown in Figure 7, in some embodiments of this application, the master device 100 includes a master control module 110, a clock generation module 120, a parallel-to-serial conversion module 130, and an interrupt status check module 140. The master control module 110 is connected to the clock generation module 120, the parallel-to-serial conversion module 130, and the interrupt status check module 140, respectively. The clock generation module 120 is used to generate a clock signal on the clock signal line. The parallel-to-serial conversion module 130 is used to perform parallel-to-serial conversion when sending data and serial-to-parallel conversion when receiving data. The interrupt status check module 140 is used to detect the interrupt signal of the slave device 200.

[0036] The main control module 110 includes a main state machine and a main counter. The main counter is used to count when the main state machine is in a corresponding state, and triggers the main state machine to perform a state transition when the count value meets the maximum count value of the corresponding state. The main state machine is used to control the working state of the main device 100. The state switching process of the main state machine is shown in Figure 8.

[0037] First, a master counter is set up. When the master state machine enters a certain state, the master counter is reset to zero and counts within the corresponding state. When the count reaches the maximum value required for the corresponding state, the master state machine is triggered to transition. During circuit reset, the master state machine is in the IDLE idle state. When the software triggers read or write commands, the master state machine enters the TX_START state. This state controls the clock generation module 120 to output a one-cycle clock on SCK, and the parallel-to-serial conversion module 130 to output a low level on SDA, thus completing the transmission of the start bit. After transmitting one start bit, the master state machine transitions to the TX_CMD state. This state controls the clock generation module 120 to output a one-cycle clock on SCK, and the parallel-to-serial conversion module 130 to output read / write command bits on SDA, where 0 represents a read command and 1 represents a write command. After transmitting one read / write command bit, the master state machine transitions to the TX_ADDR state. This state controls the clock generation module 120 to output eight cycles of clock on SCK, and the parallel-to-serial conversion module 130 to output eight address levels on SDA. When the main counter reaches 7 in the TX_ADDR state, it instructs the state machine to jump to the TX_CPAR state. In this state, the clock generation module 120 outputs one clock cycle on SCK and the serial-to-parallel conversion module 130 outputs one bit of even parity obtained by adding the command and address on SDA.

[0038] After completing one parity bit in the TX_CPAR state, if it is a write command, the main state machine jumps to the TX_WDAT state. In this state, the clock generation module 120 outputs an 8-cycle clock on SCK, and the parallel-to-serial conversion module 130 outputs an 8-bit write data level on SDA. In the TX_WDAT state, after the main counter reaches 7, the main state machine jumps to the TX_DPAR state. In this state, the clock generation module 120 outputs a 1-cycle clock on SCK, and the parallel-to-serial conversion module 130 outputs a 1-bit even-level parity bit obtained from the write data operation on SDA. After completing one parity bit, the main state machine jumps to the TX_WEND state. In this state, the clock generation module 120 outputs a 1-cycle clock on SCK, and the parallel-to-serial conversion module 130 outputs a high-level bit on SDA. After completing the first stop bit sampling, the main state machine transitions to the WAIT_WRSP_START state. In this state, the clock generation module 120 continuously outputs a periodic clock on SCK, while simultaneously controlling the parallel-to-serial converter module 130 to synchronously sample the SDA level. When the level is low, it indicates that the write response start bit has arrived, and the main state machine transitions to the RX_WRSP state. In this state, the clock generation module 120 outputs a three-cycle clock on SCK, while simultaneously controlling the parallel-to-serial converter module 130 to synchronously sample the SDA level, checking if it is 010. If yes, the write operation is successful; if it is 101, the write operation has failed. In the RX_WRSP state, after the main counter reaches 2, it instructs the main state machine to transition to the RX_WRSP_END state. In this state, the clock generation module 120 outputs a one-cycle clock on SCK, while simultaneously controlling the parallel-to-serial converter module 130 to synchronously sample the SDA level, checking if it is high. After completing the first stop bit sampling, the main state machine transitions back to the IDLE state.

[0039] After completing one-bit verification in the TX_CPAR state, if it is a read command, the main state machine jumps to the TX_CEND state. In this state, the clock generation module 120 outputs one clock cycle on SCK, and the parallel-to-serial conversion module 130 outputs one high level on SDA. After completing one end bit, the main state machine jumps to the WAIT_RDAT_START state. In this state, the clock generation module 120 continuously outputs a clock cycle on SCK, and simultaneously controls the parallel-to-serial conversion module 130 to synchronously sample the SDA level. When the level is low, it is determined that the start bit of the read data has arrived, and the state machine jumps to the RX_RDAT state. In this state, the clock generation module 120 outputs eight clock cycles on SCK, and simultaneously controls the parallel-to-serial conversion module 130 to synchronously sample the SDA level, obtaining eight bits of read data. When the main counter reaches 7 in the RX_RDAT state, it instructs the main state machine to jump to the RX_RPAR state. In this state, the clock generation module 120 outputs one clock cycle on SCK, and simultaneously controls the parallel-to-serial conversion module 130 to synchronously sample the SDA level. The sampled level value is compared with the received read data using an even parity check. If they match, the data reception is considered successful. After receiving one read data parity bit, the main state machine jumps to the RX_RDAT_END state. In this state, the clock generation module 120 outputs one clock cycle on SCK, and simultaneously controls the parallel-to-serial conversion module 130 to synchronously sample the SDA level to determine if it is high. After sampling one end bit, the main state machine jumps back to the IDLE state.

[0040] When the master state machine is in the IDLE state, a software-triggered reset command causes the state machine to transition to the TX_RST state. In this state, the clock generation module 120 outputs a 63-cycle clock on SCK, and the parallel-to-serial conversion module 130 outputs a 63-bit low level on SDA. In the TX_RST state, after the main counter reaches 62, it instructs the master state machine to transition to the TX_RST_END state. In this state, the clock generation module 120 outputs a 1-cycle clock on SCK, and the parallel-to-serial conversion module 130 outputs a 1-bit high level on SDA. After completing the 1-bit end bit, the master state machine transitions back to the IDLE state.

[0041] The above describes the working process of the main control module 110.

[0042] As shown in Figure 9, in some embodiments of this application, the clock generation module 120 consists of a clock divider circuit and a clock gating unit. The clock divider circuit is configured with a preset divider factor, used to divide the original clock signal according to the divider factor. The gating enable signal of the clock gating unit is controlled by the main state machine of the main control module 110. The clock gating unit is used to output the divided clock signal in communication mode. The function of the clock divider circuit is to obtain an appropriate target communication frequency; the divider factor is configured by software. The function of the clock gating unit is to output a periodic clock on the SCK signal only in communication mode; in idle mode, SCK remains low.

[0043] In some embodiments of this application, the parallel-to-serial conversion module 130 is responsible for driving and sampling the SDA signal. It consists of two functional parts: a parallel-to-serial conversion circuit and a serial-to-parallel conversion circuit. The parallel-to-serial conversion circuit is used to implement the data transmission function, and the serial-to-parallel conversion circuit is used to implement the data reception function. The circuit diagram of the parallel-to-serial conversion circuit is shown in Figure 10. When the main state machine jumps to the data shift state, a high pulse of the Load signal is generated, loading the Data0~Data7 data into the Q terminal of the REG0~REG7 registers. In the data shift state, the data is shifted by one bit each time the rising edge of the clock signal arrives, until all bits of data appear on the Shift_out signal, thereby converting the parallel data into serial data and outputting it to the SDA. The circuit diagram of the serial-to-parallel conversion circuit is shown in Figure 11. When the main state machine is in the data receiving state, the serial-to-parallel conversion circuit is in the working state. It synchronously samples the SDA up-level state through a clock with the same frequency as the SCK signal. When each clock rising edge arrives, the data is shifted once until all the Shift_in data is transferred to REG0~REG7. The received data is DATA0~DATA7. During state transition, the received data is transferred to the internal register.

[0044] The interrupt status check module 140 samples the level status of the SDA signal when the master state machine is in the IDLE state. It can operate in four modes: level detection mode, rising edge detection mode, falling edge detection mode, and dual edge detection mode. It stores the identified SDA status information in a software register, allowing the software to obtain the level status information of the interrupt signal from the slave device 200. Furthermore, the detected interrupt signal status of the slave device 200 can be connected to the central processing unit of the master device to indicate the interrupt signal of the slave device 200, thus realizing the transmission of interrupt signals between devices.

[0045] Further, in some embodiments of this application, the slave device 200 includes a slave control module 210, a reset command counting module 220, a serial-to-parallel conversion module 230, an interrupt status output module 240, and an SDA signal multiplexing module 250. The slave control module 210 is connected to the reset command counting module 220, the serial-to-parallel conversion module 230, and the interrupt status output module 240, respectively. The SDA signal multiplexing module 250 is electrically connected to the serial-to-parallel conversion module 230 and the interrupt status output module 240, respectively. The reset command counting module 220 is used to monitor the reset command of the master device 100 to reset the slave device 200. The serial-to-parallel conversion module 230 is used to perform parallel-to-serial conversion when transmitting data and serial-to-parallel conversion when receiving data. The interrupt status output module 240 is used to generate an interrupt signal. The SDA signal multiplexing module 250 is used to multiplex the data signal and the interrupt signal. Unlike the master device 100, which needs to generate its own clock, the slave device 200's operating clock is provided by SCK.

[0046] The slave control module 210 mainly consists of a slave state machine and a slave counter. The operation of the slave state machine of the slave control module 210 is shown in Figure 12. First, a slave state counter is set, which is reset to zero when entering a state. It counts within the corresponding state, and when the count meets the maximum value required by the corresponding state, the slave state machine is triggered to transition to a new state. When the circuit is reset, the slave state machine is in the WAIT_CMD_START state. In this state, the slave state machine controls the serial-to-parallel conversion module 230 to sample the SDA level value on the rising edge of SCK. When the sampled SDA value is low, it is determined that a command start bit has been detected, and the slave state machine transitions to the RX_CMD state. In this state, the slave state machine controls the serial-to-parallel conversion module 230 to sample the command type on the interface. If SDA is low, it is determined to be a read command; if SDA is high, it is determined to be a write command. After receiving one command bit, the slave state machine transitions to the RX_ADDR state. In this state, the serial-to-parallel conversion module is controlled to sample the SDA level on the rising edge of SCK to obtain an 8-bit address. When the counter reaches 7, the state machine transitions to the RX_CPAR state. In this state, the serial-to-parallel conversion module samples the parity bit on the interface. The received parity bit is compared with the received command bit and the even parity operation bits of the 8-bit address bit. If they match, the system transitions to the read / write state according to the command type. If they do not match, the state machine transitions to the CPAR_ERR state.

[0047] After the slave state machine correctly receives one parity bit in the RX_CPAR state, based on the command status received in the RX_CMD state, if it is a write command, the slave state machine transitions to the RX_WDAT state. In this state, the control serial-to-parallel conversion module samples 8 bits of write data and latches the data information. In the RX_WDAT state, when the slave counter reaches 7, it instructs the slave state machine to transition to the RX_DPAR state. In the RX_DPAR state, the control serial-to-parallel conversion module samples the write data parity bit, calculates the even parity bit of the 8 bits of write data, and compares it with the received even parity bit. If they match, the slave state machine is instructed to enter the RX_WEND state; if they do not match, the slave state machine is instructed to enter the DPAR_ERR state. In the RX_WEND state, the slave state machine controls the serial-to-parallel conversion module to sample the end flag bit and determines whether it is high. If it is high, the state machine is instructed to enter the WR_REG state; if it is low, the state machine is instructed to enter the TX_WRSP_START state. In the DPAR_ERR state, the control counter waits for one clock cycle. Upon completion, it instructs the slave state machine to enter the TX_WRSP_START state. In the WR_REG state, indicating a successful write command, the slave state machine controls the external handshake circuit to synchronize the write command (write address, write data, and write trigger signal) to the slave device 200's operating clock. After completing the write command, the external handshake circuit sends a write completion response to the slave state machine. Upon receiving the write completion response, the slave state machine instructs itself to enter the TX_WRSP_START state. In the TX_WRSP_START state, the slave state machine controls the serial-to-parallel converter module to output a 1-bit low level on SDA. After sending the 1-bit write response, the state machine transitions to the TX_WRSP state, which controls the serial-to-parallel converter module to output a 3-bit response value on SDA. The response value is obtained from the state from which the TX_WRSP_START transition occurs. If the transition is from the WR_REG state to the TX_WRSP_START state, a write success response is sent, with a 3-bit response value of 010. If the transition is from the RX_WEND state or the DPAR_ERR state to the TX_WRSP_START state, a write failure response is sent, with a 3-bit response value of 101. Within the TX_WRSP state, when the counter reaches 2, it indicates a transition from the slave state machine to the TX_WRSP_END state. This state controls the serial-to-parallel conversion module to output a high level on SDA. After sending the 1-bit write response end bit, the slave state machine completes the reception and response to the write command and transitions back to the initial state WAIT_CMD_START.

[0048] After the slave state machine correctly receives one parity bit in the RX_CPAR state, based on the command status received in the RX_CMD state, if it is a read command, the slave state machine transitions to the RX_CEND state. This state controls the serial-to-parallel converter (SPC) to receive one read command end bit. After receiving the one read command end bit, the slave state machine transitions to the RD_REG state. This state controls the external handshake circuit to synchronize the read command (read address and read trigger signal) to the slave device's operating clock. After completing the read command, the external handshake circuit inputs a read completion response to the slave state machine and inputs read data to the SPC. In the RD_REG state, after receiving the read completion response signal, the slave state machine indicates a transition to the TX_RDAT_START state. This state controls the SPC to output a low level on SDA. After completing the transmission of the one start bit, the slave state machine transitions to the TX_RDAT state, controlling the SPC to output 8 bits of write data on SDA. When the counter value reaches 7, the indicator transitions from the state machine to the TX_RPAR state, controlling the serial-to-parallel converter to output a 1-bit even parity bit on SDA. The even parity bit is obtained from the read data. After sending the 1-bit read data parity bit, the indicator transitions from the state machine to the TX_RDAT_END state, which controls the serial-to-parallel converter to output a 1-bit high level on SDA. After sending the 1-bit read data end bit, the read command reception and data transmission are complete, and the indicator transitions back to the initial state WAIT_CMD_START.

[0049] The above describes the working process of the slave state machine of the control module 210.

[0050] In some embodiments of this application, the reset command counting module 220 monitors reset commands on the interface. It operates independently of the slave control module 210. Upon detecting a reset command on the interface, it triggers the slave state machine of the slave control module 210 to enter the initial state WAIT_CMD_START. This ensures that if the interface system fails to communicate or enters an error state, the master device 100 can restore the slave device 200's state via a reset command. The reset command counting module 220 has a built-in reset counter. It samples the level of SDA on the rising edge of the SCK clock signal. If the level is low, the reset counter increments by 1; if the level is high, the reset counter resets to 0. When the reset counter value reaches 63, it stops incrementing when SDA is low and inputs a valid reset command signal to the master control module 110.

[0051] In some embodiments of this application, the serial-to-parallel conversion module 230 is responsible for driving and sampling the SDA signal. It consists of two functional parts: a parallel-to-serial conversion circuit and a serial-to-parallel conversion circuit. The parallel-to-serial conversion circuit is used to implement the data transmission function, and the serial-to-parallel conversion circuit is used to implement the data reception function. Its structural composition is the same as that of the parallel-to-serial conversion module of the main device 100, and will not be described again.

[0052] In some embodiments of this application, the circuit of the interrupt status output module 240 is shown in Figure 13. Its function is to generate the interrupt status of the slave device 200. Generally, the device has multiple interrupt sources. Each interrupt source signal is ANDed with an independent interrupt source enable signal, and then multiple interrupt sources are combined into one interrupt signal output through OR logic.

[0053] The function of the SDA signal multiplexing module 250 is to multiplex the SDA control signal of the serial-to-parallel conversion module 230 and the interrupt signal of the interrupt status output module 240 on the SDA signal. When the slave state machine of the slave control module 210 is in the WAIT_CMD_START state, the SDA signal is selected as the interrupt signal output; when the slave state machine of the slave control module 210 is not in the WAIT_CMD_START state, the SDA signal is selected as the SDA signal of the serial-to-parallel conversion module 230. It should be noted that, in order to ensure that there is no conflict between the low level of the start bit of the serial communication transmission of the master device 100 and the high level of the interrupt signal multiplexing, the high level of the interrupt signal is provided by the pull-up resistor on SDA during the bus idle phase. The master and slave devices drive SCK and SDA in a push-pull manner, the principle of which is shown in Figure 14.

[0054] According to the synchronous serial communication system of this application, a fully synchronous serial communication method is provided, in which the transmission forms of the start bit, end bit, and data bits are consistent; the communication interface can reuse the level signals of the slave device 200, simplifying the number of interfaces between chips; the toggle of the interface signals relies entirely on the push-pull drive circuit, avoiding the need for open-drain drive circuits to drive high levels; the serial communication method defines a unique command structure, eliminating the need for device addresses and ensuring the shortest communication frame time; a reset command structure is defined, and the reset command form is simple. The communication speed of this system depends on the speed of the digital circuit implementation, which can expand the application scenarios of the communication interface. All stages of the communication frame in the communication method used employ synchronous driving and sampling, resulting in a simple implementation structure and communication speed independent of a third-party clock on the device side. The toggle of all signals of the master and slave devices adopts push-pull driving, avoiding the low-speed problem caused by open-drain driving, and simultaneously simplifying the signal connections between the master and slave devices.

[0055] Secondly, based on the aforementioned synchronous serial communication system, this application also provides a synchronous serial communication method applied to a master device 100. The master device 100 includes a master control module 110, a clock generation module 120, a parallel-to-serial conversion module 130, and an interrupt status check module 140. The master control module 110 includes a master state machine and a master counter. As shown in Figure 15, the synchronous serial communication method includes, but is not limited to, steps S10-S60: Step S10: During communication, the master state machine enters the first state (TX_START state), and the clock generation module 120 outputs a one-cycle clock on the clock signal line, and the parallel-to-serial conversion module 130 outputs a start bit on the data signal line; Step S20: After completing the transmission of the start bit, the master state machine enters the second state (TX_CMD state), and the clock generation module 120 outputs a one-cycle clock on the clock signal line, and the parallel-to-serial conversion module 130 outputs a read / write command bit on the data signal line; Step S30: The master state machine enters the third state (TX_ADDR state), and the clock generation module 120 outputs a one-cycle clock on the clock signal line, and the parallel-to-serial conversion module 130 outputs a read / write command bit on the data signal line; Step S30: The master state machine enters the third state (TX_ADDR state), and the clock generation module 120 outputs a one-cycle clock on the clock signal line, and the parallel-to-serial conversion module 130 outputs a read / write command bit on the data signal line; Step S40: Output eight clock cycles on the clock signal line and output the address field on the data signal line through the parallel-to-serial conversion module 130; Step S50: Make the main state machine enter the fourth state (TX_CPAR state), output one clock cycle on the clock signal line through the clock generation module 120, and output the first parity bit on the data signal line through the parallel-to-serial conversion module 130; Step S60: Determine whether to perform a read operation or a write operation based on the read / write command bit; Step S60: When performing a read operation, make the main state machine enter the fifth state (TX_CEND state), in the fifth state, output one clock cycle on the clock signal line through the clock generation module 120, and output the end bit on the data signal line through the parallel-to-serial conversion module 130.

[0056] Specifically, the operation of the master state machine of the master device 100 is shown in Figure 8. First, a master counter is set. When the master state machine enters a certain state, the master counter is reset to zero and counts within the corresponding state. When the count reaches the maximum value required by the corresponding state, the master state machine is triggered to transition to another state. During circuit reset, the master state machine is in the IDLE idle state. When the software triggers read or write commands, the master state machine enters the TX_START state. This state controls the clock generation module 120 to output a one-cycle clock on SCK, and the parallel-to-serial conversion module 130 to output a low level on SDA, thus completing the transmission of the start bit. After transmitting one start bit, the master state machine transitions to the TX_CMD state. This state controls the clock generation module 120 to output a one-cycle clock on SCK, and the parallel-to-serial conversion module 130 to output read / write command bits on SDA, where 0 represents a read command and 1 represents a write command. After completing one read / write command bit, the main state machine transitions to the TX_ADDR state. In this state, the clock generation module 120 outputs an 8-cycle clock on SCK, and the parallel-to-serial conversion module 130 outputs an 8-bit address level on SDA. In the TX_ADDR state, after the main counter reaches 7, it instructs the state machine to transition to the TX_CPAR state. In this state, the clock generation module 120 outputs a 1-cycle clock on SCK, and the parallel-to-serial conversion module 130 outputs a 1-bit even parity bit obtained by adding the command and address to SDA.

[0057] After completing one-bit verification in the TX_CPAR state, if it is a read command, the main state machine jumps to the TX_CEND state. In this state, the clock generation module 120 outputs one clock cycle on SCK, and the parallel-to-serial conversion module 130 outputs one high level on SDA. After completing one end bit, the main state machine jumps to the WAIT_RDAT_START state. In this state, the clock generation module 120 continuously outputs a clock cycle on SCK, and simultaneously controls the parallel-to-serial conversion module 130 to synchronously sample the SDA level. When the level is low, it is determined that the start bit of the read data has arrived, and the state machine jumps to the RX_RDAT state. In this state, the clock generation module 120 outputs eight clock cycles on SCK, and simultaneously controls the parallel-to-serial conversion module 130 to synchronously sample the SDA level, obtaining eight bits of read data. When the main counter reaches 7 in the RX_RDAT state, it instructs the main state machine to jump to the RX_RPAR state. In this state, the clock generation module 120 outputs one clock cycle on SCK, and simultaneously controls the parallel-to-serial conversion module 130 to synchronously sample the SDA level. The sampled level value is compared with the received read data using an even parity check. If they match, the data reception is considered successful. After receiving one read data parity bit, the main state machine jumps to the RX_RDAT_END state. In this state, the clock generation module 120 outputs one clock cycle on SCK, and simultaneously controls the parallel-to-serial conversion module 130 to synchronously sample the SDA level to determine if it is high. After sampling one end bit, the main state machine jumps back to the IDLE state.

[0058] Further, as shown in Figure 16, in some embodiments of this application, after determining whether to perform a read or write operation based on the read / write command bit in step S50, the synchronous serial communication method further includes the following three steps: Step S51: When performing a write operation, the main state machine enters the sixth state (TX_WDAT state), the clock generation module 120 outputs eight-cycle clocks on the clock signal line, and the parallel-to-serial conversion module 130 outputs the write data field on the data signal line; Step S52: The main state machine enters the seventh state (TX_DPAR state), the clock generation module 120 outputs one-cycle clocks on the clock signal line, and the parallel-to-serial conversion module 130 outputs the second parity bit on the data signal line; Step S53: The main state machine enters the eighth state (TX_WEND state), the clock generation module 120 outputs one-cycle clocks on the clock signal line, and the parallel-to-serial conversion module 130 outputs the end bit on the data signal line.

[0059] Specifically, as shown in Figure 8, after completing one parity bit in the TX_CPAR state, if it is a write command, the main state machine jumps to the TX_WDAT state. In this state, the clock generation module 120 outputs an 8-cycle clock on SCK, and the parallel-to-serial conversion module 130 outputs an 8-bit write data level on SDA. In the TX_WDAT state, after the main counter reaches 7, the main state machine jumps to the TX_DPAR state. In this state, the clock generation module 120 outputs one-cycle clock on SCK, and the parallel-to-serial conversion module 130 outputs a 1-bit even-level parity bit obtained from the write data operation on SDA. After completing one parity bit, the main state machine jumps to the TX_WEND state. In this state, the clock generation module 120 outputs one-cycle clock on SCK, and the parallel-to-serial conversion module 130 outputs a high-level bit on SDA. After completing the first stop bit sampling, the main state machine transitions to the WAIT_WRSP_START state. In this state, the clock generation module 120 continuously outputs a periodic clock on SCK, while simultaneously controlling the parallel-to-serial converter module 130 to synchronously sample the SDA level. When the level is low, it indicates that the write response start bit has arrived, and the main state machine transitions to the RX_WRSP state. In this state, the clock generation module 120 outputs a three-cycle clock on SCK, while simultaneously controlling the parallel-to-serial converter module 130 to synchronously sample the SDA level, checking if it is 010. If yes, the write operation is successful; if it is 101, the write operation has failed. In the RX_WRSP state, after the main counter reaches 2, it instructs the main state machine to transition to the RX_WRSP_END state. In this state, the clock generation module 120 outputs a one-cycle clock on SCK, while simultaneously controlling the parallel-to-serial converter module 130 to synchronously sample the SDA level, checking if it is high. After completing the first stop bit sampling, the main state machine transitions back to the IDLE state.

[0060] When the master state machine is in the IDLE state, a software-triggered reset command causes the state machine to transition to the TX_RST state. In this state, the clock generation module 120 outputs a 63-cycle clock on SCK, and the parallel-to-serial conversion module 130 outputs a 63-bit low level on SDA. In the TX_RST state, after the main counter reaches 62, it instructs the master state machine to transition to the TX_RST_END state. In this state, the clock generation module 120 outputs a 1-cycle clock on SCK, and the parallel-to-serial conversion module 130 outputs a 1-bit high level on SDA. After completing the 1-bit end bit, the master state machine transitions back to the IDLE state.

[0061] The above describes the working process of the main control module 110.

[0062] According to the synchronous serial communication method of this application, a fully synchronous serial communication method is provided, in which the transmission forms of the start bit, end bit, and data bits are consistent; the communication interface can reuse the level signals of the slave device 200, simplifying the number of interfaces between chips; the toggle of the interface signals relies entirely on the push-pull drive circuit, avoiding the need for open-drain drive circuits to drive high levels; the serial communication method defines a unique command structure, eliminating the need for device addresses and ensuring the shortest communication frame time; a reset command structure is defined, and the reset command form is simple. The communication speed of this system depends on the speed of the digital circuit implementation, which can expand the application scenarios of the communication interface. The signals in all stages of the communication frame of the communication method used are synchronously driven and sampled, resulting in a simple implementation structure and communication speed that does not depend on a third-party clock at the device end. The toggle of all signals of the master and slave devices adopts push-pull drive, avoiding the low-speed problem caused by open-drain drive, and at the same time, simplifying the signal connections between the master and slave devices.

[0063] Thirdly, based on the aforementioned synchronous serial communication system, this application also provides another synchronous serial communication method applied to a slave device 200. The slave device 200 includes a slave control module 210, a reset command counting module 220, a serial-to-parallel conversion module 230, an interrupt status output module 240, and an SDA signal multiplexing module 250. The slave control module 210 also includes a slave state machine and a slave state counter. As shown in Figure 17, the method includes, but is not limited to, steps S100-S800: Step S100: The serial-to-parallel conversion module 230 detects the start bit on the data signal line; Step S200: When the start bit is detected, the slave state machine enters the ninth state (RX_CMD state), and the serial-to-parallel conversion module 230 samples the read / write command bit; Step S300: Based on the read / write command bit, it is determined whether the master device 100 sent a read command or a write command; Step S400: The slave state machine enters the tenth state (RX_ADDR state), and the serial-to-parallel conversion module 230 samples the address field to obtain the read / write address; Step S500: The slave state machine... Entering the eleventh state (RX_CPAR state), the first parity bit is sampled by the serial-to-parallel conversion module 230 and parity is checked; Step S600: After the parity check passes, if the master device 100 sends a read command, the slave state machine enters the twelfth state (RX_CEND state), and the end bit is sampled by the serial-to-parallel conversion module 230; Step S700: The slave state machine enters the thirteenth state (RD_REG state), and the slave device 200 performs a read operation according to the read / write address to obtain read data; Step S800: The slave state machine enters the fourteenth state (TX_RDAT state), and the read data is sent to the master device 100.

[0064] Specifically, the operation of the slave state machine of the control module 210 is shown in Figure 12. First, a slave state counter is set, resetting to zero upon entering a new state. It counts within the corresponding state, and when the count reaches the maximum value required for that state, a state transition is triggered in the slave state machine. During circuit reset, the slave state machine is in the WAIT_CMD_START state. In this state, the slave state machine controls the serial-to-parallel conversion module 230 to sample the SDA level on the rising edge of SCK. When the sampled SDA value is low, it is determined that a command start bit has been detected, and the slave state machine transitions to the RX_CMD state. In this state, the slave state machine controls the serial-to-parallel conversion module 230 to sample the command type on the interface. If SDA is low, it is determined to be a read command; if SDA is high, it is determined to be a write command. After receiving one command bit, the slave state machine transitions to the RX_ADDR state. In this state, the serial-to-parallel conversion module samples the SDA level on the rising edge of SCK to obtain an 8-bit address. When the counter reaches 7, the state machine transitions to the RX_CPAR state. In this state, the serial-to-parallel conversion module samples the parity bit on the interface. The received parity bit is compared with the received command bit and the even parity operation bits of the 8-bit address bit. If they match, the system transitions to the read / write state according to the command type. If they do not match, the state machine transitions to the CPAR_ERR state.

[0065] After the slave state machine correctly receives one parity bit in the RX_CPAR state, based on the command status received in the RX_CMD state, if it is a read command, the slave state machine transitions to the RX_CEND state. This state controls the serial-to-parallel converter (SPC) to receive one read command end bit. After receiving the one read command end bit, the slave state machine transitions to the RD_REG state. This state controls the external handshake circuit to synchronize the read command (read address and read trigger signal) to the slave device's operating clock. After completing the read command, the external handshake circuit inputs a read completion response to the slave state machine and inputs read data to the SPC. In the RD_REG state, after receiving the read completion response signal, the slave state machine indicates a transition to the TX_RDAT_START state. This state controls the SPC to output a low level on SDA. After completing the transmission of the one start bit, the slave state machine transitions to the TX_RDAT state, controlling the SPC to output 8 bits of write data on SDA. When the counter value reaches 7, the indicator transitions from the state machine to the TX_RPAR state, controlling the serial-to-parallel converter to output a 1-bit even parity bit on SDA. The even parity bit is obtained from the read data. After sending the 1-bit read data parity bit, the indicator transitions from the state machine to the TX_RDAT_END state, which controls the serial-to-parallel converter to output a 1-bit high level on SDA. After sending the 1-bit read data end bit, the read command reception and data transmission are complete, and the indicator transitions back to the initial state WAIT_CMD_START.

[0066] Further, as shown in Figure 18, in some embodiments of this application, after step S500: the slave state machine enters the eleventh state (RX_CPAR state), the serial-to-parallel conversion module 230 samples the first parity bit, and performs parity checking, the synchronous serial communication method further includes the following five steps: Step S510: after parity checking passes, if the master device 100 sends a write command, the slave state machine enters the fifteenth state (RX_WDAT state), the serial-to-parallel conversion module 230 samples the write data field, and the write data is obtained; Step S520: the slave state machine enters the sixteenth state. (RX_DPAR state), the second parity bit is sampled by the serial-to-parallel conversion module 230 and parity check is performed; Step S530: When the parity check passes, the slave state machine enters the seventeenth state (RX_WEND state), and the end bit is sampled by the serial-to-parallel conversion module 230; Step S540: The slave state machine enters the eighteenth state (WR_REG state), and the slave device performs a write operation according to the read / write address and write data; Step S550: When a write response is received, the slave state machine enters the nineteenth state (TX_WRSP state), and the response value is sent to the master device by the serial-to-parallel conversion module 230.

[0067] Specifically, as shown in Figure 12, after the slave state machine correctly receives one parity bit in the RX_CPAR state, based on the command status received in the RX_CMD state, if it is a write command, the slave state machine jumps to the RX_WDAT state. In this state, the serial-to-parallel conversion module samples 8 bits of write data and latches the data information. In the RX_WDAT state, when the slave counter reaches 7, it instructs the slave state machine to jump to the RX_DPAR state. In the RX_DPAR state, the serial-to-parallel conversion module samples the write data parity bit, calculates the even parity bit of the 8 bits of write data, and compares it with the received even parity bit. If they match, the slave state machine is instructed to enter the RX_WEND state; if they do not match, the slave state machine is instructed to enter the DPAR_ERR state. In the RX_WEND state, the slave state machine controls the serial-to-parallel conversion module to sample the end flag bit and determines whether it is high. If it is high, the state machine is instructed to enter the WR_REG state; if it is low, the state machine is instructed to enter the TX_WRSP_START state. In the DPAR_ERR state, the control counter waits for one clock cycle. Upon completion, it instructs the slave state machine to enter the TX_WRSP_START state. In the WR_REG state, indicating a successful write command, the slave state machine controls the external handshake circuit to synchronize the write command (write address, write data, and write trigger signal) to the slave device 200's operating clock. After completing the write command, the external handshake circuit sends a write completion response to the slave state machine. Upon receiving the write completion response, the slave state machine instructs itself to enter the TX_WRSP_START state. In the TX_WRSP_START state, the slave state machine controls the serial-to-parallel converter module to output a 1-bit low level on SDA. After sending the 1-bit write response, the state machine transitions to the TX_WRSP state, which controls the serial-to-parallel converter module to output a 3-bit response value on SDA. The response value is obtained from the state from which the TX_WRSP_START transition occurs. If the transition is from the WR_REG state to the TX_WRSP_START state, a write success response is sent, with a 3-bit response value of 010. If the transition is from the RX_WEND state or the DPAR_ERR state to the TX_WRSP_START state, a write failure response is sent, with a 3-bit response value of 101. Within the TX_WRSP state, when the counter reaches 2, it indicates a transition from the slave state machine to the TX_WRSP_END state. This state controls the serial-to-parallel conversion module to output a high level on SDA. After sending the 1-bit write response end bit, the slave state machine completes the reception and response to the write command and transitions back to the initial state WAIT_CMD_START.

[0068] According to the synchronous serial communication method of this application, a fully synchronous serial communication method is provided, in which the transmission forms of the start bit, end bit, and data bits are consistent; the communication interface can reuse the level signals of the slave device 200, simplifying the number of interfaces between chips; the toggle of the interface signals relies entirely on the push-pull drive circuit, avoiding the need for open-drain drive circuits to drive high levels; the serial communication method defines a unique command structure, eliminating the need for device addresses and ensuring the shortest communication frame time; a reset command structure is defined, and the reset command form is simple. The communication speed of this system depends on the speed of the digital circuit implementation, which can expand the application scenarios of the communication interface. The signals in all stages of the communication frame of the communication method used are synchronously driven and sampled, resulting in a simple implementation structure and communication speed that does not depend on a third-party clock at the device end. The toggle of all signals of the master and slave devices adopts push-pull drive, avoiding the low-speed problem caused by open-drain drive, and at the same time, simplifying the signal connections between the master and slave devices.

[0069] Fourthly, embodiments of this application also provide a storage medium, which is a computer-readable storage medium storing a computer program that, when executed by a processor, implements the aforementioned synchronous serial communication method.

[0070] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof. The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate, and may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0071] Although specific embodiments are described herein, those skilled in the art will recognize that many other modifications or alternative embodiments are also within the scope of this disclosure. For example, any of the functions and / or processing capabilities described in connection with a particular device or component can be performed by any other device or component. Furthermore, while various exemplary embodiments and architectures have been described according to embodiments of this disclosure, those skilled in the art will recognize that many other modifications to the exemplary embodiments and architectures described herein are also within the scope of this disclosure.

[0072] The foregoing description, with reference to block diagrams and flowcharts of systems, methods, systems, and / or computer program products according to exemplary embodiments, has described certain aspects of this disclosure. It should be understood that one or more blocks in the block diagrams and flowcharts, as well as combinations of blocks in the block diagrams and flowcharts, can be implemented by executing computer-executable program instructions, respectively. Similarly, according to some embodiments, some blocks in the block diagrams and flowcharts may not need to be executed in the order shown, or may not all need to be executed. Furthermore, additional components and / or operations beyond those shown in the blocks in the block diagrams and flowcharts may exist in some embodiments.

[0073] Therefore, blocks in block diagrams and flowcharts support combinations of means for performing a specified function, combinations of elements or steps for performing a specified function, and program instruction means for performing a specified function. It should also be understood that each block in a block diagram and flowchart, and combinations of blocks in block diagrams and flowcharts, can be implemented by a dedicated hardware computer system or a combination of dedicated hardware and computer instructions that performs a specific function, element, or step.

[0074] The program modules, applications, etc., described herein may include one or more software components, including, for example, software objects, methods, data structures, etc. Each such software component may include computer-executable instructions that, in response to execution, cause at least a portion of the functionality described herein (e.g., one or more operations of the exemplary methods described herein) to be performed.

[0075] Software components can be coded using any of a variety of programming languages. An exemplary programming language could be a low-level programming language, such as assembly language associated with a specific hardware architecture and / or operating system platform. Software components including assembly language instructions may need to be converted into executable machine code by an assembler before being executed by the hardware architecture and / or platform. Another exemplary programming language could be a higher-level programming language that is portable across multiple architectures. Software components including higher-level programming languages ​​may need to be converted into an intermediate representation by an interpreter or compiler before execution. Other examples of programming languages ​​include, but are not limited to, macro languages, shell or command languages, job control languages, scripting languages, database query or search languages, or report writing languages. In one or more exemplary embodiments, a software component containing instructions from one of the above-described programming language examples can be executed directly by the operating system or other software components without first being converted into another form.

[0076] Software components can be stored as files or other data storage structures. Software components of similar type or related function can be stored together in a specific directory, folder, or library. Software components can be static (e.g., pre-defined or fixed) or dynamic (e.g., created or modified at runtime).

[0077] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A synchronous serial communication system, characterized in that, The system includes a master device and a slave device, which are connected via clock signal lines and data signal lines. The data signal lines are connected to pull-up resistors. The data frame for a write command sent from the master device to the slave device includes: a start bit, a read / write command bit, an address field, a first parity bit, a write data field, a second parity bit, and an end bit. The data frame for a read command sent from the master device to the slave device includes a start bit, a read / write command bit, an address field, a first parity bit, and an end bit. When the start bit is active, the data signal line is low; when the end bit is active, the data signal line is high. During idle time slots in the data frame, the slave device transmits a level signal to the master device via the data signal lines.

2. The synchronous serial communication system according to claim 1, characterized in that, When the master device sends the write command to the slave device, the slave device's response data frame includes a start bit, a write command response field, and an end bit; when the master device sends the read command to the slave device, the slave device's response data frame includes a start bit, a read data field, a third parity bit, and an end bit.

3. The synchronous serial communication system according to claim 1, characterized in that, The master device includes a master control module, a clock generation module, a parallel-to-serial conversion module, and an interrupt status check module. The master control module is connected to the clock generation module, the parallel-to-serial conversion module, and the interrupt status check module. The clock generation module is used to generate a clock signal on the clock signal line. The parallel-to-serial conversion module is used to perform parallel-to-serial conversion when transmitting data and serial-to-parallel conversion when receiving data. The interrupt status check module is used to detect the interrupt signal of the slave device.

4. The synchronous serial communication system according to claim 3, characterized in that, The main control module includes a main state machine and a main counter. The main counter is used to count when the main state machine is in a corresponding state, and to trigger the main state machine to perform a state transition when the count value meets the maximum count value of the corresponding state. The main state machine is used to control the working state of the main device.

5. The synchronous serial communication system according to claim 3, characterized in that, The clock generation module includes a clock divider circuit and a clock gating unit. The clock divider circuit is configured with a preset divider factor, which is used to divide the original clock signal according to the divider factor. The gating enable signal of the clock gating unit is controlled by the main control module. The clock gating unit is used to output the divided clock signal in the communication state.

6. The synchronous serial communication system according to claim 1, characterized in that, The slave device includes a slave control module, a reset command counting module, a serial-to-parallel conversion module, an interrupt status output module, and an SDA signal multiplexing module. The slave control module is connected to the reset command counting module, the serial-to-parallel conversion module, and the interrupt status output module. The SDA signal multiplexing module is electrically connected to the serial-to-parallel conversion module and the interrupt status output module. The reset command counting module monitors the reset command from the master device to reset the slave device. The serial-to-parallel conversion module performs parallel-to-serial conversion when transmitting data and serial-to-parallel conversion when receiving data. The interrupt status output module generates an interrupt signal. The SDA signal multiplexing module multiplexes data signals and interrupt signals.

7. A synchronous serial communication method, characterized in that, A master device applied to a synchronous serial communication system as described in any one of claims 1-6, the master device comprising a master control module, a clock generation module, a parallel-to-serial conversion module, and an interrupt status check module, the master control module comprising a master state machine and a master counter; the method comprising: during communication, causing the master state machine to enter a first state, outputting a one-cycle clock on the clock signal line through the clock generation module, and outputting a start bit on the data signal line through the parallel-to-serial conversion module; after completing the transmission of the start bit, causing the master state machine to enter a second state, outputting a one-cycle clock on the clock signal line through the clock generation module, and outputting a read / write command bit on the data signal line through the parallel-to-serial conversion module. The main state machine is then set to the third state, where the clock generation module outputs eight clock cycles on the clock signal line, and the parallel-to-serial conversion module outputs the address field on the data signal line. The main state machine is then set to the fourth state, where the clock generation module outputs one clock cycle on the clock signal line, and the parallel-to-serial conversion module outputs the first parity bit on the data signal line. Based on the read / write command bit, a read or write operation is determined. When a read operation is performed, the main state machine is set to the fifth state, where the clock generation module outputs one clock cycle on the clock signal line, and the parallel-to-serial conversion module outputs the end bit on the data signal line.

8. The synchronous serial communication method according to claim 7, characterized in that, After determining whether to perform a read or write operation based on the read / write command bit, the method further includes: when performing a write operation, causing the main state machine to enter a sixth state, outputting eight clock cycles on the clock signal line through the clock generation module, and outputting a write data field on the data signal line through the parallel-to-serial conversion module; causing the main state machine to enter a seventh state, outputting one clock cycle on the clock signal line through the clock generation module, and outputting a second parity bit on the data signal line through the parallel-to-serial conversion module; causing the main state machine to enter an eighth state, outputting one clock cycle on the clock signal line through the clock generation module, and outputting an end bit on the data signal line through the parallel-to-serial conversion module.

9. A synchronous serial communication method, characterized in that, Based on a slave device in a synchronous serial communication system as described in any one of claims 1-6, the slave device includes a slave control module, a reset command counting module, a serial-to-parallel conversion module, an interrupt status output module, and an SDA signal multiplexing module. The slave control module further includes a slave state machine and a slave state counter. The method includes: detecting a start bit on a data signal line through the serial-to-parallel conversion module; when the start bit is detected, causing the slave state machine to enter a ninth state; sampling read / write command bits through the serial-to-parallel conversion module; determining whether the master device is sending a read command or a write command based on the read / write command bits; and causing the master device to... The slave state machine enters the tenth state, and obtains the read / write address by sampling the address field through the serial-to-parallel conversion module; the slave state machine then enters the eleventh state, and samples the first parity bit through the serial-to-parallel conversion module and performs parity checking; if the master device sends a read command after the parity check passes, the slave state machine enters the twelfth state, and samples the end bit through the serial-to-parallel conversion module; the slave state machine then enters the thirteenth state, and the slave device performs a read operation according to the read / write address to obtain read data; the slave state machine then enters the fourteenth state, and sends the read data to the master device.

10. The synchronous serial communication method according to claim 9, characterized in that, After the steps of causing the slave state machine to enter the eleventh state, sampling the first parity bit through the serial-to-parallel conversion module, and performing parity verification, the method further includes: when the parity verification passes, if the master device sends a write command, causing the slave state machine to enter the fifteenth state, sampling the write data field through the serial-to-parallel conversion module to obtain the write data; causing the slave state machine to enter the sixteenth state, sampling the second parity bit through the serial-to-parallel conversion module, and performing parity verification; when the parity verification passes, causing the slave state machine to enter the seventeenth state, sampling the end bit through the serial-to-parallel conversion module; causing the slave state machine to enter the eighteenth state, causing the slave device to perform a write operation according to the read / write address and the write data; when a write response is received, causing the slave state machine to enter the nineteenth state, sending a response value to the master device through the serial-to-parallel conversion module.

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