Time synchronization method, system and device, computer equipment and readable storage medium

Abstract

The invention relates to a time synchronization method, system and device, computer equipment and a readable storage medium. The method comprises the following steps: receiving an RGMII signal from a physical layer chip through an RGMII interface of the FPGA, and converting the RGMII signal into a GMII signal; under the condition that the GMII signal is matched with a preset signal feature, performing latching processing on the current time of a local clock to obtain a latched timestamp; the local clock is driven by a global clock generated by a crystal oscillator; and performing time synchronization on the local clock according to the latch timestamp. By adopting the method, the time synchronization precision can be improved.

Description

Technical Field

[0001] This application relates to the field of precision measurement and control technology, and in particular to a time synchronization method, system, device, computer equipment, and readable storage medium. Background Technology

[0002] In fields such as magnetic confinement fusion, high-energy physics experiments, and precision industrial measurement and control, nanosecond-level time synchronization among distributed nodes is the core foundation for ensuring data temporal consistency and achieving precise event correlation. The IEEE 1588 Precision Time Protocol (PTP) is the mainstream technology for networked clock synchronization, and its existing implementations include software and hardware solutions. Hardware solutions often use voltage-controlled crystal oscillators (VCXOs) and analog circuits to implement clock servoing. While this can improve synchronization accuracy, it is costly and complex. Software solutions capture timestamps in the network driver layer of the operating system kernel or higher-level protocol stacks, which is susceptible to random delay jitter caused by factors such as task scheduling and interrupt response delays. The synchronization accuracy only reaches the microsecond level, which cannot meet the nanosecond-level synchronization requirements. Therefore, existing time synchronization technologies have accuracy bottlenecks. Summary of the Invention

[0003] Therefore, it is necessary to provide a time synchronization method, system, device, computer equipment, computer-readable storage medium, and computer program product that can improve accuracy in addressing the aforementioned technical problems.

[0004] Firstly, this application provides a time synchronization method applied to an FPGA, comprising:

[0005] The FPGA receives RGMII signals from the physical layer chip via its RGMII interface and converts these RGMII signals into GMII signals.

[0006] When the GMII signal matches the preset signal characteristics, the current time of the local clock is latched to obtain a latched timestamp; the local clock is driven by a global clock generated by a crystal oscillator.

[0007] The local clock is synchronized based on the latched timestamp.

[0008] Secondly, this application also provides a time synchronization system, the system including a crystal oscillator, a physical layer chip and an FPGA, wherein the FPGA communicates with the physical layer chip through an RGMII interface;

[0009] The crystal oscillator is used to generate a global clock; the global clock is used to drive the local clock of the FPGA.

[0010] The physical layer chip is used to transmit RGMII signals to the FPGA through the RGMII interface;

[0011] The FPGA is used to convert the RGMII signal received through the RGMII interface into a GMII signal. When the GMII signal matches a preset signal characteristic, the FPGA latches the current time of the local clock to obtain a latched timestamp and synchronizes the local clock according to the latched timestamp.

[0012] Thirdly, this application also provides a time synchronization device for use in FPGA, comprising:

[0013] The signal conversion module is used to receive RGMII signals from the physical layer chip through the RGMII interface of the FPGA and convert the RGMII signals into GMII signals.

[0014] The feature matching module is used to latch the current time of the local clock to obtain a latched timestamp when the GMII signal matches a preset signal feature; the local clock is driven by a global clock generated by a crystal oscillator.

[0015] The time synchronization module is used to synchronize the local clock according to the latched timestamp.

[0016] Fourthly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0017] The FPGA receives RGMII signals from the physical layer chip via its RGMII interface and converts these RGMII signals into GMII signals.

[0018] When the GMII signal matches the preset signal characteristics, the current time of the local clock is latched to obtain a latched timestamp; the local clock is driven by a global clock generated by a crystal oscillator.

[0019] The local clock is synchronized based on the latched timestamp.

[0020] Fifthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0021] The FPGA receives RGMII signals from the physical layer chip via its RGMII interface and converts these RGMII signals into GMII signals.

[0022] When the GMII signal matches the preset signal characteristics, the current time of the local clock is latched to obtain a latched timestamp; the local clock is driven by a global clock generated by a crystal oscillator.

[0023] The local clock is synchronized based on the latched timestamp.

[0024] Sixthly, this application also provides a computer program product, including a computer program that, when executed by a processor, performs the following steps:

[0025] The FPGA receives RGMII signals from the physical layer chip via its RGMII interface and converts these RGMII signals into GMII signals.

[0026] When the GMII signal matches the preset signal characteristics, the current time of the local clock is latched to obtain a latched timestamp; the local clock is driven by a global clock generated by a crystal oscillator.

[0027] The local clock is synchronized based on the latched timestamp.

[0028] The aforementioned time synchronization method, system, device, computer equipment, computer-readable storage medium, and computer program product receive RGMII signals from the physical layer chip through the Reduced Gigabit Media Independent Interface (RGMII) of the Field Programmable Gate Array (FPGA), convert the RGMII signals into GMII signals, and latch the current time of the local clock to obtain a latched timestamp when the GMII signals match preset signal characteristics. The local clock is driven by a global clock generated by a crystal oscillator, and time synchronization is performed on the local clock based on the latched timestamp. This allows the FPGA to complete RGMII signal conversion and feature matching at the RGMII physical interface layer and directly latch the timestamp based on the local clock, avoiding random delay jitter introduced by the operating system network driver layer or protocol stack, eliminating the nondeterministic error in the timestamp capture stage, and thus improving the accuracy of time synchronization. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a flowchart illustrating a time synchronization method in one embodiment;

[0031] Figure 2 This is a flowchart illustrating the local clock time synchronization process in one embodiment;

[0032] Figure 3 This is a schematic diagram of the architecture of a time synchronization system in one embodiment;

[0033] Figure 4 This is a schematic diagram of the logical architecture for zero-wait timestamp capture at the physical layer in one embodiment;

[0034] Figure 5 This is a flowchart illustrating the real-time clock state update process in one embodiment;

[0035] Figure 6 This is an interactive flowchart for peer-to-peer delay link measurement in one embodiment;

[0036] Figure 7 This is a flowchart illustrating the time synchronization method in another embodiment;

[0037] Figure 8 This is a structural block diagram of a time synchronization device in one embodiment;

[0038] Figure 9 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0040] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0041] Furthermore, it should be noted that the signal reception, feature matching, timestamp latching, and all-digital time synchronization operations involved in the embodiments of this application are all executed in parallel by pure hardware logic gate circuits configured inside the FPGA within the underlying clock cycle, without the intervention of the microprocessor (CPU) software instruction cycle, completely bypassing the computer operating system and the high-level protocol stack.

[0042] In fields such as magnetic confinement fusion devices, high-energy physics experiments, and precision industrial measurement and control, achieving nanosecond-level time synchronization among distributed nodes is a crucial foundation for ensuring data temporal consistency and conducting accurate event correlation analysis. For example, in transient physical processes such as tokamak plasma rupture, sensors and actuators distributed in different locations must work collaboratively under the same time reference; synchronization deviations of microseconds or more can lead to physical misjudgments or control mismatches. Currently, IEEE 1588 PTP is the mainstream technology for achieving networked clock synchronization, but it struggles to simultaneously meet the comprehensive performance requirements of high precision, low cost, and high environmental robustness.

[0043] On the one hand, widely used software-based PTP solutions (such as PTP software running on general-purpose Linux systems) are architecturally limited. The timestamp capture point is located in the network driver layer of the operating system kernel or in the protocol stack at a higher level. From the physical interface to the tagging point, the packet must pass through multiple processing stages, including the physical layer (PHY) chip, the media access control (MAC) controller, the system bus, the kernel protocol stack, and the application. Software and system-level behaviors such as operating system task scheduling, interrupt response latency, protocol stack buffer queue management, and bus arbitration introduce unpredictable microsecond-level random latency jitter. Such errors introduced by non-deterministic transmission paths cannot be fully compensated by protocol algorithms, resulting in synchronization accuracy being limited to the microsecond level, making it difficult to stably reach sub-microsecond to nanosecond levels, and unsuitable for precision scientific and industrial scenarios with high requirements for timing determinism.

[0044] On the other hand, hardware-assisted PTP solutions (such as dedicated switches or synchronization chips) developed to improve synchronization accuracy can effectively avoid random jitter caused by software protocol stacks by implementing hardware timestamp marking within FPGAs or application-specific integrated circuits (ASICs). However, the core clock synchronization mechanism of such solutions often adopts an analog circuit architecture, typically using a voltage-controlled crystal oscillator (VCXO) as the local clock source, and continuously adjusting the VCXO by outputting an analog voltage through a high-resolution digital-analog converter (DAC). While this analog servo architecture improves accuracy, it also brings higher hardware costs, complex mixed-signal circuit design, and inherent environmental sensitivity. Analog devices such as VCXOs and DACs are susceptible to environmental factors such as temperature changes and electromagnetic interference. Under harsh operating conditions such as strong electromagnetic noise and wide temperature fluctuations around nuclear fusion devices, their control voltage is easily interfered with, and the crystal oscillator output frequency is prone to drift, thereby reducing the long-term stability and reliability of the synchronization system.

[0045] Given that software solutions are low-cost but lack precision, while hardware solutions offer high precision but are expensive and have poor environmental adaptability, it is generally believed that achieving high-precision frequency servo control is difficult without analog adjustment methods such as VCXOs, and low-cost time synchronization technology has a precision bottleneck.

[0046] Based on the aforementioned traditional technologies, this application provides a time synchronization method. The method receives RGMII signals from a physical layer chip via the FPGA's RGMII interface, converts the RGMII signals into GMII signals, and latches the current time of the local clock to obtain a latched timestamp when the GMII signals match preset signal characteristics. The local clock is driven by a global clock generated by a crystal oscillator. Time synchronization is performed on the local clock based on the latched timestamp. This allows the FPGA to complete RGMII signal conversion and feature matching at the RGMII physical interface layer and directly latch the timestamp based on the local clock, avoiding random delay jitter introduced by the operating system's network driver layer or protocol stack, eliminating the nondeterministic error in the timestamp capture stage, and thus improving the accuracy of time synchronization.

[0047] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0048] In one exemplary embodiment, such as Figure 1 As shown, a time synchronization method is provided. This embodiment illustrates the application of this method to an FPGA. It is understood that this method can also be applied to a terminal or server, and further to a system including both a terminal and a server, and is implemented through interaction between the terminal and the server. In this embodiment, the method includes the following steps:

[0049] Step S102: Receive the RGMII signal from the physical layer chip through the FPGA's RGMII interface, and convert the RGMII signal into a GMII signal.

[0050] RGMII signal refers to the Gigabit Ethernet interface signal transmitted between the MAC and PHY via the RGMII interface, using Double Data Rate (DDR) and double-edge sampling. GMII signal refers to the Gigabit Ethernet interface signal using Single Data Rate (SDR) and single-edge sampling.

[0051] Optionally, the FPGA can connect to the physical layer chip via the RGMII interface. The physical layer chip sends double-rate, double-edge RGMII signals to the FPGA via the RGMII interface. After receiving the RGMII signals via the RGMII interface, the FPGA can sample and recover the RGMII signals, converting them into single-rate, single-edge GMII signals. For example, the FPGA receives control signals (RX_CTL) and double-edge data signals (RXD[3:0]) from the gigabit PHY chip via the RGMII interface. It can directly call the FPGA's underlying Input Double Data Rate (IDDR) hardware primitive at the input / output (I / O) boundary, accurately sampling at the rising and falling edges of the 125MHz recovery clock, converting the 4-bit double-edge RGMII signal into an 8-bit single-edge parallel data stream, and recovering it into a standard GMII format signal.

[0052] Step S104: When the GMII signal matches the preset signal characteristics, the current time of the local clock is latched to obtain a latched timestamp; the local clock is driven by the global clock generated by the crystal oscillator.

[0053] The preset signal characteristics can be defined as bytes at preset positions in the GMII signal satisfying a specified matching rule. For example, if bytes 20 and 21 in a data frame are the Ethernet type identifier 0x88F7 specific to the IEEE 1588 PTP protocol, then the GMII signal is considered to match the preset signal characteristics. The current time refers to the current absolute physical time. The latched timestamp can be the physical timestamp obtained by instantaneously latching and storing the current absolute physical time into a register. The crystal oscillator used to generate the global clock includes, but is not limited to, various passive quartz crystals and ordinary active crystal oscillators.

[0054] Optionally, a passive quartz crystal or a regular active crystal can be deployed in the external hardware environment of the FPGA to provide a reference clock input for the FPGA. The reference clock can be multiplied by the FPGA's internal logic circuit to generate a global clock. The global clock can drive the local clock to generate a high-precision local time in real time. The FPGA can monitor in real time whether the GMII signal matches the preset signal characteristics. When the GMII signal matches the preset signal characteristics, the current time of the local clock is read and latched into a register to obtain a latched timestamp. For example, the FPGA logic circuit can monitor the valid enable signal (RX_DV) in RX_CTL in real time. When RX_DV is detected to be high, it indicates the start of the physical layer data envelopment, and the byte counter can be started immediately. When the byte counter steps to a specific offset (such as the 20th and 21st bytes), the FPGA logic circuit can compare the value of the data bus in real time within the current clock cycle to see if it is the Ethernet type identifier (0x88F7) specific to the IEEE 1588 PTP protocol. If the comparison is successful, the subsequent bytes are used to determine the message subtype code, and a trigger pulse with a clock cycle width is output instantaneously within the same clock cycle. In response to the trigger pulse, the FPGA logic circuit can instantly latch and store the current absolute physical time from the local clock into the register as a latched timestamp.

[0055] It should be noted that the latched timestamp type differs depending on the message subtype code. For example, when the message subtype code is 0x00, the latched timestamp may include the sending timestamp of the master clock's synchronization (Sync) message. And the timestamp of the local clock (from the clock) when it receives the synchronization message. When the message subtype code is 0x01, the latched timestamp may include the timestamp of the local clock (slave clock) sending the Delay Request (Delay_Req) ​​message. And the timestamp of the master clock receiving the delay request message. .

[0056] Step S106: Synchronize the local clock according to the latched timestamp.

[0057] Optionally, the FPGA can synchronize its local clock with the master clock based on the latched timestamp obtained from the latched local time, thus achieving local clock time synchronization. For example, the FPGA logic circuit can synchronize the local clock based on the latched timestamp. Calculate the frequency deviation of the local clock, and combine it with the phase deviation of the local clock to synchronize the local clock with the master clock.

[0058] The aforementioned time synchronization method receives RGMII signals from the physical layer chip via the FPGA's RGMII interface, converts the RGMII signals into GMII signals, and latches the current time of the local clock to obtain a latched timestamp when the GMII signals match preset signal characteristics. The local clock is driven by a global clock generated by a crystal oscillator, and time synchronization is performed on the local clock based on the latched timestamp. This allows the FPGA to complete RGMII signal conversion and feature matching at the RGMII physical interface layer and directly latch the timestamp based on the local clock, avoiding random delay jitter introduced by the operating system's network driver layer or protocol stack, eliminating the nondeterministic error in the timestamp capture stage, and thus improving the accuracy of time synchronization.

[0059] In an exemplary embodiment, step S104 may specifically include: starting the byte counter of the FPGA in response to a valid enable signal in the GMII signal; generating a trigger pulse if the GMII signal matches a preset signal feature when the byte counter steps to a preset offset; the preset signal feature includes a preset Ethernet type identifier; and latching the current time from the local clock into the latch register of the FPGA in response to the trigger pulse to obtain a latched timestamp.

[0060] The valid enable signal can be, but is not limited to, RX_DV in RX_CTL. The byte counter can be a sequential logic circuit within the FPGA, incrementing in bytes on the GMII parallel data bus to locate the position of each protocol field in the Ethernet frame. The preset offset can be a fixed byte position pre-configured in the FPGA logic. The preset Ethernet type identifier can be, but is not limited to, the Ethernet type identifier 0x88F7. The latch register can be another sequential logic circuit within the FPGA, used to momentarily capture and store the local time.

[0061] Optionally, a byte counter and latch register can be configured in the FPGA. The FPGA monitors the valid enable signal in the GMII signal in real time. When a valid enable signal is detected in the GMII signal, the byte counter is started. When the byte counter steps to a preset offset, it compares the current byte of the GMII signal with a preset rule in real time. If they match, a trigger signal is generated. The FPGA can respond to the trigger signal and latch the current time generated by the local clock into the register to obtain a latched timestamp. For example, the FPGA logic circuit can monitor RX_DV in RX_CTL in real time. When RX_DV is detected to be high, the byte counter is started immediately. When the byte counter steps to the 20th and 21st bytes, the FPGA logic circuit can compare the value of the data bus with the Ethernet type identifier 0x88F7 in real time within the current clock cycle. If the comparison is successful, the subsequent bytes are used to determine the message subtype code, and a trigger pulse with a clock cycle width is output instantaneously within the same clock cycle. In response to the trigger pulse, the FPGA logic circuit can instantaneously latch and store the current absolute physical time from the local clock into the register as a latched timestamp. The local clock can be a local accumulator deployed in the FPGA.

[0062] In this embodiment, by responding to the valid enable signal in the GMII signal, the FPGA's byte counter is started, which avoids the risk of false triggering caused by preamble truncation when searching for the start of frame symbol (0xD5) in the traditional way. When the byte counter steps to a preset offset, if the GMII signal matches the preset signal characteristics, a trigger pulse is generated, which allows the listening process and the data flow to the MAC layer to occur in parallel without interference, reducing the impact on data transmission. In response to the trigger pulse, the current time from the local clock is latched in the FPGA's latch register to obtain a latched timestamp. Since the trigger determination is completed by a pure counter and combinational logic, and the timestamp acquisition path adopts an extremely simplified timing logic design, the internal delay from the signal arriving at the FPGA pin to the timestamp latch can be fixed as a number of constant logic gate transmission delays, thereby eliminating queuing jitter, achieving zero-wait capture at the physical layer, significantly reducing synchronization errors, and ultimately achieving nanosecond-level high-precision time synchronization.

[0063] In one exemplary embodiment, such as Figure 2 As shown, step S106 above can specifically include:

[0064] Step S201: Determine the frequency adjustment amount of the local clock based on the latch timestamps of two adjacent synchronization cycles;

[0065] Step S202: Determine the phase adjustment amount of the local clock based on the phase error between two adjacent synchronization cycles;

[0066] Step S203: Adjust the clock beat of the local clock according to the frequency adjustment amount and the phase adjustment amount so that the local clock is synchronized with the master clock.

[0067] Here, two adjacent synchronization cycles refer to the time interval between two consecutive PTP timestamp exchanges between the master and slave clocks, i.e., the complete cycle between the (k-1)th synchronization process and the kth synchronization process. The frequency adjustment can be the slave clock frequency correction value calculated based on the master-slave clock frequency ratio. The phase adjustment can be the phase offset correction value between the master and slave clocks, used to eliminate the current phase deviation between them. The clock tick refers to the smallest timing unit of the FPGA's internal clock, determined by the global clock cycle (e.g., a 125MHz clock corresponds to an 8ns tick).

[0068] Optionally, the FPGA can use the latch timestamps of two adjacent synchronization cycles. The frequency ratio between the master and slave clocks is determined, and the frequency adjustment amount of the local clock is obtained based on the frequency ratio. Alternatively, based on the incremental discrete proportional-integral (PI) control law, the phase adjustment increment between two adjacent synchronization cycles can be determined according to the phase error between two adjacent synchronization cycles. Based on the phase adjustment increment, the phase adjustment amount of the local clock in the current synchronization cycle is determined. Combining the frequency adjustment amount and the phase adjustment amount, the FPGA can insert or subtract pulses in the clock beat of the local clock to adjust the clock pulse and synchronize the local clock with the master clock.

[0069] In this embodiment, the frequency adjustment amount of the local clock is determined based on the latch timestamps of two adjacent synchronization cycles, the phase adjustment amount of the local clock is determined based on the phase error of two adjacent synchronization cycles, and the clock beat of the local clock is adjusted according to the frequency adjustment amount and the phase adjustment amount to synchronize the local clock with the master clock. This can achieve high-stability frequency-phase closed-loop locking of ordinary crystal oscillators based on lightweight pure digital logic, get rid of the hardware dependence of high-precision time synchronization on VCXO and high-bit-width DAC, and reduce synchronization costs.

[0070] In an exemplary embodiment, step S201 may specifically include: determining a timestamp increment based on the latch timestamps of two adjacent synchronization cycles; the timestamp increment includes the master timestamp increment of the master clock and the local timestamp increment of the local clock; obtaining the frequency ratio of the master clock relative to the local clock based on the master timestamp increment and the local timestamp increment; and obtaining the frequency adjustment amount of the local clock based on the frequency ratio.

[0071] The timestamp increment can be the difference between the timestamp of the k-th synchronization process and the timestamp of the (k-1)-th synchronization process. The master timestamp increment can be the timestamp increment corresponding to the master clock, for example, , The local timestamp increment can be the timestamp increment corresponding to the local clock, for example, , The frequency ratio refers to the ratio of the physical frequency of the master clock to the physical frequency of the local clock.

[0072] Alternatively, the FPGA logic circuit can utilize the latch timestamps of two adjacent synchronization cycles. , , , , , , , Get the main timestamp increment , and local timestamp increment , ; Calculate the cumulative sum of the master timestamp increments And the accumulation of local timestamp increments Based on the ratio of the two, the precise physical frequency ratio of the master clock relative to the local clock is obtained. The specific calculation formula is as follows:

[0073] ;

[0074] in, The master clock frequency, This is the local clock frequency. Because... Reflecting the frequency ratio between the master and slave clocks, it can be based on Determine the frequency adjustment amount to synchronize the local clock with the master clock.

[0075] In this embodiment, the timestamp increment is determined based on the latched timestamps of two adjacent synchronization cycles. The frequency ratio of the master clock relative to the local clock is obtained based on the master timestamp increment and the local timestamp increment. The frequency adjustment amount of the local clock is obtained based on the frequency ratio. The basic accumulation step size of the local counter can be directly modified using the frequency ratio to smooth out the rate difference between the master and slave clocks and prevent the time error from diverging over time.

[0076] In an exemplary embodiment, step S202 may specifically include: performing proportional-integral processing based on the phase error of two adjacent synchronization cycles to obtain the phase adjustment increment of the second synchronization cycle relative to the first synchronization cycle; the two adjacent synchronization cycles include the first synchronization cycle and the second synchronization cycle, and the first synchronization cycle is earlier than the second synchronization cycle; obtaining the phase adjustment amount of the second synchronization cycle based on the phase adjustment increment and the phase adjustment amount of the first synchronization cycle; and obtaining the phase adjustment amount of the local clock based on the phase adjustment amount of the second synchronization cycle.

[0077] The phase error includes the absolute phase error between the master and slave clocks measured during the k-th synchronization. And the absolute phase error between the master and slave clocks measured during the (k-1)th synchronization. The second synchronization period refers to the period in which the k-th synchronization occurs. The first synchronization period refers to the period in which the (k-1)-th synchronization occurs. The phase adjustment increment refers to the phase value that the k-th synchronization needs to adjust relative to the (k-1)-th synchronization.

[0078] Optionally, the FPGA logic circuit can be based on the phase error of the (k-1)th synchronization cycle. and the phase error of the kth synchronization period. The phase adjustment increment of the k-th synchronization period relative to the (k-1)-th synchronization period is determined by an incremental discrete PI control law. The specific calculation formula is as follows:

[0079] ;

[0080] in, For proportional gain, This is the integral gain.

[0081] Using phase adjustment increment Phase adjustment amount for the (k-1)th synchronization period By making adjustments, the phase adjustment amount for the kth synchronization period can be obtained. The specific calculation formula is as follows:

[0082]

[0083] The phase adjustment amount of the kth synchronization period As a phase adjustment amount for the local clock.

[0084] In this embodiment, the phase adjustment increment of the second synchronization cycle relative to the first synchronization cycle is obtained by performing proportional-integral processing based on the phase error of two adjacent synchronization cycles. The phase adjustment amount of the second synchronization cycle is obtained based on the phase adjustment increment and the phase adjustment amount of the first synchronization cycle. The phase adjustment amount of the local clock is obtained based on the phase adjustment amount of the second synchronization cycle. This allows the FPGA to generate the phase adjustment amount in real time using the current absolute phase error, without the need to maintain a gradually increasing global integral accumulator, avoiding the risk of digital register overflow and improving the reliability of hardware operation.

[0085] In an exemplary embodiment, step S203 may specifically include: determining the pulse throughput control word corresponding to the clock tick based on the frequency adjustment amount and the phase adjustment amount; and inserting or subtracting pulses in the clock tick based on the pulse throughput control word.

[0086] The pulse throughput control word refers to the micro-control quantity used to adjust a single timing beat of the local clock. For example, if the control word indicates that the local clock is too slow, a pulse is inserted into the current beat; if the control word indicates that the local clock is too fast, a pulse is subtracted from the current beat.

[0087] Optionally, the FPGA logic circuit can combine frequency adjustment and phase adjustment to determine the pulse throughput control word corresponding to each individual clock cycle of the local clock. Construct a high-bit-width fractional accumulator Accumulation is performed on each rising edge of the clock:

[0088] ;

[0089] in, This indicates the cumulative number of times.

[0090] When the accumulated decimal error reaches When the time exceeds the limit, an insertion action can be triggered to insert a pulse into the clock tick; when the local overrun reaches... When the clock ticks, a deduction action can be triggered to deduct a pulse from the clock tick.

[0091] In this embodiment, the pulse throughput control word corresponding to the clock beat is determined based on the frequency adjustment amount and the phase adjustment amount. According to the pulse throughput control word, pulses are inserted or deducted in the clock beat. The pulse throughput action can be used to synchronize the local clock with the master clock, reducing the time synchronization complexity.

[0092] To facilitate a deeper understanding of the embodiments of this application by those skilled in the art, a specific example will be used for illustration below.

[0093] Currently, achieving high-precision time synchronization faces challenges from two aspects: accuracy bottlenecks and hardware costs.

[0094] On the one hand, the software protocol stack introduces uncontrollable random jitter. Traditional software PTP solutions based on general-purpose processors typically acquire timestamps at the driver or application layer. During the process of a message traveling from the physical line to the tagging point, it must traverse the Ethernet PHY, MAC controller, Peripheral Component Interconnect Express (PCIE) / Advanced eXtensible Interface (AXI) bus, and the operating system kernel protocol stack. Affected by operating system interrupt response delays, buffer queue congestion, and the randomness of the bus arbitration mechanism, the dwell time generated by this transmission path exhibits microsecond-level uncertain jitter. Such nondeterministic errors cannot be fully compensated for by algorithms, making it difficult to break through the microsecond barrier in synchronization accuracy, thus failing to meet the stringent nanosecond-level synchronization requirements of nuclear fusion devices.

[0095] On the other hand, traditional hardware solutions rely on expensive and fragile analog servo architectures. While existing high-precision hardware synchronization solutions have solved the marking accuracy problem, their frequency locking mechanisms heavily depend on analog adjustment paths. Specifically, these solutions require expensive VCXOs and high-bandwidth DACs to physically drive the clock frequency. This architecture not only leads to high material costs and complex printed circuit board (PCB) designs, but more importantly, analog devices are extremely sensitive to the environment. In the strong magnetic fields, high radiation, and wide temperature ranges of nuclear fusion devices, analog control voltages are highly susceptible to noise interference, and crystal oscillator aging and temperature drift significantly deteriorate synchronization stability, resulting in increased system maintenance costs.

[0096] To address the shortcomings of the existing technologies, this application provides a time synchronization method based on RGMII physical layer zero-wait marking and all-digital frequency servo. It abandons the traditional approach of relying on MAC layer hardware and software marking and VCXO analog voltage regulation. By constructing RGMII physical layer feature listening logic and all-digital pulse throughput servo loop, nanosecond-level synchronization is achieved under ordinary crystal oscillator conditions.

[0097] Figure 3 A schematic diagram of the architecture of a time synchronization system is provided. Figure 3 The time synchronization system can include an FPGA and external hardware. The external connection only requires a low-cost 50MHz active crystal oscillator and a gigabit Ethernet PHY chip. The internal logic of the FPGA can be divided into five core functional areas: clock management unit, physical interface layer, zero-wait timestamp unit (TSU), all-digital frequency servo loop, and protocol processing engine (PTP message parsing / encapsulation engine).

[0098] In one exemplary embodiment, this application provides a zero-wait timestamp capture method for the RGMII physical layer based on envelope counting. Currently, conventional time synchronization solutions in the industry either rely on Ethernet MAC layer IP cores (where data must be queued through an internal First-In-First-Out (FIFO) queue and arbitrated with the AXI bus, introducing severe microsecond-level nondeterministic jitter) or expensive dedicated physical layer chips. This application proposes a technique combining bypass hardware listening and instantaneous physical snapshots. This technique eliminates the need for any MAC layer protocol stack or buffer queue, directly constructing extremely lightweight pure logic circuits at the RGMII physical pin boundaries of the FPGA, achieving zero-wait, zero-jitter timestamp capture using low-cost, ordinary PHY chips.

[0099] Figure 4 A hardware logic architecture diagram of a physical layer zero-wait timestamp capture circuit is provided. Based on... Figure 4 The timestamp capture method may include the following steps:

[0100] Step 1: Rapid demodulation of dual-edge signals at the physical boundary. The FPGA receives control signals (RX_CTL) and dual-edge data signals (RXD[3:0]) from a standard gigabit PHY chip via the RGMII interface. The system directly calls the FPGA's underlying double data rate hardware primitives at the I / O boundary, precisely sampling the rising and falling edges of the 125MHz recovery clock and rapidly converting them into an 8-bit single-edge parallel data stream (GMII format). This step establishes the lowest-level physical time base for the message entering the FPGA chip.

[0101] Step 2, bypass hard listening based on data envelopment and offset. For example... Figure 4 As shown by the comparison between the dashed and solid lines, unlike traditional data streams which must be fully queued in the MAC layer's receive FIFO, this application directly connects a bypass feature matching circuit in parallel at the IDDR demodulation output. This circuit does not contain any store-and-forward buffer; instead, it employs a streaming listening mechanism that counts data as it flows, specifically including:

[0102] First, envelope triggering and counting are performed. The logic circuit monitors the receive valid enable signal (RX_DV) in real time. Once RX_DV is detected to be high, indicating the start of the physical layer data envelope, the internal parallel byte counter is immediately started. This mechanism avoids the risk of false triggering caused by preamble truncation when searching for the start of frame symbol (0xD5) in the traditional method.

[0103] Then, offset feature matching is performed. As the byte counter steps to a specific protocol offset (such as bytes 20 and 21), combinational logic gates compare the value of the data bus in real time within the current clock cycle to see if it is the Ethernet type identifier (0x88F7) specific to the IEEE 1588 protocol and the corresponding message subtype code.

[0104] Finally, rapid trigger generation occurs. Once the logic gates match successfully, the listening circuit instantly outputs a classification trigger pulse one clock cycle wide within the same clock cycle. The entire listening process occurs in parallel with the data flow to the MAC layer, without interference.

[0105] Step 3, Unbuffered Instantaneous Physical Snapshot. Traditional timestamp acquisition operations often require cross-clock domain handshakes or waiting for AXI protocol bus signals, resulting in timing delays. This application designs a purely hardware-connected instantaneous snapshot mechanism: the trigger pulse generated by the aforementioned bypass listening circuit is directly hardwired to the enable terminal of the tagging register. The input of this register is continuously connected to an 80-bit high-precision global absolute time maintained by the local digital servo loop. On the rising edge of the trigger pulse, without any handshake protocol or FIFO buffer queue intervention, the hardware logic unconditionally latches and stores the current absolute physical time instantaneously into the register. Since the trigger action is generated by a pure counter and combinational logic, and the time acquisition path is an extremely simplified sequential logic, this mechanism fixes the internal delay from the signal arriving at the FPGA pin to the timestamp latching to a few constant logic gate delays, completely eliminating queuing jitter and achieving true physical layer zero-wait capture.

[0106] In one exemplary embodiment, this application provides a fully digital frequency servo method based on pulse throughput. Addressing the problem of large frequency deviations and the inability to physically adjust the voltage of ordinary crystal oscillators, this embodiment employs pulse throughput technology to achieve nanosecond-level fine-tuning of the clock rate in the fully digital domain. The system internally constructs an All-Digital Frequency-Locked Loop (ADFLL), which, through a frequency-phase dual-locking mechanism combining feedforward frequency compensation and closed-loop phase feedback, transforms the macroscopic control algorithm into microscopic logic actions of the underlying clock tick, specifically including:

[0107] Step 1, High-precision frequency difference calculation model.

[0108] The system implements the arithmetic engine through a DSP hard core unit, based on four timestamps exchanged using the PTP protocol. Establish a master-slave clock frequency relationship model. Define the master clock frequency as... From the clock frequency of Extract the increments of two adjacent synchronization cycles (k-th and (k-1)-th) to calculate the precise physical frequency ratio of the master and slave clocks. The formula is as follows:

[0109] ;

[0110] This formula plays a central role as the "feedforward compensation reference" in the servo loop. Under extreme environmental temperature drift (such as around a nuclear fusion device), network transmission delay dynamically changes. This solution model mathematically perfectly isolates this symmetrical physical temperature drift interference, extracting the pure physical frequency difference of the crystal oscillator. The system utilizes this ratio... By directly modifying the base accumulation step size of the local counter, the system can quickly level off the speed difference between master and slave nodes in the initial stage, preventing time errors from spreading over time.

[0111] Step 2, incremental discrete PI control law.

[0112] After resolving the basic rate alignment, the system employs an incremental discrete PI control law to eliminate the residual absolute time deviation between the master and slave clocks. The control formula is as follows:

[0113] .

[0114] in, This represents the absolute phase time error calculated in the k-th iteration. This represents the absolute phase time error calculated in the (k-1)th iteration. This is the phase adjustment control value of the current output. This is the phase adjustment control value from the previous output. and These are the proportional and integral gains, respectively.

[0115] Frequency ratio The discrete PI control law solves the problem of "equal speeds," while addressing the problem of "distance alignment." When startup times differ or network jitter occurs, the system may experience phase lag or lead. This formula can adjust the current absolute error based on the... Real-time generation of dynamic adjustment amount This forces the local time to catch up with the master clock phase. The engineering significance of using an "incremental" rather than a "positional" approach is that the FPGA does not need to maintain an infinitely large global integrator accumulator; it only needs to save the previous error state, thereby completely avoiding the risk of digital register overflow and greatly improving the long-term reliability of the underlying hardware.

[0116] Step 3, Local Real-Time Clock (RTC) state update equation.

[0117] The total adjustment calculated above is ultimately converted into pulse throughput for each clock cycle (125MHz, period 8ns), and its real-time state update formula is:

[0118] ;

[0119] in, The reference accumulation step size, for example, corresponding to 125MHz. It is 8ns. For throughput regulation, the set of values ​​is: . For the first Each clock tick corresponds to a local real-time clock.

[0120] This is an extremely lightweight low-level hardware executor. The standard step size is 8ns. Macroscopic control quantity. The fractional parts are evenly distributed and input into a high-bit-width fractional accumulator. When the accumulator overflows, a trigger is activated. This generates a +1ns or -1ns step. The larger the macroscopically calculated phase adjustment, the higher the density of +1ns / -1ns triggers at the underlying level. This mechanism perfectly reduces complex mathematical operations that are performed every few seconds to pure logic gate addition and subtraction every 8 nanoseconds, achieving a high-precision and extremely low-resource-consumption "all-digital frequency servo".

[0121] refer to Figure 5 The specific implementation logic can be as follows: ① Stuffing: When the algorithm determines that the local clock (RTC) is too slow, the controller issues an increment (INC) instruction, causing the counter to accumulate 8 + 1 = 9 ns in the current clock cycle, which is equivalent to inserting 1 ns into the time stream. ② Skipping: When the algorithm determines that the local clock is too fast, the controller issues a decrement (DEC) instruction, causing the counter to accumulate 8 - 1 = 7 ns in the current clock cycle, which is equivalent to subtracting 1 ns from the time stream. ③ Dynamic density modulation: The controller achieves precise compensation for minute frequency differences at the ppm level by adjusting the density of the inserted / skipping pulses. For example, inserting one pulse every 1000 cycles is equivalent to adjusting the frequency by 1000 ppm.

[0122] In summary, this application provides a zero-wait timestamp capture method for the RGMII physical layer based on envelope counting and offset matching. A pure hardware listening circuit, completely bypassing the traditional MAC layer FIFO buffer queue, is constructed at the physical pin boundaries of the FPGA. This circuit uses the valid data signal (RX_DV) as the envelope start point to initiate parallel clock counting. At a specific byte offset, a hard-wired comparison of the protocol signature (e.g., 0x88F7) is performed directly, and within the current single clock cycle of a successful match, the register is unconditionally driven to lock the global absolute time. This architecture completely eliminates the nondeterministic jitter introduced by the protocol stack and bus queuing, achieving nanosecond-level zero-wait capture of the physical arrival time of the message.

[0123] Furthermore, a high-precision clock locking method based on all-digital frequency servo and pulse throughput is presented, constructing a dual regulation architecture that integrates "feedforward frequency compensation" and "closed-loop phase feedback." First, a precise frequency ratio is calculated using a cross-cycle four-timestamp cross-summation differential model to isolate dynamic environmental temperature drift interference from a purely mathematical perspective. Second, an incremental discrete PI control law is used to calculate the absolute phase catch-up amount. The system amortizes the aforementioned macroscopic regulation amount into a microscopic compensation control word within a single clock cycle, triggering nanosecond-level pulse throughput (+1ns / -1ns) actions using the overflow mechanism of a low-level high-bit-width fractional accumulator. This method achieves highly stable frequency-phase closed-loop locking of ordinary low-cost crystal oscillators by relying on lightweight pure digital logic, completely eliminating the need for expensive voltage-controlled crystal oscillators and digital-to-analog converters.

[0124] The above method can eliminate nondeterministic jitter and achieve high-precision nanosecond-level synchronization. By embedding listening logic in the RGMII physical interface layer of the FPGA, the timestamp capture point is moved to the very beginning of the data link. This "zero-wait" tagging technology completely bypasses the Ethernet MAC controller, transmit / receive FIFO queue, and upper-layer software protocol stack, eliminating microsecond-level nondeterministic jitter introduced by operating system interrupt response delays, bus arbitration waits, and protocol stack buffer queuing from a physical perspective. Compared to traditional software solutions, this invention significantly improves the determinism of time synchronization, with measured synchronization errors stably controlled within ±50ns, meeting the requirements of nuclear fusion devices for precise alignment and monitoring of critical equipment status.

[0125] Furthermore, it eliminates expensive analog components, significantly reducing hardware costs and design complexity. The proposed all-digital frequency servo technology successfully eliminates the hardware dependence of high-precision synchronization systems on voltage-controlled crystal oscillators and high-bit-width digital-to-analog converters. The system only needs to use a low-cost, ordinary active crystal oscillator to achieve frequency locking through pulse throughput logic in the digital domain. This improvement not only reduces the bill of materials (BOM) cost of a single-node clock circuit by approximately 40%, but also eliminates the need for complex analog power supply filtering and mixed-signal wiring designs, greatly simplifying PCB design and facilitating large-scale, low-cost deployment in industrial monitoring networks.

[0126] Furthermore, it enhances environmental adaptability and strengthens the system's robustness in environments with strong interference. Traditional analog servo loops (DAC+VCXO) are extremely sensitive to changes in ambient temperature and electromagnetic interference, easily generating temperature drift and control voltage noise. This application uses pure digital logic for frequency and phase adjustment, with its control parameters embedded within the FPGA, unaffected by external analog signal interference. This "fully digital" characteristic enables the system to maintain extremely high long-term operational stability and reliability even when facing strong electromagnetic radiation, wide temperature ranges (such as low-temperature superconducting environments), and power fluctuations at nuclear fusion device sites, solving the problems of easy lockout and large drift in traditional analog solutions.

[0127] Finally, rapid convergence and locking are achieved through hardware-level ultra-fast response. A pipelined arithmetic engine is constructed using the DSP hard core unit within the FPGA, enabling hardware acceleration of frequency difference calculation and loop filtering. Compared to the traditional method of relying on CPU software to calculate floating-point numbers, the all-hardware servo loop in this application has extremely low feedback latency, enabling microsecond-level rapid responses to frequency changes in the clock source. This allows the system to complete frequency locking and phase alignment much faster during cold starts or under conditions of severe network load fluctuations, significantly improving the system's dynamic performance.

[0128] In one exemplary embodiment, a voltage monitoring node synchronization system for a tokamak device is provided, the system comprising:

[0129] Firstly, the core hardware includes:

[0130] FPGA core board: FPGA chip, equipped with a 50MHz ordinary active crystal oscillator (frequency stability ±50ppm).

[0131] Ethernet interface: Gigabit PHY chip, used with shielded gigabit network cable to achieve inter-node connection;

[0132] Auxiliary circuitry: FPGA peripheral configuration includes a power management module (12V to 3.3V / 1.8V) and an RGMII signal matching circuit (50-ohm terminating resistor).

[0133] Monitoring terminal: 8 voltage sensors (range 0~10V), connected to the FPGA acquisition interface via shielded cable.

[0134] Secondly, the software and logic configuration includes:

[0135] FPGA internal logic: includes RGMII physical layer listening module, pulse throughput servo loop ( , ), PTP protocol processing engine;

[0136] Synchronization parameters: Nominal transmission interval of Sync messages The timestamp capture accuracy is ±2ns, and the RTC counter reference step size is 8ns (corresponding to a 125MHz clock).

[0137] Thirdly, the deployment architecture adopts a 1-master-4-slave distributed architecture. The master node is deployed in the central control unit of the tokamak device, and the four slave nodes are deployed in four key areas of the device, such as the vacuum chamber and divertor. The maximum communication distance between nodes is ≤50 meters, and there is no direct connection with intermediate switches.

[0138] In terms of synchronization accuracy, the measured time deviation between the four slave nodes and the master node was stable within ±35ns, meeting the nanosecond-level synchronization requirements of the voltage sensor. In terms of stability, after 72 hours of continuous operation (covering one complete nuclear fusion experiment cycle), the synchronization error fluctuation was ≤5ns, with no loss of lock and no time base drift in the acquired data. In terms of cost, the BOM cost of a single-node clock circuit is approximately 120 yuan (ordinary crystal oscillator + PHY + FPGA core board), which is 40% lower than the traditional VCXO + DAC solution (cost of approximately 200 yuan per node). In terms of environmental adaptability, in the strong electromagnetic radiation environment of the tokamak device (electric field strength ≤100V / m) and the operating temperature range of -10℃ to 60℃, the synchronization performance showed no significant attenuation, and the data acquisition continuity met the standards.

[0139] In an exemplary embodiment, the above-mentioned high-precision frequency difference calculation model specifically includes:

[0140] refer to Figure 6 In a servo loop, the precise physical frequency ratio of the master and slave clocks must first be calculated. The system exchanges four timestamps based on the PTP protocol. Extract two adjacent synchronization cycles (the first one) Next and first The high-precision frequency difference calculation formula for the increment (times) is as follows:

[0141] ;

[0142] Frequency ratio The derivation process includes:

[0143] Step 1, Construct the underlying physical time model: Assume the absolute true physical time is... The operating frequency of the master clock is... The operating frequency of the clock is The local timestamps generated by the hardware counters of both. and All of these are absolute physical times. A linear function of the first degree:

[0144] ;

[0145] ;

[0146] in and These are the initial phase constants of their respective systems at startup.

[0147] Step 2, construct a single-cycle bidirectional measurement model: in the first cycle... Within each synchronization cycle, the master node is in physical time Sending messages, from the node at Receive (forward delay is) The one-way transmission delay of the message from the master clock port to the slave clock port is t-ms); the slave node in Sending messages, the master node is Receive (reverse delay is) The one-way transmission delay of the message from the clock port to the master clock port is t-sm. The generated timestamp is:

[0148] ;

[0149] ;

[0150] ;

[0151] .

[0152] Difference between adjacent periods to eliminate initial constants: extract the difference between two adjacent periods ( and timestamp increment At this time, the initial constant and Completely eliminated:

[0153] ;

[0154] ;

[0155] ;

[0156] .

[0157] in, and It is the absolute physical time interval between actions of the master and slave nodes. and This represents the path delay drift caused by changes in ambient temperature between two cycles.

[0158] Using physical symmetry for cross-summation elimination: Due to the symmetry of temperature drift in the physical medium of a local area network, i.e. .

[0159] Sum the timestamp increments of the master node: ;

[0160] Sum of the node timestamp increments: ;

[0161] Dividing the two equations reveals a complex term that includes the physical time interval and environmental temperature drift. The fractions cancel each other out, thus yielding the final, precise frequency ratio formula. .

[0162] In an exemplary embodiment, the discrete PI control law and phase adjustment amount mentioned above include:

[0163] In use After resolving the frequency alignment issue, the system employs a discrete PI control law to eliminate the absolute time deviation (i.e., phase error) between the master and slave clocks. The control formula (incremental) is as follows:

[0164] ;

[0165] in, For the current number The absolute phase error measured in this measurement. This is the phase adjustment amount for the current output. For proportional gain, This is the integral gain.

[0166] The relationship between the discrete PI control law and the ratio R is as follows:

[0167] Frequency ratio Together with the discrete PI control law, they constitute the "frequency-phase dual lock-in" mechanism:

[0168] Precise frequency ratio It solves the "speed alignment" problem. As a feedforward, it cancels out the inherent frequency drift of the local crystal oscillator, ensuring that the local clock's operating speed is consistent with the master clock.

[0169] Discrete PI control law This addresses the "distance catch-up" problem. Due to differences in power-on time or momentary random network jitter, residual phase errors may exist in the absolute time of the master and slave clocks. The PI controller uses this error to generate a dynamic adjustment. It forcibly pulls the local time to catch up with and coincide with the phase of the master clock.

[0170] Ultimately, the total adjustment step size inside the FPGA is the sum of the two. When the phase error is completely eliminated ( and When the system (tends to stabilize) completely falls back to the state it was in before... It operates smoothly at the determined baseline rate.

[0171] The derivation process of the discrete PI control law is as follows:

[0172] Step 1, Establish the continuous-time control model: In classical analog control theory, the physical and mathematical expression of the PI controller is a continuous-time model:

[0173] ;

[0174] in Represents the continuous flow of physical time.

[0175] Step 2, Discretization of the time axis: Since FPGA digital circuits rely on discrete clock cycles to operate, continuous time needs to be discretized. The arrival events of the synchronization messages are divided into discrete sampling points. Continuous variables are replaced with discrete sequences, i.e., errors. Output .

[0176] Step 3, Digital Mapping of Calculus: In the digital domain, continuous-time integration is equivalent to the discrete summation of each error sample value. Let the discretized integral gain be... The continuous integral term is transformed into a discrete summation term, leading to the positional discrete PI formula:

[0177] .

[0178] Step 4, Derive the incremental discrete control law: To avoid the need for the FPGA's internal integral accumulator... As time increases indefinitely, register overflow occurs; the system uses incremental differential derivation. Write out the... The positional output equation of the next step and with the first The equation of degree minus the first Equation of degree:

[0179] ;

[0180] After rearranging the terms, the final incremental discrete PI control law can be obtained:

[0181] ;

[0182] This approach requires minimal register resources to store the previous error state, significantly improving the long-term operational reliability of the all-digital underlying hardware.

[0183] In an exemplary embodiment, the derivation and transformation of the above local RTC state update equation includes:

[0184] Macroscopic frequency ratio With phase adjustment amount This is an overall metric calculated only once every synchronization cycle (e.g., 1 second). The FPGA's underlying local time (RTC), however, is calculated as... The physical clock, every An additive update is required.

[0185] The derivation process of the local RTC state update equation is as follows:

[0186] Step 1, establish the "ideal physical step size" for a single clock tick: Ideally, in order to ensure that the local clock rate is completely consistent with the master clock, the local RTC counter cannot increase the nominal time at a fixed time with each rising edge of the clock. (like Instead, a frequency ratio should be added. The revised "ideal step size". Let the ideal step size be... Then we have:

[0187] ;

[0188] For example, if the master clock is faster than the local clock, calculate Ideally, then each local clock tick should be... Instead .

[0189] Step 2, stripping away the base step size and extracting the "frequency feedforward micro-compensation": In the actual hardware logic of the FPGA, to reduce the complexity of the adder, the RTC counter is designed as a dual-channel architecture of "reference accumulation + dynamic throughput". The reference accumulation channel unconditionally adds a fixed amount in each clock cycle. .

[0190] Since the baseline channel has already been increased by "1 copy" Therefore, the additional micro-compensation required for the dynamic compensation channel is equal to the "ideal step size" minus the "already added nominal step size":

[0191]

[0192] This is in the formula The physical source of this is the extremely small amount of time that needs to be inserted (or subtracted) within a single clock cycle solely to overcome the crystal oscillator frequency deviation.

[0193] Step 3: Superimpose the "closed-loop phase micro-compensation amount" to form the final control word. In addition to the frequency feedforward compensation mentioned above, the system also needs to absorb the macroscopic absolute phase error adjustment calculated by the PI controller. .

[0194] Assume the physical system clock frequency is (like Then, during the synchronization cycle of the two Sync messages... The system went through a total of One clock beat, that is .

[0195] The system needs to adjust the total phase amount. Distributed equally to this Within each beat, the phase compensation amount for a single beat is obtained as follows:

[0196] ;

[0197] Adding the "frequency micro-compensation amount" and the "phase micro-compensation amount" yields the total additional micro-control word required for each system clock cycle. :

[0198] .

[0199] Step 4, High-precision decimal accumulation and overflow judgment: Calculated It is an extremely small fixed-point decimal (typically on the sub-nanosecond scale, such as...). The FPGA's integer adder cannot process decimals within a single clock cycle. Therefore, a high-bit-width decimal accumulator is built internally into the logic. Accumulation is performed on each rising edge of the clock:

[0200] .

[0201] This accumulator acts as a "digital trigger" for pulse throughput. It sets the physical compensation granularity threshold (typically...). and ):

[0202] When the accumulated decimal error reaches When the insertion action is triggered, output: and will minus To eliminate the already compensated amount.

[0203] When the local extra travel time reaches When this occurs, the deduction action is triggered: Output and will Plus .

[0204] In a normal clock cycle that does not reach the overflow threshold, output .

[0205] Step 5: Derive the final RTC state update equation: This involves applying the discrete control sequence generated in real-time by the fractional accumulator. Combined with the baseline accumulation channel, the final, extremely simplified underlying hardware micro-execution formula was derived:

[0206] .

[0207] In one exemplary embodiment, such as Figure 7 As shown, a time synchronization method is provided, taking its application in FPGA as an example. The method includes the following steps:

[0208] Step S301: Receive the RGMII signal from the physical layer chip through the FPGA's RGMII interface, and convert the RGMII signal into a GMII signal;

[0209] Step S302: When the GMII signal matches the preset signal characteristics, the current time of the local clock is latched to obtain a latched timestamp; the local clock is driven by the global clock generated by the crystal oscillator.

[0210] Step S303: Determine the frequency adjustment amount of the local clock based on the latch timestamps of two adjacent synchronization cycles;

[0211] Step S304: Determine the phase adjustment amount of the local clock based on the phase error between two adjacent synchronization cycles;

[0212] Step S305: Adjust the clock beat of the local clock according to the frequency adjustment amount and the phase adjustment amount so that the local clock is synchronized with the master clock.

[0213] Optionally, the FPGA can receive RGMII signals sent by the physical layer chip via the RGMII interface, sample and recover the RGMII signals, and convert them into GMII signals. The FPGA can monitor in real time whether the GMII signals match preset signal characteristics. When a match is detected, the FPGA reads the current time from the local clock, latches the current time into a register, and obtains a latched timestamp. The FPGA can then use the latched timestamps from two adjacent synchronization cycles... The frequency ratio between the master and slave clocks is determined, and the frequency adjustment amount of the local clock is obtained based on the frequency ratio. Alternatively, based on the incremental discrete proportional-integral control law, the phase adjustment increment between two adjacent synchronization cycles is determined according to the phase error between two adjacent synchronization cycles. Based on the phase adjustment increment, the phase adjustment amount of the local clock in the current synchronization cycle is determined. Combining the frequency adjustment amount and the phase adjustment amount, the FPGA can insert or subtract pulses in the clock beat of the local clock to adjust the clock pulse and synchronize the local clock with the master clock.

[0214] The aforementioned time synchronization method enables the FPGA to complete RGMII signal conversion and feature matching at the RGMII physical interface layer and directly latch the timestamp based on the local clock, avoiding random delay jitter introduced by the operating system network driver layer or protocol stack, eliminating the nondeterministic error in the timestamp capture stage, thereby improving the accuracy of time synchronization.

[0215] In one exemplary embodiment, a time synchronization system is provided, including a crystal oscillator, a physical layer chip, and an FPGA, wherein the FPGA communicates with the physical layer chip via an RGMII interface; wherein:

[0216] A crystal oscillator is used to generate a global clock; the global clock is used to drive the local clock of the FPGA.

[0217] The physical layer chip is used to transmit RGMII signals to the FPGA via the RGMII interface.

[0218] The FPGA is used to convert the RGMII signal received through the RGMII interface into a GMII signal. When the GMII signal matches the preset signal characteristics, the current time of the local clock is latched to obtain a latched timestamp. Based on the latched timestamp, the local clock is synchronized.

[0219] Optionally, a crystal oscillator can be deployed in the external hardware environment of the FPGA to provide a reference clock input. This reference clock can be multiplied by the FPGA's internal logic circuitry to generate a global clock. This global clock can then drive the local clock, generating a high-precision local time in real time. The physical layer chip sends an RGMII signal to the FPGA via the RGMII interface. After receiving the RGMII signal, the FPGA samples and recovers it, converting it into a GMII signal. The FPGA can monitor in real time whether the GMII signal matches a preset signal characteristic. When a match is detected, the FPGA reads the current time from the local clock, latches it in a register, and obtains a latched timestamp. The FPGA can then use the latched timestamps from two adjacent synchronization cycles... The frequency ratio between the master and slave clocks is determined, and the frequency adjustment amount of the local clock is obtained based on the frequency ratio. Alternatively, based on the incremental discrete proportional-integral control law, the phase adjustment increment between two adjacent synchronization cycles is determined according to the phase error between two adjacent synchronization cycles. Based on the phase adjustment increment, the phase adjustment amount of the local clock in the current synchronization cycle is determined. Combining the frequency adjustment amount and the phase adjustment amount, the FPGA can insert or subtract pulses in the clock beat of the local clock to adjust the clock pulse and synchronize the local clock with the master clock.

[0220] The aforementioned time synchronization system enables the FPGA to complete RGMII signal conversion and feature matching at the RGMII physical interface layer, and directly latch the timestamp based on the local clock. This avoids random delay jitter introduced by the operating system network driver layer or protocol stack, eliminates the nondeterministic error in the timestamp capture stage, and thus improves the accuracy of time synchronization.

[0221] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0222] Based on the same inventive concept, this application also provides a time synchronization device for implementing the time synchronization method described above. The solution provided by this device is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more time synchronization device embodiments provided below can be found in the limitations of the time synchronization method described above, and will not be repeated here.

[0223] In one exemplary embodiment, such as Figure 8 As shown, a time synchronization device is provided, including: a signal conversion module 401, a feature matching module 402, and a time synchronization module 403, wherein:

[0224] The signal conversion module 401 is used to receive the RGMII signal from the physical layer chip through the RGMII interface of the FPGA and convert the RGMII signal into a GMII signal.

[0225] The feature matching module 402 is used to latch the current time of the local clock to obtain a latched timestamp when the GMII signal matches a preset signal feature; the local clock is driven by a global clock generated by a crystal oscillator.

[0226] The time synchronization module 403 is used to synchronize the local clock according to the latched timestamp.

[0227] In an exemplary embodiment, the feature matching module 402 is further configured to start the byte counter of the FPGA in response to a valid enable signal in the GMII signal; if the GMII signal matches the preset signal feature when the byte counter steps to a preset offset, a trigger pulse is generated; the preset signal feature includes a preset Ethernet type identifier; in response to the trigger pulse, the current time from the local clock is latched in the latch register of the FPGA to obtain the latched timestamp.

[0228] In an exemplary embodiment, the time synchronization module 403 is further configured to determine the frequency adjustment amount of the local clock based on the latch timestamps of two adjacent synchronization cycles; determine the phase adjustment amount of the local clock based on the phase error of the two adjacent synchronization cycles; and adjust the clock beat of the local clock based on the frequency adjustment amount and the phase adjustment amount so that the local clock is synchronized with the master clock.

[0229] In an exemplary embodiment, the time synchronization module 403 is further configured to determine a timestamp increment based on the latched timestamps of the two adjacent synchronization cycles; the timestamp increment includes the master timestamp increment of the master clock and the local timestamp increment of the local clock; based on the master timestamp increment and the local timestamp increment, the frequency ratio of the master clock relative to the local clock is obtained; based on the frequency ratio, the frequency adjustment amount of the local clock is obtained.

[0230] In an exemplary embodiment, the time synchronization module 403 is further configured to perform proportional-integral processing based on the phase error of the two adjacent synchronization cycles to obtain the phase adjustment increment of the second synchronization cycle relative to the first synchronization cycle; the two adjacent synchronization cycles include the first synchronization cycle and the second synchronization cycle, and the first synchronization cycle is earlier than the second synchronization cycle; the phase adjustment amount of the second synchronization cycle is obtained according to the phase adjustment increment and the phase adjustment amount of the first synchronization cycle; the phase adjustment amount of the local clock is obtained according to the phase adjustment amount of the second synchronization cycle.

[0231] In an exemplary embodiment, the time synchronization module 403 is further configured to determine the pulse throughput control word corresponding to the clock beat based on the frequency adjustment amount and the phase adjustment amount; and to insert or subtract pulses from the clock beat based on the pulse throughput control word.

[0232] The modules in the aforementioned time synchronization device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0233] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 9As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a time synchronization method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0234] Those skilled in the art will understand that Figure 9 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0235] In one exemplary embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0236] In one exemplary embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above-described method embodiments.

[0237] In one exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0238] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0239] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0240] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0241] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A time synchronization method, characterized in that, Applied to FPGA, the method includes: The FPGA receives RGMII signals from the physical layer chip via its RGMII interface and converts these RGMII signals into GMII signals. When the GMII signal matches the preset signal characteristics, the current time of the local clock is latched to obtain a latched timestamp; the local clock is driven by a global clock generated by a crystal oscillator. The local clock is synchronized based on the latched timestamp.

2. The method according to claim 1, characterized in that, When the GMII signal matches a preset signal characteristic, the current time of the local clock is latched to obtain a latched timestamp, including: In response to the valid enable signal in the GMII signal, the byte counter of the FPGA is started; When the byte counter steps to a preset offset, if the GMII signal matches the preset signal feature, a trigger pulse is generated; the preset signal feature includes a preset Ethernet type identifier. In response to the trigger pulse, the current time from the local clock is latched in the latch register of the FPGA to obtain the latched timestamp.

3. The method according to claim 1, characterized in that, The step of synchronizing the local clock according to the latched timestamp includes: The frequency adjustment amount of the local clock is determined based on the latch timestamps of two adjacent synchronization cycles; The phase adjustment amount of the local clock is determined based on the phase error between the two adjacent synchronization cycles. The clock beat of the local clock is adjusted according to the frequency adjustment amount and the phase adjustment amount so that the local clock is synchronized with the master clock.

4. The method according to claim 3, characterized in that, The step of determining the frequency adjustment amount of the local clock based on the latch timestamps of two adjacent synchronization cycles includes: The timestamp increment is determined based on the latch timestamps of the two adjacent synchronization cycles; the timestamp increment includes the master timestamp increment of the master clock and the local timestamp increment of the local clock. The frequency ratio of the master clock relative to the local clock is obtained based on the master timestamp increment and the local timestamp increment. The frequency adjustment amount of the local clock is obtained based on the frequency ratio.

5. The method according to claim 3, characterized in that, Determining the phase adjustment amount of the local clock based on the phase error between two adjacent synchronization cycles includes: The phase error between the two adjacent synchronization cycles is used for proportional-integral processing to obtain the phase adjustment increment of the second synchronization cycle relative to the first synchronization cycle; the two adjacent synchronization cycles include the first synchronization cycle and the second synchronization cycle, and the first synchronization cycle is earlier than the second synchronization cycle. The phase adjustment amount of the second synchronization period is obtained based on the phase adjustment increment and the phase adjustment amount of the first synchronization period; The phase adjustment amount of the local clock is obtained based on the phase adjustment amount of the second synchronization period.

6. The method according to claim 3, characterized in that, The step of adjusting the clock beat of the local clock according to the frequency adjustment amount and the phase adjustment amount includes: Based on the frequency adjustment amount and the phase adjustment amount, determine the pulse throughput control word corresponding to the clock tick; According to the pulse throughput control word, pulses are inserted or subtracted from the clock beat.

7. A time synchronization system, characterized in that, The system includes a crystal oscillator, a physical layer chip, and an FPGA, wherein the FPGA communicates with the physical layer chip via an RGMII interface; The crystal oscillator is used to generate a global clock; the global clock is used to drive the local clock of the FPGA. The physical layer chip is used to transmit RGMII signals to the FPGA through the RGMII interface; The FPGA is used to convert the RGMII signal received through the RGMII interface into a GMII signal. When the GMII signal matches a preset signal characteristic, the FPGA latches the current time of the local clock to obtain a latched timestamp and synchronizes the local clock according to the latched timestamp.

8. A time synchronization device, characterized in that, The device, applied to an FPGA, includes: The signal conversion module is used to receive RGMII signals from the physical layer chip through the RGMII interface of the FPGA and convert the RGMII signals into GMII signals. The feature matching module is used to latch the current time of the local clock to obtain a latched timestamp when the GMII signal matches a preset signal feature; the local clock is driven by a global clock generated by a crystal oscillator. The time synchronization module is used to synchronize the local clock according to the latched timestamp.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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