Audio chip testing device and audio chip testing method

Abstract

The embodiment of the invention provides an audio chip testing device and an audio chip testing method. The audio chip testing device comprises a receiving module, a driving module, a control module and a storage module, the receiving module is used for receiving radio frequency data; the audio chip to be tested is used for processing the radio frequency data to obtain intermediate frequency data and audio data, and an audio clock signal corresponding to the audio data corresponds to an intermediate frequency clock signal corresponding to the intermediate frequency data; the driving module is used for driving the playing device to play audio data; the control module is used for receiving intermediate frequency data and audio data sent by the audio chip to be tested, calculating and processing the intermediate frequency data and the audio data to obtain a test result, and storing the audio data and the intermediate frequency data in the memory according to a preset caching strategy which at least comprises three levels of caching strategies, the portable audio chip testing device is provided, and the communication function and the audio data quality of the audio chip to be tested can be tested at any time in different scenes.

Description

An audio chip testing apparatus and a testing method for audio chips. Technical Field

[0001] This application relates to the field of testing technology, and more specifically, to a testing apparatus and a testing method for an audio chip. Background Technology

[0002] With the continuous development of communication technology, wireless communication technology is being applied in more and more scenarios, such as Bluetooth headsets, Bluetooth speakers, voice interaction devices in car audio systems, and wireless microphones. These wireless audio chips support wireless communication protocols and integrate digital signal processing modules to achieve functions such as wireless audio transmission, audio encoding and decoding, and noise reduction. Before using a wireless audio chip, it needs to be tested by connecting it to a test device to test its various functions. However, in some scenarios, if testing of a wireless audio chip is required, it is not possible to move the test device to the actual scene, which causes inconvenience to the testing of the wireless audio chip. Summary of the Invention

[0003] The purpose of some embodiments of this application is to provide a testing device and a testing method for an audio chip. Through the technical solutions of the embodiments of this application, an audio chip testing device is provided, including a receiving module, a driving module, a control module, and a storage module, wherein: the receiving module, the driving module, and the control module are respectively connected to the audio chip under test; the receiving module is used to receive radio frequency data; the audio chip under test is used to process the radio frequency data to obtain intermediate frequency data and audio data, and the audio clock signal corresponding to the audio data corresponds to the intermediate frequency clock signal corresponding to the intermediate frequency data; the driving module is used to drive a playback device to play the audio data; the control module is used to... The device receives intermediate frequency (IF) data and audio data sent by the audio chip under test, performs calculations and processing on the IF data and audio data to obtain test results corresponding to the audio chip under test, and stores the audio data and IF data in a memory according to a preset caching strategy. The preset caching strategy includes at least a three-level caching strategy, which provides a portable audio chip testing device that can test the communication function and audio data quality of the audio chip under test at any time in different scenarios and store the test results. It realizes the functions of audio chip control, data acquisition, calculation and storage, and can complete the configuration and data acquisition of wireless audio chips without additional testing equipment.

[0004] In a first aspect, some embodiments of this application provide a testing device for an audio chip, comprising: a receiving module, a driving module, a control module, and a storage module, wherein: the receiving module, the driving module, and the control module are respectively connected to the audio chip under test; the receiving module is used to receive radio frequency data; the audio chip under test is used to process the radio frequency data to obtain intermediate frequency data and audio data, and the audio clock signal corresponding to the audio data corresponds to the intermediate frequency clock signal corresponding to the intermediate frequency data; the driving module is used to drive a playback device to play the audio data; the control module is used to receive the intermediate frequency data and audio data sent by the audio chip under test, and to calculate and process the intermediate frequency data and the audio data to obtain a test result corresponding to the audio chip under test, and to store the audio data and the intermediate frequency data in a memory according to a preset caching strategy, wherein the preset caching strategy includes at least a three-level caching strategy.

[0005] Some embodiments of this application provide a portable audio chip testing device that can test the communication function and audio data quality of the audio chip under test at any time in different scenarios, and store the test results. This realizes the functions of audio chip control, data acquisition, calculation and storage, and can complete the configuration and data acquisition of wireless audio chips without additional testing equipment.

[0006] Optionally, the three-level caching strategy in the preset caching strategy includes at least a first caching strategy, a second caching strategy, and a third caching strategy, wherein: the first caching strategy is used to convert the asynchronous intermediate frequency data and audio data into synchronous intermediate frequency data and audio data; the second caching strategy is used to determine the synchronous intermediate frequency data and audio data within a preset time period and cache them in a first storage space; the third caching strategy is used to store the synchronous intermediate frequency data and audio data within the preset time period in a second storage space in the memory.

[0007] Some embodiments of this application first implement asynchronous data transmission of intermediate frequency data and audio data to the clock domain of the hard core MCU according to the first caching strategy through the control module, and then control the audio data and intermediate frequency data to read data according to the second caching strategy and write data to the non-volatile storage device according to the third caching strategy.

[0008] Optionally, the capacity of the first storage space corresponding to the second caching strategy is determined based on the data throughput, the operating frequency of the control module, and the interrupt frequency.

[0009] Some embodiments of this application need to take into account factors such as data throughput, hard-core MCU operating frequency, and hard-core MCU interrupt frequency. Excessive capacity will lead to an increase in system size, power consumption, and cost.

[0010] Optionally, the third caching strategy is used to store the synchronized intermediate frequency data and audio data within the preset time period into a circular queue in the second storage space.

[0011] In some embodiments of this application, the third caching strategy is allocated using static addresses, thereby avoiding additional stack management overhead and facilitating queue pointer management. This fully utilizes the circular queue space, simplifies queue capacity calculation, and optimizes the write speed of non-volatile storage devices. Optionally, the capacity of the second storage space is determined based on the data throughput, the operating frequency of the control module, the interrupt frequency of the control module, the DDR operating frequency, and the parameters of the non-volatile storage devices.

[0012] In some embodiments of this application, the selection of external DDR chips and circular queue depth needs to take into account factors such as data throughput, hard core MCU operating frequency, hard core MCU interrupt frequency, DDR operating frequency, and non-volatile memory device parameters. Excessive capacity will lead to an increase in system size, power consumption, and cost.

[0013] Optionally, the receiving module includes at least an antenna, an analog circuit, and a first wireless communication interface, wherein the receiving module is used to connect the first wireless communication interface to the second wireless communication interface of the audio chip under test.

[0014] In some embodiments of this application, the receiving module includes an antenna and analog circuitry for connecting radio electromagnetic signals to a wireless audio chip interface.

[0015] Optionally, the testing device further includes a touch module and a display module, which are respectively connected to the control module; the touch module is used to receive user input commands; and the display module is used to display the status information of the audio chip under test, the test results of the testing device, and the latitude and longitude information.

[0016] Some embodiments of this application use the UART interface protocol to connect to a touch module, which implements human-computer interaction functions and displays system power supply mode, temperature, date and time, status information of each module, etc., and receives user configuration of the system through touch interaction.

[0017] Optionally, the testing device further includes a geolocation module, which is connected to the control module via the IIC interface protocol. The geolocation module is used to acquire latitude and longitude information. The control module is also used to determine the motion trajectory of the audio chip under test based on the latitude and longitude information, perform data analysis on the motion trajectory to obtain the spatiotemporal information of the audio chip under test, and determine the corresponding velocity and acceleration based on the spatiotemporal information. The spatiotemporal information, the velocity, and the acceleration are used to determine the adaptability of the audio chip under test to motion behavior.

[0018] Some embodiments of this application can reflect the spatiotemporal conditions of intermediate frequency data and audio data acquisition of wireless audio chips through non-real-time computer data analysis. The obtained information such as velocity and acceleration can be used to evaluate the adaptability of wireless audio chips to non-ideal factors such as Doppler frequency shift. The three-dimensional spatial environment information obtained by combining with the map database can be used to evaluate the adaptability of wireless audio chips to non-ideal factors such as fading.

[0019] Secondly, some embodiments of this application provide a testing method for an audio chip, applied to a testing apparatus for any of the audio chips described in the first aspect. The method includes: receiving radio frequency (RF) data; processing the RF data using an audio chip under test to obtain intermediate frequency (IF) data and audio data, wherein the audio clock signal corresponding to the audio data corresponds to the IF clock signal corresponding to the IF data; receiving the IF data and audio data sent by the audio chip under test, and calculating and processing the IF data and audio data to obtain a test result corresponding to the audio chip under test; storing the audio data and the IF data in a memory according to a preset caching strategy, wherein the preset caching strategy includes at least a three-level caching strategy.

[0020] Optionally, the three-level caching strategy in the preset caching strategy includes at least a first caching strategy, a second caching strategy, and a third caching strategy, wherein: the first caching strategy is used to convert the asynchronous intermediate frequency data and audio data into synchronous intermediate frequency data and audio data; the second caching strategy is used to determine the synchronous intermediate frequency data and audio data within a preset time period and cache them in a first storage space; the third caching strategy is used to store the synchronous intermediate frequency data and audio data within the preset time period in a second storage space in the memory. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of some embodiments of this application, the accompanying drawings used in some embodiments of this application will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 is a structural block diagram of an audio chip testing device provided in an embodiment of this application; Figure 2 is a structural block diagram of an audio chip testing device provided in an embodiment of this application; Figure 3 is a schematic diagram of a caching process provided in an embodiment of this application; Figure 4 is a schematic diagram of a third-level cache circular queue provided in an embodiment of this application; Figure 5 is a schematic diagram of the connection between the auxiliary function module and the main control module provided in an embodiment of this application. Detailed Implementation

[0023] The technical solutions of some embodiments of this application will now be described with reference to the accompanying drawings.

[0024] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0025] Glossary: ​​ADC: Analog-to-digital Converter; DAC: Digital-to-analog Converter; MCU: Micro-controller Unit; FPGA: Field-Programmable Gate Array; MPSOC: Multi-Processor System-on-Chip; RTC: Real-Time Clock; GNSS: Global Navigation Satellite System; GPIO: General-Purpose Input / Output; UART: Universal Asynchronous Receiver / Transmitter; IIC: Inter-Integrated Circuit; DDR: Double Data Rate SDRAM; SDIO: Secure Digital Input / Output; QSPI FLASH: Quad Serial Peripheral Interface Flash; FIFO: First In First Out: First-in, first-out; MB: Megabyte; GB: Gigabyte; EXFAT: Extended File Allocation Table File System; UTC: Coordinated Universal Time; PWM: Pulse Width Modulation.With the continuous development of communication technology, the application scenarios of wireless communication technology are also increasing. Examples include Bluetooth headsets, Bluetooth speakers, voice interaction devices in car audio systems, and wireless microphones. These wireless audio chips support wireless communication protocols and integrate digital signal processing modules, enabling functions such as wireless audio transmission, audio encoding / decoding, and noise reduction. Before use, wireless audio chips need to be tested, specifically their wireless communication and audio processing sections. The wireless communication section is susceptible to interference from environmental electromagnetic signals, electronic devices, and other wireless communication signals, leading to inaccurate analysis of the intermediate frequency signal. The audio processing section is affected by the wireless communication section, as well as the audio signal, DAC, audio analog circuit, and the sound-generating unit. Therefore, pre-testing is necessary before use. The specific testing process involves connecting the wireless audio chip to a test device and testing its wireless communication and audio processing sections. However, in some scenarios, it is impossible to bring the test device to the actual environment, causing inconvenience. Therefore, some embodiments of this application provide an audio... A testing device for an audio chip includes a receiving module, a driving module, a control module, and a storage module. The receiving module, driving module, and control module are respectively connected to the audio chip under test. The receiving module receives radio frequency (RF) data. The audio chip under test processes the RF data to obtain intermediate frequency (IF) data and audio data, with the audio clock signal corresponding to the audio data and the IF clock signal corresponding to the IF data corresponding to the IF data. The driving module drives a playback device to play the audio data. The control module receives the IF data and audio data sent by the audio chip under test, calculates and processes the IF data and audio data to obtain test results corresponding to the audio chip under test, and stores the audio data and IF data in a memory according to a preset caching strategy. The preset caching strategy includes at least a three-level caching strategy. This provides a portable audio chip testing device that can test the communication function and audio data quality of the audio chip under test at any time in different scenarios and store the test results. It realizes the functions of audio chip control, data acquisition, calculation, and storage, and can complete the configuration and data acquisition of wireless audio chips without additional testing equipment.

[0026] As shown in Figure 1, an embodiment of this application provides a testing device for an audio chip, including: a receiving module 101, a driving module 102, a control module 103, and a storage module 104, wherein: the receiving module 101, the driving module 102, and the control module 103 are respectively connected to an audio chip 105 under test; the receiving module 101 is used to receive radio frequency data; the audio chip 105 under test is used to process the radio frequency data to obtain intermediate frequency data and audio data, and the audio clock signal corresponding to the audio data corresponds to the intermediate frequency clock signal corresponding to the intermediate frequency data; the driving module 102 is used to drive a playback device to play the audio data; the control module 103 is used to receive the intermediate frequency data and audio data sent by the audio chip under test, and to calculate and process the intermediate frequency data and the audio data to obtain a test result corresponding to the audio chip under test, and to store the audio data in the storage module 104 according to a preset caching strategy, wherein the preset caching strategy includes at least a three-level caching strategy.

[0027] Specifically, this application provides a testing device for an audio chip, including a receiving module 101, a driving module 102, a control module 103, and a storage module 104. In situations where a testing environment cannot be provided, if it is necessary to test an audio chip, the audio chip to be tested needs to be installed in the audio chip testing device. When the audio chip testing device is powered on, the receiving module receives radio frequency data transmitted over the air, and then processes the radio frequency data through the audio chip to obtain intermediate frequency data and audio data. The audio clock signal corresponding to the audio data corresponds to the intermediate frequency clock signal corresponding to the intermediate frequency data. After the audio chip to be tested processes the received radio frequency data, it obtains intermediate frequency data and audio data, and sends the obtained intermediate frequency data and audio data to the control module. The control module calculates and processes the received intermediate frequency data and audio data, and caches the obtained audio data and intermediate frequency data in the storage module using a preset caching strategy. In this way, a portable testing device can be used to test the audio chip in any environment.

[0028] Some embodiments of this application provide a portable audio chip testing device that can test the communication function and audio data quality of the audio chip under test at any time in different scenarios, and store the test results. This realizes the functions of audio chip control, data acquisition, calculation and storage, and can complete the configuration and data acquisition of wireless audio chips without additional testing equipment.

[0029] This application provides a portable wireless audio chip control, data acquisition, calculation, and storage device, providing data support for the testing and analysis of wireless audio chips, and also presents a verified specific implementation scheme. Using the audio chip testing device provided in this application, the technical difficulties, technical indicators, and effectiveness of improvement measures of the wireless communication section and audio processing section can be effectively evaluated during the chip design, hardware design, and software design processes of wireless audio chips.

[0030] This application provides another embodiment to further illustrate the testing apparatus for the audio chip provided in the above embodiments.

[0031] As shown in Figure 2, the test device for the audio chip includes an RF circuit 101, an audio chip under test 105, an audio analog circuit 102, a main control and peripheral circuit 103, a non-volatile memory 104, and an auxiliary function module 106.

[0032] The receiving module 101, i.e., the radio frequency circuit, includes an antenna and analog circuitry, used to connect the radio electromagnetic signal to the wireless audio chip interface; the audio chip under test is a wireless audio chip; the driving module 102, i.e., the audio analog circuit, connects the wireless audio chip interface to the audio output interface, used to drive the sound-generating unit or audio acquisition device, such as connecting to a speaker; the control module 103 is the main control and peripheral circuitry, providing control, data acquisition, calculation, and storage functions, with options including but not limited to MCU, FPGA, and MPSOC; the storage module 104 is a non-volatile storage device, specifically an actual storage device. The storage medium can be selected from, but is not limited to, solid-state drives, flash memory cards, and embedded multimedia cards. The auxiliary function module 105 includes the following components as shown in Figure 5, including but not limited to, an RTC module 107, a touch screen 108, a temperature measurement fan control module 109, a GNSS module 110, a UART input / output module 111, and a power management module 112. Each module is connected to the control module 103, and the RTC module 107 and the GNSS module 110 communicate with the control module 103 via IIC. The touch screen 108 communicates with the control module 103 via UART.

[0033] In this embodiment, an MPSOC (Multiprocessor System-on-a-Chip) is used as the control module. This control module includes an MCU unit and an FPGA unit. The FPGA programmable logic implements functions such as multi-level input / output interfaces, clock generation, wireless audio chip interface protocol parsing, asynchronous data transmission, data buffering, hardware computing units, hardware interrupts, and hardware GPIO. On the other hand, a hard-core MCU implements functions such as multi-channel UART communication, multi-channel IIC communication, DDR communication, SDIO communication, and QSPI FLASH communication, while also providing certain control, computing, and data analysis capabilities. Therefore, this embodiment uses an MPSOC as the main controller, allowing a single chip to simultaneously possess FPGA programmable logic hardware programming capabilities and hard-core MCU software programming capabilities, meeting the requirements for miniaturization and portability.

[0034] The connection interface between the audio chip under test and the control module includes at least an intermediate frequency (IF) data interface, an audio data interface, and an IIC configuration interface. The IF data interface uses a source clock synchronization method, with the clock corresponding to the IF data provided by the wireless audio chip to adapt to different IF data interface rates under different communication systems and different communication frequency bands.

[0035] The audio data interface uses a source clock synchronization method. The FPGA programmable logic generates the audio data interface clock according to the intermediate frequency data interface clock, which is used to drive the wireless audio chip to output digital audio, thereby ensuring a strict correspondence between the audio data and the intermediate frequency data.

[0036] In this embodiment, FPGA programmable logic is used to implement protocol parsing and data conversion for intermediate frequency data interface and audio data interface, and the converted parallel data enters the buffer section.

[0037] Optionally, the three-level caching strategy in the preset caching strategy includes at least a first caching strategy, a second caching strategy, and a third caching strategy, wherein: the first caching strategy is used to convert the asynchronous intermediate frequency data and audio data into synchronous intermediate frequency data and audio data; the second caching strategy is used to determine the synchronous intermediate frequency data and audio data within a preset time period and cache them in a first storage space; the third caching strategy is used to store the synchronous intermediate frequency data and audio data within the preset time period in a second storage space in the memory.

[0038] As shown in Figure 3, the embodiment of this application uses a three-level cache structure, specifically including: the first cache strategy includes: the first level cache is an asynchronous FIFO implemented by FPGA programmable logic. This FIFO only needs a very small depth (about 1E1 level) to realize the asynchronous data transmission of intermediate frequency data and audio data to the clock domain of the hard core MCU, that is, to turn the asynchronous transmission of audio data and intermediate frequency data into synchronous transmission.

[0039] The second caching strategy is as follows: the second-level cache is a synchronous FIFO implemented by FPGA programmable logic. This FIFO has a large depth (approximately on the order of 1E4) and implements the peripheral bus interface of the hard core MCU. It is used to cache intermediate frequency data and audio data collected within a certain period of time. When the cached data reaches a certain amount, an interrupt is generated, and the hard core MCU reads into the third-level cache. The large depth and interrupt threshold value avoid frequent interruptions of the hard core MCU, freeing up more hard core MCU clock cycles for calculation and control work.

[0040] The setting of the capacity of the second-level buffer FIFO needs to take into account factors such as data throughput, hard-core MCU operating frequency, and hard-core MCU interrupt frequency. Excessive capacity will lead to an increase in system size, power consumption, and cost.

[0041] The third caching strategy is as follows: the third-level cache is a circular queue implemented by an external DDR chip (when the pointer increases from the lowest address to the highest address, it will return to the lowest address again). This circular queue corresponds to a continuous address in the hard-core MCU memory, providing a large cache capacity (approximately 1E2MB). Since the write operation of non-volatile memory devices has access latency, transmission latency, protocol latency, etc., and the relevant latency will further increase as the available space of non-volatile memory devices decreases, while the data throughput of the wireless audio chip is constant, a large cache capacity is required to cache the newly acquired intermediate frequency data and audio data when performing write operations to non-volatile memory devices, so as to ensure the continuity of the two in time, and at the same time, make full use of the available space of non-volatile memory devices.

[0042] The selection of external DDR chips and the depth of the circular queue needs to comprehensively consider factors such as data throughput, the operating frequency of the hard-core MCU, the interrupt frequency of the hard-core MCU, the operating frequency of the DDR, and the parameters of non-volatile memory devices. Excessive capacity will lead to an increase in system size, power consumption, and cost. When the hard-core MCU starts up, the third-level cache is allocated a static address, thereby avoiding additional stack management overhead and providing convenience for queue pointer management.

[0043] As shown in Figure 4, the hard-core MCU software uses read pointers and write pointers to manage the contiguous memory corresponding to the third-level cache. When setting the alignment boundary parameters of the read and write pointers, it is necessary to comprehensively consider the capacity of the second-level cache, the interrupt threshold of the hard-core MCU, and the parameters of non-volatile storage devices, so as to make full use of the circular queue space, simplify the queue capacity calculation, and optimize the write speed of non-volatile storage devices. In addition, the information such as the read and write pointers of the third-level cache can effectively evaluate the overall performance of the three-level cache structure and can intuitively reflect the data throughput bottleneck of the three-level cache structure, so as to optimize the design parameters of the three-level cache structure. As shown in Figure 4, if the read pointer and the write pointer point to the same location in the storage space, it means that the queue of the storage space is empty or full. If the read pointer and the write pointer point to different locations in the storage space, it means that the queue of the storage space is not empty, and audio data and intermediate frequency data can continue to be stored in the circular queue.

[0044] Some embodiments of this application first implement asynchronous data transmission of intermediate frequency data and audio data to the clock domain of the hard core MCU according to the first caching strategy through the control module, and then control the audio data and intermediate frequency data to read data according to the second caching strategy and write data to the non-volatile storage device according to the third caching strategy.

[0045] Optionally, the capacity of the first storage space corresponding to the second caching strategy is determined based on the data throughput, the operating frequency of the control module, and the interrupt frequency.

[0046] Some embodiments of this application need to take into account factors such as data throughput, hard-core MCU operating frequency, and hard-core MCU interrupt frequency. Excessive capacity will lead to an increase in system size, power consumption, and cost.

[0047] Optionally, the third caching strategy is used to store the synchronized intermediate frequency data and audio data within the preset time period into a circular queue in the second storage space.

[0048] In some embodiments of this application, the third caching strategy is allocated using static addresses, thereby avoiding additional stack management overhead and facilitating queue pointer management. This fully utilizes the circular queue space, simplifies queue capacity calculation, and optimizes the write speed of non-volatile storage devices. Optionally, the capacity of the second storage space is determined based on the data throughput, the operating frequency of the control module, the interrupt frequency of the control module, the DDR operating frequency, and the parameters of the non-volatile storage devices.

[0049] In some embodiments of this application, the selection of external DDR chips and circular queue depth needs to take into account factors such as data throughput, hard core MCU operating frequency, hard core MCU interrupt frequency, DDR operating frequency, and non-volatile memory device parameters. Excessive capacity will lead to an increase in the size, power consumption, and cost of the test device.

[0050] Specifically, considering factors such as capacity, read / write speed, size and power consumption, cost, and development cycle, this embodiment uses an ultra-small flash memory card (SDIO interface) as the storage medium, implementing an EXFAT file system within it, allowing direct connection to a computer for data analysis via a card reader or other devices. The collected intermediate frequency data and audio data are not compressed; the log file stores information such as the time of data acquisition, latitude and longitude, and the wireless audio chip's status. The aforementioned three-level cache structure design and its specific parameters are closely related to the storage medium parameters and the wireless audio chip's data rate.

[0051] This application embodiment can automatically adapt to flash memory cards with capacities of 8GB, 16GB, 32GB, 64GB, and 128GB. Taking a single flash memory card with a labeled capacity of 64GB as an example, when the total throughput of intermediate frequency data and audio data of the wireless audio chip is approximately 2.893MB / s, it can meet the continuous acquisition requirements for approximately 5.6 hours. This application embodiment implements flash memory card mounting, formatting, and detection functions for the total and available capacity of the flash memory card. In addition to the write function, it also provides file retrieval and file reading functions.

[0052] Optionally, the receiving module includes at least an antenna, an analog circuit, and a first wireless communication interface, wherein the receiving module is used to connect the first wireless communication interface to the second wireless communication interface of the audio chip under test.

[0053] In some embodiments of this application, the receiving module includes an antenna and analog circuitry for connecting radio electromagnetic signals to a wireless audio chip interface.

[0054] As shown in Figure 5, the auxiliary function module includes an RTC unit 107, a touch screen unit 108, a temperature measurement fan control unit 109, a GNSS unit 110, a UART input / output unit 111, and a power management unit 112. Each unit is connected to the control module 103. The touch screen unit 108 consists of a touch module and a display module, which are connected to the control module. The touch module is used to receive user input commands.

[0055] Specifically, the control module connects to the touch module via a UART interface protocol, enabling human-machine interaction. During user configuration, the touch module displays system power supply mode, temperature, date and time, and status information of each module, receiving user configurations for the test device through touch interaction. Optionally, the test device also includes a display module connected to the control module. The display module displays the status information of the audio chip under test, the test results of the test device, and the latitude and longitude information. During the operation of the test device, the display module displays system status, including the status of the wireless audio chip (such as intermediate frequency signal strength, frequency offset, bandwidth, etc.), progress of writing / reading non-volatile memory devices, date and time, latitude and longitude, and other information.

[0056] Except for the power switch, which is a mechanical switch, all interactions in this application embodiment are completed through the touch module to reduce the system size and improve the system portability. Some embodiments of this application display the system power supply mode, temperature, date and time, status information of each module, etc., and receive user configuration of the system through touch interaction.

[0057] This application implements a hardware interrupter in the FPGA programmable logic to identify and filter the UART transmission of the touch screen module during data acquisition, and generates an interrupt only for specific information, thereby freeing up more hard-core MCU clock cycles for computing and control work.

[0058] This application provides a private instruction set and instruction interaction format, which completes instruction interaction under the premise that the main controller and the touch screen communicate asynchronously using the UART interface protocol. The instruction set consists of frame header, instruction, payload length, data payload, frame tail, etc., and the instruction interaction has functions such as request, response, and status indication.

[0059] Some embodiments of this application use the UART interface protocol to connect to a touch module, which implements human-computer interaction functions.

[0060] In this embodiment, the control module is connected to the RTC unit 107 using the IIC interface protocol. The RTC unit 107 provides UTC (Coordinated Universal Time) to record the acquisition time information of intermediate frequency data and audio data in a log file stored in a non-volatile storage device, thereby providing time information for computer non-real-time data analysis.

[0061] Optionally, the testing device further includes a geographic location module, namely a GNSS unit 110, which is connected to the control module 103 via the IIC interface protocol and is used to acquire latitude and longitude information.

[0062] Some embodiments of this application use the IIC interface protocol to connect to a geolocation module, which provides latitude and longitude information to record the acquisition location information of intermediate frequency data and audio data in a log file stored in a non-volatile storage device, thereby providing geographic coordinate information for computer non-real-time data analysis.

[0063] Optionally, the control module is further configured to determine the motion trajectory of the audio chip under test based on the latitude and longitude information, perform data analysis on the motion trajectory to obtain the spatiotemporal information of the audio chip under test, and determine the corresponding velocity and acceleration based on the spatiotemporal information. The spatiotemporal information, the velocity, and the acceleration are used to determine the adaptability of the audio chip under test to motion behavior.

[0064] Some embodiments of this application can reflect the spatiotemporal conditions of intermediate frequency data and audio data acquisition of wireless audio chips through non-real-time computer data analysis. The obtained information such as velocity and acceleration can be used to evaluate the adaptability of wireless audio chips to non-ideal factors such as Doppler frequency shift. The three-dimensional spatial environment information obtained by combining with the map database can be used to evaluate the adaptability of wireless audio chips to non-ideal factors such as fading.

[0065] Specifically, in this embodiment of the application, the control module is used to connect to the GNSS unit 110 (geographic location module) using the IIC interface protocol. The GNSS unit provides latitude and longitude information and is used to record the acquisition location information of intermediate frequency data and audio data in a log file stored in a non-volatile storage device, thereby providing geographic coordinate information for computer non-real-time data analysis.

[0066] The time information provided by RTC unit 107 and the latitude and longitude information provided by GNSS unit 110 can jointly reconstruct the displacement trajectory of the system during data acquisition. Through non-real-time data analysis by computer, the spatiotemporal conditions of intermediate frequency data and audio data acquisition of the wireless audio chip can be reflected. The obtained velocity, acceleration and other information can be used to evaluate the adaptability of the wireless audio chip to non-ideal factors such as Doppler frequency shift. The three-dimensional spatial environment information obtained by combining the map database can be used to evaluate the adaptability of the wireless audio chip to non-ideal factors such as fading.

[0067] This application provides a UART input / output unit 111 for lightweight field debugging (not dependent on a specific development environment). It mainly inputs developer debugging instructions not included in the touch screen module and mainly outputs key information of the three-level cache structure during data acquisition and information stored in non-volatile storage device files during data reading.

[0068] The control module 103 uses the hard-core ADC in the FPGA programmable logic to implement temperature measurement and monitor the temperature status of the system itself.

[0069] The main control module (control module) uses a temperature measurement fan control unit 109 to adjust the system fan speed using the monitored temperature information, thereby dynamically adjusting the system's heat dissipation performance. The fan speed control is implemented by hardware GPIO in the FPGA programmable logic. The hard-core MCU is only configured with PWM duty cycle parameters, and the hardware GPIO generates corresponding PWM outputs to drive the fan based on these parameters, thus freeing up more hard-core MCU clock cycles for computation and control.

[0070] The main control (control module) uses the hard-core ADC and hardware GPIO in the FPGA programmable logic to realize power detection and management through the connected power management unit 112. The test device uses three power supply modes: 12V DC, 5V DC and lithium battery to adapt to different acquisition working environments. The hard-core MCU detects the power supply mode and performs power management. The hard-core MCU also detects the battery level and charging insertion. In special scenarios, the hard-core MCU will also perform a power-down on the system.

[0071] The main controller uses a hard-core MCU to implement functions such as system self-test and initialization, user interaction, data acquisition, monitoring and control, and lightweight debugging.

[0072] After power-on, the audio chip testing device will automatically load the program configuration stored in the QSPI FLASH device. The hard-core MCU will automatically complete the self-test and initialization of the testing device, feed back the relevant status information to the touch screen module, and enter the user configuration process.

[0073] During user configuration, the touchscreen module can be used to set the test device to the required working configuration, and then initiate tasks such as data acquisition and lightweight debugging. When the test device is in operation, the hard-core MCU will monitor and control it, feeding back key information during the operation to the touchscreen module. At the same time, it will automatically stop working and enter the user configuration process when an abnormal situation is detected.

[0074] In this embodiment, the MCU controls the reading of data from the second-level cache to the third-level cache and the writing of files from the third-level cache to the non-volatile storage device; the hard-core MCU reads the status information of the wireless audio chip, the time information of the RTC module, and the location information of the GNSS module; the hard-core MCU processes and calculates the intermediate frequency data and audio data stored in the third-level cache to obtain relevant information; the hard-core MCU monitors the system's working status and handles the work of hardware interrupts, hardware GPIO, hard-core ADC, etc.; the hard-core MCU feeds back the relevant information to the touch screen module and writes it to the log file saved in the non-volatile storage device.

[0075] For example, the audio chip testing device provided in this application embodiment can be approximately 170 mm long, 170 mm wide, and 60 mm high. This testing device externalizes the RF antenna and sound-emitting unit, providing relevant interfaces to meet the RF and audio topology requirements of real-world usage scenarios. The device provides three power supply modes: 12V DC, 5V DC, and lithium battery, allowing it to be connected to a power supply system in real-world usage scenarios or to operate using a lithium battery in situations without power.

[0076] This audio chip testing device integrates wireless audio chip control, data acquisition, computation, and storage functions, enabling configuration and data acquisition of the wireless audio chip without the need for additional testing equipment. The device itself can perform certain debugging and data analysis tasks; when connected to a laptop (without relying on a specific development environment), it can further facilitate lightweight on-site debugging. The device completely preserves the strictly corresponding intermediate frequency (IF) and audio data of the wireless audio chip, while also storing spatiotemporal information and important status monitoring information, comprehensively reflecting the relationship between the internal data flow and the external environment during the operation of the wireless audio chip. The storage medium used by the device can be directly connected to a computer for data analysis via a card reader or similar device, without requiring special formats or conversions. With a total throughput of approximately 2.893 MB / s for the wireless audio chip's IF and audio data, the device can meet the continuous acquisition requirements for approximately 5.6 hours using a single 64GB flash memory card, and the flash memory card supports rapid replacement.

[0077] This portable device allows for easy testing of wireless audio chips in real-world scenarios, improving test coverage and effectiveness by introducing non-ideal factors into the electronic system.

[0078] The audio chip testing device provided in this application embodiment can test wireless audio chips, not limited to a single chip, but can be a system composed of multiple chips, or multiple independent chips or systems. The non-volatile storage device described in this solution is not limited to a single device, but can be multiple identical independent devices, or multiple different independent devices. Utilizing the multi-level input / output interface and parallel computing capabilities of FPGA programmable logic, this solution can simultaneously acquire data from multiple wireless audio chips / systems and distribute it to different non-volatile storage devices for storage.

[0079] The main controller type can be replaced accordingly to meet different testing requirements of wireless audio chips. If the wireless audio chip can operate in multiple modes and does not require high-throughput data acquisition, an MCU can be used as the main controller. This eliminates the need for FPGA programmable logic for protocol parsing and data caching; only DDR memory or on-chip storage resources of the MCU are needed for L1 cache. This solution significantly reduces system size, power consumption, and cost, and is suitable for scenarios involving monitoring and storing the long-term operating status of the wireless audio chip. If the wireless audio chip operates in a fixed mode and requires high-throughput data acquisition, an FPGA can be used as the main controller. This eliminates the need for hard-core MCU peripherals and software programming capabilities. The touchscreen module can be simplified to simple interactive devices such as buttons, switches, and indicator lights. Protocol parsing and data caching are implemented using FPGA programmable logic, while hardware algorithm modules can process and save the wireless audio data. The storage medium interface protocol can be implemented using hardware modules. This solution significantly reduces system size, power consumption, and cost, and is suitable for data acquisition and processing scenarios of wireless audio chips with a single configuration.

[0080] For wireless audio chips / systems with high data throughput requirements, non-volatile storage devices can be replaced with high-capacity, high-speed devices such as solid-state drives (SSDs). Taking SSDs as an example, the devices already contain a large-capacity high-speed cache, eliminating the need for DDR to provide a large cache and ensuring the continuity of sampled data. SSD controllers implemented using FPGA programmable logic can be implemented in a point-to-point structure, reducing the overall number of components in the system.

[0081] This application proposes a data storage method using a three-level cache structure plus non-volatile storage devices. In the process of wireless audio chip testing, it balances the requirements of asynchronous data transmission, continuous data caching, and reduced data management overhead. While realizing the relevant functions, it minimizes resource consumption and maximizes system performance. It also provides multi-dimensional data information for wireless audio chip data acquisition through auxiliary function modules.

[0082] Some embodiments of this application provide a testing method for an audio chip, applied to the aforementioned audio chip testing apparatus. The method includes: receiving radio frequency (RF) data; processing the RF data using the audio chip under test to obtain intermediate frequency (IF) data and audio data, wherein the audio clock signal corresponding to the audio data corresponds to the IF clock signal corresponding to the IF data; receiving the IF data and audio data sent by the audio chip under test, and calculating and processing the IF data and audio data to obtain a test result corresponding to the audio chip under test; and storing the audio data and IF data in a memory according to a preset caching strategy, wherein the preset caching strategy includes at least a three-level caching strategy.

[0083] Optionally, the three-level caching strategy in the preset caching strategy includes at least a first caching strategy, a second caching strategy, and a third caching strategy, wherein: the first caching strategy is used to convert the asynchronous intermediate frequency data and audio data into synchronous intermediate frequency data and audio data; the second caching strategy is used to determine the synchronous intermediate frequency data and audio data within a preset time period and cache them in a first storage space; the third caching strategy is used to store the synchronous intermediate frequency data and audio data within the preset time period in a second storage space in the memory.

[0084] Some embodiments of this application provide a testing device for an audio chip, comprising a receiving module, a driving module, a control module, and a storage module, wherein: the receiving module, the driving module, and the control module are respectively connected to the audio chip under test; the receiving module is used to receive radio frequency data; the audio chip under test is used to process the radio frequency data to obtain intermediate frequency data and audio data, and the audio clock signal corresponding to the audio data corresponds to the intermediate frequency clock signal corresponding to the intermediate frequency data; the driving module is used to drive a playback device to play the audio data; the control module is used to receive the intermediate frequency data and audio data sent by the audio chip under test, and to calculate and process the intermediate frequency data and audio data to obtain a test result corresponding to the audio chip under test, and to store the audio data and intermediate frequency data in a memory according to a preset caching strategy, wherein the preset caching strategy includes at least a three-level caching strategy, that is, to provide a portable audio chip testing device that can test the communication function and audio data quality of the audio chip under test at any time in different scenarios, and store the test results, realizing the functions of audio chip control, data acquisition, calculation, and storage, and completing the configuration and data acquisition of wireless audio chips without additional testing equipment.

[0085] It should be noted that each of the implementable methods in this embodiment can be implemented individually or in any combination without conflict. This application does not limit this.

[0086] The above are merely embodiments of this application and are not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0087] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0088] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A testing device for an audio chip, characterized in that, The device includes a receiving module, a driving module, a control module, and a storage module, wherein: the receiving module, the driving module, and the control module are respectively connected to the audio chip under test; the receiving module is used to receive radio frequency data; the audio chip under test is used to process the radio frequency data to obtain intermediate frequency data and audio data, and the audio clock signal corresponding to the audio data corresponds to the intermediate frequency clock signal corresponding to the intermediate frequency data; the driving module is used to drive a playback device to play the audio data; the control module is used to receive the intermediate frequency data and audio data sent by the audio chip under test, and to calculate and process the intermediate frequency data and audio data to obtain a test result corresponding to the audio chip under test, and to store the audio data and intermediate frequency data in the storage according to a preset caching strategy, wherein the preset caching strategy includes at least a three-level caching strategy.

2. The testing apparatus for the audio chip according to claim 1, characterized in that, The three-level caching strategy in the preset caching strategy includes at least a first caching strategy, a second caching strategy, and a third caching strategy, wherein: the first caching strategy is used to convert asynchronous intermediate frequency (IF) data and audio data into synchronous IF data and audio data; the second caching strategy is used to determine the synchronous IF data and audio data within a preset time period and cache them in a first storage space; the third caching strategy is used to store the synchronous IF data and audio data within the preset time period in a second storage space in the memory.

3. The testing apparatus for the audio chip according to claim 2, characterized in that, The capacity of the first storage space corresponding to the second caching strategy is determined based on the data throughput, the operating frequency of the control module, and the interrupt frequency.

4. The testing apparatus for an audio chip according to claim 2, characterized in that, The third caching strategy is used to store the synchronized intermediate frequency data and audio data within the preset time period into a circular queue in the second storage space.

5. The testing apparatus for an audio chip according to claim 4, characterized in that, The capacity of the second storage space is determined based on the data throughput, the operating frequency of the control module, the interrupt frequency of the control module, the DDR operating frequency, and the parameters of the non-volatile storage devices.

6. The testing apparatus for an audio chip according to claim 2, characterized in that, The receiving module includes at least an antenna, an analog circuit, and a first wireless communication interface. The receiving module is used to connect the first wireless communication interface to the second wireless communication interface of the audio chip under test.

7. The testing apparatus for an audio chip according to claim 1, characterized in that, The testing device further includes a touch module and a display module, which are respectively connected to the control module. The touch module is used to receive user input commands, and the display module is used to display the status information of the audio chip under test, the test results of the testing device, and latitude and longitude information.

8. The testing apparatus for an audio chip according to claim 1, characterized in that, The testing device further includes a geolocation module, which is connected to the control module via the IIC interface protocol. The geolocation module is used to acquire latitude and longitude information. The control module is also used to determine the motion trajectory of the audio chip under test based on the latitude and longitude information, perform data analysis on the motion trajectory to obtain the spatiotemporal information of the audio chip under test, and determine the corresponding velocity and acceleration based on the spatiotemporal information. The spatiotemporal information, the velocity, and the acceleration are used to determine the adaptability of the audio chip under test to motion behavior.

9. A testing method for an audio chip, characterized in that, A testing apparatus for an audio chip as described in any one of claims 1-8, the method comprising: receiving radio frequency (RF) data; processing the RF data using an audio chip under test to obtain intermediate frequency (IF) data and audio data, wherein the audio clock signal corresponding to the audio data corresponds to the IF clock signal corresponding to the IF data; receiving the IF data and audio data sent by the audio chip under test, and calculating and processing the IF data and audio data to obtain a test result corresponding to the audio chip under test; and storing the audio data and the IF data in a memory according to a preset caching strategy, wherein the preset caching strategy includes at least a three-level caching strategy.

10. The method according to claim 9, characterized in that, The three-level caching strategy in the preset caching strategy includes at least a first caching strategy, a second caching strategy, and a third caching strategy, wherein: the first caching strategy is used to convert asynchronous intermediate frequency (IF) data and audio data into synchronous IF data and audio data; the second caching strategy is used to determine the synchronous IF data and audio data within a preset time period and cache them in a first storage space; the third caching strategy is used to store the synchronous IF data and audio data within the preset time period in a second storage space in the memory.

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