Preparation method of PZT loudspeaker based on back guide structure

Abstract

The invention belongs to the technical field of MEMS loudspeakers, and particularly relates to a preparation method of a PZT loudspeaker based on a back guide structure. Comprising the steps that a bottom electrode metal film and a PZT piezoelectric film are sequentially sputtered on the front face of a device at high temperature through a magnetron sputtering PVD technology; performing a bottom electrode layer structure photoetching process; performing a top electrode layer photoetching process; performing an upper and lower electrode isolation layer photoetching process, performing a front surface back guide hole structure photoetching process, and etching a top silicon layer of the SOI substrate material sheet through ICP (Inductively Coupled Plasma) to form a device back guide hole structure; depositing a Parylene protection material on the front side by a vacuum vapor deposition process; and performing a back photoetching process, and etching the back of the SOI substrate material sheet through ICP (Inductively Coupled Plasma) to form a device diaphragm cavity structure. According to the invention, the air circulation resistance of the rear cavity can be accurately controlled, the quality-spring property of the diaphragm can be matched, the rigidity and damping of the diaphragm can be balanced, the resonance peak can be effectively reduced, the low-frequency response bandwidth can be expanded, and the SPL can be improved.

Description

Technical Field

[0001] This invention belongs to the field of MEMS loudspeaker technology, and specifically relates to a method for fabricating a PZT loudspeaker based on a back-conducting structure. Background Technology

[0002] MEMS loudspeakers are divided into two types: piezoelectric and capacitive. The core principle of piezoelectric loudspeakers is that the piezoelectric material undergoes mechanical deformation under an alternating electric field, driving a silicon diaphragm to vibrate and produce sound. They are commonly used in consumer electronics, medical equipment, automotive electronics, industrial and internet applications, military noise-canceling headphones, and underwater acoustic communication miniature transducers. The core principle of electrostatic loudspeakers is that a fixed backplate and a movable conductive diaphragm form a variable capacitor; electrostatic force drives the diaphragm to vibrate and produce sound. They are commonly used in professional audio, consumer electronics, medical, and industrial fields.

[0003] Piezoelectric PZT loudspeakers are devices based on microelectromechanical systems (MEMS) technology. Their core advantages include ultra-thin miniaturization, low power consumption, easy driving, strong anti-electromagnetic interference capability, no magnetic leakage, high reliability, and long lifespan. They perform well in mid-to-high frequency response and are widely used in scenarios such as voice broadcasting, alarm prompts, high-frequency sound effect reproduction, automotive audio, medical hearing aids, and aerospace. However, traditional piezoelectric loudspeakers have problems such as difficulty in accurately controlling the air damping and leakage on the back of the diaphragm, weak low-frequency SPL, harmonic distortion, and diaphragm rupture due to heat accumulation and mechanical stress during diaphragm vibration. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing a PZT loudspeaker based on a back-conducting structure. This invention addresses the problems of traditional piezoelectric loudspeakers, such as how to accurately control the air damping and leakage on the back of the diaphragm, weak low-frequency SPL, harmonic distortion, and diaphragm rupture due to heat accumulation and mechanical stress during diaphragm vibration.

[0005] To address the aforementioned technical problems, this invention provides a method for fabricating a PZT loudspeaker based on a back-conducting structure, comprising: Provide a single-layer SOI substrate material sheet, and grow silicon dioxide layers on the front and back sides of the SOI substrate material sheet through LPCVD process in a furnace tube; A bottom electrode metal film and a PZT piezoelectric film are sequentially sputtered at high temperature on the front side of the device using a magnetron sputtering PVD process. A photolithography process for the bottom electrode layer structure is performed by etching the front PZT piezoelectric thin film using ICP, with the etching depth stopping at the surface of the bottom electrode metal thin film to form the bottom electrode structure of the device. The top electrode layer photolithography process is performed, and the top electrode material is deposited on the front side of the device through an evaporation process. Then, the liftoff process is performed to form the top electrode metal. The upper and lower electrode isolation layers are photolithographically processed. The front PZT piezoelectric film and the bottom electrode film are etched sequentially by ICP etching, and the silicon dioxide layer is etched by RIE to form the upper and lower electrode isolation trench structure. The front-side back via structure photolithography process is performed by etching the top silicon layer of the SOI substrate material using ICP etching, with the etching stopping at the surface of the buried oxide layer, to form the device back via structure. Parylene protective material is deposited on the front side using vacuum phase deposition, followed by vacuum annealing to form a device protective layer. Then, photolithography is performed to etch the Parylene protective material using ICP to expose the top electrode metal and form a PAD structure. A back-side photolithography process is performed, in which the back-side silicon dioxide layer, silicon substrate, and buried oxide layer of the SOI substrate material are etched by ICP to form the device diaphragm cavity structure.

[0006] Preferably, the SOI substrate material sheet comprises a silicon substrate, a buried oxide layer, and a top silicon layer disposed sequentially from bottom to top; the thickness of the silicon substrate is not limited, and the crystal orientation is N. <110> The resistivity is 10~60 ohm·cm; the thickness of the top silicon layer is 2~10 μm; and the thickness of the buried oxide layer is 0.2~1 μm.

[0007] Preferably, the material of the bottom electrode metal film is one or more of the conductive metal materials Pt, Au, Al and Cu, the thickness of the bottom electrode metal film is 0.1~0.5μm; the thickness of the PZT piezoelectric film is 1~5μm; and the high-temperature sputtering temperature is 500~700℃.

[0008] Preferably, the pattern of the bottom electrode structure is square, rectangular or circular; in the photolithography process of the bottom electrode layer structure, the ICP etching temperature is 20~80℃, the etching power is 500~1000W, the etching chamber pressure is 4~10mTorr, and the etching rate is 50~150nm / min.

[0009] Preferably, the top electrode material is selected from one or more conductive metal materials Pt, Au and Al, and the thickness of the top electrode metal is 0.1~0.8μm.

[0010] Preferably, in the photolithography process of the upper and lower electrode isolation layers, the selective ratio of the ICP etching system is a fluorine-chlorine mixed etching system with a PZT piezoelectric film:PR photoresist ratio of 3:1, the ICP etching source power is 600~900W, the cavity pressure is 4~7mTorr, and the etching rate is 60~100nm / min; the selective ratio of the RIE etching system is SiO2:Si = 20:1~50:1, the etching power is 200~300W, and the cavity pressure is 10~20mTorr.

[0011] Preferably, the back via of the top silicon layer is etched using sulfur hexafluoride etching gas, with an etching depth of 2~10μm, and the size of the back via is 1~10μm.

[0012] Preferably, the Parylene protective material is D-type Parylene, the temperature of the D-type Parylene pyrolysis section is controlled at 690~710℃, the vacuum degree is 15~25Pa, the deposition temperature is 30~40℃, the deposition rate is 0.2~0.6μm / h, the thickness is 1~8μm, the vacuum annealing temperature is 150~180℃, and the annealing time is 30~90min.

[0013] Preferably, in the back-side photolithography process, the dry etching of the bulk silicon layer of the substrate material uses the Bosch process, with a selectivity ratio of Si:SiO2 = 180:1~220:1 for deep reactive ion etching, a power of 800~1200W, a chamber pressure of 20~50mTorr, and a temperature of 25~65℃; the dry etching of the buried oxide layer uses CHF3 etching gas, with a selectivity ratio of SiO2:Si = 30:1~50:1 for RIE etching, an etching power of 80~150W, a chamber pressure of 5~12mTorr, and an etching temperature of 25~50℃.

[0014] This invention also provides a PZT loudspeaker device based on a back-conducting structure, which is fabricated using the fabrication method of a PZT loudspeaker based on a back-conducting structure as described above, including: SOI substrate material sheet, including a silicon substrate, a buried oxide layer and a top silicon layer arranged sequentially from bottom to top; Silicon dioxide layer; Bottom electrode metal; PZT piezoelectric film; The top electrode metal, the silicon dioxide layer, the bottom electrode metal, the PZT piezoelectric film, and the top electrode metal are formed sequentially from bottom to top on the front side of the top silicon layer; and a through groove is reserved in the PZT piezoelectric film to connect the top electrode metal and the bottom electrode metal located in the through groove. A diaphragm cavity is formed on the back side of the SOI substrate material sheet; Isolation trenches are spaced apart on the front side of the device, and the etching depth of the isolation trenches ends at the surface of the top silicon layer and is connected to the back via. Back guide holes are spaced apart on the top silicon layer; and the back guide holes penetrate the top silicon layer and are connected to the diaphragm cavity. Parylene protective material is formed on the front side of the device, exposing part of the top electrode metal; the Parylene protective material serves as a protective layer for the device to completely seal the gap between the back via and the top silicon layer.

[0015] Compared with the prior art, the present invention has the following beneficial effects: (1) This invention realizes a method for fabricating a PZT loudspeaker based on a back-conducting structure. Compared with traditional piezoelectric loudspeakers, its designed back-conducting structure can accurately control the airflow resistance of the rear cavity, match the mass-spring properties of the diaphragm, balance the stiffness and damping of the diaphragm, effectively reduce the resonance peak, expand the low-frequency response bandwidth, and improve the SPL. The back-conducting channel can suppress the asymmetric motion and segmentation motion of the diaphragm, make the diaphragm vibration more uniform, effectively reduce harmonic distortion, and improve the fidelity of audio reproduction. Its back-conducting structure can enhance the airflow of the rear cavity, dissipate the heat generated by the vibration of the piezoelectric layer in time, avoid the attenuation of the piezoelectric coefficient caused by high temperature, and buffer the pressure impact on the back of the diaphragm, greatly reducing the mechanical fatigue of the diaphragm edge and the diaphragm layer rupture caused by the accumulation of thermal stress, and improving the reliability and service life of the device.

[0016] (2) This invention uses SOI substrate material to achieve electrical, thermal and mechanical isolation between the device and the substrate, eliminates the parasitic capacitance and leakage problems of traditional bulk silicon substrates, improves the driving efficiency and signal-to-noise ratio of piezoelectric loudspeakers, and reduces distortion caused by crosstalk. The top single crystal silicon has good uniformity of Young's modulus and thermal expansion coefficient, and the deformation is minimal in the environment of -55℃~125℃, which improves the linearity and long-term reliability of the piezoelectric loudspeaker diaphragm vibration, and reduces the influence of temperature drift on sound pressure. Parylene D-type material is used as the device protective layer, which can completely cover the gap between the back guide slit and the substrate, and can also greatly eliminate the internal stress and thermal stress of the device. The bonding between the thin film and the PZT / silicon substrate is more stable in the high temperature environment, preventing the device from cracking due to thermal stress in the high temperature environment, and does not add extra diaphragm mass and rigidity. It has excellent characteristics such as high and low temperature resistance, moisture resistance, chemical corrosion resistance, radiation resistance, aging resistance and stable dielectric properties.

[0017] (3) This invention realizes a fabrication method for a PZT loudspeaker based on a back-conducting structure through piezoelectric thin film sputtering technology, piezoelectric thin film etching technology, top electrode metal interconnect structure technology, back-conducting hole structure technology, Parylene technology, and back cavity and back-conducting groove structure technology. An innovative fabrication process for a PZT loudspeaker based on a back-conducting structure is designed. This process allows for flexible adjustment of the piezoelectric thin film thickness, improving the product's resonant frequency and sound pressure level; it achieves monolithic integration of the back-conducting and damping components in a MEMS piezoelectric loudspeaker, realizing monolithic integration of the back-conducting structure with the diaphragm and piezoelectric layer, improving product yield, and reducing device size. The Parylene protective layer is integrally formed during wafer fabrication, replacing the traditional post-packaging assembly process, thus reducing production and R&D costs. Attached Figure Description

[0018] Figure 1 This is a schematic cross-sectional view of the process of depositing silicon dioxide structure on SOI substrate material sheets in a furnace tube.

[0019] Figure 2 This is a cross-sectional structural diagram of the piezoelectric thin film preparation process.

[0020] Figure 3 This is a cross-sectional structural diagram illustrating the fabrication process of the bottom electrode structure.

[0021] Figure 4 This is a cross-sectional structural diagram of the fabrication process of the top electrode structure.

[0022] Figure 5 This is a cross-sectional structural diagram of the fabrication process for the upper and lower electrode isolation.

[0023] Figure 6 This is a cross-sectional structural diagram illustrating the fabrication process of the back-guide hole structure.

[0024] Figure 7 This is a cross-sectional structural diagram of the device protective layer fabrication process.

[0025] Figure 8 This is a cross-sectional schematic diagram of the fabrication process of the device's cavity structure and back guide groove structure. Detailed Implementation

[0026] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0027] like Figures 1 to 8 As shown in the figure, this invention specifically provides a method for fabricating a PZT loudspeaker based on a back-conducting structure. The specific process includes the following steps: Step 1: Provide thickness unlimited, N <110> A single-layer polished SOI substrate with a crystal orientation, resistivity of 10~60 ohm·cm, top silicon thickness of 2~10 μm, and buried oxide thickness of 0.2~1 μm is grown on both the front and back sides of the substrate using LPCVD (low-pressure chemical vapor deposition) in a furnace tube. Figure 1 As shown.

[0028] Step 2: A bottom electrode film and a piezoelectric film are sputtered at high temperature on the front side of the device using magnetron sputtering (PVD) technology. The bottom electrode film material can be conductive metal materials such as Pt (platinum), Au (gold), Al (aluminum), and Cu (copper), with a thickness of 0.1~0.5μm; the piezoelectric film PZT (lead zirconate titanate ceramic) has a thickness of 1~5μm, and the sputtering temperature is 500~700℃. Figure 2 As shown.

[0029] Step 3: Perform photolithography on the bottom electrode layer structure. The front piezoelectric material is etched using metal ICP. The bottom electrode pattern can be square, rectangular, or circular. The ICP etching temperature is 20~80℃, the etching power is 500~1000W, the etching chamber pressure is 4~10 mTorr, and the etching rate is 50~150 nm / min. Etching stops at the bottom electrode metal film, forming the device's bottom electrode structure. The photoresist is then removed. Figure 3 As shown.

[0030] Step 4: Perform photolithography on the top electrode layer. The top electrode material is deposited onto the front side of the device via evaporation. The top electrode material can be Pt (platinum), Au (gold), Al (aluminum), etc., with a thickness of 0.1~0.8μm. Then, a liftoff process is performed to form the top electrode metal interconnect layer, such as... Figure 4 As shown.

[0031] Step 5: Perform photolithography on the upper and lower electrode isolation layers. The front piezoelectric film and the bottom electrode film are etched sequentially using ICP etching. A fluorine-chlorine mixed etching system with a PZT / PR (photoresist mask) ratio of approximately 3:1 is selected for the ICP. The ICP source power is 600-900W, the cavity pressure is 4-7 mTorr, and the etching rate is 60-100 nm / min. The LPSiO2 film is then etched using RIE. A high SiOto-Si selectivity ratio of 20:1-50:1 is selected for the RIE, with an etching power of 200-300W and a cavity pressure of 10-20 mTorr. This forms the upper and lower electrode isolation structure. The photoresist is then removed. Figure 5 As shown.

[0032] Step 6: Perform photolithography on the front-side back via structure. ICP etching is used to etch the top silicon of the SOI substrate. Sulfur hexafluoride is selected for dry Si etching of the top silicon vias, with an etching depth of 2~10μm, depending on the thickness of the top silicon on the SOI substrate. The back via size is 1~10μm. Etching stops at the SOI buried oxide layer, forming the device back via structure. The photoresist is then removed. Figure 6 As shown.

[0033] Step 7: Perform vacuum phase deposition to deposit Parylene protective material on the front side. Select D-type Parylene. Control the Parylene pyrolysis temperature at 690~710℃, the vacuum degree at 15~25Pa, the deposition temperature at 30~40℃, the deposition rate at 0.2~0.6μm / h, the thickness at 1~8μm, and the vacuum annealing temperature at 150~180℃ for 30~90min to form a protective layer for the device. Then perform photolithography, ICP etching of Parylene to expose the top electrode metal, forming the PAD structure. Remove the photoresist. Figure 7 As shown.

[0034] Step 8: Perform back-side photolithography. ICP etching is used to etch the bulk silicon layer and buried oxide layer of the SOI substrate. Bosch dry etching is used for bulk Si, employing a high selectivity Si to SiO2 ratio (180:1~220:1) deep reactive ion etching at a power of 800~1200W, a chamber pressure of 20~50 mTorr, and a temperature of 25~65℃. CHF3 gas is used for buried oxide dry etching, followed by a high selectivity SiO to Si ratio (30:1~50:1) RIE etching at a power of 80~150W, a chamber pressure of 5~12 mTorr, and an etching temperature of 25~50℃. This forms the device diaphragm cavity structure and back guide groove structure. The photoresist is then removed. Figure 8 As shown.

[0035] This invention provides a fabrication method for a PZT loudspeaker based on a back-conducting structure. Through piezoelectric thin film sputtering, piezoelectric thin film etching, top electrode metal interconnect structure, back-conducting hole structure, Parylene process, and back-conducting groove structure processes, a method for fabricating a PZT loudspeaker based on a back-conducting structure is achieved. This method cleverly integrates the back-conducting structure with the diaphragm and piezoelectric layer on a single sheet, simplifying the manufacturing process. The Parylene protective layer is integrally formed during wafer fabrication, replacing the traditional post-packaging assembly process. Simultaneously, the thickness of the piezoelectric thin film can be flexibly adjusted to improve the product's resonant frequency and sound pressure level. This accelerates the R&D cycle and reduces production and R&D costs.

[0036] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for fabricating a PZT loudspeaker based on a back-conducting structure, characterized in that, include: Provide a single-layer SOI substrate material sheet, and grow silicon dioxide layers on the front and back sides of the SOI substrate material sheet through LPCVD process in a furnace tube; A bottom electrode metal film and a PZT piezoelectric film are sequentially sputtered at high temperature on the front side of the device using a magnetron sputtering PVD process. A photolithography process for the bottom electrode layer structure is performed by etching the front PZT piezoelectric thin film using ICP, with the etching depth stopping at the surface of the bottom electrode metal thin film to form the bottom electrode structure of the device. The top electrode layer photolithography process is performed, and the top electrode material is deposited on the front side of the device through an evaporation process. Then, the liftoff process is performed to form the top electrode metal. The upper and lower electrode isolation layers are photolithographically processed. The front PZT piezoelectric film and the bottom electrode film are etched sequentially by ICP etching, and the silicon dioxide layer is etched by RIE to form the upper and lower electrode isolation trench structure. The front-side back via structure photolithography process is performed by etching the top silicon layer of the SOI substrate material using ICP etching, with the etching stopping at the surface of the buried oxide layer, to form the device back via structure. Parylene protective material is deposited on the front side using vacuum phase deposition, followed by vacuum annealing to form a device protective layer. Then, photolithography is performed to etch the Parylene protective material using ICP to expose the top electrode metal and form a PAD structure. A back-side photolithography process is performed, in which the back-side silicon dioxide layer, silicon substrate, and buried oxide layer of the SOI substrate material are etched by ICP to form the device diaphragm cavity structure.

2. The method for fabricating a PZT loudspeaker based on a back-conducting structure as described in claim 1, characterized in that, The SOI substrate material sheet comprises a silicon substrate, a buried oxide layer, and a top silicon layer arranged sequentially from bottom to top; the thickness of the silicon substrate is unlimited, and the crystal orientation is N. <110> The resistivity is 10~60 ohm·cm; the thickness of the top silicon layer is 2~10 μm; and the thickness of the buried oxide layer is 0.2~1 μm.

3. The method for fabricating a PZT loudspeaker based on a back-conducting structure as described in claim 1, characterized in that, The bottom electrode metal film is made of one or more conductive metal materials Pt, Au, Al and Cu, and the thickness of the bottom electrode metal film is 0.1~0.5μm; the thickness of the PZT piezoelectric film is 1~5μm; and the high-temperature sputtering temperature is 500~700℃.

4. The method for fabricating a PZT loudspeaker based on a back-conducting structure as described in claim 1, characterized in that, The bottom electrode structure is selected from square, rectangular or circular patterns; in the photolithography process of the bottom electrode layer structure, the ICP etching temperature is 20~80℃, the etching power is 500~1000W, the etching chamber pressure is 4~10mTorr, and the etching rate is 50~150nm / min.

5. The method for fabricating a PZT loudspeaker based on a back-conducting structure as described in claim 1, characterized in that, The top electrode material is selected from one or more of the conductive metal materials Pt, Au and Al, and the thickness of the top electrode metal is 0.1~0.8μm.

6. The method for fabricating a PZT loudspeaker based on a back-conducting structure as described in claim 1, characterized in that, In the photolithography process of the upper and lower electrode isolation layers, the selectivity ratio of the ICP etching system is a fluorine-chlorine mixed etching system with a PZT piezoelectric film:PR photoresist ratio of 3:

1. The ICP etching source power is 600~900W, the cavity pressure is 4~7mTorr, and the etching rate is 60~100nm / min. The selectivity ratio of the RIE etching system is SiO2:Si = 20:1~50:1, the etching power is 200~300W, and the cavity pressure is 10~20mTorr.

7. The method for fabricating a PZT loudspeaker based on a back-conducting structure as described in claim 1, characterized in that, The back via of the top silicon layer is etched using sulfur hexafluoride etching gas via ICP, with an etching depth of 2~10μm and a back via size of 1~10μm.

8. The method for fabricating a PZT loudspeaker based on a back-conducting structure as described in claim 1, characterized in that, The Parylene protective material is D-type Parylene. The temperature of the D-type Parylene pyrolysis section is controlled at 690~710℃, the vacuum degree is 15~25Pa, the deposition temperature is 30~40℃, the deposition rate is 0.2~0.6μm / h, the thickness is 1~8μm, the vacuum annealing temperature is 150~180℃, and the annealing time is 30~90min.

9. The method for fabricating a PZT loudspeaker based on a back-conducting structure as described in claim 1, characterized in that, In the back-side photolithography process, the dry etching of the bulk silicon layer of the substrate material uses the Bosch process, with a selectivity ratio of Si:SiO2 = 180:1~220:1 for deep reactive ion etching, a power of 800~1200W, a chamber pressure of 20~50mTorr, and a temperature of 25~65℃; the dry etching of the buried oxide layer uses CHF3 etching gas, with a selectivity ratio of SiO2:Si = 30:1~50:1 for RIE etching, an etching power of 80~150W, a chamber pressure of 5~12mTorr, and an etching temperature of 25~50℃.

10. A PZT loudspeaker device based on a back-conducting structure, fabricated using the fabrication method of a PZT loudspeaker based on a back-conducting structure as described in any one of claims 1 to 9, characterized in that, include: SOI substrate material sheet, including a silicon substrate, a buried oxide layer and a top silicon layer arranged sequentially from bottom to top; Silicon dioxide layer; Bottom electrode metal; PZT piezoelectric film; The top electrode metal, the silicon dioxide layer, the bottom electrode metal, the PZT piezoelectric film, and the top electrode metal are formed sequentially from bottom to top on the front side of the top silicon layer; and a through groove is reserved in the PZT piezoelectric film to connect the top electrode metal and the bottom electrode metal located in the through groove. A diaphragm cavity is formed on the back side of the SOI substrate material sheet; Isolation trenches are spaced apart on the front side of the device, and the etching depth of the isolation trenches ends at the surface of the top silicon layer and is connected to the back via. Back guide holes are spaced apart on the top silicon layer; and the back guide holes penetrate the top silicon layer and are connected to the diaphragm cavity. Parylene protective material is formed on the front side of the device, exposing part of the top electrode metal; the Parylene protective material serves as a protective layer for the device to completely seal the gap between the back via and the top silicon layer.

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