Design structure for connecting asynchronous double LED drive circuits with single output port

Abstract

The invention discloses a design structure of a single output port connected asynchronous double-LED drive circuit, the drive circuit comprises a PMOS tube, an NMOS tube, two light emitting diodes D1 and D2, a power supply VDD and a ground end GND, the power supply VDD and the ground end GND correspond to each other, the grid electrode of the PMOS tube is connected with an input control signal DP, and the control signal DP is used for controlling the conduction and cut-off of the PMOS tube; the grid electrode of the NMOS tube is connected with another path of input control signal DN, and the control signal DN is used for controlling the on-off state of the NMOS tube. According to the invention, a single LED output port can control and stagger two timing sequence pulse signals, the timing sequence of two LEDs can be controlled by a single output port, and a timing sequence stagger mode is used, so that a double-output port timing sequence signal can be replaced by a single output port timing sequence signal; according to the circuit, sequential logic is ensured to be accurate and not to interfere with each other, and a double-sequential LED effect can be driven through a single output pin, so that the problems of excessive occupation of output pins and over-high packaging cost in a traditional LED control scheme are effectively solved.

Description

Technical Field

[0001] This invention relates to the field of light-emitting diode (LED) technology, and more specifically to a design structure for a single-output port connected to an asynchronous dual-LED driver circuit. Background Technology

[0002] Traditional LED driver circuits, regardless of whether they use PWM output or constant current source output, adhere to the design principle of "single pulse acting on a single output." This limits them to single-sequence output circuits, meaning one output terminal can only connect to one LED, and they cannot achieve time-sequential control of multiple LEDs through a single port. Taking the most typical NMOS transistor driver circuit in the industry as an example (as shown in the attached manual)... Figure 1 As shown in the diagram, the source of the NMOS transistor is grounded (GND), and the externally input independent control signal L1 is connected to the gate of the NMOS transistor. The NMOS transistor is switched on and off by controlling the gate voltage. The drain output pin is connected to only one LED D0 to VDD (positive power supply), and the negative terminal of the circuit is connected to GND, thus forming a complete current loop. An excessive number of pins increases the technical difficulty of chip enclosure and also increases manufacturing costs.

[0003] Chinese Patent: An LED driving circuit and an LED driving system, authorized announcement number: CN111586931B. This patent discloses the specific structure and control method of the existing LED driving circuit. As can be seen from the above disclosure, it also adopts the working mode of single pulse acting on single output.

[0004] Traditional circuit design requires a separate output pin configuration for each LED. However, this technical solution improves the design of existing LED driver circuits, enabling a single LED output port to control two staggered timing pulse signals. This allows a single output port to control the timing of two LEDs. By using a staggered timing method, a single output port timing signal can replace the timing signals of two output ports, ensuring accurate timing logic without interference. This circuit can drive the effect of dual-timing LEDs with a single output pin, effectively solving the problems of excessive output pin occupation and high packaging costs in traditional LED control schemes. Summary of the Invention

[0005] The present invention discloses a design structure for a single output port connected to an asynchronous dual LED driver circuit, the main purpose of which is to overcome the above-mentioned deficiencies and shortcomings of the prior art.

[0006] The technical solution adopted in this invention is as follows:

[0007] A single-output port asynchronous dual-LED driving circuit design structure is disclosed. The driving circuit includes a PMOS transistor, an NMOS transistor, two light-emitting diodes D1 and D2, and corresponding power supply VDD and ground GND. The gate of the PMOS transistor is connected to an input control signal DP, which is used to control the conduction and cutoff of the PMOS transistor. The gate of the NMOS transistor is connected to another input control signal DN, which is used to control the switching state of the NMOS transistor. The source of the PMOS transistor is directly connected to the positive power supply VDD of the circuit, and the drain of the PMOS transistor is connected to the output port P2 of the circuit. The source of the NMOS transistor is connected to the ground GND of the circuit, and the drain of the NMOS transistor is connected to the output port P2 of the circuit, forming a topology in which the PMOS transistor and the NMOS transistor share a common output port. The light-emitting diodes D1 and D2 are connected in parallel with the output port P2.

[0008] Furthermore, the positive terminal of the light-emitting diode D1 is connected to the positive power supply VDD, and the negative terminal is connected to the output port P2; the positive terminal of the light-emitting diode D2 is connected to the output port P2, and the negative terminal is pulled into the ground terminal GND.

[0009] Furthermore, the control signals DP and DN are asynchronous double-pulse control signals.

[0010] Furthermore, the circuit control method for the control signals DP and DN specifically includes the following steps:

[0011] When the entire IC circuit is in static mode, the control signals DP and DN are at the rising and falling edges respectively. At this time, both the PMOS and NMOS transistors remain in the off state. In this state, the output port P2 is in a high impedance state.

[0012] When the circuit enters the working mode, the timing control logic is executed in a loop according to the preset program: when the DP signal is at the falling edge, the PMOS transistor is turned on by the signal control, while the NMOS transistor remains in the off state. At this time, the current flows from the circuit's positive power supply VDD through the PMOS transistor to the output port P2, and then flows into the circuit ground GND through the positive terminal of the control signal D2 and out through the negative terminal, forming a complete loop. The light-emitting diode D2 lights up, while the light-emitting diode D1 is in the off state because no effective potential difference is formed at the negative terminal.

[0013] When the DN signal is at its rising edge, the NMOS transistor is turned on and the PMOS transistor is turned off simultaneously. Current flows from the circuit's positive power supply VDD through the positive terminal of the control signal D1 to the output port P2, and then through the NMOS transistor to the circuit ground GND. The LED D1 lights up, while the LED D2 turns off due to the loss of current supply.

[0014] Furthermore, the three operating states controlled by the circuit are ordered cyclic states, with the three states switching alternately.

[0015] Furthermore, the operating timing of the PMOS transistor and the NMOD transistor is staggered, and their timing settings do not overlap.

[0016] As can be seen from the above description and explanation of the present invention, compared with the prior art, the advantages of the present invention are as follows:

[0017] Advantage 1: This invention designs an LED driving scheme adapted to asynchronous dual-pulse signals. By staggering the timing, two independent pulse signals can be stably applied to the same output port, achieving precise control of two LEDs with different timing sequences from a single output port. In the process of realizing this core function, the timing logic of the two pulse signals is strictly guaranteed to be complete and without omissions, and the control is precise and without deviation, ensuring that the two LEDs operate according to their respective preset timing parameters.

[0018] Advantage 2: Compared with the traditional design structure that requires two output PAD pins to control two LEDs, this invention can achieve dual LED control with a single output pin. By eliminating one output PAD pin, the total number of pins of the driver chip can be effectively reduced, thereby reducing the technical difficulty and manufacturing cost of chip packaging. Attached Figure Description

[0019] Figure 1 This is a structural diagram of an existing NMOS transistor drive circuit.

[0020] Figure 2 This is a structural diagram of the driving circuit of the present invention.

[0021] Figure 3 This is a diagram of the dual-pulse signal and output signal of the present invention. Detailed Implementation

[0022] The specific embodiments of the present invention will be further described and illustrated below with reference to the accompanying drawings.

[0023] like Figure 2 and Figure 3As shown, a single-output port asynchronous dual-LED driver circuit design structure is presented. The driver circuit includes a PMOS transistor, an NMOS transistor, two light-emitting diodes D1 and D2, and corresponding power supply VDD and ground GND. The gate of the PMOS transistor is connected to an input control signal DP, which is used to control the conduction and cutoff of the PMOS transistor. The gate of the NMOS transistor is connected to another input control signal DN, which is used to control the switching state of the NMOS transistor. The source of the PMOS transistor is directly connected to the positive power supply VDD of the circuit, and the drain of the PMOS transistor is connected to the output port P2 of the circuit. The source of the NMOS transistor is connected to the ground GND of the circuit, and the drain of the NMOS transistor is connected to the output port P2 of the circuit, forming a topology in which the PMOS transistor and the NMOS transistor share a common output port. The light-emitting diodes D1 and D2 are connected in parallel with the output port P2.

[0024] like Figure 2 As shown, the positive terminal of LED D1 is connected to the positive power supply VDD, and the negative terminal is connected to the output port P2; the positive terminal of LED D2 is connected to the output port P2, and the negative terminal is pulled to ground GND. The control signals DP and DN are asynchronous double-pulse control signals, and the circuit control method for the control signals DP and DN specifically includes the following steps:

[0025] When the entire IC circuit is in static mode, the control signals DP and DN are at the rising and falling edges respectively. At this time, both the PMOS and NMOS transistors remain in the off state. In this state, the output port P2 is in a high impedance state.

[0026] When the circuit enters the working mode, the timing control logic is executed in a loop according to the preset program: when the DP signal is at the falling edge, the PMOS transistor is turned on by the signal control, while the NMOS transistor remains in the off state. At this time, the current flows from the circuit's positive power supply VDD through the PMOS transistor to the output port P2, and then flows into the circuit ground GND through the positive terminal of the control signal D2 and out through the negative terminal, forming a complete loop. The light-emitting diode D2 lights up, while the light-emitting diode D1 is in the off state because no effective potential difference is formed at the negative terminal.

[0027] When the DN signal is at its rising edge, the NMOS transistor is turned on and the PMOS transistor is turned off simultaneously. Current flows from the circuit's positive power supply VDD through the positive terminal of the control signal D1 to the output port P2, and then through the NMOS transistor to the circuit ground GND. The LED D1 lights up, while the LED D2 turns off due to the loss of current supply.

[0028] The circuit controls three operating states in an ordered cyclical manner, with the three states switching alternately. The operating timing of the PMOS transistor and the NMOD transistor is staggered, and the time settings do not overlap.

[0029] In actual operation, the IC circuit of this invention is strictly divided into three clear and orderly cyclical working states. The timing staggered control is achieved by alternating between the three states, which not only ensures that the two LEDs work independently without interference, but also achieves the core goals of port simplification and cost optimization, as detailed below:

[0030] 1. Static state: This state keeps the IC in a non-leakage state. This state is the standby mode of the IC circuit. The core objective is to ensure that the circuit is in a stable state with low power consumption and no leakage.

[0031] 2. PMOS operating state: After the PMOS transistor is turned on, the current flows from the positive power supply VDD through the PMOS transistor to the output port (P2). Since the positive terminal of the light-emitting diode D2 is connected to the output port (P2) and the negative terminal is connected to GND, the current can smoothly pass through D2 to form a complete circuit and drive D2 to light up accurately.

[0032] 3. In NMOS operating state, the NMOS transistor is turned on and the PMOS transistor is turned off synchronously to prevent the two signals from superimposed and conflicting. The current flows from the positive power supply VDD through the positive terminal of LED D1 (the positive terminal of D1 is connected to VDD and the negative terminal is connected to the output port P2), and then flows to GND through the turned-on NMOS transistor, driving D1 to light up stably.

[0033] The three operating states described above alternate in a cyclical manner in the order of "static state - PMOS operating state - NMOS operating state". The operating timing of PMOS and NMOS is strictly staggered and there is no time overlap, which fundamentally avoids mutual interference between the two LED driving signals and successfully realizes independent timing control of two LEDs by a single output port.

[0034] In this way, what would normally require two output ports can be reduced to one. When there are more LED output ports, the number of output ports can be halved. For the package, the wire bonding cost will also be halved, and the number of IC output pins will also be halved. This can reduce costs, increase product competitiveness, and enhance the product's advantage in the market.

[0035] The above are merely specific embodiments of the present invention, but the design concept of the present invention is not limited thereto. Any non-substantial improvements made to the present invention using this concept should be considered as infringing on the protection scope of the present invention.

Claims

1. A design structure for a single-output port connected to an asynchronous dual-LED driver circuit, characterized in that: The driving circuit includes a PMOS transistor, an NMOS transistor, two light-emitting diodes D1 and D2, and corresponding power supply VDD and ground GND. The gate of the PMOS transistor is connected to an input control signal DP, which is used to control the conduction and cutoff of the PMOS transistor. The gate of the NMOS transistor is connected to another input control signal DN, which is used to control the switching state of the NMOS transistor. The source of the PMOS transistor is directly connected to the positive power supply VDD of the circuit, and the drain of the PMOS transistor is connected to the output port P2 of the circuit. The source of the NMOS transistor is connected to the ground GND of the circuit, and the drain of the NMOS transistor is connected to the output port P2 of the circuit, forming a topology in which the PMOS transistor and the NMOS transistor share a common output port. The light-emitting diodes D1 and D2 are connected in parallel with the output port P2.

2. The design structure of a single-output port connected to an asynchronous dual-LED driver circuit according to claim 1, characterized in that: The positive terminal of LED D1 is connected to the positive power supply VDD, and the negative terminal is connected to the output port P2; the positive terminal of LED D2 is connected to the output port P2, and the negative terminal is pulled to the ground terminal GND.

3. The design structure of a single-output port connected to an asynchronous dual-LED driver circuit according to claim 1, characterized in that: The control signals DP and DN are asynchronous double-pulse control signals.

4. The design structure of a single-output port connected to an asynchronous dual-LED driver circuit according to claim 1, characterized in that: The circuit control method for the control signals DP and DN specifically includes the following steps: When the entire IC circuit is in static mode, the control signals DP and DN are at the rising and falling edges respectively. At this time, both the PMOS and NMOS transistors remain in the off state. In this state, the output port P2 is in a high impedance state. When the circuit enters the working mode, the timing control logic is executed in a loop according to the preset program: when the DP signal is at the falling edge, the PMOS transistor is turned on by the signal control, while the NMOS transistor remains in the off state. At this time, the current flows from the circuit's positive power supply VDD through the PMOS transistor to the output port P2, and then flows into the circuit ground GND through the positive terminal of the control signal D2 and out through the negative terminal, forming a complete loop. The light-emitting diode D2 lights up, while the light-emitting diode D1 is in the off state because no effective potential difference is formed at the negative terminal. When the DN signal is at its rising edge, the NMOS transistor is turned on and the PMOS transistor is turned off simultaneously. Current flows from the circuit's positive power supply VDD through the positive terminal of the control signal D1 to the output port P2, and then through the NMOS transistor to the circuit ground GND. The LED D1 lights up, while the LED D2 turns off due to the loss of current supply.

5. The design structure of a single-output port connected to an asynchronous dual-LED driver circuit according to claim 4, characterized in that: The circuit controls three operating states in an ordered cyclical manner, with the three states switching alternately.

6. The design structure of a single-output port connected to an asynchronous dual-LED driver circuit according to claim 4, characterized in that: The operating timing of the PMOS transistor and the NMOD transistor is staggered, and their timing settings do not overlap.

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