Single-wire serial lighting circuit and light-emitting device
The single-wire serial lighting circuit achieves separate transmission of data and clock signals, solving the problems of wasted IO resources and poor communication reliability in existing technologies, and realizing efficient LED lighting control.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING ZHONGKE TENGYUE TECH DEV CO LTD
- Filing Date
- 2026-01-22
- Publication Date
- 2026-05-01
AI Technical Summary
Existing LED lighting control solutions require multiple I/O resources, have complex wiring, and poor communication reliability, especially in long-distance transmission where they are susceptible to interference.
A single-wire serial lighting circuit is adopted. Through a resistor-capacitor integration module, a voltage comparison module, a data shaping module, a clock generation module, and a capacitor delay discharge reset module, the data signal and clock signal are separated and transmitted using a single signal line, generating a synchronous sampling clock signal and performing data latching.
It saves main control resources, simplifies wiring, improves communication reliability, ensures independent transmission of signals in each cycle, and eliminates integral coupling between preceding and following cycles.
Smart Images
Figure CN121968404A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of LED technology, and more specifically, to a single-wire serial lighting circuit and a light-emitting device. Background Technology
[0002] Light-emitting diodes (LEDs) are widely used in display panels, decorative lighting, status indicators, and intelligent lighting environment control due to their advantages such as low power consumption, long lifespan, and fast response speed. As application scenarios increasingly demand higher LED counts and control precision, how to efficiently and reliably drive and control multiple LED arrays has become a key factor affecting product performance and cost.
[0003] Most common LED lighting control schemes currently employ a serial cascaded structure, using shift register chips to receive data and clock signals from the main controller, achieving step-by-step transmission and latched output. This type of scheme typically relies on two independent physical signal lines: one for clock signal synchronization and the other for data signal transmission of control information. This approach requires at least two general-purpose input / output ports on the main control chip, resulting in resource waste for microcontrollers in embedded systems with limited I / O resources. Furthermore, the existing separate transmission of clock and data signals makes them susceptible to interference over long distances, leading to decreased communication reliability. Summary of the Invention
[0004] The purpose of this application is to address the shortcomings of the prior art by providing a single-wire serial lighting circuit and a light-emitting device, which realizes the transmission of serial lighting signals by using a single signal, transmitting it based on different duty cycles, separating data signals and clock signals.
[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, embodiments of this application provide a single-wire serial lighting circuit, which includes: a resistor-capacitor integration module, a voltage comparison module, a data shaping module, a clock generation module, a capacitor delayed discharge reset module, and a reference voltage generation module. The first terminal of the resistor-capacitor integration module is used to receive the duty cycle signal, the second terminal of the resistor-capacitor integration module is connected to the second terminal of the capacitor delayed discharge reset module, and the third terminal of the resistor-capacitor integration module is connected to the negative input terminal of the voltage comparison module. The first terminal of the clock generation module is used to receive the duty cycle signal, and the second terminal of the clock generation module is connected to the first terminal of the capacitor delayed discharge reset module and the first input terminal of the shift register, respectively. The positive input terminal of the voltage comparison module is connected to the first terminal of the reference voltage generation module, and the output terminal of the voltage comparison module is connected to the first terminal of the data shaping module. The second terminal of the data shaping module is connected to the second terminal of the reference voltage generation module, and the fourth terminal of the data shaping module is connected to the second input terminal of the shift register. The resistor-capacitor integration module is used to integrate the duty cycle signal and output the integrated voltage corresponding to the duty cycle signal to the voltage comparison module. The voltage comparison module compares the reference voltage from the reference voltage generation module with the integrated voltage and outputs the comparison result signal to the data shaping module. The data shaping module is used to filter and enhance the comparison result signal, and output the target data signal to the shift register. The clock generation module is used to invert the duty cycle signal to generate a sampling clock signal that is synchronized with the target data signal, and send the sampling clock signal to the shift register and the capacitor delay discharge reset module. The capacitor delayed discharge reset module is used to perform delayed discharge reset on the integrating capacitor in the resistor-capacitor integrating module before the end of each duty cycle signal transmission cycle.
[0006] Optionally, the resistor-capacitor integration module includes: a second resistor and an integration unit; The first terminal of the integrator is used to receive the duty cycle signal, the second terminal of the integrator is connected to one end of the second resistor, the third terminal of the integrator is connected to the negative input terminal of the voltage comparison module, and the fourth terminal of the integrator and the other end of the second resistor are both grounded. The second resistor is used to limit the maximum amplitude of the integrated voltage of the integrating unit. The integrating unit is used to integrate the high duty cycle signal when the duty cycle signal is a high duty cycle signal, and output the integrated voltage corresponding to the high duty cycle signal. The integrator is used to discharge when the duty cycle signal is a low duty cycle signal.
[0007] Optionally, the integration unit includes a first resistor and a first capacitor; One end of the first resistor is used to receive the duty cycle signal, and the other end of the first resistor is connected to one end of the first capacitor, one end of the second resistor, and the negative input terminal of the voltage comparison module. The other ends of the first capacitor and the second resistor are both grounded.
[0008] Optionally, the reference voltage generation module includes: a third resistor and a fourth resistor; One end of the third resistor is connected to the other end of the fourth resistor and the positive input terminal of the voltage comparison module, the other end of the third resistor is grounded, and one end of the fourth resistor is connected to the external power supply and the second terminal of the data shaping module.
[0009] Optionally, the clock generation module includes: a voltage divider unit, a fourth capacitor, an eighth resistor, and a third transistor; The first terminal of the voltage divider unit is used to receive the duty cycle signal. The second terminal of the voltage divider unit is connected to one terminal of the fourth capacitor and the first terminal of the third transistor, respectively. The third terminal of the voltage divider unit, the other terminal of the fourth capacitor, and the third terminal of the third transistor are all grounded. The second terminal of the third transistor is connected to one terminal of the eighth resistor, the first terminal of the capacitor delayed discharge reset module, and the first input terminal of the shift register.
[0010] Optionally, the voltage divider unit includes: a ninth resistor and a tenth resistor; One end of the tenth resistor is used to receive the duty cycle signal, and the other end of the tenth resistor is connected to one end of the ninth resistor, one end of the fourth capacitor, and the first end of the third transistor, and the other end of the ninth resistor is grounded.
[0011] Optionally, the capacitor delayed discharge reset module includes: a clock delay unit and a second transistor; The first terminal of the clock delay unit is connected to the second terminal of the clock generation module, the second terminal of the clock delay unit is connected to the first terminal of the second transistor, and the third terminal of the clock delay unit and the third terminal of the second transistor are both grounded. The second terminal of the second transistor is connected to the second terminal of the resistor-capacitor integration module; The clock delay unit is used to delay the clock sampling signal when the clock generation module outputs the clock sampling signal to obtain a delayed high-level signal, and output the delayed high-level signal to the second transistor. The second transistor is turned on under the action of the delayed high-level signal to discharge and reset the first capacitor in the resistor-capacitor integration module.
[0012] Optionally, the clock delay unit includes: an eleventh resistor, a diode, and a fifth capacitor; One end of the eleventh resistor is connected to the negative terminal of the diode and the second terminal of the clock generation module, and the other end of the eleventh resistor is connected to the positive terminal of the diode, the first terminal of the second transistor, and one end of the fifth capacitor. The other end of the fifth capacitor is grounded. The eleventh resistor and the fifth capacitor delay the high-level clock signal when the clock generation module outputs a high-level clock signal to obtain a delayed high-level signal.
[0013] Optionally, the data shaping module includes: a fifth resistor, a sixth resistor, a seventh resistor, a second capacitor, and a first transistor; One end of the seventh resistor is connected to the output terminal of the voltage comparison module, and the other end of the seventh resistor is connected to one end of the fifth resistor, one end of the second capacitor, and the first terminal of the first transistor. The other end of the fifth resistor, the other end of the second capacitor, and the third terminal of the first transistor are all grounded. The second terminal of the first transistor is connected to one end of the sixth resistor and the second input terminal of the shift register, and the other end of the sixth resistor is connected to the second terminal of the reference voltage generation module.
[0014] Secondly, embodiments of this application also provide a light-emitting device, including the single-wire serial lighting circuit described in the first aspect.
[0015] The beneficial effects of this application are: This application provides a single-wire serial lighting circuit and light-emitting device. It receives a duty cycle signal via a single signal line. A resistor-capacitor integration module integrates this duty cycle signal to generate an integrated voltage proportional to the duty cycle signal. A voltage comparison module compares the integrated voltage with a reference voltage and outputs a comparison result signal. A data shaping module then filters and enhances the comparison result signal to generate a clean target data signal. Simultaneously, a clock generation module generates a synchronous sampling clock signal based on the duty cycle signal received from the single signal line. This allows the shift register to sample the target data signal upon receiving the sampling clock signal. Subsequently, a capacitor delay discharge reset module delays the sampling clock signal, delaying the sampling for a certain period after sampling and resetting the integrating capacitor in the resistor-capacitor integration module before each duty cycle signal transmission cycle, thus entering the next data cycle. The entire process requires no additional clock port, completing the complete transmission of data and synchronization information based solely on a single signal line. This significantly saves main control resources. Furthermore, the system achieves reset after sampling, ensuring the integrity of data latching, eliminating integral coupling between consecutive cycles, and ensuring independent signal transmission for each cycle. This invention enables the transmission of serial LED lighting signals using a single signal with different duty cycles. It solves problems such as wasted I / O resources, complex wiring, and poor communication reliability in existing technologies. Attached Figure Description
[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 A circuit diagram of a single-wire serial lighting circuit provided for an embodiment of this application; Figure 2 A schematic diagram of a signal timing diagram provided in an embodiment of this application; Figure 3 A circuit diagram of a second single-wire serial lighting circuit provided in an embodiment of this application; Figure 4 A circuit diagram of a third single-wire serial lighting circuit provided in the embodiments of this application; Figure 5 A circuit diagram of the fourth single-wire serial lighting circuit provided in the embodiments of this application; Figure 6 A circuit diagram of the fifth single-wire serial lighting circuit provided in the embodiments of this application; Figure 7This is a circuit diagram of the sixth single-wire serial lighting circuit provided in the embodiments of this application. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the accompanying drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.
[0019] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0020] It should be noted that the term "comprising" will be used in the embodiments of this application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.
[0021] Figure 1 A circuit diagram of a single-wire serial lighting circuit provided in this application embodiment is shown below. Figure 1 As shown, the single-wire serial lighting circuit may include: a resistor-capacitor integration module 10, a voltage comparison module 11, a data shaping module 12, a clock generation module 13, a capacitor delayed discharge reset module 14, and a reference voltage generation module 15.
[0022] like Figure 1 As shown, the first terminal of the resistor-capacitor integration module 10 is used to receive the duty cycle signal, the second terminal of the resistor-capacitor integration module 10 is connected to the second terminal of the capacitor delayed discharge reset module 14, and the third terminal of the resistor-capacitor integration module 10 is connected to the negative input terminal of the voltage comparison module 11. The duty cycle signal can be output from the main control terminal.
[0023] Continue as Figure 1As shown, the first terminal of the clock generation module 13 is used to receive the duty cycle signal, the second terminal of the clock generation module 13 is connected to the first terminal of the capacitor delay discharge reset module 14 and the first input terminal of the shift register, respectively, and the third terminal of the clock generation module 13 and the third terminal of the capacitor delay discharge reset module 14 are both grounded.
[0024] Continue as Figure 1 As shown, the positive input terminal of the voltage comparison module 11 is connected to the first terminal of the reference voltage generation module 15, and the output terminal of the voltage comparison module 11 is connected to the first terminal of the data shaping module 12; the second terminal of the data shaping module 12 is connected to the second terminal of the reference voltage generation module 15, the third terminal of the data shaping module 12 and the third terminal of the reference voltage generation module 15 are both grounded, and the fourth terminal of the data shaping module 12 is connected to the second input terminal of the shift register.
[0025] Optionally, the resistor-capacitor integration module 10 integrates the duty cycle signal and outputs an integrated voltage corresponding to the duty cycle signal to the voltage comparison module 11. The duty cycle signal is periodically transmitted and may include a high duty cycle signal and a low duty cycle signal, such as 80% high duty cycle and 20% low duty cycle. A high duty cycle signal refers to the period during which the duty cycle signal is at a high level; a low duty cycle signal refers to the period during which the duty cycle signal is at a low level. For example, a periodic duty cycle signal may include 80% high duty cycle and 20% low duty cycle. Specifically, when the duty cycle signal is a high duty cycle signal, the resistor-capacitor integration module 10 integrates this high duty cycle signal, and the integrated voltage output by the resistor-capacitor integration module 10 gradually increases, so that the integrated voltage Vresistor-capacitor output by the resistor-capacitor integration module 10 is higher than the reference voltage Vref. When the duty cycle signal is a low duty cycle signal, the resistor-capacitor integration module 10 starts to discharge, and the output integration voltage Vresistor-capacitor is lower than the reference voltage Vref.
[0026] Optionally, the reference voltage generation module 15 generates a reference voltage and outputs it to the voltage comparison module 11. The voltage comparison module 11 compares the reference voltage from the reference voltage generation module 15 with the integral voltage Vresistor-capacitor and outputs a comparison result signal to the data shaping module 12. This comparison result signal can be a digital level signal. The voltage comparison module 11 can employ a voltage comparator chip, which features fast response, low offset voltage, and high common-mode rejection ratio, ensuring accurate identification of minute voltage differences even in complex electromagnetic environments.
[0027] Optionally, the data shaping module 12 is used to filter and enhance the comparison result signal, and output the target data signal to the shift register. Since the comparison result signal output by the voltage comparison module 11 may have edge jitter, noise interference, or insufficient driving capability, directly using it to drive the shift register may cause sampling errors. Therefore, the data shaping module 12 further optimizes the comparison result signal output by the voltage comparison module 11. After processing by the data shaping module 12, the comparison result signal output by the voltage comparison module 11 is converted into a target data signal DAT with a clear rising or falling edge, sufficient driving current, and conforming to digital logic level standards. The obtained target data signal DAT is then output to the shift register through the fourth terminal of the data shaping module 12 as the data input to be latched.
[0028] Optionally, the clock generation module 13 inverts the duty cycle signal to generate a sampling clock signal synchronized with the target data signal, and sends the sampling clock signal to the shift register and the capacitor delay discharge reset module 14. This sampling clock signal is simultaneously sent to the first input terminal of the shift register and the capacitor delay discharge reset module 14. When the rising edge of the sampling clock signal arrives, the shift register can latch the target data signal currently input through the second input terminal, i.e., sample the target data signal. This ensures that the data sampling time is coordinated with the integration reset operation, enabling the shift register to correctly sample the target data signal.
[0029] Optionally, the capacitor delayed discharge reset module 14 is used to perform delayed discharge reset on the integrating capacitor in the resistor-capacitor integrating module 10 before the end of each duty cycle signal transmission cycle. After the resistor-capacitor integrating module 10 is discharged and reset, the target data signal DAT output by the data shaping module 12 is at a low level. To avoid the residual integral of the duty cycle signal from the previous cycle affecting the judgment accuracy of the duty cycle signal in the next cycle, the accumulated charge in the resistor-capacitor integrating module 10 is cleared in a timely manner after each signal sampling. Moreover, if the discharge is performed immediately after sampling, the data that has not yet been latched may be lost. Therefore, the capacitor delayed discharge reset module 14 enables controllable delayed discharge reset of the resistor-capacitor integrating module 10 before the end of each duty cycle signal transmission cycle. The delayed reset effectively avoids the sampling window of the target data signal, decouples the operation of clearing the integral and latching the data, and significantly improves the reliability of multi-cycle continuous communication.
[0030] Figure 2 This is a schematic diagram of a signal timing diagram provided in an embodiment of this application, such as... Figure 2As shown, when the duty cycle signal is a high duty cycle signal of 80%, the sampling clock signal generated by the clock generation module 13 is a rising edge signal. When DAT is high and the sampling clock signal is at the rising edge, DAT is sampled. When the duty cycle signal is low at 20%, that is, after the sampling of DAT is completed, the capacitor delay discharge reset module 14 performs a delayed reset on the resistor-capacitor integration module 10. That is, DAT is delayed and returns to a low level before the transmission of the 20% low duty cycle signal in the current cycle ends, ensuring the integrity of the sampled target data signal.
[0031] In this embodiment, the duty cycle signal is received via a single signal line. A resistor-capacitor integration module integrates this signal to generate an integrated voltage proportional to the duty cycle. A voltage comparison module compares this integrated voltage with a reference voltage and outputs a comparison result signal. A data shaping module then filters and enhances the comparison result signal to generate a clean target data signal. Simultaneously, a clock generation module generates a synchronous sampling clock signal based on the duty cycle signal received from the single signal line. This ensures the shift register samples the target data signal upon receiving the sampling clock signal. Subsequently, a capacitor delay discharge reset module delays the sampling clock signal, delaying the sampling for a period after sampling and resetting the integrating capacitor in the resistor-capacitor integration module before each duty cycle signal transmission cycle, thus entering the next data cycle. The entire process requires no additional clock port; data and synchronization information can be completely transmitted using only a single signal line, significantly saving main control resources. Furthermore, the system achieves reset after sampling, ensuring the integrity of the data latch, eliminating integral coupling between cycles, and ensuring independent signal transmission for each cycle. This invention enables the transmission of serial LED lighting signals using a single signal with different duty cycles. It solves problems such as wasted I / O resources, complex wiring, and poor communication reliability in existing technologies.
[0032] Figure 3 A circuit diagram of the second single-wire serial lighting circuit provided in the embodiments of this application is shown below. Figure 3 As shown, the resistor-capacitor integration module 10 includes a second resistor R2 and an integration unit.
[0033] The first terminal of the integrator is used to receive the duty cycle signal, the second terminal of the integrator is connected to one end of the second resistor, the third terminal of the integrator is connected to the negative input terminal of the voltage comparison module 11, and the fourth terminal of the integrator and the other end of the second resistor are both grounded.
[0034] Optionally, the second resistor is used to limit the maximum amplitude of the integration voltage V of the resistor-capacitor of the integration unit. The integration unit is used to integrate the high duty cycle signal when the duty cycle signal is a high duty cycle signal and output the integration voltage corresponding to the high duty cycle signal. The integration unit is used to discharge when the duty cycle signal is a low duty cycle signal.
[0035] Continue as Figure 2 As shown, the integration unit includes a first resistor R1 and a first capacitor C1.
[0036] One end of the first resistor R1 is used to receive the duty cycle signal. The other end of the first resistor R1 is connected to one end of the first capacitor C1, one end of the second resistor R2, and the negative input terminal of the voltage comparison module 11. The other ends of the first capacitor C1 and the second resistor R2 are both grounded.
[0037] Optionally, when the duty cycle signal is a high duty cycle signal, the first resistor R1 and the first capacitor C1 integrate the high duty cycle signal, charging the first capacitor C1; when the duty cycle signal is a low duty cycle signal, the first capacitor C1 discharges. Figure 2 The integrated voltage obtained by integrating 80% of the high duty cycle signal is higher than the reference voltage; the integrated voltage obtained by integrating 20% of the low duty cycle signal is lower than the reference voltage. Furthermore, when the signal is at a low duty cycle of 20%, the first capacitor C1 in the integration unit is discharged and reset. After the discharge, the integrated voltage V output by the resistor-capacitor integration module 10 is lower than the reference voltage.
[0038] Figure 4 A circuit diagram of the third single-wire serial lighting circuit provided in the embodiments of this application is shown below. Figure 4 As shown, the reference voltage generation module 15 includes a third resistor R3 and a fourth resistor R4.
[0039] like Figure 4 As shown, one end of the third resistor R3 is connected to the other end of the fourth resistor R4 and the positive input terminal of the voltage comparison module 11, the other end of the third resistor R3 is grounded, and one end of the fourth resistor R4 is connected to the external power supply and the second terminal of the data shaping module 12.
[0040] The positive input terminal of the voltage comparison module 11 is connected to the reference voltage Vref, and the negative input terminal of the voltage comparison module 11 is connected to the integral voltage V resistor and capacitor. Therefore, when the integral voltage V resistor and capacitor is less than the reference voltage Vref, the comparison result signal output by the voltage comparison module 11 is a high-level signal; when the integral V resistor and capacitor is greater than the reference voltage Vref, the comparison result signal output by the voltage comparison module 11 is a low-level signal.
[0041] Optionally, the reference voltage can be generated by a voltage divider using a third and fourth resistor, and the external power supply can be directly drawn from the power supply on the circuit board. The reference voltage obtained by the voltage divider using the third and fourth resistors can be flexibly adjusted according to the integrated voltage output by the resistor-capacitor integration module, and the obtained reference voltage can be within the voltage range of integrated voltage with high duty cycle and integrated voltage with low duty cycle.
[0042] Figure 5 A circuit diagram of the fourth single-wire serial lighting circuit provided in this application embodiment is shown below. Figure 5 As shown, the clock generation module 13 includes: a voltage divider unit, a fourth capacitor C4, an eighth resistor R8, and a third transistor M3.
[0043] Continue as Figure 5 As shown, the first terminal of the voltage divider unit receives the duty cycle signal. The second terminal of the voltage divider unit is connected to one end of the fourth capacitor C4 and the first terminal of the third transistor M3, respectively. The third terminal of the voltage divider unit, the other end of the fourth capacitor C4, and the third terminal of the third transistor M3 are all grounded. The second terminal of the third transistor M3 is connected to one end of the eighth resistor R8, the first terminal of the capacitor delayed discharge reset module 14, and the first input terminal of the shift register. The third transistor can be an NMOS transistor, with the first terminal of the third transistor M3 serving as the gate, the second terminal as the drain, and the third terminal as the source.
[0044] Continue as Figure 5 As shown, the voltage divider unit may include a ninth resistor R9 and a tenth resistor R10.
[0045] like Figure 5 As shown, one end of the tenth resistor R10 is used to receive the duty cycle signal, and the other end of the tenth resistor R10 is connected to one end of the ninth resistor R9, one end of the fourth capacitor C4, and the first end of the third transistor M3, while the other end of the ninth resistor R9 is grounded.
[0046] Optionally, the clock generation module 13 inverts the duty cycle signal, such as... Figure 2 As shown in the timing diagram, when the duty cycle signal changes from a high duty cycle signal to a low duty cycle signal, the clock generation module 13 generates a rising edge clock sampling signal.
[0047] Figure 6 A circuit diagram of the fifth single-wire serial lighting circuit provided in the embodiments of this application is shown below. Figure 6 As shown, the capacitor delay discharge reset module 14 may include a clock delay unit and a second transistor M2.
[0048] like Figure 6As shown, the first terminal of the clock delay unit is connected to the second terminal of the clock generation module 13, the second terminal of the clock delay unit is connected to the first terminal of the second transistor M2, and the third terminal of the clock delay unit and the third terminal of the second transistor M2 are both grounded. The second terminal of the second transistor M2 is connected to the second terminal of the resistor-capacitor integration module 10. Specifically, the first terminal of the clock delay unit is connected to the second terminal of the third transistor M3 of the clock generation module 13, and the second terminal of the second transistor M2 is connected to the other end of the first resistor R1 in the resistor-capacitor integration module 10. The second transistor can be an NMOS transistor, the first terminal of the second transistor M2 can be the gate, the second terminal of the second transistor M2 can be the drain, and the third terminal of the second transistor M2 can be the source.
[0049] Optionally, the clock delay unit is used to delay the clock sampling signal when the clock generation module 13 outputs the clock sampling signal, obtaining a delayed high-level signal, and outputting the delayed high-level signal to the second transistor M2; the second transistor M2 is turned on under the action of the delayed high-level signal to discharge and reset the first capacitor in the resistor-capacitor integration module. Figure 6 As shown, when the second transistor M2 is turned on, the second transistor M2 is grounded. At this time, the first capacitor C1 in the resistor-capacitor integration module 10 can achieve rapid discharge.
[0050] Continue as Figure 6 As shown, the clock delay unit includes: an eleventh resistor R11, a diode D1, and a fifth capacitor C5.
[0051] One end of the eleventh resistor R11 is connected to the negative terminal of diode D1 and the second terminal of clock generation module 13, respectively. The other end of the eleventh resistor R11 is connected to the positive terminal of diode D1, the first terminal of second transistor M2 and one end of fifth capacitor C5, respectively. The other end of fifth capacitor C5 is grounded.
[0052] Optionally, when the clock generation module 13 outputs the clock sampling signal, the eleventh resistor R11 and the fifth capacitor C5 perform delay processing on the clock sampling signal to obtain a delayed high-level signal.
[0053] Optionally, the clock sampling signal is a rising edge signal, i.e., a high-level signal. The clock sampling signal is delayed by integrating the eleventh resistor R11 and the fifth capacitor C5. When the clock sampling signal remains high for a certain period, the second transistor M2 will turn on. Furthermore, when the clock sampling signal is high, the input duty cycle signal is a low duty cycle signal, causing the first capacitor C1 to discharge. Therefore, when the second transistor M2 turns on, the first capacitor C1 can be discharged quickly. During the delay period of the eleventh resistor R11 and the fifth capacitor C5, the shift register can accurately sample the target data based on the clock sampling signal.
[0054] Without the second transistor M2 being turned on, when the input duty cycle signal is a low duty cycle signal, the first capacitor C1 can only discharge through the first resistor R1, resulting in a slow discharge speed. However, when the second transistor M2 is connected, it short-circuits, allowing the first capacitor C1 to discharge rapidly. After the first capacitor C1 discharges, the integrated voltage Vresistance-capacitance output by the resistor-capacitor integration module 10 is lower than the reference voltage Vref. At this time, the comparison result signal output by the voltage comparison module 11 is high, and the first transistor M1 in the data shaping module 12 is turned on, outputting a low target data signal to facilitate the transmission of the duty cycle signal in the next cycle. Furthermore, through the delay of the eleventh resistor R11 and the fifth capacitor C5, the time when the value of the target data signal changes from high level to low level is later than the time when the duty cycle signal input in the current cycle changes from high duty cycle signal to low duty cycle signal. Thus, the eleventh resistor R11 and the fifth capacitor C5 can ensure that after the target data signal is sampled, the target data signal does not immediately become low, but rather remains at a high level for a period of time after sampling before becoming low. Moreover, the period during which the target data signal remains high cannot exceed the transmission time of the duty cycle signal in the current cycle.
[0055] Diode D1 can be a low-voltage diode. When the clock sampling signal is high, diode D1 is not conducting. When the clock sampling signal becomes low, diode D1 allows the fifth capacitor C5 to discharge quickly, thereby turning on the second transistor M2 to facilitate the transmission of the duty cycle signal for the next cycle, allowing the duty cycle signal of the next cycle to charge the first capacitor C1.
[0056] Figure 7 A circuit diagram of the sixth single-wire serial lighting circuit provided in the embodiments of this application is shown below. Figure 7 As shown, the data shaping module 12 may include: a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a second capacitor C2, and a first transistor M1.
[0057] like Figure 7 As shown, one end of the seventh resistor R7 is connected to the output terminal of the voltage comparison module, and the other end of the seventh resistor R7 is connected to one end of the fifth resistor R5, one end of the second capacitor C2, and the first terminal of the first transistor M1. The other ends of the fifth resistor R5, the second capacitor C2, and the third terminal of the first transistor M1 are all grounded. The second terminal of the first transistor M1 is connected to one end of the sixth resistor R6 and the second input terminal of the shift register. The other end of the sixth resistor R6 is connected to the second terminal of the reference voltage generation module 15. Specifically, the other end of the sixth resistor R6 is connected to one end of the fourth resistor R4 in the reference voltage generation module 15. The first transistor can be an NMOS transistor, the first terminal of the first transistor M1 can be the gate, the second terminal of the first transistor M1 can be the drain, and the third terminal of the first transistor M1 can be the source.
[0058] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.
Claims
1. A single-wire serial lighting circuit, characterized in that, The single-wire serial lighting circuit includes: a resistor-capacitor integration module, a voltage comparison module, a data shaping module, a clock generation module, a capacitor delayed discharge reset module, and a reference voltage generation module. The first terminal of the resistor-capacitor integration module is used to receive the duty cycle signal, the second terminal of the resistor-capacitor integration module is connected to the second terminal of the capacitor delayed discharge reset module, and the third terminal of the resistor-capacitor integration module is connected to the negative input terminal of the voltage comparison module. The first terminal of the clock generation module is used to receive the duty cycle signal, and the second terminal of the clock generation module is connected to the first terminal of the capacitor delayed discharge reset module and the first input terminal of the shift register, respectively. The positive input terminal of the voltage comparison module is connected to the first terminal of the reference voltage generation module, and the output terminal of the voltage comparison module is connected to the first terminal of the data shaping module. The second terminal of the data shaping module is connected to the second terminal of the reference voltage generation module, and the fourth terminal of the data shaping module is connected to the second input terminal of the shift register. The resistor-capacitor integration module is used to integrate the duty cycle signal and output the integrated voltage corresponding to the duty cycle signal to the voltage comparison module. The voltage comparison module compares the reference voltage from the reference voltage generation module with the integrated voltage and outputs the comparison result signal to the data shaping module. The data shaping module is used to filter and enhance the comparison result signal, and output the target data signal to the shift register. The clock generation module is used to invert the duty cycle signal to generate a sampling clock signal that is synchronized with the target data signal, and send the sampling clock signal to the shift register and the capacitor delay discharge reset module. The capacitor delayed discharge reset module is used to perform delayed discharge reset on the integrating capacitor in the resistor-capacitor integrating module before the end of each duty cycle signal transmission cycle.
2. The single-wire serial lighting circuit according to claim 1, characterized in that, The resistor-capacitor integration module includes: a second resistor and an integration unit; The first terminal of the integrator is used to receive the duty cycle signal, the second terminal of the integrator is connected to one end of the second resistor, the third terminal of the integrator is connected to the negative input terminal of the voltage comparison module, and the fourth terminal of the integrator and the other end of the second resistor are both grounded. The second resistor is used to limit the maximum amplitude of the integrated voltage of the integrating unit. The integrating unit is used to integrate the high duty cycle signal when the duty cycle signal is a high duty cycle signal, and output the integrated voltage corresponding to the high duty cycle signal. The integrator is used to discharge when the duty cycle signal is a low duty cycle signal.
3. The single-wire serial lighting circuit according to claim 2, characterized in that, The integration unit includes a first resistor and a first capacitor; One end of the first resistor is used to receive the duty cycle signal, and the other end of the first resistor is connected to one end of the first capacitor, one end of the second resistor, and the negative input terminal of the voltage comparison module. The other ends of the first capacitor and the second resistor are both grounded.
4. The single-wire serial lighting circuit according to claim 1, characterized in that, The reference voltage generation module includes: a third resistor and a fourth resistor; One end of the third resistor is connected to the other end of the fourth resistor and the positive input terminal of the voltage comparison module, the other end of the third resistor is grounded, and one end of the fourth resistor is connected to the external power supply and the second terminal of the data shaping module.
5. The single-wire serial lighting circuit according to claim 1, characterized in that, The clock generation module includes: a voltage divider unit, a fourth capacitor, an eighth resistor, and a third transistor; The first terminal of the voltage divider unit is used to receive the duty cycle signal. The second terminal of the voltage divider unit is connected to one terminal of the fourth capacitor and the first terminal of the third transistor, respectively. The third terminal of the voltage divider unit, the other terminal of the fourth capacitor, and the third terminal of the third transistor are all grounded. The second terminal of the third transistor is connected to one terminal of the eighth resistor, the first terminal of the capacitor delayed discharge reset module, and the first input terminal of the shift register.
6. The circuit according to claim 5, characterized in that, The voltage divider unit includes: a ninth resistor and a tenth resistor; One end of the tenth resistor is used to receive the duty cycle signal, and the other end of the tenth resistor is connected to one end of the ninth resistor, one end of the fourth capacitor, and the first end of the third transistor, and the other end of the ninth resistor is grounded.
7. The circuit according to claim 1, characterized in that, The capacitor delayed discharge reset module includes: a clock delay unit and a second transistor; The first terminal of the clock delay unit is connected to the second terminal of the clock generation module, the second terminal of the clock delay unit is connected to the first terminal of the second transistor, and the third terminal of the clock delay unit and the third terminal of the second transistor are both grounded. The second terminal of the second transistor is connected to the second terminal of the resistor-capacitor integration module; The clock delay unit is used to delay the clock sampling signal when the clock generation module outputs the clock sampling signal to obtain a delayed high-level signal, and output the delayed high-level signal to the second transistor. The second transistor is turned on under the action of the delayed high-level signal to discharge and reset the first capacitor in the resistor-capacitor integration module.
8. The circuit according to claim 7, characterized in that, The clock delay unit includes: an eleventh resistor, a diode, and a fifth capacitor; One end of the eleventh resistor is connected to the negative terminal of the diode and the second terminal of the clock generation module, and the other end of the eleventh resistor is connected to the positive terminal of the diode, the first terminal of the second transistor, and one end of the fifth capacitor. The other end of the fifth capacitor is grounded. The eleventh resistor and the fifth capacitor delay the high-level clock signal when the clock generation module outputs a high-level clock signal to obtain a delayed high-level signal.
9. The circuit according to claim 1, characterized in that, The data shaping module includes: a fifth resistor, a sixth resistor, a seventh resistor, a second capacitor, and a first transistor; One end of the seventh resistor is connected to the output terminal of the voltage comparison module, and the other end of the seventh resistor is connected to one end of the fifth resistor, one end of the second capacitor, and the first terminal of the first transistor. The other end of the fifth resistor, the other end of the second capacitor, and the third terminal of the first transistor are all grounded. The second terminal of the first transistor is connected to one end of the sixth resistor and the second input terminal of the shift register, and the other end of the sixth resistor is connected to the second terminal of the reference voltage generation module.
10. A light-emitting device, characterized in that, Includes the single-wire serial lighting circuit as described in any one of claims 1-9.