Semiconductor device and preparation method thereof, and storage system

Abstract

The invention discloses a semiconductor device, a preparation method thereof and a storage system. The semiconductor device comprises a semiconductor body and a bit line, the semiconductor body extends in a first direction, the bit line is located on one side of the semiconductor body in the first direction, the bit line comprises a metal silicide layer and a bit line metal layer, the metal silicide layer is in contact with the semiconductor body, and the bit line metal layer is in contact with the semiconductor body. A portion of the metal silicide layer facing away from the semiconductor body in the first direction is located in the bit line metal layer.

Description

Semiconductor devices and their fabrication methods, storage systems Technical Field

[0001] The embodiments of this application relate to the field of semiconductor technology, and in particular to semiconductor devices and their fabrication methods and storage systems. Background Technology

[0002] Semiconductor devices are memory devices used to store information in modern information technology. Their main function is to store programs and various data, and to perform high-speed and automatic access to programs or data during computer operation. Taking DRAM (Dynamic Random Access Memory) as an example, DRAM typically includes multiple memory cells. Each memory cell includes a transistor and a capacitor structure. One end of the transistor is connected to the capacitor structure, and the other end of the transistor is connected to a bit line. Summary of the Invention

[0003] This application provides a semiconductor device, a method for fabricating the same, and a storage system.

[0004] The first aspect of this application provides a semiconductor device including a semiconductor body and a bit line. The semiconductor body extends along a first direction, and the bit line is located on one side of the semiconductor body in the first direction. The bit line includes a metal silicide layer and a bit line metal layer. The metal silicide layer is in contact with the semiconductor body, and a portion of the metal silicide layer facing away from the semiconductor body in the first direction is located within the bit line metal layer.

[0005] In some embodiments, the metal silicide layer includes a plurality of sub-silicide layers spaced apart in a second direction, the sub-silicide layers being in contact with the semiconductor substrate, and the second direction intersecting the first direction.

[0006] In some embodiments, the bit line metal layer extends along a second direction, a portion of the bit line metal layer is located in a first direction on the side of the sub-silicide layer away from the semiconductor body, and another portion of the bit line metal layer is located in the second direction between adjacent sub-silicide layers.

[0007] In some implementations, the subsilicide layer is in contact with two adjacent semiconductor bodies in a second direction.

[0008] In some embodiments, the metal silicide layer protrudes in a first direction from the surface of the bit line metal layer toward the semiconductor body and contacts the semiconductor body.

[0009] In some embodiments, the metal silicide layer includes a first silicide surface and a second silicide surface disposed opposite each other in a first direction, and the surface of the bit line metal layer facing the semiconductor body is located between the first silicide surface and the second silicide surface in the first direction.

[0010] In some implementations, the material of the metal silicide layer includes the same metal element as the material of the bit line metal layer.

[0011] In some implementations, the metallic element includes molybdenum.

[0012] In some embodiments, the bit line metal layer extends along a second direction, and the dimension of the bit line metal layer facing the semiconductor body in a third direction is the same as the dimension of the metal silicide layer in a third direction, with the first direction, the second direction, and the third direction intersecting each other.

[0013] In some embodiments, the bit line metal layer extends along a second direction, and the dimension of the side of the semiconductor body that contacts the metal silicide layer in a third direction is the same as the dimension of the metal silicide layer in a third direction, with the first direction, the second direction, and the third direction intersecting each other.

[0014] In some implementations, the bit line extends along a second direction, the size of the bit line in a third direction is less than 10 nm, the resistivity of the bit line is less than 500 ohm-cm, and the first direction, the second direction, and the third direction intersect each other.

[0015] In some implementations, the metal silicide layer is formed by an atomic layer deposition process.

[0016] In some embodiments, the semiconductor device further includes a gate structure located on at least a portion of the sidewall of the semiconductor body extending along a first direction.

[0017] A second aspect of this application provides a method for fabricating a semiconductor device, the method comprising: forming a semiconductor body extending along a first direction; and forming a bit line on one side of the semiconductor body along the first direction; wherein the bit line includes a metal silicide layer and a bit line metal layer, the metal silicide layer is in contact with the semiconductor body, and a portion of the metal silicide layer facing away from the semiconductor body in the first direction is located within the bit line metal layer.

[0018] In some implementations, a metal silicide layer is formed during the formation of the bit line metal layer.

[0019] In some implementations, the metal silicide layer and the bit line metal layer are formed in the same process.

[0020] In some implementations, the metal silicide layer and the bit line metal layer are formed by an atomic layer deposition process.

[0021] In some embodiments, forming a bit line on one side of the semiconductor body along a first direction includes: forming a bit line trench on one side of the semiconductor body along the first direction; and depositing metal material in the bit line trench using an atomic layer deposition process to form a metal silicide layer and a bit line metal layer in situ.

[0022] In some embodiments, depositing metal material in bit line trenches using atomic layer deposition to form a metal silicide layer and a bit line metal layer in situ includes: depositing metal material in bit line trenches such that a portion of the metal material reacts with a portion of the semiconductor substrate to form a metal silicide layer, and the remaining at least a portion of the metal material forms a bit line metal layer.

[0023] In some embodiments, depositing metal material in the bitline trench to form a metal silicide layer and a bitline metal layer in situ includes: using an atomic layer deposition process to deposit metal material in the bitline trench using a molybdenum-containing material as a precursor.

[0024] In some implementations, the precursor includes molybdenum pentachloride.

[0025] In some implementations, the deposition temperature of the atomic layer deposition process is less than 1000°C.

[0026] In some embodiments, forming a semiconductor body extending in a first direction includes: forming a plurality of first trenches spaced apart in a third direction and extending in a second direction from a first surface of a wafer; wherein the wafer includes a first surface and a second surface disposed opposite to the first surface; depositing a dielectric material in the first trenches to form a first dielectric layer; forming a plurality of second trenches spaced apart in the second direction and extending in a third direction from the first surface of the wafer; doping the bottom of the second trenches to form a doped layer; wherein the doped layer is located between the first surface and the second surface in the first direction; forming a third trench in the first surface of the wafer, located between adjacent second trenches and extending in a third direction, to divide a portion of the wafer in the first direction into a plurality of initial semiconductor bodies; and doping the ends of the initial semiconductor bodies from the first surface to form semiconductor bodies; wherein the size of the third trench in the first direction is larger than the size of the second trench in the first direction and smaller than the size of the first trench in the first direction.

[0027] In some embodiments, forming a bit line trench on one side of the semiconductor body along a first direction includes removing an undoped portion of the wafer from the side of the wafer away from the first surface to form the bit line trench.

[0028] A third aspect of this application provides a storage system, which includes a controller and a semiconductor device according to the first aspect of this application. The controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0029] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0030] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. The drawings are provided for a better understanding of the invention and are not intended to limit the scope of the application. In the drawings:

[0031] Figure 1 is a perspective view of a storage unit according to one embodiment of the present application;

[0032] Figure 2 is a cross-sectional schematic diagram of a semiconductor device according to one embodiment of this application;

[0033] Figures 3 to 7 are process schematic diagrams of a method for fabricating a semiconductor device according to one embodiment of this application;

[0034] Figure 8 is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of this application;

[0035] Figures 9 and 10 are process schematic diagrams of a method for fabricating a semiconductor device according to another embodiment of this application;

[0036] Figures 11 to 13 are schematic cross-sectional views of semiconductor devices according to other different embodiments of this application;

[0037] Figure 14 is a top view schematic diagram of a semiconductor device according to yet another embodiment of this application;

[0038] Figure 15 is a schematic flowchart of a method for fabricating a semiconductor device according to yet another embodiment of this application;

[0039] Figures 16 to 27 are schematic diagrams illustrating the fabrication process of a semiconductor device according to another embodiment of this application; and

[0040] Figure 28 is a block diagram of a system having semiconductor devices according to one embodiment of the present application.

[0041] Figure label:

[0042] 100. Wafer; 101. First surface; 102. Second surface; 103. First trench;

[0043] 104. Second trench; 105. Third trench; 110. Semiconductor body;

[0044] 110', Initial semiconductor body; 111, Source; 112, Drain; 113, Channel;

[0045] 120, doped layer; 200, bit line; 201, bit line trench; 210, metal silicide layer;

[0046] 211. Sub-silicide layer; 212. First silicide surface; 213. Second silicide surface;

[0047] 220. Bit line metal layer; 230. First metal layer; 240. Protective layer;

[0048] 250. First metal silicide layer; 251. High-resistivity metal silicide layer;

[0049] 252. Low-resistivity metal silicide layer; 260. Second metal layer; 270. Bit line bonding layer;

[0050] 280, Third metal layer; 300, Gate structure; 300', Initial gate structure;

[0051] 310 Gate dielectric layer; 320 Gate conductive layer; 330 Gate adhesive layer;

[0052] 340, Gate isolation layer; 350, Gate notch structure; 400, Isolation structure;

[0053] 401. Air gap; 410. Insulating dielectric layer; 420. Insulating conductive layer;

[0054] 500, First dielectric layer; 600, Capacitor structure; 601, Capacitor via;

[0055] 610. First electrode layer; 620. Second electrode layer; 630. Capacitor dielectric layer;

[0056] 640, Support core; 700, Contact structure; 710, Semiconductor layer;

[0057] 720, Second metal silicide layer; 730, Fourth metal layer; 800, Filler dielectric layer;

[0058] 810, Second dielectric layer; 900, System; 901, Memory system;

[0059] 902. Semiconductor device; 903. Memory controller; 904. Host computer. Detailed Implementation

[0060] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0061] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence.

[0062] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale.

[0063] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0064] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0065] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0066] Furthermore, in this application, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a range smaller than that of the structure below or above. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. Furthermore, in this application, the use of "connection" or "joint" may indicate direct or indirect contact between corresponding components, unless otherwise expressly defined or inferred from the context.

[0067] With the rapid development of semiconductor technology, the size of DRAM memory cells is getting smaller and smaller, and their array architecture has expanded from 8F... 2 Developed to 6F 2 And from 6F 2 Developed to 4F 2 The architecture of memory has evolved from planar array transistors to recessed gate array transistors, then from recessed gate array transistors to buried saddle fin array transistors, and finally from buried saddle fin array transistors to vertical gate transistors.

[0068] As shown in Figure 1, DRAM typically includes multiple memory cells. Each memory cell includes a transistor and a capacitor structure 600. Its main working principle is to use the amount of charge stored in the capacitor structure 600 to represent whether a binary bit is 1 or 0. The transistor typically includes a semiconductor body 110 and a gate structure 300. The drain 112 of the semiconductor body 110 is electrically connected to the bit line 200 (BL), and the source 111 of the semiconductor body 110 is electrically connected to one electrode of the capacitor structure 600. The other electrode of the capacitor structure 600 can be grounded or connected to a reference voltage. The gate structure 300 of the transistor is electrically connected to the word line (WL). The word line is used to apply voltage to control the transistor's conduction or cutoff, and the bit line 200 is used to perform read or write operations on the capacitor structure 600 when the transistor is on.

[0069] This application provides a semiconductor device. FIG2 shows a schematic cross-sectional view of the semiconductor device in one embodiment of this application in the xz plane. As shown in FIG2, the semiconductor device includes a semiconductor body 110 and a bit line 200. The semiconductor body 110 extends along a first direction, and the bit line 200 is located on one side of the semiconductor body 110 in the first direction. The bit line 200 includes a first metal silicide layer 250, which extends along a second direction, and the first direction intersects with the second direction.

[0070] Figures 3 to 7 illustrate process diagrams of a semiconductor device fabrication method according to one embodiment of this application; wherein, Figure 3 shows a yz-plane cross-sectional view of the semiconductor body 110 formed in an embodiment of this application; Figure 4 shows a yz-plane cross-sectional view of the first metal layer 230 formed in an embodiment of this application; Figure 5 shows a yz-plane cross-sectional view of the high-resistivity metal silicide layer 251 formed by annealing in an embodiment of this application; Figure 6 shows a yz-plane cross-sectional view of the unreacted first metal layer 230 removed in an embodiment of this application; and Figure 7 shows a yz-plane cross-sectional view of the low-resistivity metal silicide layer 252 formed by annealing in an embodiment of this application.

[0071] As shown in Figures 3 to 7, the fabrication method includes: as shown in Figure 3, forming a semiconductor body 110 on a portion of a wafer 100 in a first direction; wherein the material of the wafer 100 can be any suitable semiconductor material, such as a single-element semiconductor material like silicon or germanium, or a composite semiconductor material like silicon-on-insulator (SOI) or germanium-on-insulator (GeOI); as shown in Figure 4, forming a first metal layer 230 on the remaining side of the wafer 100 where the semiconductor body 110 is not formed; for example, a Ni thin film or a NiPt thin film can be deposited on the surface of the wafer 100. To prevent the first metal layer 230 from being oxidized during subsequent rapid thermal annealing (RTA), a protective layer 240 can also be formed on the side of the first metal layer 230 facing away from the wafer 100, and the material of the protective layer 240 can include, but is not limited to, titanium nitride. As shown in Figure 5, the first metal layer 230 undergoes rapid thermal annealing. During annealing, the first metal layer 230 reacts with at least a portion of the wafer 100 to form a high-resistivity metal silicide layer 251. The growth of the high-resistivity metal silicide requires wafer 100; for every x thickness of metal silicide grown, wafer 100 of thickness y is required. For example, NiPt reacts with wafer 100 to form high-resistivity Ni2Si, which has a high resistivity. As shown in Figure 6, the protective layer 240 and the remaining unreacted first metal layer 230 are removed by selective wet etching. As shown in Figure 7, the high-resistivity metal silicide layer 251 undergoes rapid thermal annealing to convert it into a low-resistivity metal silicide layer 252. For example, after a second annealing process, the high-resistivity Ni2Si is converted into the low-resistivity NiSi, which is the first metal silicide layer 250.

[0072] This application also provides another semiconductor device. FIG8 shows a schematic cross-sectional view of the semiconductor device according to another embodiment of this application in the xz plane. As shown in FIG8, the semiconductor device includes a semiconductor body 110 and a bit line 200. The semiconductor body 110 extends along a first direction, and the bit line 200 is located on one side of the semiconductor body 110 in the first direction. The bit line 200 includes a second metal layer 260, a bit line bonding layer 270, and a third metal layer 280. The bit line bonding layer 270 and the third metal layer 280 are located on the side of the second metal layer 260 away from the semiconductor body 110. At least a portion of the bit line bonding layer 270 is located between the second metal layer 260 and the third metal layer 280 in the first direction. The material of the second metal layer 260 may include, but is not limited to, titanium, and the material of the third metal layer 280 may include, but is not limited to, tungsten.

[0073] Figures 9 and 10 show process schematic diagrams of a semiconductor device fabrication method according to another embodiment of this application; wherein, Figure 9 shows a yz plane cross-sectional schematic diagram of forming a bit line trench 201 in an embodiment of this application; and Figure 10 shows a yz plane cross-sectional schematic diagram of forming a bit line 200 in the bit line trench 201 in an embodiment of this application.

[0074] As shown in Figures 9 and 10, the fabrication method includes: forming a bit line trench 201 on one side of the semiconductor body 110, as shown in Figure 9; forming a second metal layer 260 in the bit line trench 201, as shown in Figure 10; forming a bit line adhesive layer 270 on the inner wall of the remaining space of the bit line trench 201, the bit line adhesive layer 270 forming an adhesive groove; and forming a third metal layer 280 in the adhesive groove.

[0075] This application also provides another semiconductor device. Figures 11 to 13 show cross-sectional views of the semiconductor devices according to different embodiments of this application in the xz plane; Figure 14 shows a top view of the semiconductor device according to one embodiment of this application in the xy plane.

[0076] As shown in Figures 11 to 13, the semiconductor device includes a semiconductor body 110 and a bit line 200. The semiconductor body 110 extends along a first direction, and the bit line 200 is located on one side of the semiconductor body 110 in the first direction. The bit line 200 includes a metal silicide layer 210 and a bit line metal layer 220. The metal silicide layer 210 is in contact with the semiconductor body 110, and the portion of the metal silicide layer 210 that is away from the semiconductor body 110 in the first direction is located within the bit line metal layer 220.

[0077] It should be noted that the semiconductor device provided in the embodiments of this application can be a memory or a part of a memory. For example, the memory may include peripheral circuits and the aforementioned semiconductor device, with the peripheral circuits coupled to the semiconductor device. In this case, the aforementioned semiconductor device is part of the memory. As another example, the memory may be a memory array, in which case the memory array is the aforementioned semiconductor device. As an example, in the embodiments of this application, the first direction may be the z-direction shown in the figures.

[0078] In some embodiments, the metal silicide layer 210 includes a plurality of sub-silicide layers 211 spaced apart in a second direction. The sub-silicide layers 211 are in contact with the semiconductor body 110, and the second direction intersects the first direction. The intersection of the first and second directions generally means that the first and second directions form an angle. For example, the first and second directions are perpendicular or approximately perpendicular to each other. For example, in the embodiments of this application, the first direction can be the z-direction in the figures, and the second direction can be the x-direction in the figures.

[0079] As an example, the subsilicide layer 211 is in contact with two adjacent semiconductor bodies 110 in the second direction. For example, if the semiconductor device also includes an isolation structure 400, the two semiconductor bodies 110 located on both sides of the isolation structure 400 in the second direction are in contact with the same subsilicide layer 211.

[0080] As shown in Figure 11, the bit line metal layer 220 extends along the second direction. A portion of the bit line metal layer 220 is located on the side of the sub-silicide layer 211 away from the semiconductor body 110 in the first direction, and another portion of the bit line metal layer 220 is located between adjacent sub-silicide layers 211 in the second direction.

[0081] In some embodiments, the metal silicide layer 210 protrudes in a first direction from the surface of the bit line metal layer 220 facing the semiconductor body 110 and contacts the semiconductor body 110. As shown in FIG11, the metal silicide layer 210 includes a first silicide surface 212 and a second silicide surface 213 disposed opposite to each other in a first direction, and the surface of the bit line metal layer 220 facing the semiconductor body 110 is located between the first silicide surface 212 and the second silicide surface 213 in the first direction. As an example, a portion of the metal silicide layer 210 is located within the bit line metal layer 220, and another portion of the metal silicide layer 210 is located on the side of the bit line metal layer 220 facing the semiconductor body 110 and contacts the semiconductor body 110.

[0082] In some embodiments, the metal silicide layer 210 and the bit line metal layer 220 can be formed in the same process. As an example, the metal silicide layer 210 and the bit line metal layer 220 can be formed by atomic layer deposition (ALD) process.

[0083] In some embodiments, the material of the metal silicide layer 210 and the material of the bit line metal layer 220 may include the same metal element. For example, both the material of the metal silicide layer 210 and the material of the bit line metal layer 220 include molybdenum. It should be noted that, in addition to molybdenum, other metal materials suitable for atomic layer deposition processes and capable of reacting with the semiconductor substrate 110 at high temperatures such as below 1000°C to form metal silicides can also be used as the material of the bit line metal layer 220, and this application does not limit this.

[0084] In some embodiments, the bit line metal layer 220 extends along a second direction, and the dimension of the side of the bit line metal layer 220 facing the semiconductor body 110 in the third direction is the same as the dimension of the metal silicide layer 210 in the third direction, with the first direction, second direction, and third direction intersecting each other. Those skilled in the art should understand that the extension of the bit line metal layer 220 along the second direction generally means that the dimension of the bit line metal layer 220 in the second direction is larger than the dimension of the bit line metal layer 220 in the third direction. Furthermore, the statement that the dimension of the side of the bit line metal layer 220 facing the semiconductor body 110 in the third direction is the same as the dimension of the metal silicide layer 210 in the third direction generally means that the two dimensions are completely equal or have a slight deviation, for example, the difference between the two dimensions does not exceed 15% of either of the two dimensions.

[0085] In some embodiments, the bit line metal layer 220 extends along a second direction, and the side of the semiconductor body 110 that contacts the metal silicide layer 210 has the same dimension in a third direction as the metal silicide layer 210 in a third direction. As an example, the semiconductor body 110 includes a first end and a second end disposed opposite to each other in a first direction, the first end being closer to the bit line metal layer 220 than the second end. The first end of the semiconductor body 110 contacts the metal silicide layer 210, and the dimension of the first end in a third direction is the same as the dimension of the metal silicide layer 210 in a third direction. Those skilled in the art will understand that "the dimension of the first end in a third direction is the same as the dimension of the metal silicide layer 210 in a third direction" generally means that the dimensions are completely equal or have a slight deviation, for example, the difference in dimensions does not exceed 15% of either of the two dimensions.

[0086] In the above text, the intersection of the first direction, the second direction, and the third direction can generally be understood as the first direction and the second direction forming an angle, the second direction and the third direction forming an angle, and the first direction and the third direction forming an angle. As an example, in the embodiments of this application, the first direction can be the z-direction in the attached figures, the second direction can be the x-direction in the attached figures, and the third direction can be the y-direction in the attached figures.

[0087] In some embodiments, bit line 200 includes a metal silicide layer 210 and a bit line metal layer 220. Bit line 200 extends along a second direction, has a dimension of less than 10 nm in a third direction, and has a resistivity of less than 500 ohm-cm. The first, second, and third directions intersect each other. Those skilled in the art will understand that when bit line 200 is jointly composed of bit line metal layer 220 and metal silicide layer 210, the resistivity of bit line 200 generally refers to the equivalent resistivity of bit line metal layer 220 and metal silicide layer 210. As an example, the dimension of metal silicide layer 210 in the first direction is smaller than the dimension of bit line metal layer 220 in the first direction. If the size of the metal silicide layer 210 in the first direction is much smaller than the size of the bit line metal layer 220 in the first direction, then when the bit line 200 is composed of the bit line metal layer 220 and the metal silicide layer 210, the resistivity of the bit line 200 is almost equal to the resistivity of the bit line metal layer 220. In other words, the resistivity of the bit line 200 is mainly the resistivity of the bit line metal layer 220.

[0088] In some embodiments, the bit line 200 has a dimension of 20 nm in the third direction and a dimension of 10 nm in the first direction. In this case, if the bit line 200 includes a first metal silicide layer 250, the resistivity of the bit line 200 can be 700 ohm-cm; if the bit line 200 includes a second metal layer 260, a bit line adhesive layer 270, and a third metal layer 280, the resistivity of the bit line 200 can be 906 ohm-cm; if the bit line 200 includes a metal silicide layer 210 and a bit line metal layer 220, the resistivity of the bit line 200 can be 173 ohm-cm. It is evident that the resistivity of the bit line 200 is lower when the bit line 200 includes a metal silicide layer 210 and a bit line metal layer 220.

[0089] In other embodiments, the bit line 200 has a dimension of 10 nm in the third direction and a dimension of 10 nm in the first direction. In this case, if the bit line 200 includes a first metal silicide layer 250, the resistivity of the bit line 200 can be 1400 ohm-cm; if the bit line 200 includes a second metal layer 260, a bit line adhesive layer 270, and a third metal layer 280, the resistivity of the bit line 200 can be 3280 ohm-cm; if the bit line 200 includes a metal silicide layer 210 and a bit line metal layer 220, the resistivity of the bit line 200 can be 347 ohm-cm. It is evident that the resistivity of the bit line 200 is lower when the bit line 200 includes a metal silicide layer 210 and a bit line metal layer 220.

[0090] In some embodiments, the semiconductor device may further include a gate structure 300 located on at least a portion of the sidewall of the semiconductor body 110 extending along a first direction. As an example, the gate structure 300 may include a gate dielectric layer 310 and a gate conductive layer 320, with the gate dielectric layer 310 located on the sidewall of the semiconductor body 110 and the gate conductive layer 320 located on the side of the gate dielectric layer 310 facing away from the semiconductor body 110. The material of the gate dielectric layer 310 may include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, or high-k materials such as hafnium oxide, zirconium oxide, aluminum oxide, and tantalum oxide; the material of the gate conductive layer 320 may include tungsten, aluminum, titanium, copper, cobalt, or tungsten nitride. As shown in FIG12, to improve the adhesion between the gate conductive layer 320 and the gate dielectric layer 310, the gate structure 300 may further include a gate adhesive layer 330 located between the gate dielectric layer 310 and the gate conductive layer 320. The material of the gate adhesive layer 330 may include, but is not limited to, at least one of titanium nitride, tantalum nitride, and tungsten carbide.

[0091] It should be noted that the gate structure 300 may cover part or all of the sidewalls of the semiconductor body 110. Therefore, the transistor can be classified as a single-gate transistor, a dual-gate transistor, a tri-gate transistor, or a gate all-around (GAA) transistor. Specifically, in a single-gate transistor, the gate structure 300 may be located only on one side of the semiconductor body 110 in the direction intersecting the first direction; in a dual-gate transistor, the gate structure 300 may be located on opposite sides of the semiconductor body 110 in the direction intersecting the first direction; in a tri-gate transistor, the gate structure 300 partially surrounds the semiconductor body 110 in the direction intersecting the first direction; and in a GAA transistor, the gate structure 300 surrounds the semiconductor body 110 in the direction intersecting the first direction. For example, the semiconductor body 110 includes a first and a second sidewall facing away from each other in the second direction, and a third and a fourth sidewall facing away from each other in the third direction, with the first, second, and third directions intersecting each other. If the gate structure 300 is located on any one of the first, second, third, and fourth sidewalls of the semiconductor body 110, then the transistor formed by it and the semiconductor body 110 is a single-gate transistor; if the gate structure 300 is located on the first and second (third and fourth) sidewalls of the semiconductor body 110, then the transistor formed by it and the semiconductor body 110 is a dual-gate transistor; if the gate structure 300 is located on any three of the first, second, third, and fourth sidewalls of the semiconductor body 110, then the transistor formed by it and the semiconductor body 110 is a tri-gate transistor; if the gate structure 300 is located on the first, second, third, and fourth sidewalls of the semiconductor body 110, then the transistor formed by it and the semiconductor body 110 is a full-ring gate transistor.

[0092] Taking a single-gate transistor as an example, the semiconductor device may further include an isolation structure 400, which is located on one side of the semiconductor body 110 in a second direction and extends along a third direction. A gate structure 300 is located on the side of the semiconductor body 110 opposite to the isolation structure 400 in the second direction and extends along a third direction. In some embodiments, the isolation structure 400 has an air gap 401, and the material of the isolation structure 400 may include, but is not limited to, silicon oxide, silicon oxynitride, or silicon nitride. In other embodiments, as shown in FIG13, the isolation structure 400 may include an isolation dielectric layer 410 and an isolation conductive layer 420, with the isolation dielectric layer 410 located on the sidewall of the isolation conductive layer 420 extending along a first direction. The material of the isolation dielectric layer 410 may include, but is not limited to, silicon oxide, silicon oxynitride, or silicon nitride; the material of the isolation conductive layer 420 may include, but is not limited to, at least one of tungsten, titanium nitride, copper, and silver.

[0093] In some embodiments, the semiconductor device may further include a capacitor structure 600 located on the side of the semiconductor body 110 away from the bit line 200 in a first direction. As an example, as shown in FIG11, the capacitor structure 600 may include a first electrode layer 610, a second electrode layer 620, and a capacitor dielectric layer 630. The second electrode layer 620 extends along the first direction, and the capacitor dielectric layer 630 is located on the sidewall of the second electrode layer 620 extending along the first direction and on the end face of the second electrode layer 620 facing the semiconductor body 110. The first electrode layer 610 is located on the side of the capacitor dielectric layer 630 away from the second electrode layer 620. As an example, the first electrode layer 610 has a cylindrical structure, the second electrode layer 620 is located inside the first electrode layer 610, and the capacitor dielectric layer 630 is located between the first electrode layer 610 and the second electrode layer 620.

[0094] In the above embodiments, the first electrode layer 610 is located outside the second electrode layer 620. In other embodiments, the first electrode layer 610 may also be located inside the second electrode layer 620. For example, as shown in Figures 12 and 13, the capacitor structure 600 may include a first electrode layer 610, a second electrode layer 620, and a capacitor dielectric layer 630. The first electrode layer 610 extends along a first direction, the capacitor dielectric layer 630 is located on a portion of the sidewall of the first electrode layer 610 extending along the first direction, and the second electrode layer 620 is located on the side of the capacitor dielectric layer 630 opposite to the first electrode layer 610. In this case, the first electrode layer 610 may be a cylindrical structure or a columnar structure.

[0095] For example, as shown in Figure 12, the first electrode layer 610 can be a cylindrical structure, the capacitor dielectric layer 630 is located on a portion of the outer wall of the first electrode layer 610, and the second electrode layer 620 is located on the side of the capacitor dielectric layer 630 away from the first electrode layer 610. In this case, the capacitor structure 600 may also include a support core 640 extending along a first direction, the first electrode layer 610 being located on the sidewall of the support core 640 extending along the first direction and the end face of the support core 640 facing the semiconductor body 110. The material of the support core 640 may include, but is not limited to, elemental semiconductor materials such as silicon (Si), composite semiconductor materials such as germanium silicon (GeSi), or polycrystalline silicon doped with dopants such as boron. As another example, as shown in Figure 13, the first electrode layer 610 can be a columnar structure, the capacitor dielectric layer 630 is located on a portion of the sidewall of the first electrode layer 610, and the second electrode layer 620 is located on the side of the capacitor dielectric layer 630 away from the first electrode layer 610. It should be noted that, in addition to the above-described structural form, the capacitor structure 600 in the embodiments of this application may also adopt other structural forms suitable for this application.

[0096] The materials of the first electrode layer 610 and the second electrode layer 620 mentioned above can be the same or different. The materials of the first electrode layer 610 and the second electrode layer 620 can include, but are not limited to, at least one of metals, metal compounds, semiconductor materials, and silicides; for example, the materials of the first electrode layer 610 and the second electrode layer 620 can include titanium nitride, titanium silicide, or nickel silicide. The material of the capacitor dielectric layer 630 can include, but is not limited to, at least one of aluminum oxide, tantalum oxide, titanium oxide, yttrium oxide, zirconium oxide, zirconium silicon oxide, hafnium oxide, hafnium silicon oxide, hafnium silicon nitride, hafnium zirconate, lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium aluminum oxide, and praseodymium oxide.

[0097] To reduce the contact resistance between the semiconductor body 110 and the capacitor structure 600, a contact structure 700 can also be provided between the semiconductor body 110 and the capacitor structure 600. In other words, the contact structure 700 is located between the semiconductor body 110 and the capacitor structure 600 in a first direction and contacts both the semiconductor body 110 and the capacitor structure 600. As an example, the contact structure 700 includes a semiconductor layer 710, a second metal silicide layer 720, and a fourth metal layer 730. The second metal silicide layer 720 is located on the side of the semiconductor layer 710 away from the semiconductor body 110, and the fourth metal layer 730 is located on the side of the second metal silicide layer 720 away from the semiconductor layer 710. The semiconductor layer 710 may be made of, but is not limited to, a single semiconductor material such as silicon (Si), a composite semiconductor material such as germanium silicon (GeSi), or polycrystalline silicon doped with a dopant such as boron; the second metal silicide layer 720 may be made of, but is not limited to, titanium silicide or cobalt silicide; and the fourth metal layer 730 may be made of, but is not limited to, at least one of tungsten, titanium nitride, copper, and silver.

[0098] In some embodiments, the semiconductor body 110 may include a source 111, a drain 112, and a channel 113 located between the source 111 and the drain 112 in a first direction. The semiconductor body 110 and the gate structure 300 constitute a transistor. The source 111 is connected to the capacitor structure 600, and the drain 112 is connected to the bit line 200. The gate structure 300 can be a word line, used to apply voltage to control the transistor's on or off state. The bit line 200 is used to perform read or write operations on the capacitor structure 600 when the transistor is on. The amount of charge stored in the capacitor structure 600 represents whether a binary bit is 1 or 0.

[0099] As an example, the source 111 and / or drain 112 may include a heavily doped layer and a lightly doped layer (not shown), the heavily doped layer being located on the side of the lightly doped layer away from the channel 113 in a first direction, and the doping concentration of the heavily doped layer being greater than that of the lightly doped layer.

[0100] Figure 15 shows a flow chart of a method for fabricating a semiconductor device according to one embodiment of this application, and Figures 16 to 27 show process diagrams of a method for fabricating a semiconductor device according to one embodiment of this application. As shown in Figures 15 to 27, the fabrication method 1000 includes:

[0101] S100, Forming a semiconductor body 110 extending along the first direction;

[0102] S110, A bit line 200 is formed on one side of the semiconductor body 110 along a first direction; wherein, the bit line 200 includes a metal silicide layer 210 and a bit line metal layer 220, the metal silicide layer 210 is in contact with the semiconductor body 110, and the portion of the metal silicide layer 210 that is away from the semiconductor body 110 in the first direction is located within the bit line metal layer 220.

[0103] The following is a detailed description of each step in the semiconductor device fabrication method in the embodiments of this application.

[0104] Step S100

[0105] In step S100, a semiconductor body 110 is formed, and the semiconductor body 110 extends along a first direction. The shape of the projection of the semiconductor body 110 onto a plane perpendicular to the first direction may be, but is not limited to, a rectangle, a circle, an ellipse, a semicircle, or any other arbitrary shape, and this application does not limit it in this regard.

[0106] Figure 16 shows a yz-plane cross-sectional view of the first trench 103 formed in the wafer 100 according to an embodiment of the present application; Figure 18 shows an xz-plane cross-sectional view of the second trench 104 formed in the wafer 100 according to an embodiment of the present application; Figure 20 shows an xz-plane cross-sectional view of the isolation structure 400 formed in the second trench 104 and the initial gate structure 300' formed in the third trench 105 according to an embodiment of the present application; Figure 21 shows an xz-plane cross-sectional view of the semiconductor body 110 formed based on the initial semiconductor body 110' according to an embodiment of the present application.

[0107] As an example, the semiconductor body 110 can be formed as follows: as shown in FIG16, a plurality of first trenches 103 are formed in the wafer 100, spaced apart in a third direction and all extending along a second direction; wherein, the material of the wafer 100 can be any suitable semiconductor material, such as a single semiconductor material such as silicon (Si) or germanium (Ge), or a composite semiconductor material such as silicon-on-insulator (SOI) or germanium-on-insulator (GeOI); as shown in FIG18, a plurality of second trenches 104 are formed in the wafer 100, spaced apart in the second direction and all extending along a third direction; as shown in FIG20, a third trench 105 is formed in the wafer 100, located between adjacent second trenches 104 and extending along a third direction, wherein the size of the third trench 105 in the first direction is larger than the size of the second trench 104 in the first direction and smaller than the size of the first trench 103 in the first direction. Thus, the first trench 103, the second trench 104, and the third trench 105 together divide at least a portion of the wafer 100 in the first direction into a plurality of initial semiconductor bodies 110'; as shown in FIG21, semiconductor bodies 110 are formed based on the initial semiconductor bodies 110'. For example, the semiconductor body 110 includes a source 111, a drain 112, and a channel 113 located between the source 111 and the drain 112 in the first direction, wherein the source 111 and the drain 112 can be formed by doping. The first trench 103, the second trench 104, and the third trench 105 can be formed in the wafer 100 by, but is not limited to, wet etching processes, dry etching processes such as plasma etching or reactive ion etching, or any combination of the above processes.

[0108] It should be noted that the above steps can be performed in parallel, sequentially, or in different orders, as long as the semiconductor body 110 can be formed. This application does not limit this. For example, the source 111 and drain 112 can be formed by two doping processes, one of which can be performed before the formation of the third trench 105, and the other of which can be performed after the formation of the third trench 105.

[0109] In some embodiments, the fabrication method may further include forming a gate structure 300 on at least a portion of the sidewalls extending along a first direction of the initial semiconductor body 110'. After forming the gate structure 300, a semiconductor body 110 can be formed based on the initial semiconductor body 110', and the semiconductor body 110 and the gate structure 300 together constitute a transistor. As described above, the gate structure 300 may cover a portion of the sidewalls of the semiconductor body 110 or may cover all of the sidewalls of the semiconductor body 110. Thus, the transistor can be classified as a single-gate transistor, a dual-gate transistor, a tri-gate transistor, or a gate all-around (GAA) transistor.

[0110] Figure 17 shows a schematic cross-sectional view of the yz plane of the first dielectric layer 500 formed in an embodiment of the present application; Figure 19A shows a schematic cross-sectional view of the xz plane of the doped layer 120 formed in an embodiment of the present application; Figure 19B shows a schematic cross-sectional view of the yz plane of the doped layer 120 formed in an embodiment of the present application.

[0111] The following is an example of a method for forming a single-gate transistor: A wafer 100 is provided, including a first surface 101 and a second surface 102 disposed opposite to each other in a first direction. As shown in FIG. 16, a plurality of first trenches 103 are formed in the wafer 100 from the first surface 101, spaced apart in a third direction and extending along a second direction. As an example, the size of the first trenches 103 in the first direction may be smaller than the size of the wafer 100 in the first direction; in other words, the first trenches 103 do not penetrate the wafer 100. As shown in FIG. 17, a dielectric material is deposited in the first trenches 103 to form a first dielectric layer 500. The material of the first dielectric layer 500 may include, but is not limited to, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxide. As shown in FIG. 18, a plurality of second trenches 104 are formed in the wafer 100 from the first surface 101, spaced apart in the second direction and extending along a third direction. As shown in Figures 19A and 19B, the bottom of the second trench 104 is doped to form a doped layer 120, which is located between the first surface 101 and the second surface 102 in a first direction. As shown in Figure 20, an isolation structure 400 is formed within the second trench 104. A third trench 105 is formed in the wafer 100 from the first surface 101, located between adjacent second trenches 104 and extending along a third direction. The third trench 105 penetrates the doped layer 120 in a first direction to divide the doped layer 120 into a plurality of drains 112. As an example, the dimension of the third trench 105 in the first direction is larger than the dimension of the second trench 104 in the first direction and smaller than the dimension of the first trench 103 in the first direction. Thus, the first trench 103, the second trench 104, and the third trench 105 together divide a portion of the wafer 100 in the first direction into multiple initial semiconductor bodies 110'; an initial gate structure 300' is formed in the third trench 105; the initial gate structure 300' is divided into two gate structures 300 disposed opposite each other in the second direction; as shown in FIG21, the ends of the initial semiconductor bodies 110' are doped from the first surface 101 to form a source 111. Thus, the semiconductor body 110 can be formed after the above two doping processes. The semiconductor body 110 includes a source 111, a drain 112, and a channel 113 located between the source 111 and the drain 112 in the first direction. The source 111 and the drain 112 can be both doped with P-type dopant or both doped with N-type dopant. The dopant of the source 111 and the drain 112 can be the same or different. For example, the dopants mentioned above may include, but are not limited to, boron (B), aluminum (Al), gallium (Ga), phosphorus (P), arsenic (As), or antimony (Sb).

[0112] As an example, as shown in FIG20, the initial gate structure 300' may include a gate dielectric layer 310 and a gate conductive layer 320. The initial gate structure 300' may be formed as follows: a gate dielectric layer 310 is formed on the inner wall of the third trench 105; wherein, the gate dielectric layer 310 may be formed by in-situ oxidation of the inner wall of the third trench 105 or by a thin film deposition process, and the material of the gate dielectric layer 310 may include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, or high-k materials such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide; a gate conductive layer 320 is formed on the side of the gate dielectric layer 310 opposite to the inner wall of the third trench 105, and the material of the gate conductive layer 320 may include, but is not limited to, polysilicon, metal, metal compound, silicide, or any combination thereof. For example, the material of the gate conductive layer 320 may include tungsten, aluminum, titanium, copper, cobalt, or tungsten nitride. Furthermore, to improve the adhesion between the gate conductive layer 320 and the gate dielectric layer 310, the initial gate structure 300' may also include a gate adhesive layer 330. Thus, before forming the gate conductive layer 320, the gate adhesive layer 330 may be formed on the side of the gate dielectric layer 310 facing away from the inner wall of the third trench 105. The material of the gate adhesive layer 330 may include, but is not limited to, at least one of titanium nitride, tantalum nitride, and tungsten carbide.

[0113] The gate dielectric layer 310, the gate conductive layer 320, and the gate adhesive layer 330 can all be formed by thin film deposition processes. The thin film deposition process can be, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination of the above processes.

[0114] After the initial gate structure 300' is formed, it can be divided into two gate structures 300 as follows: At least a portion of the initial gate structure 300' located on the bottom surface of the third trench 105 is removed through a punching process, so that the remaining initial gate structure 300' covers the sidewalls of the third trench 105 extending in the first direction and forms a ring. A gate isolation layer 340 is formed within the gap formed by the initial gate structure 300'. The material of the gate isolation layer 340 may include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, or high-k materials such as hafnium oxide, zirconium oxide, aluminum oxide, and tantalum oxide. A gate trench (not shown) is formed by removing a portion of the initial gate structure 300' from the first surface 101 of the wafer 100. An isolation material is filled within the gate trench. The isolation material may be the same as or different from the material of the gate dielectric layer 310 and the gate isolation layer 340. If all three are the same, then there may be no obvious detectable interface between the isolation material filling the gate trench and the gate dielectric layer 310, and between the isolation material and the gate isolation layer 340. Gate cutout structures 350 are formed at both ends of the remaining initial gate structure 300' along a third direction. The gate cutout structures 350 penetrate the initial gate structure 300' along a first direction to divide the remaining initial gate structure 300' into two gate structures 300 disposed opposite each other in a second direction.

[0115] As an example, the isolation structure 400 can be formed by depositing a medium material within the second trench 104. As an example, the isolation structure 400 may have an air gap 401. When forming the isolation structure 400, two different deposition rates can be used to deposit the isolation material within the second trench 104. For example, a first deposition rate can be used to form one part of the isolation structure 400 on the inner wall of the second trench 104, while a second deposition rate greater than the first deposition rate can be used to form another part of the isolation structure 400 at the opening of the second trench 104. Because the second deposition rate is greater than the first deposition rate, when both parts are deposited simultaneously, the isolation material at the opening of the second trench 104 will quickly seal the opening. However, because the first deposition rate is slower, after sealing, some space within the second trench 104 remains unfilled with isolation material, thus forming the air gap 401. Because the air gap 401 has a low dielectric constant, close to that of a vacuum, its presence can reduce the overall dielectric constant of the isolation structure 400, thereby reducing parasitic capacitance and thus reducing electrical interference between two adjacent semiconductor bodies 110. During the formation of the air gap 401, its size and position can be adjusted by controlling the first deposition rate and the second deposition rate. The larger the ratio between the second deposition rate and the first deposition rate, the larger the air gap 401 formed within the isolation structure 400, and the better its effect in reducing parasitic capacitance. For example, the ratio α between the second deposition rate and the first deposition rate can range from 1 ≤ α ≤ 3. As an example, the ratio α can range from 1.5 ≤ α ≤ 2. Furthermore, those skilled in the art should understand that, without departing from the technical solutions claimed in this application, the structure, composition, and fabrication process of the isolation structure 400 with the air gap 401 can be modified to obtain the various results and advantages described in this specification.

[0116] It should be noted that, in addition to improving the isolation effect through the air gap 401, the isolation structure 400 can also improve the isolation effect by setting an isolation conductive layer 420. Subsequently, grounding or connecting the isolation conductive layer 420 to a negative voltage can improve the coupling effect between two adjacent transistors. As an example, the isolation structure 400 may include an isolation dielectric layer 410 and an isolation conductive layer 420. The isolation structure 400 can be formed as follows: An isolation material is deposited on the inner wall of the second trench 104. The isolation material may include, but is not limited to, silicon oxide, silicon oxynitride, or silicon nitride. A conductive material is filled into the remaining space of the second trench 104. The conductive material may include, but is not limited to, at least one of tungsten, titanium nitride, copper, and silver. At least a portion of the conductive material is removed to form an isolation trench. An isolation material is deposited within the isolation trench. Thus, all the isolation material within the second trench 104 constitutes the isolation dielectric layer 410, and the remaining conductive material constitutes the isolation conductive layer 420. The isolation dielectric layer 410 surrounds the isolation conductive layer 420.

[0117] Step S110

[0118] In step 210, a bit line 200 is formed on one side of the semiconductor body 110 along a first direction. The bit line 200 may include a metal silicide layer 210 and a bit line metal layer 220. The metal silicide layer 210 is in contact with the semiconductor body 110, and the portion of the metal silicide layer 210 facing away from the semiconductor body 110 in the first direction is located within the bit line metal layer 220. As an example, the metal silicide layer 210 can be formed during the formation of the bit line metal layer 220; in other words, the metal silicide layer 210 and the bit line metal layer 220 can be formed in the same process. For example, the metal silicide layer 210 and the bit line metal layer 220 are formed by atomic layer deposition (ALD) process.

[0119] Figure 22A shows a cross-sectional view of the wafer 100 thinned in an embodiment of this application; Figure 22B shows a cross-sectional view of the wafer 100 thinned in an embodiment of this application; Figure 23A shows a cross-sectional view of the bit line trench 201 formed by removing the undoped portion of the wafer 100 in an embodiment of this application; Figure 23B shows a cross-sectional view of the bit line trench 201 formed by removing the undoped portion of the wafer 100 in an embodiment of this application; Figure 24 shows a cross-sectional view of the metal silicide layer 210 and the bit line metal layer 220 formed in an embodiment of this application; Figure 25A shows a cross-sectional view of the bit line metal layer 220 covering the first dielectric layer 500 in an embodiment of this application; Figure 25B shows a cross-sectional view of the bit line metal layer 220 covering the first dielectric layer 500 in an embodiment of this application.

[0120] As an example, bit line 200 can be formed as follows: as shown in FIG23B, a bit line trench 201 is formed on one side of semiconductor body 110 along the first direction. Taking the single-gate transistor mentioned above as an example, since the size of the first trench 103 in the first direction is smaller than the size of the wafer 100 in the first direction, and the size of the third trench 105 in the first direction is larger than the size of the second trench 104 in the first direction and smaller than the size of the first trench 103 in the first direction, as shown in FIG22A and FIG22B, when forming bit line trench 201, the wafer 100 can be thinned from the second surface 102 of the wafer 100 by a process such as Chemical Mechanical Polishing (CMP) to expose the first dielectric layer 500; as shown in FIG23A and FIG23B, the undoped portion of the wafer 100 is removed from the side of the wafer 100 away from the first surface 101 to form a bit line trench 201 extending along the second direction. As shown in Figure 24, an atomic layer deposition process is used to deposit metal material in the bit line trench 201, so that a portion of the metal material reacts with a portion of the semiconductor substrate 110 to form a metal silicide layer 210, and the remaining at least a portion of the metal material forms a bit line metal layer 220. Thus, the metal silicide layer 210 and the bit line metal layer 220 can be formed in situ. It should be noted that during the metal material deposition process, the metal material may cover the surface of the first dielectric layer 500. Therefore, as shown in Figures 25A and 25B, after the metal silicide layer 210 and the bit line metal layer 220 are formed, the metal material covering the surface of the first dielectric layer 500 can be removed by a process such as CMP, that is, the portion of the bit line metal layer 220 covering the first dielectric layer 500 can be removed.

[0121] Since the metal silicide layer 210 is formed by the reaction of metal material with the semiconductor substrate 110 during the formation of the bit line metal layer 220, one end of the metal silicide layer 210 formed by the above method is in contact with the semiconductor substrate 110, and at least part of the other end is located within the bit line metal layer 220. Therefore, the embodiments of this application, by using atomic layer deposition to deposit metal material within the bit line trench 201, not only meet the deposition requirements of the narrow bit line trench 201 and reduce the difficulty of forming the small-sized lower bit line 200, but also simultaneously form the metal silicide layer 210 during the formation of the bit line metal layer 220. This simplifies the process, reduces costs, lowers the resistivity of the entire bit line 200, and enables ohmic contact between the semiconductor pillar and the bit line metal layer 220 through the metal silicide layer 210.

[0122] Furthermore, as shown in Figure 25B, during the formation of the bit line 200, the metal material does not react with the dielectric material, but only reacts with the semiconductor material to form a metal silicide. Therefore, when the isolation structure 400 is formed in the second trench 104 and the gate structure 300 is formed in the third trench 105, the metal silicide layer 210 is discontinuous in the second direction. In other words, the metal silicide layer 210 includes a plurality of sub-silicide layers 211 spaced apart in the second direction. The sub-silicide layers 211 are located on one side of the semiconductor body 110 in the first direction. A part of the bit line metal layer 220 is located between adjacent sub-silicide layers 211 in the second direction, and another part of the bit line metal layer 220 is located on the side of the sub-silicide layer 211 away from the semiconductor body 110 in the first direction.

[0123] The following example uses a molybdenum silicide as the material for the metal silicide layer 210. After forming the bit trench 201, an atomic layer deposition (ALD) process can be used with a molybdenum-containing material as a precursor to form the bit trench metal layer 220 and the metal silicide layer 210. The deposition temperature of the ALD process can be, but is not limited to, less than 1000°C. For example, a molybdenum-containing precursor is introduced into the reaction chamber of a semiconductor device to adsorb onto the inner wall of the bit trench 201; the precursor can include, but is not limited to, molybdenum pentachloride; the reaction chamber is purged with an inert gas to remove excess unadsorbed precursor and any potential byproducts; a reducing gas is introduced into the reaction chamber to react chemically with the precursor adsorbed on the inner wall of the bit trench 201 to form a molybdenum film; the reaction chamber is purged again with an inert gas to remove unreacted gas and byproducts; the above steps are repeated to deposit a molybdenum film layer by layer onto the inner wall of the bit trench 201. During the above process, a portion of the molybdenum thin film located at the bottom of the bit line trench 201 reacts with the semiconductor body 110 to form a molybdenum silicide, i.e., a metal silicide layer 210, while the remaining unreacted portion of the molybdenum thin film constitutes the bit line metal layer 220.

[0124] It should be noted that the aforementioned precursor may be, but is not limited to, molybdenum pentachloride. Other materials that can chemically react with reducing gases at high temperatures such as below 1000°C to form elemental metals and have good adsorption properties with the semiconductor host 110 may also be used as precursors for forming the metal silicide layer 210 and the bit line metal layer 220.

[0125] Figure 26 shows a cross-sectional view of the capacitor hole 601 formed in the dielectric layer 800 in an embodiment of this application; Figure 27 shows a cross-sectional view of the capacitor structure 600 formed in the capacitor hole 601 in an embodiment of this application.

[0126] In some embodiments, the fabrication method may further include forming a capacitor structure 600, which is located on one side of the semiconductor body 110 away from the bit line 200 in a first direction. As an example, the capacitor structure 600 may be formed as follows: As shown in FIG26, a filling dielectric layer 800 is formed on one side of the semiconductor body 110; wherein the filling dielectric layer 800 may be a single-layer structure or a multi-layer structure, which is not limited in this application. A capacitor hole 601 is formed that penetrates the filling dielectric layer 800 along the first direction and exposes the semiconductor body 110. As shown in FIG27, a first electrode layer 610 is formed on the inner wall of the capacitor hole 601, and the first electrode layer 610 surrounds the formed electrode hole (not shown); a capacitor dielectric layer 630 is formed on the inner wall of the electrode hole; and a second electrode layer 620 is formed within the dielectric hole surrounded by the capacitor dielectric layer 630. Thus, the capacitor structure 600 formed by the above steps includes a first electrode layer 610, a second electrode layer 620 and a capacitor dielectric layer 630, with the capacitor dielectric layer 630 located between the first electrode layer 610 and the second electrode layer 620, and the first electrode layer 610 located outside the second electrode layer 620.

[0127] In some other embodiments, as shown in Figures 12 and 13, the first electrode layer 610 may also be located inside the second electrode layer 620. As an example, the capacitor structure 600 can be formed by forming a filled dielectric layer 800 on one side of the semiconductor body 110. For example, the filled dielectric layer 800 may include a second dielectric layer 810 and a filled sacrificial layer alternately stacked in a first direction. The material of the second dielectric layer 810 may include, but is not limited to, at least one of silicon nitride, silicon oxynitride, and aluminum oxide, and the material of the second dielectric layer 810 may also be doped with dopants such as boron or carbon. For example, the material of the second dielectric layer 810 may include silicon carbide (SiCN) or silicon boron nitride (SiBN); the material of the filled sacrificial layer may include, but is not limited to, silicon oxide and / or silicon oxynitride. For example, the material filling the sacrificial layer may include silicon oxide or silicon oxide treated with an organic solution, which may include, but is not limited to, TEOS (Tetraethoxysilane), BPSG (Boron-Phosphosilicate Glass), or PGS (Phosphosilicate Glass). A capacitor hole 601 is formed that penetrates the filled dielectric layer 800 along a first direction and exposes the semiconductor body 110; a metal material is deposited within the capacitor hole 601 to form a first electrode layer 610. The metal material may fill or almost fill the capacitor hole 601, making the first electrode layer 610 columnar. Conversely, the metal material may only cover the inner wall of the capacitor hole 601, making the formed first electrode layer 610 cylindrical; in other words, the first electrode layer 610 can surround the electrode hole. If the first electrode layer 610 is cylindrical, a support core 640 can be formed within the electrode holes formed in the first electrode layer 610 after its formation. The material of the support core 640 can be, but is not limited to, elemental semiconductor materials such as silicon (Si), composite semiconductor materials such as germanium silicon (GeSi), or polycrystalline silicon doped with dopants such as boron. The filling sacrificial layer is removed to expose at least a portion of the sidewalls of the first electrode layer 610; a capacitor dielectric layer 630 is formed on the exposed sidewalls of the first electrode layer 610; and a second electrode layer 620 is formed on the side of the capacitor dielectric layer 630 opposite to the first electrode layer 610.

[0128] The materials of the first electrode layer 610 and the second electrode layer 620 mentioned above may include, but are not limited to, at least one of metals, metal compounds, semiconductor materials, and silicides; for example, the materials of the first electrode layer 610 and the second electrode layer 620 may include titanium nitride, titanium silicide, or nickel silicide. The material of the capacitor dielectric layer 630 may include, but is not limited to, at least one of aluminum oxide, tantalum oxide, titanium oxide, yttrium oxide, zirconium oxide, zirconium silicon oxide, hafnium oxide, hafnium silicon oxide, hafnium silicon nitride, hafnium zirconate, lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium aluminum oxide, and praseodymium oxide.

[0129] In addition, this application also provides a storage system, which includes a controller and the aforementioned semiconductor device. The controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0130] Figure 28 shows a block diagram of a system with semiconductor devices according to one embodiment of this application. System 900 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device with storage located therein. As shown in Figure 28, system 900 can include a host 904 and a memory system 901, the memory system 901 having one or more semiconductor devices 902 and a memory controller 903. Host 904 can be a processor of the electronic device, such as a central processing unit (CPU), or it can be a system-on-a-chip (SoC), such as an application processor (AP). Host 904 can be configured to send or receive data from semiconductor devices 902.

[0131] Semiconductor device 902 can be any semiconductor device disclosed in this application, such as the semiconductor devices shown in Figures 11 to 14. According to some embodiments, memory controller 903 is coupled to semiconductor device 902 and host 904 and is configured to control semiconductor device 902. Memory controller 903 can manage data stored in semiconductor device 902 and communicate with host 904.

[0132] In some embodiments, the memory controller 903 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 903 is designed to operate in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC), which is used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. The memory controller 903 can be configured to control the operation of the semiconductor device 902, such as read, erase, and program operations. The memory controller 903 can also be configured to manage various functions related to data stored in or to be stored in the semiconductor device 902, including but not limited to bad block management, garbage collection, logic-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 903 is further configured to process error correction codes (ECC) related to data read from or written to the semiconductor device 902. The memory controller 903 may also perform any other appropriate functions, such as formatting the semiconductor device 902. The memory controller 903 may communicate with external devices (e.g., the host 904) according to a specific communication protocol. For example, the memory controller 903 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0133] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. As an example, the steps described in this invention disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0134] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A semiconductor device, comprising: The semiconductor body extends along a first direction; And a bit line located on one side of the semiconductor body in the first direction; wherein the bit line includes a metal silicide layer and a bit line metal layer, the metal silicide layer is in contact with the semiconductor body, and the portion of the metal silicide layer facing away from the semiconductor body in the first direction is located within the bit line metal layer.

2. The semiconductor device according to claim 1, wherein, The metal silicide layer includes a plurality of sub-silicide layers spaced apart in a second direction, the sub-silicide layers being in contact with the semiconductor body, and the second direction intersecting the first direction.

3. The semiconductor device according to claim 2, wherein, The bit line metal layer extends along the second direction, a portion of the bit line metal layer is located on the side of the sub-silicide layer away from the semiconductor body in the first direction, and another portion of the bit line metal layer is located between adjacent sub-silicide layers in the second direction.

4. The semiconductor device according to claim 2, wherein, The subsilicide layer is in contact with two adjacent semiconductor bodies in the second direction.

5. The semiconductor device according to claim 1, wherein, The metal silicide layer protrudes from the surface of the bit line metal layer toward the semiconductor body in the first direction and is in contact with the semiconductor body.

6. The semiconductor device according to claim 1, wherein, The metal silicide layer includes a first silicide surface and a second silicide surface disposed opposite each other in the first direction, and the surface of the bit line metal layer facing the semiconductor body is located between the first silicide surface and the second silicide surface in the first direction.

7. The semiconductor device according to claim 1, wherein, The material of the metal silicide layer and the material of the bit line metal layer include the same metal elements.

8. The semiconductor device according to claim 7, wherein, The metallic element includes molybdenum.

9. The semiconductor device according to any one of claims 1 to 8, wherein, The bit line metal layer extends along the second direction, and the dimension of the bit line metal layer facing the semiconductor body in the third direction is the same as the dimension of the metal silicide layer in the third direction. The first direction, the second direction, and the third direction intersect each other.

10. The semiconductor device according to any one of claims 1 to 8, wherein, The bit line metal layer extends along the second direction, and the dimension of the side of the semiconductor body that contacts the metal silicide layer in the third direction is the same as the dimension of the metal silicide layer in the third direction. The first direction, the second direction, and the third direction intersect each other.

11. The semiconductor device according to any one of claims 1 to 8, wherein, The bit line extends along the second direction, the size of the bit line in the third direction is less than 10 nm, the resistivity of the bit line is less than 500 ohm-cm, and the first direction, the second direction and the third direction intersect each other.

12. The semiconductor device according to any one of claims 1 to 8, wherein, The metal silicide layer is formed by atomic layer deposition.

13. The semiconductor device according to any one of claims 1 to 8, wherein, The semiconductor device further includes a gate structure located on at least a portion of the sidewall of the semiconductor body extending along the first direction.

14. A method for fabricating a semiconductor device, comprising: A semiconductor body extending along the first direction is formed; A bit line is formed on one side of the semiconductor body along the first direction; wherein the bit line includes a metal silicide layer and a bit line metal layer, the metal silicide layer is in contact with the semiconductor body, and the portion of the metal silicide layer facing away from the semiconductor body in the first direction is located within the bit line metal layer.

15. The method for fabricating a semiconductor device according to claim 14, wherein, The metal silicide layer is formed during the formation of the bit line metal layer.

16. The method for fabricating a semiconductor device according to claim 14, wherein, The metal silicide layer and the bit line metal layer are formed in the same process.

17. The method for fabricating a semiconductor device according to claim 14, wherein, The metal silicide layer and the bit line metal layer are formed by atomic layer deposition.

18. The method for fabricating a semiconductor device according to any one of claims 14 to 17, wherein, Forming a bit line on one side of the semiconductor body along the first direction includes: forming a bit line trench on one side of the semiconductor body along the first direction; and depositing metal material in the bit line trench using an atomic layer deposition process to form the metal silicide layer and the bit line metal layer in situ.

19. The method for fabricating a semiconductor device according to claim 18, wherein, Depositing metal material in the bit line trench using atomic layer deposition to form the metal silicide layer and the bit line metal layer in situ includes: depositing metal material in the bit line trench such that a portion of the metal material reacts with a portion of the semiconductor substrate to form the metal silicide layer, and the remaining at least a portion of the metal material forms the bit line metal layer.

20. The method for fabricating a semiconductor device according to claim 18, wherein, Depositing metal material in the bitline trench to form the metal silicide layer and the bitline metal layer in situ includes: using an atomic layer deposition process to deposit metal material in the bitline trench using a molybdenum-containing material as a precursor.

21. The method for fabricating a semiconductor device according to claim 20, wherein, The precursor includes molybdenum pentachloride.

22. The method for fabricating a semiconductor device according to claim 18, wherein, The deposition temperature of the atomic layer deposition process is less than 1000℃.

23. The method for fabricating a semiconductor device according to claim 18, wherein, Forming a semiconductor body extending along a first direction includes: forming a plurality of first trenches spaced apart in a third direction and extending along a second direction from a first surface of a wafer; wherein the wafer includes the first surface and a second surface disposed opposite to the first surface; depositing a dielectric material in the first trenches to form a first dielectric layer; forming a plurality of second trenches spaced apart in the second direction and extending along the third direction from the first surface of the wafer; doping the bottom of the second trenches to form a doped layer; wherein the doped layer is located between the first surface and the second surface in the first direction; forming a third trench from the first surface of the wafer, located between adjacent second trenches and extending along the third direction, to divide a portion of the wafer in the first direction into a plurality of initial semiconductor bodies; and doping the ends of the initial semiconductor bodies from the first surface to form the semiconductor body; wherein the dimension of the third trench in the first direction is larger than the dimension of the second trench in the first direction and smaller than the dimension of the first trench in the first direction.

24. The method for fabricating a semiconductor device according to claim 23, wherein, Forming a bit line trench on one side of the semiconductor body along the first direction includes: removing an undoped portion of the wafer from the side of the wafer opposite to the first surface to form the bit line trench.

25. A storage system, characterized in that, The storage system includes a controller and a semiconductor device according to any one of claims 1 to 13, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

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