Semiconductor device and preparation method thereof, and storage system

Abstract

The invention discloses a semiconductor device, a preparation method thereof and a storage system. The semiconductor device includes a first semiconductor structure including a semiconductor body extending in a first direction, a capacitor structure located at one side of the semiconductor body in the first direction and including a first electrode layer, and a connection structure in contact with the semiconductor body at one end in the first direction, at least part of the other end is located in the first electrode layer.

Description

Technical Field

[0001] The embodiments of this application relate to the field of semiconductor technology, and in particular to semiconductor devices and their fabrication methods and storage systems. Background Technology

[0002] Semiconductor devices are memory devices used to store information in modern information technology. Their main function is to store programs and various data, and to perform high-speed and automatic access to programs or data during computer operation. Taking DRAM (Dynamic Random Access Memory) as an example, DRAM typically includes multiple memory cells. Each memory cell includes a transistor and a capacitor structure. One end of the transistor is connected to the capacitor structure, and the other end of the transistor is connected to a bit line. Summary of the Invention

[0003] This application provides a semiconductor device, a method for fabricating the same, and a storage system.

[0004] The first aspect of this application provides a semiconductor device, which includes a first semiconductor structure. The first semiconductor structure includes a semiconductor body, a capacitor structure, and a connection structure. The semiconductor body extends along a first direction. The capacitor structure is located on one side of the semiconductor body in the first direction and includes a first electrode layer. One end of the connection structure in the first direction is in contact with the semiconductor body, and at least a portion of the other end is located within the first electrode layer.

[0005] In some embodiments, the connection structure protrudes in a first direction from the surface of the first electrode layer facing the semiconductor body and contacts the semiconductor body.

[0006] In some embodiments, the connection structure includes a first connection surface and a second connection surface disposed opposite to each other in a first direction, and the surface of the first electrode layer facing the semiconductor body is located between the first connection surface and the second connection surface in the first direction.

[0007] In some embodiments, the material of the connection structure includes the same metallic elements as the material of the first electrode layer.

[0008] In some implementations, the metallic element includes molybdenum.

[0009] In some embodiments, the material of the connecting structure includes metal silicides containing metallic elements.

[0010] In some implementations, the connection structure is a single-layer structure.

[0011] In some implementations, the dimension of the connection structure in the first direction is less than 10 nm.

[0012] In some implementations, the connection structure is formed using an atomic layer deposition process.

[0013] In some embodiments, the dimension of the end of the first electrode layer facing the semiconductor body in the second direction is larger than the dimension of the connection structure in the second direction, and the second direction intersects the first direction.

[0014] In some embodiments, the dimension of the end of the semiconductor body that contacts the connection structure in the second direction is the same as the dimension of the connection structure in the second direction, and the second direction intersects the first direction.

[0015] In some embodiments, the capacitor structure further includes a second electrode layer and a capacitor dielectric layer, the second electrode layer extending along a first direction, the capacitor dielectric layer located on the sidewall of the second electrode layer extending along the first direction and the end face of the second electrode layer facing the semiconductor pillar, and the first electrode layer located on the side of the capacitor dielectric layer away from the second electrode layer.

[0016] In some embodiments, the capacitor structure further includes a capacitor dielectric layer and a second electrode layer, wherein the capacitor dielectric layer is located at least on a portion of the sidewall of the first electrode layer extending in a first direction, and the second electrode layer is located on the side of the capacitor dielectric layer opposite to the first electrode layer.

[0017] In some embodiments, the capacitor structure further includes a support core, with a first electrode layer located on the sidewall of the support core extending in a first direction and on the end face of the support core facing the semiconductor body.

[0018] In some embodiments, the first electrode layer has a columnar structure, and the end of the connection structure that is away from the semiconductor body in a first direction is located within the first electrode layer.

[0019] In some embodiments, the first semiconductor structure further includes a filling dielectric layer, and the first electrode layer penetrates the filling dielectric layer along a first direction.

[0020] In some embodiments, the first semiconductor structure further includes a gate structure located on at least a portion of the sidewall of the semiconductor body extending along a first direction.

[0021] In some embodiments, the first semiconductor structure further includes an isolation structure located on one side of the semiconductor body in a second direction and extending along a third direction, and a gate structure located on the side of the semiconductor body away from the isolation structure in a second direction and extending along a third direction, wherein the first direction, the second direction and the third direction intersect each other.

[0022] In some implementations, the isolation structure has an air gap.

[0023] In some embodiments, the first semiconductor structure further includes a bit line located in a first direction on the side of the semiconductor body away from the capacitor structure and extending along a second direction, the first direction intersecting the second direction.

[0024] In some embodiments, the semiconductor device further includes a second semiconductor structure located on one side of the first semiconductor structure in a first direction and coupled to the first semiconductor structure, the second semiconductor structure including a memory array and / or peripheral circuitry.

[0025] A second aspect of this application provides a method for fabricating a semiconductor device, the method comprising: forming a semiconductor body extending along a first direction; and forming a capacitor structure and a connection structure; wherein the capacitor structure is located on one side of the semiconductor body in the first direction and includes a first electrode layer, and one end of the connection structure in the first direction is in contact with the semiconductor body, and at least a portion of the other end is located within the first electrode layer.

[0026] In some implementations, the connection structure is formed during the formation of the first electrode layer.

[0027] In some implementations, the first electrode layer and the connection structure are formed in the same process.

[0028] In some implementations, the first electrode layer and the interconnect structure are formed by atomic layer deposition.

[0029] In some embodiments, forming the capacitor structure and the connection structure includes: forming a filling dielectric layer on one side of the semiconductor body; forming a capacitor hole that penetrates the filling dielectric layer along a first direction; and depositing a metal material in the capacitor hole using an atomic layer deposition process to form a first electrode layer and the connection structure in situ.

[0030] In some embodiments, depositing metal material in a capacitor aperture using an atomic layer deposition process to form a first electrode layer and a connection structure in situ includes: depositing metal material in the capacitor aperture such that a portion of the metal material reacts with a portion of the semiconductor substrate to form a connection structure, and the remaining at least a portion of the metal material forms the first electrode layer.

[0031] In some embodiments, depositing metallic material within the capacitor aperture to form a first electrode layer and connection structure in situ includes: using an atomic layer deposition process with a molybdenum-containing material as a precursor to form the first electrode layer and connection structure.

[0032] In some implementations, the precursor includes molybdenum pentachloride.

[0033] In some implementations, the deposition temperature of the atomic layer deposition process is less than 1000°C.

[0034] A third aspect of this application provides a storage system, which includes a controller and a semiconductor device according to the first aspect of this application. The controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0035] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0036] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. The drawings are provided for a better understanding of the invention and are not intended to limit the scope of the application. In the drawings:

[0037] Figure 1 This is a perspective view of a storage unit according to one embodiment of this application;

[0038] Figure 2 This is a cross-sectional schematic diagram of a semiconductor device according to one embodiment of this application;

[0039] Figure 3 This is a cross-sectional schematic diagram of a contact structure according to one embodiment of this application;

[0040] Figure 4 This is a schematic flowchart of a method for fabricating a semiconductor device according to one embodiment of this application;

[0041] Figures 5 to 11 This is a process schematic diagram of a method for fabricating a semiconductor device according to one embodiment of this application;

[0042] Figures 12 to 15 These are cross-sectional schematic diagrams of semiconductor devices according to other different embodiments of this application;

[0043] Figure 16 This is a top view schematic diagram of a semiconductor device according to another embodiment of this application;

[0044] Figure 17 This is a schematic flowchart of a method for fabricating a semiconductor device according to another embodiment of this application;

[0045] Figures 18 to 30B This is a schematic diagram of the fabrication method of a semiconductor device according to another embodiment of this application; and

[0046] Figure 31 This is a block diagram of a system having semiconductor devices according to one embodiment of this application.

[0047] Figure label:

[0048] 100. First semiconductor structure; 110. Second semiconductor structure; 200. Semiconductor body;

[0049] 200', Initial semiconductor body; 201, Wafer; 202, First surface;

[0050] 203. Second surface; 204. First groove; 205. Second groove;

[0051] 205-1, First wafer trench; 205-2, Second wafer trench; 210, Source; 220, Drain;

[0052] 230, Channel; 240, First dielectric layer; 250, Doped layer; 300, Capacitor structure;

[0053] 301, Capacitor hole; 310, First electrode layer; 320, Second electrode layer;

[0054] 330, capacitor dielectric layer; 340, support core; 350, filler dielectric layer;

[0055] 351, Second dielectric layer; 400, Connection structure; 401, First connection surface;

[0056] 402. Second connecting surface; 500. Contact structure; 501. First contact hole;

[0057] 502, Second contact hole; 510, Semiconductor layer; 520, Metal silicide layer;

[0058] 530, Adhesive layer; 540, Metal layer; 550, Dielectric layer; 600, Gate structure;

[0059] 600' Initial gate structure; 610 Gate dielectric layer; 620 Gate conductive layer;

[0060] 630, Gate adhesive layer; 640, Gate isolation layer; 650, Gate notch structure;

[0061] 700, Isolation structure; 700', Initial isolation structure; 701, Air gap;

[0062] 710, Isolation dielectric layer; 720, Isolation conductive layer; 800, Bit line;

[0063] 801, Bit line trench; 810, Bit line connection layer; 900, System;

[0064] 901. Memory system; 902. Semiconductor device; 903. Memory controller;

[0065] 904, host computer. Detailed Implementation

[0066] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0067] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence.

[0068] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale.

[0069] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0070] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0071] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0072] Furthermore, in this application, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a range smaller than that of the structure below or above. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. Furthermore, in this application, the use of "connection" or "joint" may indicate direct or indirect contact between corresponding components, unless otherwise expressly defined or inferred from the context.

[0073] With the rapid development of semiconductor technology, the size of DRAM memory cells is getting smaller and smaller, and their array architecture has expanded from 8F... 2 Developed to 6F 2 And from 6F 2 Developed to 4F 2 The architecture of memory has evolved from planar array transistors to recessed gate array transistors, then from recessed gate array transistors to buried saddle fin array transistors, and finally from buried saddle fin array transistors to vertical gate transistors.

[0074] like Figure 1 As shown, DRAM typically includes multiple memory cells, each comprising a transistor and a capacitor structure 300. Its main operating principle is to use the amount of charge stored within the capacitor structure 300 to represent whether a binary bit is 1 or 0. The transistor typically includes a semiconductor body 200 and a gate structure 600. The drain 220 of the semiconductor body 200 is electrically connected to the bit line 800 (BL), and the source 210 of the semiconductor body 200 is electrically connected to one electrode of the capacitor structure 300. The other electrode of the capacitor structure 300 can be grounded or connected to a reference voltage. The gate structure 600 of the transistor is electrically connected to the word line (WL). The word line is used to apply voltage to control the transistor's on or off state, and the bit line 800 is used to perform read or write operations on the capacitor structure 300 when the transistor is on.

[0075] In view of the continuous reduction in the feature size of transistors, in order to reduce the contact resistance between the semiconductor body 200 and the capacitor structure 300, the embodiments of this application provide a contact structure 500 between the semiconductor body 200 and the capacitor structure 300. Figure 2 A schematic cross-sectional view of the semiconductor device according to one embodiment of this application is shown. Figure 3A schematic cross-sectional view of the contact structure 500 according to one embodiment of this application is shown in the xz plane. Figure 2 As shown, the semiconductor device includes a semiconductor body 200, a capacitor structure 300, and a contact structure 500. The contact structure 500 is located on one side of the semiconductor body 200 in a first direction, and the capacitor structure 300 is located on the side of the contact structure 500 opposite to the semiconductor body 200 in the first direction. In other words, the contact structure 500 is located between the semiconductor body 200 and the capacitor structure 300 in the first direction. Figure 3 As shown, the contact structure 500 includes a semiconductor layer 510, a metal silicide layer 520, an adhesive layer 530, and a metal layer 540. The metal silicide layer 520 is located on the side of the semiconductor layer 510 away from the semiconductor body 200. The adhesive layer 530 and the metal layer 540 are both located on the side of the metal silicide layer 520 away from the semiconductor layer 510. The adhesive layer 530 is located on the sidewall of the metal layer 540 extending in a first direction and on the surface of the metal layer 540 facing the metal silicide layer 520 in the first direction.

[0076] Figure 4 A schematic flowchart of a method for fabricating a semiconductor device according to one embodiment of this application is shown. Figures 5 to 11 A schematic diagram of the fabrication method of a semiconductor device according to one embodiment of this application is shown. Figures 4 to 11 As shown, this application provides a method for fabricating a semiconductor device, the method 1000 comprising:

[0077] S100, such as Figure 5 As shown, a dielectric layer 550 is formed on one side of the semiconductor body 200 along the first direction. The material of the dielectric layer 550 may include, but is not limited to, silicon nitride, silicon oxynitride, silicon carbide, or silicon boronitride.

[0078] S110, such as Figure 6 As shown, a first contact hole 501 is formed on the side of the dielectric layer 550 opposite to the semiconductor body 200, penetrating the dielectric layer 550 in a first direction and exposing the semiconductor body 200.

[0079] S120, such as Figure 7 As shown, a semiconductor layer 510 is formed in the first contact hole 501. The material of the semiconductor layer 510 may include, but is not limited to, elemental semiconductor materials such as silicon, composite semiconductor materials such as germanium-silicon, or polycrystalline silicon.

[0080] S130, such as Figure 8 As shown, a portion of the semiconductor layer 510 is removed to form a second contact hole 502;

[0081] S140, such as Figure 9As shown, the semiconductor layer 510 is doped through the second contact hole 502; wherein the dopant may include, but is not limited to, boron, gallium, phosphorus, arsenic or antimony;

[0082] S150, such as Figure 10 As shown, a metal material is deposited in the second contact hole 502 and annealed to react with the semiconductor layer 510 to form a metal silicide layer 520; wherein, the material of the metal silicide layer 520 may include, but is not limited to, titanium silicide or cobalt silicide;

[0083] S160, such as Figure 11 As shown, an adhesive layer 530 is formed on the inner wall of the remaining space of the second contact hole 502. The material of the adhesive layer 530 may include, but is not limited to, at least one of titanium nitride, tantalum nitride, and tungsten carbide.

[0084] S170. A metal layer 540 is formed within the pores formed by the adhesive layer 530. The material of the metal layer 540 may include, but is not limited to, at least one of tungsten, copper and silver.

[0085] The following example illustrates the formation process of the metal silicide layer 520, using polysilicon as the material of the semiconductor layer 510 and cobalt silicide as the material of the metal silicide layer 520: After doping the semiconductor layer 510 through the second contact hole 502, a Co thin film is deposited on the surface of the semiconductor layer 510; a CoN thin film is deposited on the side of the Co thin film away from the semiconductor layer 510 to prevent Co from flowing during subsequent rapid thermal annealing (RTA); the Co thin film undergoes rapid thermal annealing, during which Co reacts with the semiconductor layer 510 to generate a high-resistivity metal silicide. The growth of the high-resistivity metal silicide requires the consumption of the semiconductor layer 510; for every x thickness of metal silicide grown, y thickness of semiconductor layer 510 is consumed. During this process, Co does not react with the dielectric layer 550; Co only reacts with the semiconductor layer 510 to generate a high-resistivity metal silicide. The high-resistivity metal silicide has a body-centered orthorhombic structure and a relatively high resistance. The CoN film and unreacted Co film were removed by selective wet etching. The high-resistivity metal silicide was rapidly thermally annealed to convert it into low-resistivity CoSi. The low-resistivity CoSi has a face-centered orthorhombic structure with low resistance. The low-resistivity CoSi is the metal silicide layer 520.

[0086] In order to reduce the contact resistance between the semiconductor body 200 and the capacitor structure 300, this application provides another semiconductor device. Figures 12 to 15 The following are schematic cross-sectional views of the semiconductor devices according to different embodiments of this application. Figure 16A top view of a semiconductor device according to one embodiment of this application is shown.

[0087] like Figures 12 to 16 As shown, the semiconductor device includes a first semiconductor structure 100, which includes a semiconductor body 200, a capacitor structure 300, and a connection structure 400. The semiconductor body 200 extends along a first direction, the capacitor structure 300 is located on one side of the semiconductor body 200 in the first direction, the capacitor structure 300 includes a first electrode layer 310, one end of the connection structure 400 is in contact with the semiconductor body 200 in the first direction, and at least a portion of the other end of the connection structure 400 is located within the first electrode layer 310.

[0088] It should be noted that, in the embodiments of this application, the first electrode layer 310 may be, but is not limited to, a columnar structure or a cylindrical structure. When the first electrode layer 310 is a cylindrical structure, one end of the connecting structure 400 contacts the semiconductor body 200, and the other end of the connecting structure 400 is located within the first electrode layer 310 or extends through the bottom of the first electrode layer 310 along the first direction. When the first electrode layer 310 is a columnar structure, one end of the connecting structure 400 contacts the semiconductor body 200, and the other end of the connecting structure 400 is located within the first electrode layer 310. As an example, the dimension of the connecting structure 400 in the first direction may be, but is not limited to, less than 10 nm. In some embodiments, the connecting structure 400 may be a single-layer structure.

[0089] Furthermore, the semiconductor device provided in this application embodiment can be a memory or a part of a memory. For example, if the semiconductor device only includes the first semiconductor structure 100, and the memory includes peripheral circuitry and the aforementioned semiconductor device, then the aforementioned semiconductor device is part of the memory. As an example, the first direction in this application embodiment can be the z-direction shown in the figures.

[0090] In some embodiments, the connection structure 400 protrudes from the surface of the first electrode layer 310 toward the semiconductor body 200 in a first direction and contacts the semiconductor body 200. For example... Figure 27B As shown, the connection structure 400 includes a first connection surface 401 and a second connection surface 402 disposed opposite to each other in a first direction. The surface of the first electrode layer 310 facing the semiconductor body 200 is located between the first connection surface 401 and the second connection surface 402 in the first direction. As an example, a portion of the connection structure 400 is located within the first electrode layer 310, and another portion of the connection structure 400 is located on the side of the first electrode layer 310 facing the semiconductor body 200 and connected to the semiconductor body 200.

[0091] In some embodiments, the connection structure 400 and the first electrode layer 310 can be formed in the same process. As an example, the connection structure 400 and the first electrode layer 310 can be formed by atomic layer deposition (ALD) process.

[0092] In some embodiments, the material of the connection structure 400 and the material of the first electrode layer 310 may include the same metallic element. For example, both the material of the connection structure 400 and the material of the first electrode layer 310 include molybdenum.

[0093] In some embodiments, the material of the first electrode layer 310 includes a metallic element, and the material of the connection structure 400 includes a metal silicide having the aforementioned metallic element. For example, the material of the first electrode layer 310 includes molybdenum, and the material of the connection structure 400 includes molybdenum silicide. It should be noted that, in addition to molybdenum, other metallic materials suitable for atomic layer deposition processes and capable of reacting with the semiconductor substrate 200 at high temperatures such as below 1000°C to form metal silicides can also be used as the material of the first electrode layer 310, and this application does not limit this.

[0094] In some embodiments, the dimension of the end of the first electrode layer 310 facing the semiconductor body 200 in the second direction is larger than the dimension of the connecting structure 400 in the second direction, and the second direction intersects the first direction. Those skilled in the art should understand that if the first electrode layer 310 is cylindrical, then the dimension of the first electrode layer 310 in the second direction generally refers to the outer diameter of the first electrode layer 310. The intersection of the first and second directions can generally be understood as the first and second directions having an angle. For example, the first and second directions are perpendicular or approximately perpendicular to each other. As an example, in the embodiments of this application, the first direction can be the z-direction in the figures, and the second direction can be the x-direction in the figures.

[0095] For example, the first electrode layer 310 includes a first electrode and a second electrode (not shown) disposed opposite to each other in a first direction. The first electrode is closer to the semiconductor body 200 than the second electrode. At least a portion of the connection structure 400 is located within the first electrode. The size of the first electrode in the second direction is larger than the size of the connection structure 400 in the second direction.

[0096] In some embodiments, the end of the semiconductor body 200 that contacts the connection structure 400 has the same dimension in a second direction as the connection structure 400 in the second direction, and the second direction intersects the first direction. For example, the semiconductor body 200 includes a first end and a second end disposed opposite to each other in the first direction, the first end being closer to the first electrode layer 310 than the second end, the first end of the semiconductor body 200 contacting the connection structure 400, and the dimension of the first end in the second direction being the same as the dimension of the connection structure 400 in the second direction. Those skilled in the art should understand that "the dimension of the first end in the second direction being the same as the dimension of the connection structure 400 in the second direction" generally means that the dimension of the first end in the second direction is completely equal to the dimension of the connection structure 400 in the second direction, or that there is a slight deviation, for example, the difference between the two dimensions does not exceed 15% of either of the two dimensions.

[0097] In some implementations, such as Figure 12 As shown, the capacitor structure 300 may include a first electrode layer 310, a second electrode layer 320, and a capacitor dielectric layer 330. The second electrode layer 320 extends along a first direction, and the capacitor dielectric layer 330 is located on the sidewall of the second electrode layer 320 extending along the first direction and on the end face of the second electrode layer 320 facing the semiconductor body 200. The first electrode layer 310 is located on the side of the capacitor dielectric layer 330 opposite to the second electrode layer 320. As an example, the first electrode layer 310 has a cylindrical structure, the second electrode layer 320 is located inside the first electrode layer 310, and the capacitor dielectric layer 330 is located between the first electrode layer 310 and the second electrode layer 320.

[0098] In the above embodiments, the first electrode layer 310 may be located outside the second electrode layer 320; in other embodiments, the first electrode layer 310 may also be located inside the second electrode layer 320. For example, as... Figure 14 and Figure 15 As shown, the capacitor structure 300 includes a first electrode layer 310, a second electrode layer 320, and a capacitor dielectric layer 330. The first electrode layer 310 extends along a first direction, the capacitor dielectric layer 330 is located on a portion of the sidewall of the first electrode layer 310 extending along the first direction, and the second electrode layer 320 is located on the side of the capacitor dielectric layer 330 opposite to the first electrode layer 310. For example, as... Figure 14As shown, the first electrode layer 310 has a cylindrical structure, the capacitor dielectric layer 330 is located on a portion of the outer wall of the first electrode layer 310, and the second electrode layer 320 is located on the side of the capacitor dielectric layer 330 facing away from the first electrode layer 310. In this case, the capacitor structure 300 may further include a support core 340 extending along a first direction, with the first electrode layer 310 located on the side wall of the support core 340 extending along the first direction and on the end face of the support core 340 facing the semiconductor body 200. The material of the support core 340 may include, but is not limited to, elemental semiconductor materials such as silicon (Si), composite semiconductor materials such as germanium-silicon (GeSi), or polycrystalline silicon doped with dopants such as boron. For example, as... Figure 15 As shown, the first electrode layer 310 has a columnar structure, the capacitor dielectric layer 330 is located on a portion of the sidewall of the first electrode layer 310, and the second electrode layer 320 is located on the side of the capacitor dielectric layer 330 facing away from the first electrode layer 310. It should be noted that, in addition to the above-described structural form, other structural forms suitable for this application can also be used for the capacitor structure 300 in the embodiments of this application.

[0099] In some embodiments, the first semiconductor structure 100 may further include a filling dielectric layer 350, through which the first electrode layer 310 penetrates along a first direction. The filling dielectric layer 350 may be a single-layer structure or a multi-layer structure. For example, as... Figure 14 and Figure 15 As shown, the filling dielectric layer 350 may include a plurality of second dielectric layers 351 spaced apart in a first direction.

[0100] Furthermore, the materials of the first electrode layer 310 and the second electrode layer 320 mentioned above can be the same or different. The materials of the first electrode layer 310 and the second electrode layer 320 can include, but are not limited to, at least one of metals, metal compounds, semiconductor materials, and silicides; for example, the materials of the first electrode layer 310 and the second electrode layer 320 can include titanium nitride, titanium silicide, or nickel silicide. The material of the capacitor dielectric layer 330 can include, but is not limited to, at least one of aluminum oxide, tantalum oxide, titanium oxide, yttrium oxide, zirconium oxide, zirconium silicon oxide, hafnium oxide, hafnium silicon oxide, hafnium silicon nitride, hafnium zirconate, lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium aluminum oxide, and praseodymium oxide.

[0101] In some embodiments, the first semiconductor structure 100 may further include a gate structure 600, which is located on at least a portion of the sidewall of the semiconductor body 200 extending along a first direction. As an example, the gate structure 600 may include a gate dielectric layer 610 and a gate conductive layer 620, with the gate dielectric layer 610 located on the sidewall of the semiconductor body 200 and the gate conductive layer 620 located on the side of the gate dielectric layer 610 facing away from the semiconductor body 200. The material of the gate dielectric layer 610 may include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, or high-k materials such as hafnium oxide, zirconium oxide, aluminum oxide, and tantalum oxide; the material of the gate conductive layer 620 may include tungsten, aluminum, titanium, copper, cobalt, or tungsten nitride. To improve the adhesion between the gate conductive layer 620 and the gate dielectric layer 610, the gate structure 600 may further include a gate adhesive layer 630, which is located between the gate dielectric layer 610 and the gate conductive layer 620. The material of the gate adhesive layer 630 may include, but is not limited to, at least one of titanium nitride, tantalum nitride, and tungsten carbide.

[0102] It should be noted that the gate structure 600 may cover part or all of the sidewalls of the semiconductor body 200. Therefore, the transistor can be classified as a single-gate transistor, a dual-gate transistor, a tri-gate transistor, or a gate all-around (GAA) transistor. Specifically, in a single-gate transistor, the gate structure 600 may be located only on one side of the semiconductor body 200 in the direction intersecting the first direction; in a dual-gate transistor, the gate structure 600 may be located on opposite sides of the semiconductor body 200 in the direction intersecting the first direction; in a tri-gate transistor, the gate structure 600 partially surrounds the semiconductor body 200 in the direction intersecting the first direction; and in a GAA transistor, the gate structure 600 surrounds the semiconductor body 200 in the direction intersecting the first direction. For example, the semiconductor body 200 includes a first and a second sidewall disposed opposite to each other in a second direction, and a third and a fourth sidewall disposed opposite to each other in a third direction, with the first, second, and third directions intersecting each other. If the gate structure 600 is located on any one of the first, second, third, and fourth sidewalls of the semiconductor body 200, then the transistor formed by it and the semiconductor body 200 is a single-gate transistor; if the gate structure 600 is located on the first and second (third and fourth) sidewalls of the semiconductor body 200, then the transistor formed by it and the semiconductor body 200 is a dual-gate transistor; if the gate structure 600 is located on any three of the first, second, third, and fourth sidewalls of the semiconductor body 200, then the transistor formed by it and the semiconductor body 200 is a tri-gate transistor; if the gate structure 600 is located on the first, second, third, and fourth sidewalls of the semiconductor body 200, then the transistor formed by it and the semiconductor body 200 is a full-ring gate transistor.

[0103] In this context, the intersection of the first direction, the second direction, and the third direction can generally be understood as the first direction and the second direction forming an angle, the second direction and the third direction forming an angle, and the first direction and the third direction forming an angle. As an example, in the embodiments of this application, the first direction can be the z-direction in the attached drawings, the second direction can be the x-direction in the attached drawings, and the third direction can be the y-direction in the attached drawings.

[0104] Taking a single-gate transistor as an example, the first semiconductor structure 100 may further include an isolation structure 700, which is located on one side of the semiconductor body 200 in the second direction and extends along the third direction. The gate structure 600 is located on the side of the semiconductor body 200 away from the isolation structure 700 in the second direction and extends along the third direction. The first direction, the second direction and the third direction intersect each other.

[0105] As an example, such as Figure 12As shown, the isolation structure 700 has an air gap 701. In other embodiments, such as Figure 13 As shown, the isolation structure 700 may include an isolation dielectric layer 710 and an isolation conductive layer 720, with the isolation dielectric layer 710 located at least on the sidewall of the isolation conductive layer 720 extending along a first direction. The material of the isolation dielectric layer 710 may include, but is not limited to, silicon oxide, silicon oxynitride, or silicon nitride; the material of the isolation conductive layer 720 may include, but is not limited to, at least one of tungsten, titanium nitride, copper, and silver.

[0106] In some embodiments, the first semiconductor structure 100 may further include a bit line 800, which is located in a first direction on the side of the semiconductor body 200 opposite to the capacitor structure 300. The bit line 800 may extend along a second direction, and a plurality of semiconductor bodies 200 spaced apart in the second direction are connected to the bit line 800. The material of the bit line 800 may include, but is not limited to, metallic materials such as tungsten, copper, or aluminum. As an example, the first semiconductor structure 100 may further include a bit line connection layer 810, which is located on the side of the bit line 800 facing the semiconductor body 200. In other words, the bit line connection layer 810 is located in the first direction between the bit line 800 and the semiconductor body 200, and extends along the second direction. The material of the bit line connection layer 810 may include, but is not limited to, semiconductor materials having P-type dopants such as boron or gallium, or N-type dopants such as phosphorus or arsenic.

[0107] As an example, the semiconductor body 200 may include a source 210, a drain 220, and a channel 230 located between the source 210 and the drain 220 in a first direction. The semiconductor body 200 and the gate structure 600 constitute a transistor. The source 210 is in contact with the connection structure 400, the drain 220 is connected to the bit line 800, and the gate structure 600 can be a word line. The word line is used to apply voltage to control the transistor's on or off state. The bit line 800 is used to perform read or write operations on the capacitor structure 300 when the transistor is on. The amount of charge stored in the capacitor structure 300 represents whether a binary bit is 1 or 0.

[0108] In some embodiments, the semiconductor device may further include a second semiconductor structure 110 located on one side of the first semiconductor structure 100 in a first direction. The second semiconductor structure 110 is coupled to the first semiconductor structure 100, and may include, but is not limited to, a memory array and / or peripheral circuitry. For example, the first semiconductor structure 100 and the second semiconductor structure 110 may be coupled by bonding.

[0109] The memory array may be, but is not limited to, a DRAM memory array. The peripheral circuitry may include peripheral devices, which may include, but are not limited to, at least one of high-voltage devices, low-voltage devices, and ultra-low-voltage devices. High-voltage devices, low-voltage devices, or ultra-low-voltage devices may include, but are not limited to, at least one of active or passive devices such as transistors, diodes, resistors, and capacitors. High-voltage devices may include, but are not limited to, at least one of row decoders, column decoders, word line drivers, and bit line drivers. Low-voltage devices may include, but are not limited to, page buffers or logic devices. Ultra-low-voltage devices may include, but are not limited to, I / O circuitry. High-voltage devices typically operate at voltages greater than 3.3V, for example, 5V to 30V. For example, the operating voltage of a high-voltage device could be 5V, 10V, 15V, 20V, 25V, or 30V. Low-voltage devices typically operate at voltages between 1.3V and 3.3V. For example, the operating voltage of a low-voltage device could be 1.3V, 1.8V, 2.3V, 2.8V, or 3.3V. Ultra-low-voltage devices typically operate at voltages lower than 1.3V, for example, 0.9V to 1.2V. For example, the operating voltage of an ultra-low-voltage device could be 0.9V, 0.95V, 1V, 1.05V, 1.1V, 1.15V, or 1.2V. It should be noted that the operating voltage of a high-voltage, low-voltage, or ultra-low-voltage device can also be any value between any two of the above voltage values. Those skilled in the art should understand that the description of the operating voltage ranges of high-voltage, low-voltage, and ultra-low-voltage devices above is for better understanding of this solution and does not constitute a limitation of this application.

[0110] Figure 17 A schematic flowchart of a method for fabricating a semiconductor device according to one embodiment of this application is shown. Figures 18 to 30B A schematic diagram illustrating a method for fabricating a semiconductor device according to one embodiment of this application is shown. Figures 17 to 30B As shown, the preparation method 2000 includes:

[0111] S200, forming a semiconductor body 200 extending along the first direction;

[0112] S210, forming a capacitor structure 300 and a connection structure 400, the capacitor structure 300 being located on one side of the semiconductor body 200 in a first direction and including a first electrode layer 310, the connection structure 400 having one end in contact with the semiconductor body 200 in the first direction, and at least a portion of the other end located within the first electrode layer 310.

[0113] The following is a detailed description of each step in the semiconductor device fabrication method in the embodiments of this application.

[0114] Step S200

[0115] In step 200, a semiconductor body 200 is formed, which extends along a first direction. The projection shape of the semiconductor body 200 onto a plane perpendicular to the first direction may be, but is not limited to, a rectangle, a circle, an ellipse, a semicircle, or any other arbitrary shape; this application does not limit this.

[0116] Figure 18 This shows a schematic cross-sectional view of the yz plane in which the first trench 204 is formed in the wafer 201 according to an embodiment of this application; Figure 23 This shows a schematic cross-sectional view of the xz plane of the initial gate structure 600' formed in the second wafer trench 205-2 in an embodiment of this application; Figure 24 A schematic cross-sectional view of the source electrode 210 formed in the embodiment of this application is shown.

[0117] As an example, the semiconductor body 200 can be formed in the following manner: Figure 18 As shown, a plurality of first trenches 204 are formed in wafer 201, spaced apart in a third direction and all extending along a second direction; wherein, the material of wafer 201 can be any suitable semiconductor material, such as a single semiconductor material such as silicon (Si) or germanium (Ge), or a composite semiconductor material such as silicon-on-insulator (SOI) or germanium-on-insulator (GeOI); as Figure 23 As shown, a plurality of second trenches 205, spaced apart in a second direction and all extending along a third direction, are formed in wafer 201 to divide wafer 201 into a plurality of initial semiconductor bodies 200'; as Figure 24 As shown, the semiconductor body 200 is formed based on the initial semiconductor body 200'. For example, the semiconductor body 200 can be formed by doping both ends of the initial semiconductor body 200' in the first direction. The first trench 204 and the second trench 205 can be formed in the wafer 201 using, but is not limited to, wet etching, dry etching processes such as plasma etching or reactive ion etching, or any combination of these processes. As an example, the dimensions of the first trench 204 and the second trench 205 in the first direction can be smaller than the dimensions of the wafer 201 in the first direction.

[0118] It should be noted that the above steps can be performed in parallel, sequentially, or in different orders, as long as the semiconductor body 200 can be formed, and this application does not limit this. For example, taking a plurality of second trenches 205 including first wafer trenches 205-1 and second wafer trenches 205-2 alternately distributed in the second direction as an example, the first wafer trenches 205-1 and second wafer trenches 205-2 can be formed in different process technologies.

[0119] In some embodiments, the fabrication method may further include forming a gate structure 600 on at least a portion of the sidewalls extending along a first direction of the initial semiconductor body 200'. After forming the gate structure 600, a semiconductor body 200 can be formed based on the initial semiconductor body 200', and the semiconductor body 200 and the gate structure 600 together constitute a transistor. As described above, the gate structure 600 may cover a portion of the sidewalls of the semiconductor body 200 or may cover all of the sidewalls of the semiconductor body 200. Thus, the transistor can be classified as a single-gate transistor, a dual-gate transistor, a tri-gate transistor, or a gate all-around (GAA) transistor.

[0120] Figure 19 This shows a schematic cross-sectional view of the yz plane of the first dielectric layer 240 formed in the first trench 204 in an embodiment of this application; Figure 20 It shows Figure 19 Cross-sectional view at point AA; Figure 21 This paper shows a schematic cross-sectional view of the first wafer trench 205-1 formed in wafer 201 according to an embodiment of this application. Figure 22A This paper shows a schematic cross-sectional view of the xz plane of the bottom of the first wafer trench 205-1 to form a doped layer 250 in an embodiment of this application. Figure 22B This illustration shows a cross-sectional view of the yz plane of the bottom of the first wafer trench 205-1 to form a doped layer 250, according to an embodiment of this application.

[0121] The following is an example illustrating a method for forming a single-gate transistor: A wafer 201 is provided, which includes a first surface 202 and a second surface 203 disposed opposite to each other in a first direction; as shown below. Figure 18 As shown, a plurality of first trenches 204 are formed on the first surface 202 of wafer 201, spaced apart in a third direction and all extending along a second direction. As an example, the size of the first trenches 204 in the first direction is smaller than the size of wafer 201 in the first direction; in other words, the first trenches 204 do not penetrate wafer 201. Figure 19 and Figure 20 As shown, a dielectric material is deposited within the first trench 204 to form a first dielectric layer 240; wherein, the material of the first dielectric layer 240 may include, but is not limited to, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxide. Figure 21 As shown, a plurality of first wafer trenches 205-1 are formed in the wafer 201 from the first surface 202 of the wafer 201, spaced apart in the second direction and all extending along the third direction. Figure 22A and Figure 22BAs shown, a doped layer 250 is formed by doping the bottom of the first wafer trench 205-1. The doped layer 250 is located between the first surface 202 and the second surface 203 in a first direction. Figure 23 As shown, an isolation structure 700 is formed within the first wafer trench 205-1. A second wafer trench 205-2 extending in a third direction is formed between adjacent first wafer trenches 205-1 from the first surface 202 of the wafer 201. The second wafer trench 205-2 penetrates the doped layer 250 in a first direction. As an example, the dimension of the second wafer trench 205-2 in the first direction is larger than the dimension of the first wafer trench 205-1 in the first direction and smaller than the dimension of the first trench 204 in the first direction. Thus, the first trench 204, the first wafer trench 205-1, and the second wafer trench 205-2 together divide a portion of the wafer 201 in the first direction into multiple initial semiconductor bodies 200', while the doped layer 250 is divided into multiple drains 220 by the multiple second wafer trenches 205-2; an initial gate structure 600' is formed within the second wafer trench 205-2; as shown... Figure 24 As shown, the initial gate structure 600' is divided into two gate structures 600 disposed opposite each other in a second direction; the end of the initial semiconductor body 200' is doped from the first surface 202 to form a source 210. Thus, the initial semiconductor body 200' is formed into a semiconductor body 200 through the above two doping processes. The semiconductor body 200 includes a source 210, a drain 220, and a channel 230 located between the source 210 and the drain 220. The source 210 and the drain 220 can be both doped with P-type dopant or both doped with N-type dopant. The dopant of the source 210 and the drain 220 can be the same or different. For example, the dopant can include, but is not limited to, boron (B), aluminum (Al), gallium (Ga), phosphorus (P), arsenic (As), or antimony (Sb).

[0122] As an example, the initial gate structure 600' may include a gate dielectric layer 610 and a gate conductive layer 620. The initial gate structure 600' may be formed as follows: a gate dielectric layer 610 is formed on the inner wall of the second wafer trench 205-2; wherein, the gate dielectric layer 610 may be formed by in-situ oxidation of the inner wall of the second wafer trench 205-2, or by a thin-film deposition process; the material of the gate dielectric layer 610 may include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, or high-k materials such as hafnium oxide, zirconium oxide, aluminum oxide, and tantalum oxide; a gate conductive layer 620 is formed on the side of the gate dielectric layer 610 facing away from the inner wall of the second wafer trench 205-2; the material of the gate conductive layer 620 may include, but is not limited to, polysilicon, metal, metal compound, silicide, or any combination thereof. For example, the material of the gate conductive layer 620 may include tungsten, aluminum, titanium, copper, cobalt, or tungsten nitride. Furthermore, to improve the adhesion between the gate conductive layer 620 and the gate dielectric layer 610, the initial gate structure 600' may also include a gate adhesive layer 630. Thus, before forming the gate conductive layer 620, the gate adhesive layer 630 may be formed on the side of the gate dielectric layer 610 facing away from the inner wall of the second wafer trench 205-2. The material of the gate adhesive layer 630 may include, but is not limited to, at least one of titanium nitride, tantalum nitride, and tungsten carbide.

[0123] The gate dielectric layer 610, the gate conductive layer 620, and the gate adhesive layer 630 can all be formed by thin film deposition processes. The thin film deposition process can be, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination of the above processes.

[0124] After forming the initial gate structure 600', the initial gate structure 600' can be divided into two gate structures 600 in the following manner: At least a portion of the initial gate structure 600' located on the bottom surface of the second wafer trench 205-2 is removed through the gap formed by the initial gate structure 600', so that the remaining initial gate structure 600' covers the sidewall of the second wafer trench 205-2 extending along the first direction and forms a ring; as shown... Figure 16As shown, a gate isolation layer 640 is formed within the gap enclosed by the initial gate structure 600'. The material of the gate isolation layer 640 may include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, or high-k materials such as hafnium oxide, zirconium oxide, aluminum oxide, and tantalum oxide. A gate trench (not shown) is formed by removing a portion of the initial gate structure 600' from the first surface 202 of the wafer 201. An isolation material is filled within the gate structure 600. The isolation material may be the same as or different from the material of the gate dielectric layer 610 and the gate isolation layer 640. If all three are the same, there may be no noticeable interface between the isolation material filling the gate trench and the gate dielectric layer 610, and between the isolation material and the gate isolation layer 640. Gate cut structures 650 are formed at both ends of the remaining initial gate structure 600' along a third direction. The gate cut structures 650 penetrate the initial gate structure 600' along a first direction to divide the remaining initial gate structure 600' into two gate structures 600 disposed opposite each other in a second direction.

[0125] As an example, the isolation structure 700 can be formed by depositing a dielectric material within the first wafer trench 205-1. As an example, the isolation structure 700 may have an air gap 701. When forming the isolation structure 700, two different deposition rates can be used to deposit the isolation material within the first wafer trench 205-1. For example, a portion of the isolation structure 700 can be formed on the inner wall of the first wafer trench 205-1 using a first deposition rate, while another portion of the isolation structure 700 can be formed at the opening of the first wafer trench 205-1 using a second deposition rate greater than the first deposition rate. Because the second deposition rate is greater than the first deposition rate, when both portions are deposited simultaneously, the isolation material at the opening of the first wafer trench 205-1 will quickly seal the opening. However, because the first deposition rate is slower, after sealing, some space within the first wafer trench 205-1 remains unfilled with isolation material, thus forming the air gap 701. Because the air gap 701 has a low dielectric constant, close to that of a vacuum, its presence can reduce the overall dielectric constant of the isolation structure 700, thereby reducing parasitic capacitance and thus reducing electrical interference between two adjacent semiconductor bodies 200. During the formation of the air gap 701, its size and position can be adjusted by controlling the first deposition rate and the second deposition rate. The larger the ratio between the second deposition rate and the first deposition rate, the larger the air gap 701 formed within the isolation structure 700, and the better its effect on reducing parasitic capacitance. For example, the ratio α between the second deposition rate and the first deposition rate can range from 1 ≤ α ≤ 3. As an example, the ratio α can range from 1.5 ≤ α ≤ 2. Furthermore, those skilled in the art should understand that, without departing from the technical solutions claimed in this application, the structure, composition, and fabrication process of the isolation structure 700 with the air gap 701 can be modified to obtain the various results and advantages described in this specification.

[0126] In the above description, the drain 220 is formed from the front side of wafer 201. In other embodiments, the drain 220 may also be formed from the back side of wafer 201. For example, as... Figure 13As shown, a transistor can be formed as follows: a plurality of first trenches 204, spaced apart in a third direction and extending along a second direction, are formed on the first surface 202 of wafer 201; a dielectric material is deposited within the first trenches 204 to form a first dielectric layer 240; and first wafer trenches 205-1 and second wafer trenches 205-2, alternately distributed in a second direction and extending along a third direction, are formed on the first surface 202 of wafer 201. The dimensions of the first wafer trenches 205-1 and second wafer trenches 205-2 in the first direction are smaller than the dimensions of the first trenches 204 in the first direction. Thus, the first trenches 204, the first wafer trenches 205-1, and the second wafer trenches 205-2 together divide a portion of wafer 201 in the first direction into a plurality of initial semiconductor bodies 200'. An isolation structure 700 is formed in the first wafer trench 205-1; an initial gate structure 600' is formed in the second wafer trench 205-2; the end of the initial semiconductor body 200' is doped from the first surface 202 of the wafer 201 to form a source 210. The wafer 201 is thinned from the second surface 203; the end of the initial semiconductor body 200' away from the first surface 202 is doped to form a drain 220.

[0127] In addition to the methods mentioned above, the initial gate structure 600' can also be divided in the following ways: After forming the initial gate structure 600' in the second wafer trench 205-2, a gate isolation layer 640 is formed within the gap formed by the initial gate structure 600'; the wafer 201 is thinned from the second surface 203 to expose the first dielectric layer 240; a portion of the first dielectric layer 240 is removed to form a first sub-trench (not shown) exposing the initial gate structure 600', and the first sub-trench extends along the second direction; a portion of the initial gate structure 600' is removed through the first sub-trench to form a second sub-trench (not shown) extending along the third direction. Thus, the remaining initial gate structure 600' covers the sidewall of the first wafer trench 205-1 extending along the first direction and is annular. The first sub-trench and the second sub-trench are filled with dielectric material; gate cut-out structures 650 are formed at both ends of the remaining initial gate structure 600' along a third direction, and the gate cut-out structures 650 penetrate the initial gate structure 600' along a first direction to divide the remaining initial gate structure 600' into two gate structures 600 disposed opposite each other in a second direction.

[0128] Furthermore, it should be noted that in addition to improving the isolation effect through the air gap 701, the isolation structure 700 can also improve the isolation effect by setting the isolation conductive layer 720. Subsequently, grounding or connecting the isolation conductive layer 720 to a negative voltage can improve the coupling effect between two adjacent transistors. As an example, the isolation structure 700 may include an isolation dielectric layer 710 and an isolation conductive layer 720. The isolation structure 700 can be formed as follows: an initial isolation structure 700' is formed in the first wafer trench 205-1, and the initial isolation structure 700' includes an isolation dielectric layer 710, an isolation conductive layer 720, and a conductive sacrificial layer (not shown). For example, an isolation material is deposited on the inner wall of the first wafer trench 205-1. The isolation material may include, but is not limited to, silicon oxide, silicon oxynitride, or silicon nitride. A conductive material is filled in the remaining space of the first wafer trench 205-1 to form a conductive sacrificial layer. The material of the conductive sacrificial layer may include, but is not limited to, at least one of tungsten, titanium nitride, copper, and silver. At least a portion of the conductive sacrificial layer is removed to form a first isolation trench. An isolation material is deposited on the inner wall of the first isolation trench to cover the conductive sacrificial layer. The remaining space of the first isolation trench is filled with conductive material to form an isolation conductive layer 720. The material of the isolation conductive layer 720 may include, but is not limited to, at least one of tungsten, titanium nitride, copper, and silver. At least a portion of the isolation conductive layer 720 is removed to form a second isolation trench. An isolation material is then filled in the second isolation trench. Thus, all the isolation material within the first wafer trench 205-1 constitutes an isolation dielectric layer 710, which surrounds the isolation conductive layer 720 and the conductive sacrificial layer. When a portion of the initial gate structure 600' is removed through the first sub-trench, the conductive sacrificial layer can be removed simultaneously to form the isolation structure 700. During this process, the portion of the isolation dielectric layer 710 located between the conductive sacrificial layer and the isolation conductive layer 720 can serve as an etching stop layer.

[0129] Step S210

[0130] In step 210, a capacitor structure 300 and a connection structure 400 are formed. The capacitor structure 300 includes a first electrode layer 310. One end of the connection structure 400 is in contact with the semiconductor body 200, and at least a portion of the other end of the connection structure 400 is located within the first electrode layer 310. As an example, the connection structure 400 can be formed during the formation of the first electrode layer 310; in other words, the first electrode layer 310 and the connection structure 400 can be formed in the same process. For example, the first electrode layer 310 and the connection structure 400 are formed using an atomic layer deposition (ALD) process.

[0131] Figure 25 This paper shows a schematic cross-sectional view of the xz plane of the filling medium layer 350 formed in an embodiment of this application; Figure 26AThis shows a schematic cross-sectional view of the xz plane of the capacitor hole 301 formed in the dielectric layer 350 in the embodiment of this application; Figure 26B This is a partially enlarged schematic diagram showing the formation of capacitor holes 301 in the filling dielectric layer 350 in an embodiment of this application; Figure 27A This shows a schematic cross-sectional view of the xz plane of the capacitor hole 301 forming the first electrode layer 310 and the connection structure 400 in the embodiment of this application. Figure 27B This is a partially enlarged schematic diagram showing the formation of a first electrode layer 310 and a connection structure 400 within the capacitor hole 301 in an embodiment of this application.

[0132] For example, the capacitor structure 300 and the connection structure 400 can be formed in the following manner: Figure 25 As shown, a filling dielectric layer 350 is formed on one side of the semiconductor body 200; wherein, the filling dielectric layer 350 can be a single-layer structure or a multi-layer structure, and this application does not limit it in this regard; Figure 26A and Figure 26B As shown, a capacitor hole 301 is formed that penetrates the filled dielectric layer 350 along the first direction and exposes the semiconductor body 200; as Figure 27A and Figure 27B As shown, an atomic layer deposition process is used to deposit metal material in the capacitor hole 301, so that a portion of the metal material reacts with a portion of the semiconductor substrate 200 to form a connection structure 400, and the remaining at least a portion of the metal material forms the first electrode layer 310. This allows the first electrode layer 310 and the connection structure 400 to be formed in situ.

[0133] Since the connection structure 400 is formed by the reaction of metal material with semiconductor body 200 during the formation of first electrode layer 310, one end of the connection structure 400 formed by the above method is in contact with semiconductor body 200, and at least a portion of the other end is located within first electrode layer 310. Therefore, the embodiment of this application, by using atomic layer deposition to deposit metal material within capacitor hole 301, not only meets the deposition requirements of capacitor hole 301 with a large aspect ratio, but also simultaneously forms connection structure 400 during the formation of first electrode layer 310. This simplifies the process, reduces costs, and also enables ohmic contact between semiconductor body 200 and first electrode layer 310 through connection structure 400.

[0134] Taking the material of the connection structure 400 as molybdenum silicide as an example, after forming the capacitor hole 301, an atomic layer deposition process can be used to form the first electrode layer 310 and the connection structure 400 using a molybdenum-containing material as a precursor. The deposition temperature of the atomic layer deposition process can be, but is not limited to, less than 1000°C. For example, a molybdenum-containing precursor is introduced into the reaction chamber of the semiconductor device to adsorb onto the inner wall of the capacitor hole 301; the precursor can include, but is not limited to, molybdenum pentachloride; the reaction chamber is purged with an inert gas to remove excess unadsorbed precursor and any possible byproducts; a reducing gas is introduced into the reaction chamber to react chemically with the precursor adsorbed on the inner wall of the capacitor hole 301 to form a molybdenum film; the reaction chamber is purged again with an inert gas to remove unreacted gas and byproducts; the above steps are repeated to deposit a molybdenum film layer by layer onto the inner wall of the capacitor hole 301. During the above process, a portion of the molybdenum film located on the bottom surface of the capacitor hole 301 reacts with the semiconductor body 200 to form molybdenum silicide, i.e., the connection structure 400, and the remaining unreacted portion of the molybdenum film constitutes the first electrode layer 310.

[0135] It should be noted that the aforementioned precursor may be, but is not limited to, molybdenum pentachloride. Other materials that can chemically react with reducing gases at high temperatures such as below 1000°C to form elemental metals and have good adsorption properties with the semiconductor host 200 may also be used as precursors for forming the connection structure 400 and the first electrode layer 310.

[0136] Furthermore, during the formation of the first electrode layer 310 and the connecting structure 400, the metal material can fill or almost fill the capacitor hole 301, making the formed first electrode layer 310 columnar. Conversely, during the formation of the first electrode layer 310 and the connecting structure 400, the metal material can also only cover the inner wall of the capacitor hole 301, making the formed first electrode layer 310 cylindrical. In other words, the first electrode layer 310 can surround the electrode hole.

[0137] Figure 28 The diagram shows a cross-sectional view of the capacitor dielectric layer 330 and the second electrode layer 320 formed in the electrode hole in the embodiment of this application.

[0138] like Figure 28As shown, taking the cylindrical first electrode layer 310 as an example, the step of forming the capacitor structure 300 may further include: forming a capacitor dielectric layer 330 on the inner wall of the electrode hole formed by the first electrode layer 310; and forming a second electrode layer 320 within the dielectric hole formed by the capacitor dielectric layer 330. Thus, the capacitor structure 300 includes a first electrode layer 310, a second electrode layer 320, and a capacitor dielectric layer 330, with the capacitor dielectric layer 330 located between the first electrode layer 310 and the second electrode layer 320, and the first electrode layer 310 located outside the second electrode layer 320.

[0139] In some other embodiments, the first electrode layer 310 may also be located inside the second electrode layer 320. In this case, the filling dielectric layer 350 may include a second dielectric layer 351 and a filling sacrificial layer (not shown) alternately stacked in the first direction; wherein, the material of the second dielectric layer 351 may include, but is not limited to, at least one of silicon nitride, silicon oxynitride, and aluminum oxide, and the material of the second dielectric layer 351 may also be doped with dopants such as boron or carbon. For example, the material of the second dielectric layer 351 may include silicon carbide (SiCN) or silicon boron nitride (SiBN); the material of the filling sacrificial layer may include, but is not limited to, silicon oxide and / or silicon oxynitride. For example, the material of the filling sacrificial layer may include silicon oxide or silicon oxide treated with an organic solution, and the organic solution may include, but is not limited to, TEOS (Tetraethoxysilane), BPSG (Boron-Phosphosilicate Glass), or PGS (Phosphosilicate Glass). If the first electrode layer 310 is columnar, then after the first electrode layer 310 and the connection structure 400 are formed, the filling sacrificial layer can be removed to expose at least part of the sidewalls of the first electrode layer 310; a capacitor dielectric layer 330 is formed on the exposed sidewalls of the first electrode layer 310; and a second electrode layer 320 is formed on the side of the capacitor dielectric layer 330 away from the first electrode layer 310. If the first electrode layer 310 is cylindrical, after the first electrode layer 310 and the connecting structure 400 are formed, a support core 340 can be formed in the first electrode layer 310 to surround the electrode hole. The material of the support core 340 can be, but is not limited to, elemental semiconductor materials such as silicon (Si), composite semiconductor materials such as germanium silicon (GeSi), or polycrystalline silicon doped with dopants such as boron. Then, the filling sacrificial layer is removed to expose at least part of the sidewalls of the first electrode layer 310. A capacitor dielectric layer 330 is formed on the exposed sidewalls of the first electrode layer 310. A second electrode layer 320 is formed on the side of the capacitor dielectric layer 330 away from the first electrode layer 310.

[0140] The materials of the first electrode layer 310 and the second electrode layer 320 mentioned above may include, but are not limited to, at least one of metals, metal compounds, semiconductor materials, and silicides; for example, the materials of the first electrode layer 310 and the second electrode layer 320 may include titanium nitride, titanium silicide, or nickel silicide. The material of the capacitor dielectric layer 330 may include, but is not limited to, at least one of aluminum oxide, tantalum oxide, titanium oxide, yttrium oxide, zirconium oxide, zirconium silicon oxide, hafnium oxide, hafnium silicon oxide, hafnium silicon nitride, hafnium zirconate, lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium aluminum oxide, and praseodymium oxide.

[0141] In some embodiments, the fabrication method may further include forming a bit line 800 on the side of the semiconductor body 200 away from the capacitor structure 300, the bit line 800 extending along a second direction. The material of the bit line 800 may include, but is not limited to, metallic materials such as tungsten, copper, or aluminum. In other embodiments, before forming the bit line 800, a bit line connection layer 810 may be formed on the side of the semiconductor body 200 away from the capacitor structure 300, the bit line connection layer 810 extending along the second direction. The material of the bit line connection layer 810 may include, but is not limited to, semiconductor materials having P-type dopants such as boron or gallium, or N-type dopants such as phosphorus or arsenic.

[0142] Figure 29A This illustration shows a schematic cross-sectional view of the xz plane of the removed undoped portion of wafer 201 in an embodiment of this application. Figure 29B This illustration shows a partial cross-sectional view of the yz plane of the removed undoped portion of wafer 201 in an embodiment of this application. Figure 30A This paper shows a schematic cross-sectional view of the bit line 800 formed in the embodiment of this application. Figure 30B A partial cross-sectional view of the yz plane forming bit line 800 in an embodiment of this application is shown.

[0143] The following is based on Figure 28 Taking the single-gate transistor shown as an example, the wafer 201 can be thinned from the second surface 203 of the wafer 201 using a process such as Chemical Mechanical Polishing (CMP) to expose the first dielectric layer 240; as Figure 29A and Figure 29B As shown, an undoped portion of wafer 201 is removed from the side of wafer 201 opposite to the first surface 202 to form a first line trench 801 extending along the second direction; as Figure 30A and Figure 30B As shown, a bit line connection layer 810 is formed in the first bit line trench 801; a portion of the bit line connection layer 810 is removed to form a second bit line trench (not shown) extending in the second direction; a bit line 800 is formed in the second bit line trench.

[0144] In some embodiments, the fabrication method may further include: forming a second semiconductor structure 110, the second semiconductor structure 110 may include, but is not limited to, a memory array and / or peripheral circuitry; and coupling the second semiconductor structure 110 to a first semiconductor structure 100 such that the second semiconductor structure 110 is located on one side of the first semiconductor structure 100 in a first direction and is connected to the first semiconductor structure 100.

[0145] In addition, this application also provides a storage system, which includes a controller and the aforementioned semiconductor device. The controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0146] Figure 31 A block diagram of a system with semiconductor devices according to one embodiment of this application is shown. System 900 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device with storage located therein. Figure 31 As shown, system 900 may include host 904 and memory system 901, the memory system 901 having one or more semiconductor devices 902 and memory controller 903. Host 904 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-a-chip (SoC), such as an application processor (AP). Host 904 may be configured to send or receive data from semiconductor device 902.

[0147] Semiconductor device 902 can be any semiconductor device disclosed in this application, such as Figures 12 to 16 The semiconductor device is shown. According to some embodiments, a memory controller 903 is coupled to the semiconductor device 902 and the host 904, and is configured to control the semiconductor device 902. The memory controller 903 can manage data stored in the semiconductor device 902 and communicate with the host 904.

[0148] In some embodiments, the memory controller 903 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 903 is designed to operate in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC), which is used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. The memory controller 903 can be configured to control the operation of the semiconductor device 902, such as read, erase, and program operations. The memory controller 903 can also be configured to manage various functions related to data stored in or to be stored in the semiconductor device 902, including but not limited to bad block management, garbage collection, logic-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 903 is further configured to process error correction codes (ECC) related to data read from or written to the semiconductor device 902. The memory controller 903 may also perform any other appropriate functions, such as formatting the semiconductor device 902. The memory controller 903 may communicate with external devices (e.g., the host 904) according to a specific communication protocol. For example, the memory controller 903 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0149] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. As an example, the steps described in this invention disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0150] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A semiconductor device, comprising a first semiconductor structure, the first semiconductor structure comprising: The semiconductor body extends along a first direction; A capacitor structure located on one side of the semiconductor body in the first direction and including a first electrode layer; as well as The connection structure has one end in contact with the semiconductor body in the first direction, and at least a portion of the other end located within the first electrode layer.

2. The semiconductor device according to claim 1, wherein, The connection structure protrudes from the surface of the first electrode layer toward the semiconductor body in the first direction and contacts the semiconductor body.

3. The semiconductor device according to claim 1, wherein, The connection structure includes a first connection surface and a second connection surface disposed opposite to each other in the first direction, and the surface of the first electrode layer facing the semiconductor body is located between the first connection surface and the second connection surface in the first direction.

4. The semiconductor device according to claim 1, wherein, The material of the connection structure includes the same metallic elements as the material of the first electrode layer.

5. The semiconductor device according to claim 4, wherein, The metallic element includes molybdenum.

6. The semiconductor device according to claim 4, wherein, The material of the connecting structure includes metal silicides containing the metal element.

7. The semiconductor device according to claim 1, wherein, The connection structure is a single-layer structure.

8. The semiconductor device according to claim 1, wherein, The dimension of the connection structure in the first direction is less than 10 nm.

9. The semiconductor device according to claim 1, wherein, The connection structure is formed by atomic layer deposition.

10. The semiconductor device according to claim 1, wherein, The dimension of the end of the first electrode layer facing the semiconductor body in the second direction is larger than the dimension of the connection structure in the second direction, and the second direction intersects the first direction.

11. The semiconductor device according to claim 1, wherein, The dimension of the end of the semiconductor body that contacts the connection structure in the second direction is the same as the dimension of the connection structure in the second direction, and the second direction intersects the first direction.

12. The semiconductor device according to any one of claims 1 to 11, wherein, The capacitor structure also includes: A second electrode layer extending along the first direction; and A capacitor dielectric layer is located on the sidewall of the second electrode layer extending along the first direction and on the end face of the second electrode layer facing the semiconductor body. The first electrode layer is located on the side of the capacitor dielectric layer opposite to the second electrode layer.

13. The semiconductor device according to any one of claims 1 to 11, wherein, The capacitor structure also includes: A capacitor dielectric layer, at least located on a portion of the sidewall extending along the first direction of the first electrode layer; and The second electrode layer is located on the side of the capacitor dielectric layer opposite to the first electrode layer.

14. The semiconductor device according to claim 13, wherein, The capacitor structure further includes a support core, with the first electrode layer located on the sidewall of the support core extending along the first direction and on the end face of the support core facing the semiconductor body.

15. The semiconductor device according to claim 13, wherein, The first electrode layer has a columnar structure, and the end of the connection structure that is away from the semiconductor body in the first direction is located within the first electrode layer.

16. The semiconductor device according to any one of claims 1 to 11, wherein, The first semiconductor structure further includes a filling dielectric layer, and the first electrode layer penetrates the filling dielectric layer along the first direction.

17. The semiconductor device according to any one of claims 1 to 11, wherein, The first semiconductor structure further includes: A gate structure is located on at least a portion of the sidewall of the semiconductor body extending along the first direction.

18. The semiconductor device according to claim 17, wherein, The first semiconductor structure further includes: An isolation structure is located on one side of the semiconductor body in the second direction and extends along the third direction; The gate structure is located on the side of the semiconductor body away from the isolation structure in the second direction and extends along the third direction, wherein the first direction, the second direction and the third direction intersect each other.

19. The semiconductor device according to claim 18, wherein, The isolation structure has an air gap.

20. The semiconductor device according to any one of claims 1 to 11, wherein, The first semiconductor structure further includes: Bit lines are located on the side of the semiconductor body away from the capacitor structure in the first direction and extend along the second direction; Wherein, the first direction intersects with the second direction.

21. The semiconductor device according to any one of claims 1 to 11, wherein, The semiconductor device further includes: A second semiconductor structure is located on one side of the first semiconductor structure in the first direction and is coupled to the first semiconductor structure. The second semiconductor structure includes a memory array and / or peripheral circuitry.

22. A method for fabricating a semiconductor device, comprising: A semiconductor body extending along the first direction is formed; as well as Forming capacitor structures and connection structures; The capacitor structure is located on one side of the semiconductor body in the first direction and includes a first electrode layer. One end of the connection structure in the first direction is in contact with the semiconductor body, and at least a portion of the other end is located within the first electrode layer.

23. The method for fabricating a semiconductor device according to claim 22, wherein, The connection structure is formed during the formation of the first electrode layer.

24. The method for fabricating a semiconductor device according to claim 22, wherein, The first electrode layer and the connection structure are formed in the same process.

25. The method for fabricating a semiconductor device according to claim 22, wherein, The first electrode layer and the connection structure are formed by atomic layer deposition.

26. The method for fabricating a semiconductor device according to any one of claims 22 to 25, wherein, The formation of capacitor structures and connection structures includes: A filling dielectric layer is formed on one side of the semiconductor body; Forming a capacitor hole penetrating the filling dielectric layer along the first direction; and Metal material is deposited in the capacitor aperture using atomic layer deposition (ALD) to form the first electrode layer and the connection structure in situ.

27. The method for fabricating a semiconductor device according to claim 26, wherein, Depositing metallic material within the capacitor aperture using atomic layer deposition (ALD) to form the first electrode layer and the connection structure in situ includes: Metal material is deposited within the capacitor aperture so that a portion of the metal material reacts with a portion of the semiconductor substrate to form the connection structure, and the remaining at least a portion of the metal material forms the first electrode layer.

28. The method for fabricating a semiconductor device according to claim 26, wherein, Depositing metallic material within the capacitor aperture to form the first electrode layer and the connection structure in situ includes: The first electrode layer and the connection structure are formed using an atomic layer deposition process with a molybdenum-containing material as a precursor.

29. The method for fabricating a semiconductor device according to claim 28, wherein, The precursor includes molybdenum pentachloride.

30. The method for fabricating a semiconductor device according to claim 26, wherein, The deposition temperature of the atomic layer deposition process is less than 1000℃.

31. A storage system, characterized in that, The storage system includes a controller and a semiconductor device according to any one of claims 1 to 21, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

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