Semiconductor device and preparation method thereof, and storage system

Abstract

The invention discloses a semiconductor device, a preparation method thereof and a storage system. The semiconductor device includes a peripheral circuit structure, a first semiconductor structure on a side of the peripheral circuit structure in a first direction and coupled to the peripheral circuit structure, and a second semiconductor structure on a side of the peripheral circuit structure in a second direction. The second semiconductor structure is located on the side, away from the first semiconductor structure, of the peripheral circuit structure in the first direction and is coupled with the peripheral circuit structure, the peripheral circuit structure comprises a plurality of first transistors, the first semiconductor structure comprises a first bit line, and the second semiconductor structure comprises a second bit line; the first bit line and the second bit line are connected through a plurality of first transistors.

Description

Semiconductor devices and their fabrication methods, storage systems Technical Field

[0001] The embodiments of this application relate to the field of semiconductor technology, and in particular to semiconductor devices and their fabrication methods and storage systems. Background Technology

[0002] Semiconductor devices are memory devices used in modern information technology to store information. Their main function is to store programs and various data, and to perform high-speed, automatic access to programs or data during computer operation. For example, a semiconductor device includes a memory array and peripheral circuitry. The peripheral circuitry can accurately control the access to programs or data in the memory array, ensuring the speed and accuracy of information processing. Summary of the Invention

[0003] This application provides a semiconductor device, a method for fabricating the same, and a storage system.

[0004] The first aspect of this application provides a semiconductor device, which includes a peripheral circuit structure, a first semiconductor structure, and a second semiconductor structure. The first semiconductor structure is located on one side of the peripheral circuit structure in a first direction and is coupled to the peripheral circuit structure. The second semiconductor structure is located on the side of the peripheral circuit structure opposite to the first semiconductor structure in the first direction and is coupled to the peripheral circuit structure. The peripheral circuit structure includes a plurality of first transistors, the first semiconductor structure includes a first bit line, and the second semiconductor structure includes a second bit line. The first bit line and the second bit line are connected through the plurality of first transistors.

[0005] In some implementations, the peripheral circuitry includes a bit line selector and a sense amplifier. The bit line selector includes a plurality of first transistors, and the sense amplifier is connected to the first transistors.

[0006] In some implementations, the plurality of first bit lines include a first target bit line and a first reference bit line, and the plurality of second bit lines include a second target bit line and a second reference bit line. The first target bit line and the first reference bit line, as well as the second target bit line and the second reference bit line, are respectively connected through a plurality of first transistors.

[0007] In some embodiments, the peripheral circuit structure further includes a control circuit. A plurality of first transistors include a first selection transistor, a second selection transistor, a third selection transistor, and a fourth selection transistor. The first electrode of the first selection transistor is connected to a first target bit line, the second electrode of the first selection transistor is connected to a sense amplifier, the first electrode of the second selection transistor is connected to a first reference bit line, the second electrode of the second selection transistor is connected to a sense amplifier, the first electrode of the third selection transistor is connected to both the second electrode of the first selection transistor and the sense amplifier, the second electrode of the third selection transistor is connected to a second target bit line, the first electrode of the fourth selection transistor is connected to both the second electrode of the first reference bit line and the sense amplifier, the second electrode of the fourth selection transistor is connected to the second reference bit line, and the gates of the first, second, third, and fourth selection transistors are all connected to the control circuit.

[0008] In some embodiments, the first semiconductor structure includes a first memory array including a first bit line, the second semiconductor structure includes a second memory array including a second bit line, and the bit line selector and sense amplifier are located directly below and / or directly above the first memory array in a first direction.

[0009] In some implementations, the peripheral circuitry also includes a word line driver, with the bit line selector located in a second direction between the sense amplifier and the word line driver, where the first and second directions intersect.

[0010] In some embodiments, the peripheral circuit structure further includes a semiconductor layer and a connection structure, the connection structure extending through the semiconductor layer along a first direction, at least a portion of the first transistor being located in the semiconductor layer, one end of the connection structure being connected to the first bit line and the first transistor respectively, and the other end being connected to the second bit line.

[0011] In some embodiments, the peripheral circuit structure further includes a trench isolation structure that penetrates the semiconductor layer along a first direction and surrounds the active region of the first transistor, and the connection structure penetrates the trench isolation structure along the first direction.

[0012] In some embodiments, the peripheral circuit structure further includes a first interconnect layer and a second interconnect layer. The first interconnect layer is located in a first direction on the side of the semiconductor layer facing the first semiconductor structure and is connected to the first transistor. The second interconnect layer is located in a first direction on the side of the semiconductor layer facing the second semiconductor structure and is connected to the connection structure.

[0013] In some embodiments, the second interconnect layer includes an oxide layer, a sub-interconnect layer, and a contact structure. The oxide layer is located in a first direction on the side of the semiconductor layer facing the second semiconductor structure. The sub-interconnect layer is located in the first direction on the side of the oxide layer away from the semiconductor layer. The contact structure is located in the oxide layer, with one end of the contact structure connected to the sub-interconnect layer and the other end penetrating the oxide layer along the first direction and connected to the interconnect structure.

[0014] In some implementations, the first transistor is a fully depleted transistor.

[0015] A second aspect of this application provides a method for fabricating a semiconductor device, the method comprising: forming a peripheral circuit structure and coupling the peripheral circuit structure to a first semiconductor structure and a second semiconductor structure; wherein the first semiconductor structure is located on one side of the peripheral circuit structure in a first direction, the second semiconductor structure is located on the side of the peripheral circuit structure opposite to the first semiconductor structure in the first direction, the first semiconductor structure includes a first bit line, the second semiconductor structure includes a second bit line, the peripheral circuit structure includes a plurality of first transistors, and the first bit line and the second bit line are connected through the plurality of first transistors.

[0016] In some embodiments, forming a peripheral circuit structure and coupling the peripheral circuit structure to a first semiconductor structure and a second semiconductor structure includes: forming an initial peripheral circuit structure, the initial peripheral circuit structure including a substrate and a first transistor, at least a portion of the first transistor being located in the substrate; coupling the first semiconductor structure to the initial peripheral circuit structure; at least thinning the substrate to form the peripheral circuit structure; and coupling the second semiconductor structure to the peripheral circuit structure.

[0017] In some embodiments, forming an initial peripheral circuit structure includes: forming an oxide layer in a substrate, wherein the substrate includes a first surface and a second surface disposed opposite to each other in a first direction, the oxide layer being located between the first surface and the second surface; forming a first transistor in the substrate from the first surface, the first transistor being located on the side of the oxide layer opposite to the second surface; and forming a first interconnect layer from the first surface of the substrate covering and connecting the first transistor, the first interconnect layer being coupled to a first semiconductor structure.

[0018] In some embodiments, forming the initial peripheral circuit structure further includes: forming a trench isolation structure in the substrate extending along a first direction to an oxide layer, the trench isolation structure surrounding the active region of the first transistor; and forming a connection structure extending along the first direction through the trench isolation structure, the connection structure being connected to the first interconnect layer.

[0019] In some embodiments, forming an oxide layer in a substrate includes: implanting oxygen ions into the substrate from a first surface of the substrate; and annealing the substrate to allow the oxygen ions to react with the substrate to form an oxide layer.

[0020] In some embodiments, thinning at least the side of the substrate away from the first interconnect layer includes: thinning the substrate from a second surface of the substrate and stopping at an oxide layer; forming a second interconnect layer on the remaining side of the substrate away from the first interconnect layer.

[0021] In some embodiments, forming a second interconnect layer on the side of the substrate away from the first interconnect layer includes: forming a contact structure extending through the oxide layer in a first direction and connected to the first transistor from the side of the oxide layer away from the substrate; and forming a sub-interconnect layer covering the oxide layer, the sub-interconnect layer being connected to the contact structure.

[0022] A third aspect of this application provides a storage system, which includes a controller and a semiconductor device according to the first aspect of this application. The controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0023] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0024] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. The drawings are provided for a better understanding of the invention and are not intended to limit the scope of the application. In the drawings:

[0025] Figure 1 is a cross-sectional schematic diagram of a semiconductor device according to one embodiment of this application;

[0026] Figure 2 is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of this application;

[0027] Figure 3 is a partial circuit diagram of the peripheral circuit structure according to one embodiment of the present application;

[0028] Figure 4 is a schematic plan view of the peripheral circuit structure according to one embodiment of the present application;

[0029] Figure 5 is a planar layout schematic diagram of the peripheral circuit structure according to another embodiment of this application;

[0030] Figure 6 is a schematic flowchart of a method for fabricating a semiconductor device according to one embodiment of this application;

[0031] Figures 7 to 15 are schematic diagrams illustrating the fabrication process of a semiconductor device according to one embodiment of this application; and

[0032] Figure 16 is a block diagram of a system having semiconductor devices according to one embodiment of the present application.

[0033] Figure label:

[0034] 100. Peripheral circuit structure; 100'. Initial peripheral circuit structure; 101. First region;

[0035] 102. Second region; 103. Sensing amplifier; 104. Word line driver;

[0036] 105. Bit line selector; 110. Substrate; 110-1. First surface;

[0037] 110-2, Second surface; 111, Semiconductor layer; 120, First transistor;

[0038] 121. First selection transistor; 122. Second selection transistor;

[0039] 123. Third selection transistor; 124. Fourth selection transistor; 125. First source;

[0040] 126. First drain; 127. Gate conductive layer; 130. Trench isolation structure;

[0041] 140. Connection structure; 150. First interconnect layer; 160. Second interconnect layer;

[0042] 161. Oxide layer; 162. Sub-interconnect layer; 163. Contact structure;

[0043] 170. First N-type transistor; 171. Second N-type transistor;

[0044] 172. First P-type transistor; 173. Second P-type transistor;

[0045] 200. First semiconductor structure; 210. First memory array; 211. First bit line;

[0046] 212, First target bit line; 213, First reference bit line; 220, First semiconductor pillar;

[0047] 221. Source; 222. Drain; 223. Channel; 230. First gate structure;

[0048] 231. Gate dielectric layer; 232. Gate layer; 240. First capacitor;

[0049] 300. Second semiconductor structure; 310. Second memory array; 311. Second bit line;

[0050] 312. Second target bit line; 313. Second reference bit line; 320. Second semiconductor pillar;

[0051] 330, Second gate structure; 340, Second capacitor; 410, First structure;

[0052] 420. Second structure; 500. System; 501. Memory system;

[0053] 502. Semiconductor device; 503. Memory controller; 504. Host computer. Detailed Implementation

[0054] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0055] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence.

[0056] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale.

[0057] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0058] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0059] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0060] Furthermore, in this application, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a range smaller than that of the structure below or above. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. Furthermore, in this application, the use of "connection" or "joint" may indicate direct or indirect contact between corresponding components, unless otherwise expressly defined or inferred from the context.

[0061] Figure 1 shows a cross-sectional schematic diagram of a semiconductor device according to one embodiment of the present application. As shown in Figure 1, the present application provides a semiconductor device including a first structure 410 and a second structure 420. The second structure 420 is located on one side of the first structure 410 in a first direction and is coupled to the first structure 410. The first structure 410 includes a memory array, and the second structure 420 includes peripheral circuitry connected to the memory array.

[0062] Figure 2 shows a cross-sectional schematic diagram of a semiconductor device according to another embodiment of this application. Figure 3 shows a partial circuit diagram of the peripheral circuit structure 100 of a semiconductor device according to one embodiment of this application. Figures 4 and 5 show planar layout schematic diagrams of the peripheral circuit structure 100 according to different embodiments of this application. As shown in Figures 2 to 5, the semiconductor device includes a peripheral circuit structure 100, a first semiconductor structure 200, and a second semiconductor structure 300. The first semiconductor structure 200 is located on one side of the peripheral circuit structure 100 in a first direction and is coupled to the peripheral circuit structure 100. The second semiconductor structure 300 is located on the side of the peripheral circuit structure 100 opposite to the first semiconductor structure 200 in the first direction and is coupled to the peripheral circuit structure 100. The peripheral circuit structure 100 includes a plurality of first transistors 120. The first semiconductor structure 200 includes a first bit line 211, and the second semiconductor structure 300 includes a second bit line 311. The first bit line 211 and the second bit line 311 are connected through the plurality of first transistors 120.

[0063] In this embodiment, the two sides of the peripheral circuit structure 100 are coupled to the first semiconductor structure 200 and the second semiconductor structure 300, respectively. Since the first bit line 211 of the first semiconductor structure 200 and the second bit line 311 of the second semiconductor structure 300 are connected through a plurality of first transistors 120 of the peripheral circuit structure 100, this embodiment can realize the switching control of the first semiconductor structure 200 and the second semiconductor structure 300 by adjusting the on and off of the plurality of first transistors 120. In other words, the first semiconductor structure 200 and the second semiconductor structure 300 can be controlled by one peripheral circuit structure 100, thereby not only reducing costs, but also increasing the storage density per unit area of ​​the entire semiconductor device, and the storage efficiency can be increased several times at the same technology node.

[0064] It should be noted that the first transistor 120 in the embodiments of this application may be, but is not limited to, a fully depleted transistor. The types of the plurality of first transistors 120 may be different; for example, some of the first transistors 120 may be N-type transistors, while the remaining first transistors 120 may be P-type transistors.

[0065] In some embodiments, the first semiconductor structure 200 may include a first memory array 210, which includes a first bit line 211 and a plurality of first memory cells respectively connected to the first bit line 211. The second semiconductor structure 300 includes a second memory array 310, which includes a second bit line 311 and a plurality of second memory cells respectively connected to the second bit line 311. The first memory array 210 and the second memory array 310 may be, but are not limited to, DRAM memory arrays.

[0066] In some embodiments, the peripheral circuit structure 100 includes a bit line selector 105 and a sensing amplifier 103. The bit line selector 105 includes a plurality of first transistors 120, and the sensing amplifier 103 is connected to the first transistors 120. As an example, as shown in FIG3, the first semiconductor structure 200 may include a plurality of first bit lines 211, the plurality of first bit lines 211 including a first target bit line 212 and a first reference bit line 213. The second semiconductor structure 300 includes a plurality of second bit lines 311, the plurality of second bit lines 311 including a second target bit line 312 and a second reference bit line 313. The first target bit line 212 and the first reference bit line 213, and the second target bit line 312 and the second reference bit line 313 are respectively connected through the bit line selector 105, i.e., the plurality of first transistors 120. The first transistors 120 are connected to the sensing amplifier 103. Therefore, the embodiments of this application can realize the connection between the sensing amplifier 103 and the first target bit line 212 and the second reference bit line 313, or the sensing amplifier 103 and the second target bit line 312 and the second reference bit line 313, by controlling the on and off of the plurality of first transistors 120.

[0067] In some embodiments, the bit line selector 105 and the sensing amplifier 103 may be located directly below the first memory array 210 and / or directly above the second memory array 310 in the first direction. It should be noted that the terms "directly above" and "directly below" used above are merely for ease of describing the relative positional relationship between the bit line selector 105 and the sensing amplifier 103 and the first and second memory arrays 210, and do not indicate or imply that the first memory array 210 must be located above the second memory array 310. Therefore, they should not be construed as limitations on the embodiments of this application. For example, the bit line selector 105 and the sensing amplifier 103 being located directly below the first memory array 210 and directly above the second memory array 310 in the first direction can be understood as the projections of the bit line selector 105 and the sensing amplifier 103 at least partially overlapping the projection of the first memory array 210 and the projection of the second memory array 310 in a plane perpendicular to the first direction.

[0068] In some embodiments, as shown in FIG4, the peripheral circuit structure 100 may further include a word line driver 104, and a bit line selector 105 located between the sense amplifier 103 and the word line driver 104 in a second direction, with the first direction intersecting the second direction. The intersection of the first and second directions generally means that there is an angle between them. For example, the first and second directions are perpendicular or approximately perpendicular to each other. As an example, in this embodiment, the first direction may be the z-direction in the figures, and the second direction may be the x-direction in the figures. As an example, the word line driver 104, the bit line selector 105, and the sense amplifier 103 are located directly below the first memory array 210 in the first direction. Since the area of ​​the word line driver 104 and the sense amplifier 103 is usually smaller than the area of ​​the first memory array 210, in other words, the projection of the first memory array 210 is not completely covered by the projection of the word line driver 104 and the sense amplifier 103 on the plane perpendicular to the first direction. Therefore, by adding a bit line selector 105 and placing the bit line selector 105 between the word line driver 104 and the sense amplifier 103, this embodiment of the application can not only realize the switching control of the peripheral circuit structure 100 on the first semiconductor structure 200 and the second semiconductor structure 300, but also does not affect the area of ​​the entire semiconductor device.

[0069] In some embodiments, the peripheral circuit structure 100 may further include a control circuit. A bit line selector 105 is connected to the control circuit, which controls the on / off state of a plurality of first transistors 120. As shown in FIG5, the peripheral circuit structure 100 has a first region 101 and a second region 102. The second region 102 is located to one side of the first region 101 in a third direction. A word line driver 104, a bit line selector 105, and a sense amplifier 103 are disposed in the first region 101, and a control circuit (not shown) is disposed in the second region 102. The first region 101 may be located directly below the first memory array 210 and / or directly above the second memory array 310 in a first direction. The first direction, the second direction, and the third direction intersect each other.

[0070] The following description uses an external circuit structure 100, including a bit line selector 105, a sensing amplifier 103, and a control circuit, with the bit line selector 105 comprising four first transistors 120, as an example to illustrate the connection relationship between the bit line selector 105, the sensing amplifier 103, and the control circuit. As shown in Figure 3, for ease of description, the four first transistors 120 are referred to sequentially as the first selection transistor 121, the second selection transistor 122, the third selection transistor 123, and the fourth selection transistor 124. The first electrode of the first selection transistor 121 is connected to the first target bit line 212, and the second electrode of the first selection transistor 121 is connected to the sense amplifier 103; the first electrode of the second selection transistor 122 is connected to the first reference bit line 213, and the second electrode of the second selection transistor 122 is connected to the sense amplifier 103; the first electrode of the third selection transistor 123 is connected to the second electrode of the first selection transistor 121 and the sense amplifier 103, respectively, and the second electrode of the third selection transistor 123 is connected to the second target bit line 312; the first electrode of the fourth selection transistor 124 is connected to the second electrode of the first reference bit line 213 and the sense amplifier 103, respectively, and the second electrode of the fourth selection transistor 124 is connected to the second reference bit line 313; the gates of the first selection transistor 121, the second selection transistor 122, the third selection transistor 123, and the fourth selection transistor 124 are all connected to the control circuit.

[0071] Therefore, by controlling the first selection transistor 121 and the second selection transistor 122 to be turned on, and controlling the third selection transistor 123 and the fourth selection transistor 124 to be turned off, the sensing amplifier 103 can be connected to the first target bit line 212 and the first reference bit line 213. Similarly, by controlling the first selection transistor 121 and the second selection transistor 122 to be turned off, and controlling the third selection transistor 123 and the fourth selection transistor 124 to be turned on, the sensing amplifier 103 can be connected to the second target bit line 312 and the second reference bit line 313.

[0072] As an example, the sensing amplifier 103 includes a first N-type transistor 170, a second N-type transistor 171, a first P-type transistor 172, and a second P-type transistor 173. Specifically, the gate of the first N-type transistor 170 is connected to the second electrode of the second selection transistor 122 and the first electrode of the fourth selection transistor 124, respectively, and the source of the first N-type transistor 170 is connected to the first voltage node SAN; the gate of the second N-type transistor 171 is connected to the second electrode of the first selection transistor 121 and the first electrode of the third selection transistor 123, respectively, and the source of the second N-type transistor 171 is connected to the first voltage node SAN; the gate of the first P-type transistor 172 is connected to the second electrode of the second selection transistor 122 and the first electrode of the fourth selection transistor 124, respectively, and the source of the first P-type transistor 172 is connected to the first voltage node SAP, and the drain of the first P-type transistor 172 is connected to the drain of the first N-type transistor 170; the gate of the second P-type transistor 173 is connected to the second electrode of the first selection transistor 121 and the first electrode of the third selection transistor 123, respectively, and the source of the second P-type transistor 173 is connected to the second voltage node SAP, and the drain of the second P-type transistor 173 is connected to the drain of the second N-type transistor 171. The connection point between the first N-type transistor 170 and the first P-type transistor 172 is BLB, and the connection point between the second N-type transistor 171 and the second P-type transistor 173 is BLT.

[0073] Assuming that during the charging process of the first target bit line 212 to the memory cell of the first semiconductor structure 200, the voltage of the first target bit line 212 changes to 0.3Vcc, the potential of the first reference bit line 213 is 0.5Vcc, the voltage of the first voltage node SAN is 0, and the voltage of the second voltage node SAP is 1Vcc, then when the control circuit controls the first selection transistor 121 and the second selection transistor 122 to be turned on, and the third selection transistor 123 and the fourth selection transistor 124 to be turned off, since the first electrode of the second selection transistor 122 is connected to the first reference bit line 213, and the second electrode of the second selection transistor 122 is connected to the gate of the first N-type transistor 170, the voltage of the gate of the first N-type transistor 170 is the same as the voltage of the first reference bit line 213 when the second selection transistor 122 is turned on, that is, the voltage of the gate of the first N-type transistor 170 is 0.5Vcc. Similarly, since the first electrode of the first selection transistor 121 is connected to the first target bit line 212, and the second electrode of the first selection transistor 121 is connected to the gate of the second N-type transistor 171, the gate voltage of the second N-type transistor 171 is the same as the voltage of the first target bit line 212 when the first selection transistor 121 is turned on; that is, the gate voltage of the second N-type transistor 171 is 0.3Vcc. Given that the threshold voltages of both the first N-type transistor 170 and the second N-type transistor 171 are greater than 0, when the gate voltage of the first N-type transistor 170 is 0.5Vcc and the gate voltage of the second N-type transistor 171 is 0.3Vcc, the first N-type transistor 170 is turned on preferentially compared to the second N-type transistor 171. When the first N-type transistor 170 is turned on, the voltage at connection point BLB is the same as the voltage at the first voltage node SAN. Therefore, when the voltage at the first voltage node SAN is 0, the voltage at connection point BLB is also 0, and consequently, the voltage at the gate of the second N-type transistor 171 becomes 0, causing the second N-type transistor 171 to remain off. Similarly, since the first electrode of the second selection transistor 122 is connected to the first reference bit line 213, and the second electrode of the second selection transistor 122 is connected to the gate of the first P-type transistor 172, when the second selection transistor 122 is turned on, the voltage at the gate of the first P-type transistor 172 is the same as the voltage at the first reference bit line 213, that is, the voltage at the gate of the first P-type transistor 172 is 0.5Vcc. Since the first electrode of the first selection transistor 121 is connected to the first target bit line 212, and the second electrode of the first selection transistor 121 is connected to the gate of the second P-type transistor 173, the voltage of the gate of the second P-type transistor 173 is the same as the voltage of the first target bit line 212 when the first selection transistor 121 is turned on. That is, the voltage of the gate of the second P-type transistor 173 is 0.3Vcc.Since the threshold voltages of both the first P-type transistor 172 and the second P-type transistor 173 are less than 0, when the gate voltage of the first P-type transistor 172 is 0.5Vcc and the gate voltage of the second P-type transistor 173 is 0.3Vcc, the second P-type transistor 173 will conduct preferentially compared to the first P-type transistor 172. After the second P-type transistor 173 conducts, the voltage at the connection point BLT is the same as the voltage at the second voltage node SAP. Therefore, when the voltage at the second voltage node is 1Vcc, the voltage at the connection point BLT is also 1Vcc, and thus the gate voltage of the first P-type transistor 172 changes to 1Vcc, causing the first P-type transistor 172 to remain off. As can be seen, at this time, the first N-type transistor 170 and the second P-type transistor 173 are turned on, while the second N-type transistor 171 and the first P-type transistor 172 are turned off. Consequently, the gate voltage of the first N-type transistor 170 and the voltage of the first reference bit line 213 become 1Vcc, and the gate voltage of the second P-type transistor 173 and the voltage of the first target bit line 212 become 0. Therefore, through the amplification effect of the sensing amplifier 103, the voltage difference between the first target bit line 212 and the first reference bit line 213 is amplified from 0.2Vcc to 1Vcc.

[0074] It should be noted that the control circuit controls the first selection transistor 121 and the second selection transistor 122 to be turned off, while the third selection transistor 123 and the fourth selection transistor 124 are turned on in a similar manner as described above, and will not be repeated here.

[0075] In some embodiments, the peripheral circuit structure 100 may further include a semiconductor layer 111 and a connection structure 140. The connection structure 140 extends through the semiconductor layer 111 in a first direction. At least a portion of the first transistor 120 is located in the semiconductor layer 111. One end of the connection structure 140 is connected to the first bit line 211 and the first transistor 120, respectively, and the other end of the connection structure 140 is connected to the second bit line 311.

[0076] As an example, the peripheral circuit structure 100 also includes a trench isolation structure 130, which penetrates the semiconductor layer 111 along a first direction and surrounds the active region of the first transistor 120, and the connection structure 140 penetrates the trench isolation structure 130 along the first direction.

[0077] In some embodiments, the peripheral circuit structure 100 may further include a first interconnect layer 150 and a second interconnect layer 160. The first interconnect layer 150 is located in a first direction on the side of the semiconductor layer 111 facing the first semiconductor structure 200 and is connected to the first transistor 120. The second interconnect layer 160 is located in the first direction on the side of the semiconductor layer 111 facing the second semiconductor structure 300 and is connected to the connection structure 140. As an example, the second interconnect layer 160 may include an oxide layer 161, a sub-interconnect layer 162, and a contact structure 163. The oxide layer 161 is located in the first direction on the side of the semiconductor layer 111 facing the second semiconductor structure 300. The sub-interconnect layer 162 is located in the first direction on the side of the oxide layer 161 away from the semiconductor layer 111. The contact structure 163 is located in the oxide layer 161. One end of the contact structure 163 is connected to the sub-interconnect layer 162, and the other end of the contact structure 163 extends through the oxide layer 161 in a first direction and is connected to the connection structure 140.

[0078] In some embodiments, the first semiconductor structure 200 may further include a first semiconductor pillar 220, a first gate structure 230, and a first capacitor 240. The first semiconductor pillar 220 extends along a first direction, the first gate structure 230 is located on the sidewall of the first semiconductor pillar 220 extending along the first direction, the first capacitor 240 is located on one side of the first semiconductor pillar 220 in the first direction and connected to the first semiconductor pillar 220, and a first line 211 is located on the side of the first semiconductor pillar 220 away from the first capacitor 240 in the first direction and connected to the first semiconductor pillar 220. As an example, the first line 211 extends along a second direction and is connected to a plurality of first semiconductor pillars 220 spaced apart in the second direction, and the first gate structure 230 extends along a third direction. The first direction, the second direction, and the third direction intersect each other. The intersection of the first direction, the second direction, and the third direction can generally be understood as an angle between the first direction and the second direction, an angle between the second direction and the third direction, and an angle between the first direction and the third direction. As an example, in the embodiments of this application, the first direction can be the z direction in the figure, the second direction can be the x direction in the figure, and the third direction can be the y direction in the figure.

[0079] In some embodiments, the second semiconductor structure 300 further includes a second semiconductor pillar 320, a second gate structure 330, and a second capacitor 340. The second semiconductor pillar 320 extends along a first direction, the second gate structure 330 is located on the sidewall of the second semiconductor pillar 320 extending along the first direction, the second capacitor 340 is located on one side of the second semiconductor pillar 320 in the first direction and is connected to the second semiconductor pillar 320, and the second bit line 311 is located on the side of the second semiconductor pillar 320 away from the second capacitor 340 in the first direction and is connected to the second semiconductor pillar 320.

[0080] As an example, both the first semiconductor pillar 220 and the second semiconductor pillar 320 may include a source 221, a drain 222, and a channel 223, with the channel 223 located between the source 221 and the drain 222 in a first direction. Furthermore, both the first gate structure 230 and the second gate structure 330 may include a gate dielectric layer 231 and a gate layer 232. Taking the first semiconductor structure 200 as an example, the gate dielectric layer 231 is located on the sidewall of the first semiconductor pillar 220 extending along the first direction, and the gate layer 232 is located on the side of the gate dielectric layer 231 facing away from the first semiconductor pillar 220. The material of the gate dielectric layer 231 may include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, or high-k materials such as hafnium oxide, zirconium oxide, aluminum oxide, and tantalum oxide. The material of the gate layer 232 may include, but is not limited to, polysilicon, tungsten, aluminum, titanium, copper, cobalt, tungsten nitride, or any combination thereof. To improve the adhesion between the gate dielectric layer 231 and the gate layer 232, a gate adhesive layer (not shown) may also be provided between the gate dielectric layer 231 and the gate layer 232. The material of the gate adhesive layer may include, but is not limited to, at least one of titanium nitride, tantalum nitride, and tungsten carbide.

[0081] Therefore, the first semiconductor structure 200 and the second semiconductor structure 300 include multiple memory cells. Taking the first semiconductor structure 200 as an example, each memory cell includes a first gate transistor and a first capacitor 240. The first gate transistor includes a first semiconductor pillar 220 and a first gate structure 230. The memory cell uses the amount of charge stored in the first capacitor 240 to represent whether a binary bit is 1 or 0. The drain 222 of the first gate transistor is typically electrically connected to the first bit line 211, and the source 221 of the first gate transistor is typically electrically connected to one electrode of the first capacitor 240. The other electrode of the first capacitor 240 can be grounded or connected to a reference voltage. The first gate structure 230 of the first gate transistor is electrically connected to the word line (WL). The word line is used to apply voltage to control the conduction or cutoff of the first gate transistor, and the first bit line 211 is used to perform read or write operations on the first capacitor 240 when the first gate transistor is on.

[0082] Figure 6 shows a flow chart of a semiconductor device fabrication method according to one embodiment of this application; Figures 7 to 15 show process diagrams of a semiconductor device fabrication method according to another embodiment of this application. As shown in Figures 6 to 15, the fabrication method includes:

[0083] S100: Forming a peripheral circuit structure 100 and coupling the peripheral circuit structure 100 to a first semiconductor structure 200 and a second semiconductor structure 300.

[0084] The first semiconductor structure 200 is located on one side of the peripheral circuit structure 100 in the first direction, and the second semiconductor structure 300 is located on the side of the peripheral circuit structure 100 away from the first semiconductor structure 200 in the first direction. The first semiconductor structure 200 includes a first bit line 211, and the second semiconductor structure 300 includes a second bit line 311. The peripheral circuit structure 100 includes a plurality of first transistors 120, and the first bit line 211 and the second bit line 311 are connected through the plurality of first transistors 120.

[0085] The steps in the semiconductor device fabrication method described in the embodiments of this application are described in detail below.

[0086] Step S100

[0087] In step S100, a peripheral circuit structure 100 is formed and coupled to a first semiconductor structure 200 and a second semiconductor structure 300. As an example, step S100 may include: as shown in FIG10, forming an initial peripheral circuit structure 100', the initial peripheral circuit structure 100' including a substrate 110 and a first transistor 120, at least a portion of the first transistor 120 being located in the substrate 110; as shown in FIG11, coupling the first semiconductor structure 200 to the initial peripheral circuit structure 100'; as shown in FIG14, at least thinning the substrate 110 to form the peripheral circuit structure 100; and as shown in FIG15, coupling the second semiconductor structure 300 to the peripheral circuit structure 100.

[0088] As shown in FIG. 7, the substrate 110 includes a first surface 110-1 and a second surface 110-2 disposed opposite to each other in a first direction. The material of the substrate 110 may include, but is not limited to, silicon-on-insulator (SOI). As an example, the initial peripheral circuit structure 100' can be formed by: forming an oxide layer 161 in the substrate 110, for example, as shown in FIG. 7, implanting oxygen ions into the substrate 110 from the first surface 110-1; as shown in FIG. 8, annealing the substrate 110 to react the oxygen ions with the substrate 110 to form the oxide layer 161, the oxide layer 161 being located in the substrate 110, in other words, the oxide layer 161 being located between the first surface 110-1 and the second surface 110-2 in the first direction; as shown in FIG. 10, forming a first transistor 120 in the substrate 110 from the first surface 110-1, the first transistor 120 being located on the side of the oxide layer 161 opposite to the second surface 110-2. For example, as shown in Figure 9, a well region is formed in the substrate 110 from the first surface 110-1 of the substrate 110. The well region is located on the side of the oxide layer 161 opposite to the second surface 110-2 in the first direction. If the first transistor 120 is an N-type transistor, a P-type doped well can be formed in the substrate 110 using ion implantation or diffusion processes. The dopant can be a P-type dopant such as boron (B). Conversely, if the first transistor 120 is a P-type transistor, an N-type doped well can be formed in the substrate 110 using ion implantation or diffusion processes. The dopant can be an N-type dopant such as phosphorus (P), arsenic (As), and antimony (Sb). A first drain 126 and a first source 125 are formed in the well region. If the first transistor 120 is an N-type transistor, the first drain 126 and the first source 125 can be formed in the well region from the first surface 110-1 of the substrate 110 using N-type dopants such as phosphorus (P), arsenic (As), and antimony (Sb). If the first transistor 120 is a P-type transistor, the first drain 126 and the first source 125 can be formed in the well region from the first surface 110-1 of the substrate 110 using P-type dopants such as boron (B). It should be noted that the first source 125 and the first drain 126 of the first transistor 120 can also be formed directly in the substrate 110; in other words, the above steps may not include the step of forming the well region. A gate structure is formed on one side of the substrate 110 from the first surface 110-1 of the substrate 110. The gate structure includes a gate dielectric layer (not shown) and a gate conductive layer 127. For example, a gate dielectric layer is formed on the first surface 110-1 of the substrate 110; a portion of the gate dielectric layer is removed so that the remaining gate dielectric layer is located between the first source 125 and the first drain 126; a gate conductive layer 127 is formed on the side of the gate dielectric layer away from the substrate 110; a portion of the gate conductive layer 127 is removed so that the remaining gate conductive layer 127 is located between the first source 125 and the first drain 126 and covers the gate dielectric layer.The gate dielectric layer is made of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, zirconium oxide, aluminum oxide, magnesium oxide, and tantalum oxide. The gate conductive layer 127 is made of polysilicon, conductive metal, or conductive alloy. For example, the gate conductive layer 127 is made of at least one of tungsten, titanium nitride, copper, and silver. In some embodiments, a trench isolation structure 130 extending along a first direction to the oxide layer 161 can be formed in the substrate 110, and the trench isolation structure 130 surrounds the active region of the first transistor 120. As shown in FIG10, a connection structure 140 is formed that extends through the trench isolation structure 130 along the first direction. The material of the connection structure 140 may include, but is not limited to, conductive materials such as polysilicon, conductive metal, or conductive alloy. A first interconnect layer 150 is formed from the first surface 110-1 of the substrate 110, covering the first transistor 120 and connecting the first transistor 120 and the connection structure 140. The first interconnect layer 150 is coupled to the first semiconductor structure 200.

[0089] As shown in FIG11, after the initial peripheral circuit structure 100' is formed, the first semiconductor structure 200 can be coupled to the first interconnect layer 150 of the initial peripheral circuit structure 100'. As shown in FIG12, the substrate 110 is thinned from the second surface 110-2 of the substrate 110, stopping at the oxide layer 161. A second interconnect layer 160 is formed on the remaining substrate 110 away from the first interconnect layer 150. For example, as shown in FIG13, a contact structure 163 is formed from the side of the oxide layer 161 away from the substrate 110, penetrating the oxide layer 161 along the first direction and connected to the first transistor 120. As shown in FIG14, a sub-interconnect layer 162 is formed covering the oxide layer 161 and connected to the contact structure 163. Thus, the peripheral circuit structure 100 is formed. As shown in FIG15, the second semiconductor structure 300 is coupled to the second interconnect layer 160 of the peripheral circuit structure 100.

[0090] It should be noted that the first semiconductor structure 200 and the initial peripheral circuit structure 100', as well as the second semiconductor structure 300 and the peripheral circuit structure 100, can be coupled by, but are not limited to, bonding. Specifically, the second semiconductor structure 300 has pads formed on the side facing away from the peripheral circuit structure 100, and these pads are connected to the peripheral circuit structure 100 via conductive structures. For example, the pads are connected to the connection structure 140 of the peripheral circuit structure 100 via conductive structures.

[0091] In some embodiments, the fabrication method may further include: forming a first semiconductor structure 200; and forming a second semiconductor structure 300. Taking the first semiconductor structure 200 as an example, the first semiconductor structure 200 can be formed as follows: forming a plurality of first trenches spaced apart in a third direction and extending in a second direction in a wafer; wherein the wafer material can be any suitable semiconductor material, such as a single-element semiconductor material like silicon (Si) or germanium (Ge), or a composite semiconductor material like silicon-on-insulator (SOI) or germanium-on-insulator (GeOI); filling the first trenches with a dielectric material; forming a plurality of second and third trenches alternately distributed in the second direction and extending in a third direction in the wafer to divide the wafer into a plurality of initial semiconductor pillars; forming a second... A gate structure 230 is provided, which may include a gate dielectric layer 231 and a gate layer 232. For example, the gate dielectric layer 231 can be formed by in-situ oxidation of the inner wall of the second trench, or by a thin-film deposition process. The material of the gate dielectric layer 231 may include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, or high-k materials such as hafnium oxide, zirconium oxide, aluminum oxide, and tantalum oxide. The gate layer 232 is formed on the side of the gate dielectric layer 231 facing away from the initial semiconductor pillar. The material of the gate layer 232 may include, but is not limited to, polysilicon, tungsten, aluminum, titanium, copper, cobalt, tungsten nitride, or any combination thereof. An isolation structure is formed in a third trench, for example, by depositing an isolation material in the third trench to form an isolation structure with an air gap. Because air gaps have a low dielectric constant, close to that of a vacuum, their presence reduces the overall dielectric constant of the isolation structure, thereby reducing parasitic capacitance and thus reducing electrical interference between adjacent first semiconductor pillars 220. The first semiconductor pillars 220 are formed based on the initial semiconductor pillars. For example, the two ends of the initial semiconductor pillars are doped to form a source 221 and a drain 222. The source 221 and drain 222 can be both doped with P-type dopant or both doped with N-type dopant. The doping types of the source 221 and drain 222 can be the same or different. For example, the dopant can include, but is not limited to, boron (B), aluminum (Al), gallium (Ga), phosphorus (P), arsenic (As), or antimony (Sb). Thus, the first gate structure 230 and the first semiconductor pillars 220 together constitute the first gate transistor. A first line 211 is formed on one side of the first semiconductor pillar 220 along a first direction, and the first line 211 extends along a second direction; a first capacitor 240 is formed on the side of the first semiconductor pillar 220 opposite to the first line 211.

[0092] The thin film deposition process can be, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination of the above processes.

[0093] It should be noted that, in addition to the single-gate transistor described above, the first gate transistor in the embodiments of this application can also be a dual-gate transistor, a tri-gate transistor, or a gate all-around (GAA) transistor; this application does not limit its application in this regard. Furthermore, the formation processes of the second semiconductor structure 300 and the first semiconductor structure 200 can be the same or different; this application also does not limit its application in this regard.

[0094] In addition, this application also provides a storage system, which includes a controller and the aforementioned semiconductor device. The controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0095] Figure 16 shows a block diagram of a system with semiconductor devices according to one embodiment of this application. System 500 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage located therein. As shown in Figure 16, system 500 may include a host 504 and a memory system 501, the memory system 501 having one or more semiconductor devices 502 and a memory controller 503. Host 504 may be a processor of the electronic device, such as a central processing unit (CPU), or may be a system-on-a-chip (SoC), such as an application processor (AP). Host 504 may be configured to send or receive data to or from semiconductor devices 502.

[0096] Semiconductor device 502 can be any semiconductor device disclosed in this application, such as the semiconductor device shown in FIG2. According to some embodiments, memory controller 503 is coupled to semiconductor device 502 and host 504 and is configured to control semiconductor device 502. Memory controller 503 can manage data stored in semiconductor device 502 and communicate with host 504.

[0097] In some embodiments, the memory controller 503 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 503 is designed to operate in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC), which is used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. The memory controller 503 may be configured to control the operation of the semiconductor device 502, such as read, erase, and program operations. The memory controller 503 may also be configured to manage various functions related to data stored in or to be stored in the semiconductor device 502, including but not limited to bad block management, garbage collection, logic-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 503 is further configured to process error correction codes (ECC) related to data read from or written to the semiconductor device 502. The memory controller 503 may also perform any other appropriate functions, such as formatting the semiconductor device 502. The memory controller 503 may communicate with external devices (e.g., the host 504) according to a specific communication protocol. For example, the memory controller 503 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0098] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. As an example, the steps described in this invention disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0099] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A semiconductor device, comprising: The peripheral circuit structure includes multiple first transistors; A first semiconductor structure includes a first bit line, the first semiconductor structure being located on one side of the peripheral circuit structure in a first direction and coupled to the peripheral circuit structure. And a second semiconductor structure, including a second bit line, the second semiconductor structure being located on the side of the peripheral circuit structure opposite to the first semiconductor structure in the first direction and coupled to the peripheral circuit structure; wherein the first bit line and the second bit line are connected through a plurality of the first transistors.

2. The semiconductor device according to claim 1, wherein, The peripheral circuit structure includes: a bit line selector, comprising a plurality of the first transistors; and a sensing amplifier connected to the first transistors.

3. The semiconductor device according to claim 2, wherein, The plurality of first bit lines include a first target bit line and a first reference bit line, and the plurality of second bit lines include a second target bit line and a second reference bit line. The first target bit line and the first reference bit line, as well as the second target bit line and the second reference bit line, are respectively connected through the plurality of first transistors.

4. The semiconductor device according to claim 3, wherein, The peripheral circuit structure further includes a control circuit; wherein the plurality of first transistors include: a first selection transistor, whose first electrode is connected to the first target bit line and whose second electrode is connected to the sensing amplifier; a second selection transistor, whose first electrode is connected to the first reference bit line and whose second electrode is connected to the sensing amplifier; a third selection transistor, whose first electrode is connected to the second electrode of the first selection transistor and the sensing amplifier respectively, and whose second electrode is connected to the second target bit line; and a fourth selection transistor, whose first electrode is connected to the second electrode of the first reference bit line and the sensing amplifier respectively, and whose second electrode is connected to the second reference bit line; wherein the gates of the first selection transistor, the second selection transistor, the third selection transistor, and the fourth selection transistor are all connected to the control circuit.

5. The semiconductor device according to claim 2, wherein, The first semiconductor structure includes a first memory array, the first memory array including a first bit line; the second semiconductor structure includes a second memory array, the second memory array including a second bit line; the bit line selector and the sense amplifier are located directly below the first memory array and / or directly above the second memory array in the first direction.

6. The semiconductor device according to claim 5, wherein, The peripheral circuit structure further includes a word line driver, and the bit line selector is located between the sense amplifier and the word line driver in a second direction, wherein the first direction intersects the second direction.

7. The semiconductor device according to any one of claims 1 to 6, wherein, The peripheral circuit structure further includes: a semiconductor layer; and a connection structure extending through the semiconductor layer along the first direction, wherein at least a portion of the first transistor is located in the semiconductor layer, one end of the connection structure is connected to the first bit line and the first transistor respectively, and the other end is connected to the second bit line.

8. The semiconductor device according to claim 7, wherein, The peripheral circuit structure further includes a trench isolation structure that penetrates the semiconductor layer along the first direction and surrounds the active region of the first transistor, and the connection structure penetrates the trench isolation structure along the first direction.

9. The semiconductor device according to claim 7, wherein, The peripheral circuit structure further includes: a first interconnect layer located on the side of the semiconductor layer facing the first semiconductor structure in the first direction and connected to the first transistor; and a second interconnect layer located on the side of the semiconductor layer facing the second semiconductor structure in the first direction and connected to the connection structure.

10. The semiconductor device according to claim 9, wherein, The second interconnect layer includes: an oxide layer located on the side of the semiconductor layer facing the second semiconductor structure in the first direction; a sub-interconnect layer located on the side of the oxide layer away from the semiconductor layer in the first direction; and a contact structure located in the oxide layer, one end of the contact structure being connected to the sub-interconnect layer, and the other end penetrating the oxide layer along the first direction and being connected to the connection structure.

11. The semiconductor device according to any one of claims 1 to 6, wherein, The first transistor is a fully depleted transistor.

12. A method for fabricating a semiconductor device, comprising: A peripheral circuit structure is formed and the peripheral circuit structure is coupled to a first semiconductor structure and a second semiconductor structure; wherein the first semiconductor structure is located on one side of the peripheral circuit structure in a first direction, and the second semiconductor structure is located on the side of the peripheral circuit structure opposite to the first semiconductor structure in the first direction, the first semiconductor structure includes a first bit line, the second semiconductor structure includes a second bit line, the peripheral circuit structure includes a plurality of first transistors, and the first bit line and the second bit line are connected through the plurality of first transistors.

13. The method for fabricating a semiconductor device according to claim 12, wherein, Forming a peripheral circuit structure and coupling the peripheral circuit structure to a first semiconductor structure and a second semiconductor structure includes: forming an initial peripheral circuit structure, the initial peripheral circuit structure including a substrate and a first transistor, at least a portion of the first transistor being located in the substrate; coupling the first semiconductor structure to the initial peripheral circuit structure; at least thinning the substrate to form the peripheral circuit structure; and coupling the second semiconductor structure to the peripheral circuit structure.

14. The method for fabricating a semiconductor device according to claim 13, wherein, Forming an initial peripheral circuit structure includes: forming an oxide layer in the substrate, wherein the substrate includes a first surface and a second surface disposed opposite to each other in the first direction, the oxide layer being located between the first surface and the second surface; forming a first transistor in the substrate from the first surface, the first transistor being located on the side of the oxide layer opposite to the second surface; and forming a first interconnect layer from the first surface of the substrate covering and connecting the first transistor, the first interconnect layer being coupled to the first semiconductor structure.

15. The method for fabricating a semiconductor device according to claim 14, wherein, The formation of the initial peripheral circuit structure further includes: forming a trench isolation structure in the substrate extending along the first direction to the oxide layer, the trench isolation structure surrounding the active region of the first transistor; and forming a connection structure extending along the first direction through the trench isolation structure, the connection structure being connected to the first interconnect layer.

16. The method for fabricating a semiconductor device according to claim 14, wherein, Forming an oxide layer in the substrate includes: implanting oxygen ions from a first surface of the substrate into the substrate; and annealing the substrate to cause the oxygen ions to react with the substrate to form the oxide layer.

17. The method for fabricating a semiconductor device according to claim 14, wherein, Thinning at least one side of the substrate away from the first interconnect layer includes: thinning the substrate from a second surface of the substrate and stopping at the oxide layer; forming a second interconnect layer on the remaining side of the substrate away from the first interconnect layer.

18. The method for fabricating a semiconductor device according to claim 17, wherein, Forming a second interconnect layer on the side of the substrate opposite to the first interconnect layer includes: forming a contact structure extending through the oxide layer in the first direction and connected to the first transistor from the side of the oxide layer opposite to the substrate; and forming a sub-interconnect layer covering the oxide layer, the sub-interconnect layer being connected to the contact structure.

19. A storage system, characterized in that, The storage system includes a controller and a semiconductor device according to any one of claims 1 to 11, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

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