Semiconductor device

Abstract

A semiconductor device includes: a first structure including a substrate; and a second structure overlapping the first structure and including a peripheral circuit. The first structure includes: a device isolation structure in the substrate; channel structures spaced apart from each other; an insulating pattern between the channel structures; a bit line extending in a vertical direction and contacting the channel structure; a gate electrode surrounding the channel structure; a data storage structure contacting the channel structure; and a plate electrode connected to the data storage structure. The device isolation structure includes: a first device isolation pattern overlapping a bit line in a vertical direction; a second device isolation pattern overlapping the plate electrode in the vertical direction; and a third device isolation pattern overlapping the insulating pattern in the vertical direction and extending between the first device isolation pattern and the second device isolation pattern, and at least one of the first device isolation pattern, the second device isolation pattern, and the third device isolation pattern penetrating the substrate.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0150280, filed on October 30, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The exemplary embodiments disclosed herein relate to semiconductor devices. Background Technology

[0004] As the demand for high performance, high speed, and / or multifunctionality in semiconductor devices continues to increase, the integration density of semiconductor devices has also increased. In the case of two-dimensional or planar semiconductor devices, the integration density can be primarily determined by the area occupied by the array region of a unit memory cell. Therefore, the integration density may be limited by the capability of fine patterning processes. Consequently, three-dimensional semiconductor devices incorporating three-dimensionally arranged memory cells have been proposed. Summary of the Invention

[0005] Some example embodiments of this disclosure provide semiconductor devices with reduced dimensions by reducing the thickness of the substrate through a polishing process.

[0006] According to some example embodiments of this disclosure, a semiconductor device includes: a first structure including a substrate; and a second structure overlapping the first structure in a vertical direction and including peripheral circuitry. The first structure includes: a device isolation structure located in the substrate; a channel structure extending on the substrate in a first horizontal direction, the channel structures being spaced apart from each other in a second horizontal direction, the second horizontal direction intersecting the first horizontal direction; an insulating pattern located between the channel structures; bit lines extending vertically on the substrate and contacting first ends of the channel structures; a gate electrode extending in a second horizontal direction and surrounding the channel structure; a data storage structure contacting a second end of the channel structure and being spaced apart from each other in a second horizontal direction, the second end opposite to the first end of the channel structure; and a plate electrode connected to the data storage structure and extending in both the second horizontal and vertical directions. The device isolation structure includes: a first device isolation pattern that overlaps with a bit line in a vertical direction; a second device isolation pattern that overlaps with a plate electrode in a vertical direction; and a third device isolation pattern that overlaps with an insulating pattern in a vertical direction, is spaced apart from each other in a second horizontal direction, and extends between the first device isolation pattern and the second device isolation pattern in a first horizontal direction, and at least one of the first device isolation pattern, the second device isolation pattern and the third device isolation pattern penetrates the substrate.

[0007] According to some example embodiments of this disclosure, a semiconductor device includes: a substrate having a first region and a second region; a device isolation structure located in the substrate; a channel structure extending in a first region of the substrate in a first horizontal direction, spaced apart from each other in a second horizontal direction, the second horizontal direction intersecting the first horizontal direction, and also spaced apart in a vertical direction, the vertical direction intersecting the first and second horizontal directions; bit lines extending in a vertical direction in the first region of the substrate, spaced apart from each other in the second horizontal direction, and respectively contacting a first end of the channel structure; gate electrodes surrounding the channel structure, spaced apart from each other in the vertical direction, extending in the second horizontal direction, and including gate pads arranged in a stepped shape in the second region; a data storage structure contacting a second end of the channel structure, the second end opposite to the first end of the channel structure; and a plate electrode connected to the data storage structure, the plate electrode extending in both the second horizontal and vertical directions. The device isolation structure includes: a first device isolation pattern overlapping the bit lines in the vertical direction; and a second device isolation pattern overlapping the plate electrode in the vertical direction. At least one of the lower surfaces of the first device isolation pattern and the second device isolation pattern is coplanar with the lower surface of the substrate.

[0008] According to some example embodiments of this disclosure, a semiconductor device includes: a first structure including a substrate; and a second structure overlapping the first structure in a vertical direction, the second structure including a peripheral circuit region. The first structure includes: a device isolation structure located in the substrate; channel structures extending in a first horizontal direction and spaced apart from each other in a second horizontal direction, the second horizontal direction intersecting the first horizontal direction, each of the channel structures including a channel region and a first source / drain region and a second source / drain region isolated from each other by the channel regions; an insulating pattern located between the channel structures; bit lines extending in a vertical direction and contacting a first end of the channel structure; a gate dielectric layer extending in the second horizontal direction and surrounding the channel region of the channel structure; a gate electrode extending in the second horizontal direction and surrounding the gate dielectric layer; a data storage structure contacting a second end of the channel structure, the second end opposite to the first end of the channel structure; and a plate electrode connected to the data storage structure, the plate electrode extending in the second horizontal direction and also extending in the vertical direction. The device isolation structure includes: a first device isolation pattern having an upper surface in contact with the lower surface of a bit line and extending in a second horizontal direction; a second device isolation pattern having an upper surface in contact with the lower surface of a plate electrode and extending in a second horizontal direction; and a third device isolation pattern overlapping an insulating pattern in a vertical direction, extending between the first and second device isolation patterns in a first horizontal direction and spaced apart from each other in a second horizontal direction, wherein at least one of the first, second, and third device isolation patterns penetrates a substrate.

[0009] According to some example embodiments of this disclosure, a method of manufacturing a semiconductor device includes: providing a semiconductor structure including a substrate and a memory cell array; initiating a polishing process on a back surface of the semiconductor device, the back surface being a surface opposite to the memory cell array; and stopping the polishing process on the back surface when an etch stop layer is exposed from the substrate. The etch stop layer includes at least one of a first device isolation pattern, a second device isolation pattern, and a third device isolation pattern. The semiconductor structure further includes: a first region and a second region; a device isolation structure located in a substrate; a channel structure extending in a first horizontal direction on the first region of the substrate, spaced apart from each other in a second horizontal direction, and also spaced apart in a vertical direction, the second horizontal direction intersecting the first horizontal direction, and the vertical direction intersecting the first and second horizontal directions; bit lines extending in a vertical direction on the first region of the substrate, spaced apart from each other in the second horizontal direction, and respectively contacting a first end of the channel structure; gate electrodes surrounding the channel structure, spaced apart from each other in the vertical direction, extending in the second horizontal direction, and including gate pads arranged in a stepped shape on the second region; a data storage structure contacting a second end of the channel structure, the second end being opposite to the first end of the channel structure; and a plate electrode connected to the data storage structure, the plate electrode extending in both the second horizontal and vertical directions. The device isolation structure includes: a first device isolation pattern that overlaps with a bit line in a vertical direction; and a second device isolation pattern that overlaps with a plate electrode in a vertical direction, wherein at least one of the lower surfaces of the first device isolation pattern and the second device isolation pattern is coplanar with the lower surface of the substrate.

[0010] According to some example embodiments of this disclosure, the etch stop layer includes a first device isolation pattern, and a second and a third device isolation pattern remain embedded after the stop polishing process.

[0011] According to some example embodiments of this disclosure, the etch stop layer includes a second device isolation pattern, and the first and third device isolation patterns remain embedded after the stop polishing process.

[0012] According to some example embodiments of this disclosure, the etch stop layer includes a third device isolation pattern, and the first and second device isolation patterns remain embedded after the stop polishing process. Attached Figure Description

[0013] The above and other aspects, features and advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 This is a perspective view illustrating a semiconductor device according to some exemplary embodiments of the present disclosure;

[0015] Figure 2 This is a circuit diagram illustrating a memory cell in a memory cell array region according to some example embodiments of the present disclosure;

[0016] Figure 3 This is a plan view illustrating a semiconductor device according to some example embodiments of the present disclosure;

[0017] Figure 4 This is a perspective view illustrating a semiconductor device according to some exemplary embodiments of the present disclosure;

[0018] Figure 5 It is shown Figure 3 A vertical cross-sectional view of the semiconductor device shown, taken along line I-I';

[0019] Figure 6 It is shown Figure 3 A vertical cross-sectional view of the semiconductor device shown, taken along line II-II';

[0020] Figure 7 It is shown Figure 3 A vertical cross-sectional view of the semiconductor device shown, taken along line III-III';

[0021] Figure 8A These are examples illustrating some embodiments according to this disclosure. Figure 5 An enlarged view of the semiconductor device shown;

[0022] Figure 8B These are examples illustrating some embodiments according to this disclosure. Figure 6 An enlarged view of the semiconductor device shown;

[0023] Figure 9A These are examples illustrating some embodiments according to this disclosure. Figure 5 An enlarged view of the semiconductor device shown;

[0024] Figure 9B These are examples illustrating some embodiments according to this disclosure. Figure 6 An enlarged view of the semiconductor device shown;

[0025] Figure 10 These are examples illustrating some embodiments according to this disclosure. Figure 6 An enlarged view of the semiconductor device shown; and

[0026] Figure 11 , Figure 12 and Figure 13 These are examples illustrating some embodiments according to this disclosure. Figure 5 An enlarged view of the semiconductor device shown. Detailed Implementation

[0027] In the following description, some exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0028] Figure 1 This is a perspective view illustrating a semiconductor device according to some example embodiments.

[0029] Reference Figure 1 The semiconductor device 100 may include a first structure ST1 and a second structure ST2 that is vertically overlapped with the first structure ST1. The second structure ST2 may be disposed on the first structure ST1.

[0030] The first structure ST1 may be a first chip structure including a memory cell MC, and the second structure ST2 may be a second chip structure including peripheral circuitry capable of operating the memory cell MC. The first structure ST1 and the second structure ST2 may be formed by bonding via a bonding process such as a wafer bonding process. Therefore, the first structure ST1 may contact and be bonded to the second structure ST2.

[0031] Semiconductor device 100 may include multiple memory banks BA and peripheral circuit regions PERI. The peripheral circuit regions PERI may include a first peripheral circuit region PERI1 in a first structure ST1 and a second peripheral circuit region PERI2 in a second structure ST2. The peripheral circuit region PERI may be a peripheral circuit region where peripheral circuitry for data or command input / output or power / ground input is disposed.

[0032] Each of the multiple memory banks BA may include a first memory bank region BA1 in the first structure ST1 and a second memory bank region BA2 in the second structure ST2.

[0033] The first storage region BA1 in the first structure ST1 may include a memory cell array region. The memory cell array region may include memory cells MC. The memory cell array region may be arranged in a first direction (X direction) and a second direction (Y direction). The first direction (X direction) and the second direction (Y direction) may be perpendicular to each other. The first direction (X direction) and the second direction (Y direction) may be referred to as the horizontal direction, and the third direction (Z direction) may be referred to as the vertical direction.

[0034] The second memory bank region BA2 in the second structure ST2 may include a core circuit region. The core circuit region may be arranged in a first direction (X direction) and a second direction (Y direction). The core circuit region may include a sense amplifier and a sub-word line driver.

[0035] The first peripheral circuit region PERI1 and the second peripheral circuit region PERI2 may include control circuitry that can control the sense amplifier and the sub-word line driver.

[0036] Figure 2 This is a circuit diagram illustrating memory cells in a memory cell array region according to some example embodiments.

[0037] Reference Figure 2 The memory cell array region may include memory cells MC arranged in a first direction (X direction) and a second direction (Y direction), word lines WL connected to the memory cells MC and extending in the second direction (Y direction), and bit lines BL connected to the memory cells MC and extending in the vertical direction (Z direction). Each of the memory cells MC may include a cell transistor CTR and a data storage structure DS that can function as data storage.

[0038] A memory cell MC can be a structure in which two or more memory cells are stacked in the vertical direction (Z direction). In some example embodiments, two memory cells MC can be arranged as a pair in the horizontal direction.

[0039] The gate of the unit transistor CTR can be connected to the word line WL, the first source / drain region of the unit transistor CTR can be connected to the bit line BL, and the second source / drain region of the unit transistor CTR can be connected to the data storage structure DS.

[0040] The unit transistor (CTR) and data storage structure (DS) can be arranged horizontally, extending in a first direction (X direction). Adjacent data storage structures (DS) can share a plate electrode (PP). The plate electrode (PP) can extend in a vertical direction (Z direction) and can be electrically connected to the data storage structure (DS). The plate electrode (PP) can be vertically oriented. The plate electrode (PP) can be referred to as a vertical plate electrode. Two memory cells (MC) arranged as a pair in the horizontal direction can share a single plate electrode (PP). Each of the data storage structure (DS) and the plate electrode (PP) can serve as a unit capacitor for each of the memory cells (MC). The data storage structure (DS) and the plate electrode (PP) can be referred to as a capacitor structure.

[0041] Memory cells MC can be disposed between bit lines BL and plate electrodes PP. Memory cells MC can be arranged horizontally in a first direction (X direction). Each memory cell MC can be connected to one of the bit lines BL, one of the word lines WL, and one of the plate electrodes PP.

[0042] Word lines WL may be spaced apart from each other in a first direction (X direction) and may extend in a second direction (Y direction). Word lines WL may be arranged in a vertical direction (Z direction). In some example embodiments, word lines WL may be oriented horizontally relative to the plane of the first structure ST1. Word lines WL may be referred to as horizontal word lines. A plurality of memory cells MC arranged horizontally in the second direction (Y direction) may be connected to a single word line WL.

[0043] Bit lines BL can be spaced apart from each other in the second direction (Y direction) and can extend in the third direction (Z direction). Bit lines BL can be vertically oriented from the plane of the second structure ST2. Bit lines BL can be referred to as vertical bit lines. Multiple memory cells MC arranged vertically in the third direction (Z direction) can be connected to a bit line BL.

[0044] Figure 3 This is a plan view illustrating a semiconductor device according to some example embodiments. Figure 4 This is a perspective view illustrating a semiconductor device according to some example embodiments.

[0045] Reference Figure 3 and Figure 4 The semiconductor device 100 may include a substrate 103 having a memory cell array region R1 and a stepped region R2. In the memory cell array region R1 of the substrate 103, a cell transistor CTR may be disposed between a vertical conductive pattern 160 and a capacitor structure 150. In the stepped region R2 of the substrate 103, a gate electrode 140 extending from the memory cell array region R1 for different lengths may be disposed. The memory cell array region R1 and the stepped region R2 may be arranged side-by-side in a second direction (Y direction). In some example embodiments, the memory cell array region R1 may be referred to as a first region, and the stepped region R2 may be referred to as a second region.

[0046] Substrate 103 may include semiconductor materials, such as group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors. Substrate 103 may be configured as a bulk wafer or an epitaxial layer. For example, substrate 201 may be bulk silicon or silicon-on-insulator (SOI). However, the example embodiments are not limited thereto.

[0047] The single-cell transistor (CTR) may include a channel structure 110, a gate electrode 140, and a gate dielectric layer 142 disposed between the channel structure 110 and the gate electrode 140. The single-cell transistor (CTR) may include a gate all-around field-effect transistor (GAAFET).

[0048] The channel structure 110 may include multiple channel structures that extend in a first direction (X direction) and are spaced apart from each other in a second direction (Y direction) and a third direction (Z direction). Four channel structures 110 may be arranged in the same plane (XY plane) in the second direction (Y direction), but the example embodiments are not limited thereto, and may include three or fewer channel structures or five or more channel structures.

[0049] The channel structure 110 may include a semiconductor material, such as silicon, germanium, or silicon-germanium. However, the example embodiments are not limited thereto.

[0050] The vertical conductive pattern 160 may include a plurality of vertical conductive patterns extending in a vertical direction (Z direction) and spaced apart from each other in a second direction (Y direction). The vertical conductive pattern 160 may contact a first end of the channel structure 110. The vertical conductive pattern 160 may contact the first end of the channel structure 110 arranged in the vertical direction (Z direction) respectively.

[0051] The vertical conductive pattern 160 may include doped polycrystalline silicon, metal, conductive metal nitride, metal semiconductor compound, conductive metal oxide, conductive graphene, carbon nanotube, or combinations thereof. For example, at least one of the vertical conductive patterns 160 may be made of doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x RuO x It is formed from graphene, carbon nanotubes, or combinations thereof. However, the example embodiments are not limited thereto. Each of the vertical conductive patterns 160 can be coupled with... Figure 2 The bit line BL in the middle corresponds to this.

[0052] The capacitor structure 150 may include a data storage structure DS and a plate electrode PP connected to the data storage structure DS.

[0053] The data storage structure DS can contact the second end of the channel structure 110 opposite to the first end.

[0054] Gate electrodes 140 may surround a channel structure 110 disposed between a vertical conductive pattern 160 and a data storage structure DS. Each of the gate electrodes 140 may be configured as a gate-all-around structure surrounding the channel structure 110. The gate electrodes 140 may extend in a second direction (Y direction) and may be spaced apart from each other in a vertical direction (Z direction). Each of the gate electrodes 140 may surround the channel structure 110 spaced apart from each other in the second direction (Y direction) on the same plane (XY plane). Each of the gate electrodes 140 may be connected to... Figure 2 The character line WL corresponds to this.

[0055] Gate electrodes 140 may be stacked on the memory cell array region R1 and vertically spaced apart from each other, and may extend from the memory cell array region R1 to the stepped region R2 at different lengths, forming a stepped structure with a stepped shape. The gate electrodes 140 may form a stepped structure in the second direction (Y direction) between gate electrodes 140 spaced apart in the third direction (Z direction). The lower gate electrode 140 extends longer than the upper gate electrode 140, exposing upwards from the interlayer insulating layer 145 through the stepped structure, and the lower gate electrode 140 may have areas that respectively contact the contact plug CCP. In some example embodiments, the stepped structure may be formed by a second, fourth, and sixth gate electrode disposed below the uppermost gate electrode among the gate electrodes 140, a third gate electrode disposed below the uppermost gate electrode that may overlap with the second gate electrode, and a fifth gate electrode disposed below the uppermost gate electrode that may overlap with the fourth gate electrode, thereby forming the stepped structure. However, the example embodiments are not limited thereto, and each of the gate electrodes 140 disposed below the uppermost gate electrode can form a stepped structure. For example, the third gate electrode disposed below the uppermost gate electrode can extend longer than the second gate electrode disposed below the uppermost gate electrode, thereby forming a stepped structure.

[0056] Gate pads can be formed on the upper surfaces of the second, fourth, and sixth gate electrodes located below the uppermost gate electrode in the gate electrode 140. Contact plugs (CCPs) can be disposed on the gate pads.

[0057] The semiconductor device 100 may further include an interlayer insulating layer 145 disposed between gate electrodes 140 stacked and spaced apart from each other in the vertical direction (Z direction). The interlayer insulating layer 145 may spatially isolate gate electrodes 140 that are adjacent to each other in the vertical direction (Z direction) and may electrically insulate the gate electrodes. The interlayer insulating layer 145 may include at least one insulating material such as silicon nitride, silicon oxynitride, and silicon oxycarbide. However, the exemplary embodiments are not limited thereto.

[0058] The semiconductor device 100 may further include a gate dielectric layer 142 disposed between the channel structure 110 and the gate electrode 140. The gate dielectric layer 142 may cover the upper surface, lower surface, and side surface of each of the channel structures 110. The gate dielectric layer 142 may include at least one of silicon oxide, silicon nitride, a low-k dielectric material, and a high-k dielectric material. A high-k dielectric material may refer to a dielectric material having a dielectric constant higher than that of silicon oxide, and a low-k dielectric material may refer to a dielectric material having a dielectric constant lower than that of silicon oxide. A high-k dielectric material may be, for example, a metal oxide or a metal oxide-nitride. A high-k dielectric material may be, for example, aluminum oxide (Al₂O₃), tantalum oxide (Ta₂O₃), titanium oxide (TiO₂), yttrium oxide (Y₂O₃), zirconium oxide (ZrO₂), or zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2), hafnium silicon oxide (HfSi) x O y ), Lanthanum oxide (La₂O₃), Lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y ), Hafnium aluminum oxide (HfAl) x O y At least one of praseodymium oxide (Pr₂O₃) and praseodymium oxide (Pr₂O₃). However, the example embodiments are not limited thereto. The gate dielectric layer 142 may be formed as a single layer or multiple layers of the above-described materials.

[0059] The substrate 103 may include a first device isolation region ESA and a second device isolation region ESb extending across the memory cell array region R1 and the stepped region R2 in a second direction (Y direction), and a third device isolation region ESC extending in the memory cell array region R1 between the first device isolation region ESA and the second device isolation region ESb in a first direction (X direction). The first device isolation region ESA and the second device isolation region ESb may be spaced apart from each other in the first direction (X direction).

[0060] The first device isolation region ESa can overlap with the vertical conductive pattern 160 and can extend in the second direction (Y direction). The first device isolation region ESa can define the area in which the first device isolation pattern 104 is disposed.

[0061] The second device isolation region ESb can overlap with the plate electrode PP and can extend in the second direction (Y direction). The second device isolation region ESb can define the area in which the second device isolation pattern 105 is disposed.

[0062] The third device isolation region ESC can be located between the first device isolation region Esa and the second device isolation region ESb, and can extend in the first direction (X direction). The third device isolation region ESC can define the area in which the third device isolation pattern 106 is provided.

[0063] The semiconductor device 100 may further include a device isolation structure ISO having at least a portion disposed in the substrate 103. In some example embodiments, the device isolation structure ISO may include: a first device isolation pattern 104 disposed in a first device isolation region ESa of the substrate 103 and overlapping with a vertical conductive pattern 160 in the vertical direction (Z direction); a second device isolation pattern 105 disposed in a second device isolation region ESb of the substrate 103 and overlapping with a plate electrode PP and a data storage structure DS in the vertical direction (Z direction); and a third device isolation pattern 106 disposed in each of the third device isolation regions ESc of the substrate 103 and spaced apart from each other in the second direction (Y direction) between the first device isolation pattern 104 and the second device isolation pattern 105.

[0064] The first device isolation pattern 104 may be disposed in the first device isolation region ESa extending from the substrate 103 in the second direction (Y direction) and may overlap with the vertical conductive pattern 160 in the vertical direction (Z direction).

[0065] The second device isolation pattern 105 may be disposed in the second device isolation region ESb extending from the substrate 103 in the second direction (Y direction) and may overlap with the plate electrode PP in the vertical direction (Z direction). The second device isolation pattern 105 may be spaced apart from the first device isolation pattern 104 in the first direction (X direction), and the third device isolation pattern 106 may be interposed between the second device isolation pattern 105 and the first device isolation pattern 104.

[0066] Each of the first device isolation pattern 104 and the second device isolation pattern 105 can extend in the second direction (Y direction) and can be set from the memory cell array region R1 to the step region R2.

[0067] The third device isolation pattern 106 can be disposed in the third device isolation region Esc extending in the first direction (X direction) between the first device isolation region ESa and the second device isolation region ESb on the substrate 103, and can be disposed with the insulating pattern disposed between the channel structures 110 (e.g., Figure 8AThe first gap-filling insulating layer 126 and the second gap-filling insulating layer 136 overlap. The third device isolation pattern 106 may not overlap with the channel structure 110 and the data storage structure DS in the vertical direction (Z direction). In some example embodiments, the third device isolation pattern 106 may be disposed only on the memory cell array region R1 and may not be disposed on the stepped region R2. However, the example embodiments are not limited to this, and in some example embodiments, the third device isolation pattern 106 may be disposed between the first device isolation pattern 104 and the second device isolation pattern 105 disposed on the stepped region R2.

[0068] At least one of the first device isolation pattern 104, the second device isolation pattern 105, and the third device isolation pattern 106 can penetrate the substrate 103. In some example embodiments, the first device isolation pattern 104, the second device isolation pattern 105, and the third device isolation pattern 106 can penetrate the substrate 103. That is, the lower surfaces of the first device isolation pattern 104, the second device isolation pattern 105, and the third device isolation pattern 106 can be exposed from the lower surface of the substrate 103, such that the lower surfaces of the first device isolation pattern 104, the second device isolation pattern 105, and the third device isolation pattern 106 can be located between the lower surfaces of the substrate 103 and do not vertically overlap with the lower surface of the substrate 103.

[0069] Memory cells (e.g., Figure 2 The memory cell (MC) may include a first device isolation pattern 104 disposed on the lower surface of the vertical conductive pattern 160, a second device isolation pattern 105 disposed on the lower surface of the plate electrode PP, and an insulating pattern (e.g.,) disposed between channel structures 110 spaced apart from each other in the second direction (Y direction). Figure 8A A third device isolation pattern 106 is disposed on the lower part of the first gap-filling insulating layer 126 and the second gap-filling insulating layer 136. In some example embodiments, when the memory cell shares a plate electrode PP with an adjacent memory cell, the memory cell may also share the second device isolation pattern 105 disposed on the lower part of the plate electrode PP.

[0070] According to some example embodiments, the semiconductor device 100 may use at least one of a first device isolation pattern 104, a second device isolation pattern 105, and a third device isolation pattern 106 disposed in a device isolation structure ISO disposed in a substrate 103 as an etch stop layer in a process of polishing the substrate 103, and at least one of the first device isolation pattern 104, the second device isolation pattern 105, and the third device isolation pattern 106 may have a lower surface that is coplanar (and / or substantially coplanar) with the lower surface of the substrate 103. Therefore, using at least one of the first device isolation pattern 104, the second device isolation pattern 105, and the third device isolation pattern 106 of the device isolation structure ISO as an etch stop layer can improve process efficiency and reduce the thickness of the substrate 103, thereby also reducing the size of the semiconductor device.

[0071] Figure 5 It is shown Figure 3 The diagram shows a vertical cross-sectional view of the semiconductor device taken along line I-I'. Figure 6 It is shown Figure 3 The diagram shows a vertical cross-sectional view of the semiconductor device taken along line II-II'. Figure 7 It is shown Figure 3 The diagram shows a vertical cross-sectional view of the semiconductor device taken along line III-III'. Figure 8A This illustrates some example embodiments. Figure 5 An enlarged view of the semiconductor device shown. Figure 8B This illustrates some example embodiments. Figure 6 An enlarged view of the semiconductor device shown. Figure 8A Can be with Figure 5 Region A corresponds to, and Figure 8B Can be with Figure 6 Region B corresponds to.

[0072] Reference Figures 5 to 8B The semiconductor device 100 may include a first structure ST1 and a second structure ST2 that vertically overlaps the first structure ST1. The first structure ST1 may be... Figure 1 The example of the first structure ST1 described in the text, and the second structure ST2 can be... Figure 1 An example of the second structure ST2 described in [the document].

[0073] The first structure ST1 may be a memory region including memory cells arranged in three dimensions, and the second structure ST2 may be a peripheral region including peripheral circuitry.

[0074] The first structure ST1 may include a substrate 103, a unit transistor CTR disposed on the substrate 103, a vertical conductive pattern 160, and a capacitor structure 150.

[0075] The capacitor structures 150 of the first structure ST1 can be spaced apart from each other in the first direction (X direction). One of the vertical conductive patterns 160 can be disposed between a pair of adjacent capacitor structures 150.

[0076] The first structure ST1 may include channel structures 110 stacked and spaced apart from each other in the vertical direction (Z direction). Each of the channel structures 110 may include a first source / drain region SD1 adjacent to the vertical conductive pattern 160, a second source / drain region SD2 adjacent to the capacitor structure 150, and a channel region CH disposed between the first source / drain region SD1 and the second source / drain region SD2.

[0077] The first structure ST1 may include gate electrodes 140 stacked and spaced apart from each other in a vertical direction (Z direction). The gate electrodes 140 may overlap with the channel region CH of the channel structure 110 in the vertical direction (Z direction). Each of the gate electrodes 140 may surround the channel region CH and extend in a second direction (Y direction).

[0078] The first structure ST1 may further include a gate dielectric layer 142, a gate capping layer 144, and an insulating layer 146. The gate dielectric layer 142 may be disposed between the gate electrode 140 and the channel structure 110. The gate dielectric layer 142 may be configured as a gate-encircling structure surrounding the channel structure 110, and may cover the upper surface, lower surface, and side surface of the gate electrode 140. The gate capping layer 144 may be disposed between the gate electrode 140 and the vertical conductive pattern 160. A portion of the gate dielectric layer 142 may be disposed between the gate capping layer 144 and the channel structure 110. The insulating layer 146 may be disposed between the gate capping layer 144 and the first source / drain region SD1 of the channel structure 110.

[0079] The gate capping layer 144 may include at least one insulating material selected from silicon nitride, silicon oxynitride, and silicon oxycarbide. However, the example embodiments are not limited thereto.

[0080] The first structure ST1 may further include a first buffer layer 120, a first pad 122, and a first gap-filling insulating layer 126 disposed between the channel structures 110. The first buffer layer 120, the first pad 122, and the first gap-filling insulating layer 126 may contact the gate dielectric layer 142. For example, the first buffer layer 120 may extend horizontally on the upper and lower surfaces of the channel structures 110 and may extend vertically (Z-direction) between the channel structures 110. The first pad 122 may be conformally disposed on the first buffer layer 120. The first gap-filling insulating layer 126 may fill the space between adjacent gate dielectric layers 142. The first gap-filling insulating layer 126 may contact the gate capping layer 144 and the vertical conductive pattern 160. The first buffer layer 120 and the first gap-filling insulating layer 126 may include silicon oxide, and the first pad 122 may include silicon nitride.

[0081] The first structure ST1 may further include a second buffer layer 130, a second pad 132, and a second gap-filling insulating layer 136 disposed between the channel structures 110. In some example embodiments, the second buffer layer 130, the second pad 132, and the second gap-filling insulating layer 136 may contact the first electrode 155 of the capacitor structure 150. For example, the second buffer layer 130 may extend horizontally on the upper and lower surfaces of the channel structures 110 and may extend vertically (in the Z direction) between the channel structures 110. The second pad 132 may be conformally disposed on the second buffer layer 130, and the second gap-filling insulating layer 136 may be disposed on the second pad 132 and may fill the space between adjacent channel structures 110 and the first electrode 155. The first gap-filling insulating layer 136 and the second gap-filling insulating layer 136 may contact the first electrode 155 of the capacitor structure 150. Figure 4 The interlayer insulating layer 145 corresponds to this. The second buffer layer 130 and the second gap-filling insulating layer 136 may include silicon oxide, and the second pad 132 may include silicon nitride.

[0082] A vertical conductive pattern 160 may extend in a vertical direction (Z direction) on the substrate 103. The vertical conductive patterns 160 may be spaced apart from each other in a first direction (X direction) and a second direction (Y direction). A channel structure 110 stacked in the vertical direction (Z direction) may be electrically connected to a vertical conductive pattern 160. For example, the vertical conductive pattern 160 may be electrically connected to a first source / drain region SD1 of the channel structure 110.

[0083] The first structure ST1 may include a capacitor structure 150. Each of the capacitor structures 150 may include a first electrode 155, a second electrode 157, and a dielectric layer 153 disposed between the first electrode 155 and the second electrode 157.

[0084] The first electrode 155 may be electrically connected to the second source / drain region SD2 of the channel structure 110. Each of the first electrodes 155 may have a cylindrical shape oriented in the horizontal direction.

[0085] The second electrode 157 may include a 2-1 electrode material layer 157a in contact with the dielectric layer 153 and a 2-2 electrode material layer 157b in contact with the 2-1 electrode material layer 157a.

[0086] A dielectric layer 153 may be disposed between the first electrode 155 and the 2-1 electrode material layer 157a, and may extend in the vertical direction (Z direction) from the inner wall of the first electrode 155 to conformally cover the first electrode 155. The 2-1 electrode material layer 157a may be disposed on the dielectric layer 153 on the inner wall of the first electrode 155. The 2-2 electrode material layer 157b may be disposed on the 2-1 electrode material layer 157a, and may be disposed in a manner that extends in the vertical direction (Z direction) between the first electrodes 155 that are spaced apart from each other in the horizontal direction.

[0087] The first electrode 155 and the second electrode 157 may comprise a metal, a metal oxide, a metal nitride, a metal carbide, a metal silicide, or a combination thereof. The dielectric layer 153 may be referred to as a capacitor dielectric layer and may comprise silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may have a higher dielectric constant than silicon oxide.

[0088] The first electrode 155, the dielectric layer 153, and the 2-1 electrode material layer 157a can be formed Figure 3 and Figure 4 The data storage structure DS in the data storage structure. Electrode material layers 157a (2-1) and 157b (2-2) can represent... Figure 3 and Figure 4 The plate electrode PP in the middle, and the 2-2 electrode material layer 157b can have the same as Figure 3 and Figure 4 The plate electrodes PP in the examples have essentially the same shape, but their examples are not limited to this.

[0089] The first structure ST1 may also include a device isolation structure disposed in the substrate 103 (e.g., Figure 4 Device isolation structure (ISO).

[0090] The device isolation structure may include: a first device isolation pattern 104 that contacts the lower surface of each of the vertical conductive patterns 160; a second device isolation pattern 105 that contacts the lower surface of the capacitor structure 150; and a third device isolation pattern 106 disposed in the lower portion of the insulating pattern between the first device isolation pattern 104 and the second device isolation pattern 105, and disposed in the data storage structure (e.g., Figure 3 The data storage structure DS) and the channel structure 110 are between each other.

[0091] The first device isolation pattern 104 may overlap with the vertical conductive pattern 160 and may have an upper surface that contacts the lower surface of the vertical conductive pattern 160. In some example embodiments, the first device isolation pattern 104 may include a first portion 104a and a second portion 104b, the second portion 104b extending from the first portion 104a and contacting the lower surface of the vertical conductive pattern 160. In some example embodiments, the first portion 104a may have a first width W1 in a first direction (X direction), and each of the second portions 104b may extend from the first portion 104a and may have a width greater than the first width W1 in the first direction (X direction), and this width may increase upwards. The first portion 104a may overlap with the vertical conductive pattern 160. Figure 3 The first device isolation regions ESa overlap and can extend in the second direction (Y direction), and each of the second portions 104b can contact the lower surface of each of the vertical conductive patterns 160. The second portions 104b can be spaced apart from each other in the second direction (Y direction) on the first portion 104a.

[0092] The second device isolation pattern 105 may have an upper surface that overlaps with and contacts the lower surface of the capacitor structure 150. In some example embodiments, the second device isolation pattern 105 may include a third portion 105a and a fourth portion 105b, the fourth portion 105b extending from the third portion 105a and contacting the lower surface of the capacitor structure 150. The third portion 105a may have a first width W1 in a first direction (X direction). The fourth portion 105b may extend from the third portion 105a and may have a width greater than the first width W1 in the first direction (X direction). The third portion 105a may extend in a second direction (Y direction) and contact the lower surface of the capacitor structure 150. Figure 3 The second device isolation region ESb overlaps with the 2-2 electrode material layer 157b in the vertical direction (Z direction) (or, for example, Figure 3 and Figure 4The plate electrodes PP in the third portion 105a overlap. The fourth portion 105b may extend in the second direction (Y direction) on the third portion 105a and may contact the lower surface of the capacitor structure 150. In some example embodiments, the upper surface of each of the fourth portions 105b may contact the first electrode 155. The fourth portions 105b may be spaced apart from each other in the second direction (Y direction) on the third portion 105a.

[0093] The upper surfaces of the first device isolation pattern 104 and the second device isolation pattern 105 may be disposed at a level higher than the level of the upper surface of the substrate 103. The upper surfaces of the first device isolation pattern 104 and the second device isolation pattern 105 may be disposed at a level lower than the level of the channel structure 110 in the lowest portion. In some example embodiments, the side surface of the second portion 104b of the first device isolation pattern 104 exposed on the upper surface of the substrate 103 may contact the gate cap layer 144, the insulating layer 146, and the first gap-filling insulating layer 126 in the lowest portion. The side surface of the fourth portion 105b of the second device isolation pattern 105 exposed on the upper surface of the substrate 103 may contact the second buffer layer 130, the second pad 132, and the second gap-filling insulating layer 136.

[0094] In some example embodiments, each of the first portion 104a of the first device isolation pattern 104 and the third portion 105a of the second device isolation pattern 105 may have the same width as the first width W1 in the first direction (X direction). However, the example embodiments are not limited thereto, and in some example embodiments, the width of the first portion 104a of the first device isolation pattern 104 in the first direction (X direction) may be different from the width of the third portion 105a of the second device isolation pattern 105 in the first direction (X direction). In some example embodiments, the height of the first portion 104a of the first device isolation pattern 104 in the vertical direction may be the same as the height of the third portion 105a of the second device isolation pattern 105 in the vertical direction. However, the example embodiments are not limited thereto, and the height of the first portion 104a of the first device isolation pattern 104 in the vertical direction may be different from the height of the third portion 105a of the second device isolation pattern 105 in the vertical direction.

[0095] The third device isolation pattern 106 may be disposed between the first device isolation pattern 104 and the second device isolation pattern 105 disposed on the memory cell array region R1, and may extend in a first direction (X direction) and may be spaced apart from each other in a second direction (Y direction). The third device isolation pattern 106 may overlap with the second gap-filling insulating layer 136 of the filling channel structure 110. The third device isolation pattern 106 may not overlap with the channel structure 110 and the data storage structure (e.g., Figure 3 The data storage structure DS overlaps with the data storage structure DS. Third device isolation patterns 106 spaced apart from each other in the second direction (Y direction) may overlap with gate electrodes 140 spaced apart from each other in the vertical direction (Z direction) between capacitor structure 150 and vertical conductive pattern 160. In some example embodiments, each of the third device isolation patterns 106 may have a width that decreases toward the lower surface of substrate 103.

[0096] The upper surface of the third device isolation pattern 106 may be coplanar (and / or substantially coplanar) with the upper surface of the substrate 103. The lower surface of each of the third device isolation patterns 106 may have a second width W2 in a second direction (Y direction). The second width W2 of the third device isolation pattern 106 may be smaller than the first width W1 of the lower surface of the first device isolation pattern 104 and the first width W1 of the lower surface of the second device isolation pattern 105. For example, the first width W1 may be approximately twice the second width W2.

[0097] The first device isolation pattern 104, the second device isolation pattern 105, and the third device isolation pattern 106 can penetrate the substrate 103. The lower surfaces of the first device isolation pattern 104, the second device isolation pattern 105, and the third device isolation pattern 106 can be exposed from the lower surface of the substrate 103, such that the lower surfaces of the first device isolation pattern 104, the second device isolation pattern 105, and the third device isolation pattern 106 can be located between the lower surfaces of the substrate 103 and do not vertically overlap with the lower surface of the substrate 103. In some example embodiments, the lower surfaces of the first device isolation pattern 104, the second device isolation pattern 105, and the third device isolation pattern 106 can be coplanar (and / or substantially coplanar) with the lower surface of the substrate 103.

[0098] The height of the first device isolation pattern 104 and the second device isolation pattern 105 in the vertical direction (Z direction) may be greater than the first height H1 of the substrate 103 in the vertical direction (Z direction). In some example embodiments, the height of the third device isolation pattern 106 in the vertical direction (Z direction) may be the same as the first height H1 of the substrate 103.

[0099] The first device isolation pattern 104, the second device isolation pattern 105, and the third device isolation pattern 106 may include the same insulating material. For example, the insulating material may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, low-k dielectric, or combinations thereof. However, the example embodiments are not limited thereto.

[0100] According to some example embodiments, the semiconductor device 100 can use a first device isolation pattern 104, a second device isolation pattern 105, and a third device isolation pattern 106 disposed in the substrate 103 as etch stop layers during the polishing process of the substrate 103. Therefore, the lower surfaces of the first device isolation pattern 104, the second device isolation pattern 105, and the third device isolation pattern 106 can be coplanar (and / or substantially coplanar) with the lower surface of the substrate 103. Using the first device isolation pattern 104, the second device isolation pattern 105, and the third device isolation pattern 106 as etch stop layers without an etch stop layer can improve process efficiency and reduce the thickness of the substrate 103, thereby reducing the size of the semiconductor device.

[0101] The first structure ST1 may further include an insulating layer 183 covering the vertical conductive pattern 160 and the capacitor structure 150, a contact plug 185 penetrating the insulating layer 183 and connected to the vertical conductive pattern 160, and a conductive line 187 disposed on the insulating layer 183 and connected to the contact plug 185.

[0102] The conductive line 187 can extend in a first direction (X direction). The conductive line 187 can be electrically connected to a vertical conductive pattern 160 arranged in the first direction (X direction) via a contact plug 185.

[0103] The first structure ST1 may further include an insulating structure 196 on the conductive line 187, an interconnecting structure 190 embedded in the insulating structure 196, a first bonding insulating layer 194, and a first bonding metal layer 193 having an upper surface that is coplanar (and / or substantially coplanar) with the upper surface of the first bonding insulating layer 194.

[0104] The second structure ST2 may include Figure 1 The second memory region BA2 described herein includes peripheral circuitry such as a sense amplifier and a sub-word line driver. For example, the second structure ST2 may include a peripheral transistor PTR included in the peripheral circuitry. For instance, the first source / drain region SD1 of the unit transistor CTR disposed in the first structure ST1 can be electrically connected to the peripheral transistor PTR included in the sense amplifier disposed in the second structure ST2 via a vertical conductive pattern 160 and conductive lines 187. In some example embodiments, the electrical connection between the peripheral transistor PTR and the unit transistor CTR may be merely illustrative, and such example embodiments are not limited to... Figure 5 The structure in.

[0105] The second structure ST2 may further include a semiconductor body 203, a peripheral device isolation region 206s defining a peripheral active region 206a on the semiconductor body 203, a peripheral source / drain region pSD disposed in the peripheral active region 206a, a peripheral channel region pCH between the peripheral source / drain regions pSD, and a peripheral gate pG including a peripheral gate dielectric layer pGO and a peripheral gate electrode pGE disposed sequentially on the peripheral channel region pCH.

[0106] Each of the peripheral transistors (PTRs) may include a peripheral source / drain region (pSD), a peripheral channel region (pCH), and a peripheral gate (pG).

[0107] The second structure ST2 may further include a lower insulating layer 236 located below the semiconductor body 203, a redistribution structure 290 embedded in the lower insulating layer 236, a second bonding insulating layer 294, and a second bonding metal layer 293 connected to the redistribution structure 290 and having a lower surface coplanar (and / or substantially coplanar) with the lower surface of the second bonding insulating layer 294.

[0108] The first bonding insulating layer 194 may be bonded to and connected to the second bonding insulating layer 294. The first bonding insulating layer 194 and the second bonding insulating layer 294 may include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN. However, the exemplary embodiment is not limited thereto. The second bonding metal layer 293 may be bonded to and in contact with the first bonding metal layer 193. The first bonding metal layer 193 and the second bonding metal layer 293 may include a metallic material such as copper.

[0109] The first structure ST1 and the second structure ST2 can be joined to each other through a bonding between the first bonding insulating layer 194 and the second bonding insulating layer 294, and through a bonding between the first bonding metal layer 193 and the second bonding metal layer 293. The bonding between the first bonding metal layer 193 and the second bonding metal layer 293 can be a copper (Cu)-copper (Cu) bonding, and the bonding between the first bonding insulating layer 194 and the second bonding insulating layer 294 can be a dielectric-dielectric bonding, such as a SiCN-SiCN bonding. The first structure ST1 and the second structure ST2 can be joined to each other through a hybrid bonding including copper (Cu)-copper (Cu) bonding and dielectric-dielectric bonding. However, exemplary embodiments are not limited to this, and the first bonding metal layer 193 and the second bonding metal layer 293 may not be provided, and the first structure ST1 and the second structure ST2 may be joined to each other simply by bonding the first bonding insulating layer 194 and the second bonding insulating layer 294. In this case, the via 277 of the second structure ST2 can be directly connected to the interconnect structure 190 of the first structure ST1.

[0110] The second structure ST2 may also include an upper insulating structure 275 located on the semiconductor body 203, a peripheral interconnect structure 270 embedded in the upper insulating structure 275 and electrically connected to a peripheral transistor PTR included in the peripheral circuit, and an upper interconnect 280 located on the upper insulating structure 275.

[0111] The second structure ST2 may also include a via 277 that penetrates the semiconductor body 203 and electrically connects the peripheral interconnect structure 270 to the redistribution structure 290, and an insulating spacer 226 located on the side surface of the via 277.

[0112] Figure 9A This illustrates some example embodiments. Figure 5 An enlarged view of the semiconductor device shown. Figure 9B This illustrates some example embodiments. Figure 6 An enlarged view of the semiconductor device shown.

[0113] Reference Figure 9A and Figure 9B The components other than the first device isolation pattern 104' and the second device isolation pattern 105' in the substrate 103 can be connected with Figures 5 to 7 The components shown are the same as or may be the same as those shown. Figures 5 to 7 The components shown correspond to those shown.

[0114] Semiconductor device 100a may include a substrate 103 and a first device isolation pattern to a third device isolation pattern 104', 105' and 106 disposed in the substrate 103.

[0115] The lower part of the first device isolation pattern 104' and the second device isolation pattern 105' can be embedded in the substrate 103, and the lower surface of the third device isolation pattern 106 can be exposed from the lower surface of the substrate 103, such that the lower surface of the third device isolation pattern 106 can be located between the lower surfaces of the substrate 103 and does not vertically overlap with the lower surface of the substrate 103.

[0116] The first device isolation pattern 104' may overlap with the vertical conductive pattern 160 and may have an upper surface that contacts the lower surface of the vertical conductive pattern 160. In some example embodiments, the first device isolation pattern 104' may include a first portion 104a' and a second portion 104b', the second portion 104b' extending from the first portion 104a' and contacting the lower surface of the vertical conductive pattern 160. In some example embodiments, the first portion 104a' of the first device isolation pattern 104' may be embedded in the substrate 103. The lower surface of the first portion 104a' may be disposed at a level higher than the level of the lower surface of the substrate 103. The second portion 104b' of the first device isolation pattern 104' may have an upper surface that extends from the first portion 104a' and is disposed at a level higher than the level of the upper surface of the substrate 103.

[0117] The second device isolation pattern 105' may have an upper surface that overlaps with and contacts the lower surface of the capacitor structure 150. In some example embodiments, the second device isolation pattern 105' may include a third portion 105a' and a fourth portion 105b', the fourth portion 105b' extending from the third portion 105a' and contacting the lower surface of the capacitor structure 150. In some example embodiments, the third portion 105a' of the second device isolation pattern 105' may be embedded in the substrate 103. The lower surface of the third portion 105a' may be disposed at a level higher than the lower surface of the substrate 103. The fourth portion 105b' of the second device isolation pattern 105' may have an upper surface that extends from the third portion 105a' and is disposed at a level higher than the upper surface of the substrate 103.

[0118] In some example embodiments, the lower surface of the first device isolation pattern 104' and the lower surface of the second device isolation pattern 105' may be disposed at a higher level than the lower surface of the substrate 103, and may also be disposed at the same level. However, the example embodiments are not limited thereto, and the lower surface of the first device isolation pattern 104' may be disposed in the substrate 103 at a different level than the lower surface of the second device isolation pattern 105'.

[0119] The third device isolation pattern 106 can penetrate the substrate 103 and can have a width that decreases toward the lower surface of the substrate 103. In some example embodiments, the third device isolation pattern 106 can have an upper surface that is coplanar (and / or substantially coplanar) with the upper surface of the substrate 103 and a lower surface that is coplanar (and / or substantially coplanar) with the lower surface of the substrate 103. In some example embodiments, the height of the third device isolation pattern 106 in the vertical direction (Z direction) can be the same as the first height H1 of the substrate 103.

[0120] The height of the first device isolation pattern 104' in the vertical direction (Z direction) and the height of the second device isolation pattern 105' in the vertical direction (Z direction) may be less than the first height H1 of the substrate 103. However, the exemplary embodiments therein are not limited to this.

[0121] Semiconductor device 100a according to some example embodiments may include a third device isolation pattern 106 disposed in a substrate 103, and the third device isolation pattern 106 may be used as an etch stop layer in a process of polishing the substrate 103, and therefore, the lower surface of the third device isolation pattern 106 may be coplanar (and / or substantially coplanar) with the lower surface of the substrate 103. Using the third device isolation pattern 106 as an etch stop layer without an etch stop layer can improve process efficiency, reduce the thickness of the substrate 103, and reduce the size of the semiconductor device.

[0122] Figure 10 This illustrates some example embodiments. Figure 6 An enlarged view of the semiconductor device shown.

[0123] Reference Figure 10 Components other than the third device isolation pattern 106' in the substrate 103 of the semiconductor device 100b can be connected with Figures 5 to 7 The components shown are the same as or similar to Figures 5 to 7 The components shown correspond to those shown.

[0124] Reference Figure 10 as well as Figure 5 The semiconductor device 100b may include a substrate 103 and a first device isolation pattern 104, a second device isolation pattern 105, and a third device isolation pattern 106' disposed in the substrate 103. The third device isolation pattern 106' may be embedded in the substrate 103, and the lower surfaces of the first device isolation pattern 104 and the second device isolation pattern 105 may be exposed from the lower surface of the substrate 103, such that the lower surfaces of the first device isolation pattern 104 and the second device isolation pattern 105 may be located between the lower surfaces of the substrate 103 and do not vertically overlap with the lower surface of the substrate 103.

[0125] The third device isolation pattern 106' may have a width that decreases toward the lower surface of the substrate 103. In some example embodiments, the upper surface of the third device isolation pattern 106' may be coplanar (and / or substantially coplanar) with the upper surface of the substrate 103, and the lower surface of the third device isolation pattern 106' may be disposed at a level higher than the lower surface of the substrate 103. In some example embodiments, the height of the third device isolation pattern 106' in the vertical direction (Z direction) may be less than the first height H1 of the substrate 103.

[0126] According to some example embodiments, the semiconductor device 100b may include a first device isolation pattern 104 overlapping with a vertical conductive pattern 160 disposed in the substrate 103, and a second device isolation pattern 105 overlapping with a plate electrode PP. The first device isolation pattern 104 and the second device isolation pattern 105 can be used as etch stop layers in the process of polishing the substrate 103. Therefore, the lower surfaces of the first device isolation pattern 104 and the second device isolation pattern 105 can be coplanar (and / or substantially coplanar) with the lower surface of the substrate 103. Using the first device isolation pattern 104 and the second device isolation pattern 105 as etch stop layers without an etch stop layer can improve process efficiency, reduce the thickness of the substrate 103, and reduce the size of the semiconductor device.

[0127] Figure 11 , Figure 12 and Figure 13 This illustrates some example embodiments. Figure 5 An enlarged view of the semiconductor device shown.

[0128] Reference Figure 11 Components other than the first device isolation pattern 104' in the substrate 103 of the semiconductor device 100c can be connected with Figures 5 to 7 The components shown are the same as or similar to Figures 5 to 7 The components shown correspond to those shown.

[0129] Reference Figure 11 as well as Figure 6 and Figure 7 The semiconductor device 100c may include a substrate 103 and a first device isolation pattern 104', a second device isolation pattern 105, and a third device isolation pattern 106 disposed in the substrate 103. In some example embodiments, the lower surface of the first device isolation pattern 104' may be embedded in the substrate 103, and the lower surfaces of the second device isolation pattern 105 and the third device isolation pattern 106 may be exposed from the lower surface of the substrate 103, such that the lower surfaces of the second device isolation pattern 105 and the third device isolation pattern 106 may be located between the lower surfaces of the substrate 103 and do not vertically overlap with the lower surface of the substrate 103.

[0130] The first portion 104a' of the first device isolation pattern 104' may be embedded in the substrate 103, and the lower surface of the first device isolation pattern 104' may be disposed at a level higher than the lower surface of the substrate 103, the lower surface of the second device isolation pattern 105, and the lower surface of the third device isolation pattern 106. The lower surface of the second device isolation pattern 105 may be disposed at the same level as the lower surface of the third device isolation pattern 106, and may be coplanar (and / or substantially coplanar) with the lower surface of the substrate 103.

[0131] According to some example embodiments, the semiconductor device 100c may include a second device isolation pattern 105 and a third device isolation pattern 106 overlapping with a plate electrode PP disposed in a substrate 103, and the second device isolation pattern 105 and the third device isolation pattern 106 may be used as etch stop layers in the process of polishing the substrate 103. Therefore, the lower surfaces of the second device isolation pattern 105 and the third device isolation pattern 106 may be coplanar (and / or substantially coplanar) with the lower surface of the substrate 103. Using the second device isolation pattern 105 and the third device isolation pattern 106 as etch stop layers without an etch stop layer can improve process efficiency and reduce the thickness of the substrate 103, thereby also reducing the size of the semiconductor device.

[0132] Reference Figure 12 Components other than the second device isolation pattern 105' in the substrate 103 of the semiconductor device 100d can be connected with Figures 5 to 7 The components shown are the same as or similar to Figures 5 to 7 The components shown correspond to those shown.

[0133] Reference Figure 12 as well as Figure 6 and Figure 7 The semiconductor device 100d may include a substrate 103 and a first device isolation pattern 104, a second device isolation pattern 105', and a third device isolation pattern 106 disposed in the substrate 103. In some example embodiments, the lower surface of the second device isolation pattern 105' may be embedded in the substrate 103, and the lower surfaces of the first device isolation pattern 104 and the third device isolation pattern 106 may be exposed from the lower surface of the substrate 103, such that the lower surfaces of the first device isolation pattern 104 and the third device isolation pattern 106 may be located between the lower surfaces of the substrate 103 and do not vertically overlap with the lower surface of the substrate 103.

[0134] The lower surface of the first device isolation pattern 104 may be disposed at the same level as the lower surface of the third device isolation pattern 106, and may be coplanar (and / or substantially coplanar) with the lower surface of the substrate 103. The third portion 105a' of the second device isolation pattern 105' may be embedded in the substrate 103, and the lower surface of the second device isolation pattern 105' may be disposed at a level higher than the lower surface of the substrate 103 and the lower surface of the first device isolation pattern 104.

[0135] According to some example embodiments, the semiconductor device 100d may include a first device isolation pattern 104 and a third device isolation pattern 106 disposed in a substrate 103, and the first device isolation pattern 104 and the third device isolation pattern 106 may be used as etch stop layers in the process of polishing the substrate 103. Therefore, the lower surfaces of the first device isolation pattern 104 and the third device isolation pattern 106 may be coplanar (and / or substantially coplanar) with the lower surface of the substrate 103. Using the first device isolation pattern 104 and the third device isolation pattern 106 as etch stop layers without an etch stop layer can improve process efficiency and reduce the thickness of the substrate 103, thereby reducing the size of the semiconductor device.

[0136] Reference Figure 13 Components other than substrate 103 and the first device isolation pattern 104” and the second device isolation pattern 105” in substrate 103 can be connected with Figures 5 to 7 The components shown are the same as or similar to Figures 5 to 7 The components shown correspond to those shown.

[0137] Reference Figure 13 as well as Figure 6 The semiconductor device 100e may include a substrate 103, and a first device isolation pattern 104”, a second device isolation pattern 105” and a third device isolation pattern 106 buried in the substrate 103.

[0138] The first device isolation pattern 104” may overlap with the vertical conductive pattern 160 and may have an upper surface that contacts the lower surface of the vertical conductive pattern 160. In some example embodiments, the first device isolation pattern 104” may include a first portion 104a” and a second portion 104b”, the second portion 104b” extending from the first portion 104a” and contacting the lower surface of the vertical conductive pattern 160. In some example embodiments, the upper surface of the first device isolation pattern 104” may be disposed at a level lower than the level of the upper surface of the substrate 103. The vertical conductive pattern 160 may extend below the upper surface of the substrate 103. In some example embodiments, the upper surface of the second portion 104b” of the first device isolation pattern 104” may contact the vertical conductive pattern 160 at a level lower than the level of the upper surface of the substrate 103. The side surfaces of the first device isolation pattern 104” may be surrounded by the substrate 103.

[0139] The second device isolation pattern 105” may have an upper surface that overlaps with and contacts the lower surface of the capacitor structure 150. In some example embodiments, the second device isolation pattern 105” may include a third portion 105a” and a fourth portion 105b”, the fourth portion 105b” extending from the third portion 105a” and contacting the lower surface of the capacitor structure 150. In some example embodiments, the upper surface of the second device isolation pattern 105” may be disposed at a level lower than the level of the upper surface of the substrate 103. The lower surface of the capacitor structure 150 may be disposed at a level lower than the level of the upper surface of the substrate 103. The upper surface of the fourth portion 105b” of the second device isolation pattern 105” may contact the capacitor structure 150 at a level lower than the level of the upper surface of the substrate 103. The side surfaces of the second device isolation pattern 105” may be surrounded by the substrate 103.

[0140] In some example embodiments, the upper surfaces of the first device isolation pattern 104” and the second device isolation pattern 105” may be positioned at a lower level than the upper surface of the third device isolation pattern 106.

[0141] The height of the first device isolation pattern 104” in the vertical direction (Z direction) and the height of the second device isolation pattern 105” in the vertical direction (Z direction) can be less than the first height H1 of the substrate 103. The height of the third device isolation pattern 106 in the vertical direction (Z direction) can be substantially the same as the first height H1 of the substrate 103.

[0142] The first device isolation pattern 104", the second device isolation pattern 105", and the third device isolation pattern 106 can penetrate the substrate 103. The lower surfaces of the first device isolation pattern 104", the second device isolation pattern 105", and the third device isolation pattern 106 can be exposed from the lower surface of the substrate 103, such that the lower surfaces of the first device isolation pattern 104", the second device isolation pattern 105", and the third device isolation pattern 106 can be located between the lower surfaces of the substrate 103 and do not vertically overlap with the lower surface of the substrate 103. The lower surfaces of the first device isolation pattern 104", the second device isolation pattern 105", and the third device isolation pattern 106 can be coplanar (and / or substantially coplanar) with the lower surface of the substrate 103.

[0143] According to some example embodiments, the semiconductor device 100e may include a first device isolation pattern 104” and a second device isolation pattern 105” extending in a second direction (Y direction) and disposed in a substrate 103, and a third device isolation pattern 106 extending in a first direction (X direction) between the first device isolation pattern 104” and the second device isolation pattern 105”. The first to third device isolation patterns 104”, 105”, and 106 can be used as etch stop layers in the process of polishing the substrate 103. Therefore, the lower surfaces of the first device isolation pattern 104”, the second device isolation pattern 105”, and the third device isolation pattern 106 can be coplanar (and / or substantially coplanar) with the lower surface of the substrate 103. Using the first device isolation pattern 104”, the second device isolation pattern 105”, and the third device isolation pattern 106 as etch stop layers without an etch stop layer can improve process efficiency and reduce the thickness of the substrate 103, thereby reducing the size of the semiconductor device.

[0144] According to the foregoing example embodiments, in a semiconductor device, the thickness of the substrate can be reduced by using a first device isolation pattern that overlaps with the bit line, a second device isolation pattern that overlaps with the plate electrode of the capacitor, and a third device isolation pattern that isolates the memory cell as an etch stop layer in the process of polishing the substrate.

[0145] It will be understood that elements and / or their properties (e.g., structure, surface, orientation, etc.) that can be described as "perpendicular", "parallel", "coplanar" or the like relative to other elements and / or their properties (e.g., structure, surface, orientation, etc.) can be "perpendicular", "parallel", "coplanar" or the like relative to said other elements and / or their properties, or can be "substantially perpendicular", "substantially parallel", or "substantially coplanar".

[0146] Components and / or their properties that are "substantially coplanar" with respect to other components and / or their properties (e.g., structure, surface, orientation, etc.) will be understood as being "coplanar" with respect to the other components and / or their properties within manufacturing tolerances and / or material tolerances, and / or having a tolerance of equal to or less than 10% (e.g., ±10%) in size and / or angle with those that are "coplanar" with respect to the other components and / or their properties.

[0147] Although some exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and changes may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: The first structure includes a substrate; as well as The second structure overlaps with the first structure in the vertical direction and includes peripheral circuitry. The first structure includes: Device isolation structure, which is located in the substrate, A channel structure extending in a first horizontal direction on the substrate, the channel structures being spaced apart from each other in a second horizontal direction, the second horizontal direction intersecting the first horizontal direction. An insulating pattern is located between the channel structures. Bit lines, which extend vertically on the substrate and contact the first end of the channel structure, respectively. A gate electrode that extends in the second horizontal direction and surrounds the channel structure. A data storage structure, which contacts the second end of the channel structure and is spaced apart from each other in the second horizontal direction, the second end being opposite to the first end of the channel structure, and Plate electrodes, which are connected to the data storage structure and extend in the second horizontal direction and the vertical direction. The device isolation structure includes: The first device isolation pattern overlaps with the bit line in the vertical direction. The second device isolation pattern overlaps with the plate electrode in the vertical direction, and A third device isolation pattern overlaps the insulating pattern in the vertical direction, is spaced apart from each other in the second horizontal direction, and extends in the first horizontal direction between the first device isolation pattern and the second device isolation pattern. At least one of the first device isolation pattern, the second device isolation pattern, and the third device isolation pattern penetrates the substrate.

2. The semiconductor device according to claim 1, wherein, At least one of the lower surfaces of the first device isolation pattern, the second device isolation pattern, and the third device isolation pattern is coplanar with the lower surface of the substrate.

3. The semiconductor device according to claim 1, wherein, The first device isolation pattern extends in the second horizontal direction and includes an upper surface that contacts the lower surface of the bit line. The second device isolation pattern extends in the second horizontal direction and includes an upper surface that contacts the lower surface of the plate electrode.

4. The semiconductor device according to claim 1, wherein, The first device isolation pattern has a first width in the first horizontal direction, and Each of the third device isolation patterns has a second width in the second horizontal direction that is smaller than the first width.

5. The semiconductor device according to claim 4, wherein, The second device isolation pattern has a lower surface having the first width in the first horizontal direction.

6. The semiconductor device according to claim 1, wherein, The upper surface of each of the third device isolation patterns is coplanar with the upper surface of the substrate.

7. The semiconductor device according to claim 1, wherein, The upper surfaces of the first device isolation pattern and the second device isolation pattern are located at a level higher than the upper surface of the substrate.

8. The semiconductor device according to claim 1, wherein, Each of the third device isolation patterns has a width that decreases toward the lower surface of the substrate in the second horizontal direction.

9. The semiconductor device according to claim 1, wherein, The lower surface of the first device isolation pattern is located at the same level as the lower surface of the second device isolation pattern.

10. The semiconductor device according to claim 1, wherein, The gate electrode overlaps with the isolation pattern of the third device in the vertical direction.

11. The semiconductor device according to claim 1, wherein, The lower surfaces of the first device isolation pattern, the second device isolation pattern, and the third device isolation pattern are exposed from the lower surface of the substrate.

12. The semiconductor device according to claim 1, wherein, The first device isolation pattern includes a first portion and at least one second portion, the at least one second portion extending from the first portion and contacting the lower surface of a bit line on the substrate.

13. The semiconductor device according to claim 1, wherein, The second device isolation pattern includes a first portion and at least one second portion, the at least one second portion extending from the first portion and overlapping the data storage structure and the plate electrode in the vertical direction.

14. The semiconductor device according to claim 13, wherein, The first portion of the second device isolation pattern does not overlap with the data storage structure in the vertical direction.

15. The semiconductor device according to claim 1, wherein, The lower surfaces of the first device isolation pattern and the second device isolation pattern are located at a level higher than the lower surface of the substrate, and The lower surface of the isolation pattern of the third device is coplanar with the lower surface of the substrate.

16. A semiconductor device, comprising: A substrate having a first region and a second region; A device isolation structure located within the substrate; A channel structure extending in a first horizontal direction over a first region of the substrate, spaced apart from each other in a second horizontal direction, and also spaced apart in a vertical direction, the second horizontal direction intersecting the first horizontal direction, and the vertical direction intersecting both the first and second horizontal directions; Bit lines extend in the vertical direction over a first region of the substrate, are spaced apart from each other in the second horizontal direction, and respectively contact the first end of the channel structure; Gate electrodes, which are spaced apart from each other in the vertical direction around the channel structure, extend in the second horizontal direction, and include gate pads arranged in a stepped shape on the second region; A data storage structure that contacts a second end of the channel structure, the second end being opposite to a first end of the channel structure; as well as A plate electrode, which is connected to the data storage structure, and the plate electrode extends in the second horizontal direction and the vertical direction. The device isolation structure includes: The first device isolation pattern overlaps with the bit line in the vertical direction, and The second device isolation pattern overlaps with the plate electrode in the vertical direction, and At least one of the lower surfaces of the first device isolation pattern and the second device isolation pattern is coplanar with the lower surface of the substrate.

17. The semiconductor device according to claim 16, wherein, Each of the first device isolation pattern and the second device isolation pattern extends in the second horizontal direction over the first region and the second region.

18. The semiconductor device of claim 16, further comprising: A third device isolation pattern is located between the first device isolation pattern and the second device isolation pattern, and is spaced apart from each other in the second horizontal direction. The isolation pattern of the third device does not overlap with the channel structure in the vertical direction.

19. The semiconductor device according to claim 16, wherein, Each of the data storage structures includes: The first electrode is in contact with the second end of each of the channel structures. A dielectric layer, which is located on the first electrode, and The second electrode is located on the dielectric layer. The plate electrode extends from the data storage structure and includes the first electrode, the dielectric layer, and the second electrode stacked in the vertical direction. The upper surface of the second device isolation pattern contacts the first electrode of each of the data storage structures.

20. A semiconductor device, comprising: The first structure includes a substrate; as well as The second structure overlaps with the first structure in the vertical direction, and the second structure includes a peripheral circuit region. The first structure includes: Device isolation structure, which is located in the substrate, A channel structure extending in a first horizontal direction and spaced apart from each other in a second horizontal direction, the second horizontal direction intersecting the first horizontal direction, each of the channel structures including a channel region and a first source / drain region and a second source / drain region isolated from each other by the channel regions. An insulating pattern is located between the channel structures. The bit lines extend in the vertical direction and contact the first end of the channel structure, respectively. A gate dielectric layer that extends in the second horizontal direction and surrounds the channel region of the channel structure. A gate electrode that extends in the second horizontal direction and surrounds the gate dielectric layer. A data storage structure, which contacts a second end of the channel structure, the second end being opposite to a first end of the channel structure, and A plate electrode, which is connected to the data storage structure, extends in the second horizontal direction and also in the vertical direction. The device isolation structure includes: A first device isolation pattern having an upper surface that contacts the lower surface of the bit line, and the first device isolation pattern extending in the second horizontal direction. The second device isolation pattern has an upper surface that contacts the lower surface of the plate electrode, and the second device isolation pattern extends in the second horizontal direction. A third device isolation pattern overlaps the insulating pattern in the vertical direction, extends in the first horizontal direction between the first and second device isolation patterns, and is spaced apart from each other in the second horizontal direction. At least one of the first device isolation pattern, the second device isolation pattern, and the third device isolation pattern penetrates the substrate.

Images