Semiconductor device

Abstract

A semiconductor device may include a plurality of dies stacked in a vertical direction, wherein each of the plurality of dies includes: a first substrate; a unit capacitor on the first substrate; a cell transistor on the cell capacitor; a second substrate, wherein a vertical height of the second substrate is higher than a vertical height of the cell transistor; a peripheral circuit transistor on the second substrate; and a through-via passing through the first substrate and the second substrate in a vertical direction.

Description

semiconductor devices Technical Field

[0001] This disclosure relates to semiconductor devices, and more specifically, to semiconductor devices having a stacked structure of multiple dies. Background Technology

[0002] To improve the performance and storage capacity of semiconductor devices, semiconductor devices with structures in which multiple semiconductor dies are stacked are widely used. As semiconductor devices shrink in size, the dimensions of Dynamic Random Access Memory (DRAM) devices also decrease, and in DRAM devices with a 1T-1C structure (where one capacitor is connected to one transistor), there is a problem of gradually increasing leakage current occurring through the channel region. Therefore, vertical channel transistors are needed, which include a channel layer extending in the vertical direction to reduce leakage current. Summary of the Invention

[0003] One or more embodiments provide a semiconductor device having a structure in which a plurality of semiconductor dies are stacked, the plurality of semiconductor dies including vertical channel transistors having good electrical performance.

[0004] According to one aspect of this disclosure, a semiconductor device may include a plurality of dies stacked in a vertical direction, each of the plurality of dies including: a first substrate; a unit capacitor on the first substrate; a unit transistor on the unit capacitor; a second substrate, wherein the vertical height of the second substrate is greater than the vertical height of the unit transistor; a peripheral circuit transistor on the second substrate; and a through-path extending through the first substrate and the second substrate in a vertical direction.

[0005] According to one aspect of this disclosure, a semiconductor device may include: a first die; and a second die on the first die, wherein each of the first die and the second die includes: a first substrate; a unit capacitor on the first substrate; a unit transistor on the unit capacitor; a second substrate, wherein the vertical height of the second substrate is greater than the vertical height of the unit transistor; a peripheral circuit transistor on the second substrate; a through-path extending vertically through the first substrate and the second substrate; a wiring pattern that at least partially overlaps vertically with the through-path, wherein the vertical height of the wiring pattern is greater than the vertical height of the peripheral circuit transistor; a front pad on the upper surface of the wiring pattern; and a rear pad on the lower surface of the through-path.

[0006] According to one aspect of this disclosure, a semiconductor device may include: a first substrate including a first through-hole; a unit capacitor on the first substrate; a unit transistor on the unit capacitor; a second substrate, wherein the vertical height of the second substrate is greater than the vertical height of the unit transistor, the second substrate including a second through-hole perpendicularly overlapping the first through-hole; a peripheral circuit transistor on the second substrate; a through-hole contact extending vertically in the through-hole through the second substrate, the through-hole contact electrically connecting the peripheral circuit transistor to the unit transistor; a through-hole extending vertically through the first through-hole and the second through-hole; a through-hole insulating layer on the sidewall of the through-hole; a wiring pattern at least partially perpendicularly overlapping the through-hole, wherein the vertical height of the wiring pattern is greater than the vertical height of the peripheral circuit transistor; a front pad on the upper surface of the wiring pattern; a front insulating layer on the upper surface of the wiring pattern, the upper surface of the front insulating layer being coplanar with the upper surface of the front pad; a rear pad on the lower surface of the through-hole; and a rear insulating layer on the lower surface of the first substrate, the lower surface of the rear insulating layer being coplanar with the lower surface of the rear pad. Attached Figure Description

[0007] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a schematic diagram illustrating a semiconductor device according to an embodiment;

[0009] Figure 2 is a perspective view schematically showing each semiconductor die of Figure 1;

[0010] Figure 3 is a cross-sectional view showing region A in Figure 1;

[0011] Figure 4 is a schematic cross-sectional view of the cell array region of Figure 2;

[0012] Figure 5 is a schematic cross-sectional view of the cell array region according to an embodiment; and

[0013] Figures 6 to 8, 9A, 9B, 10 to 21, 22A and 22B are schematic diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment, wherein Figure 9B is an enlarged view of a portion of Figure 9A and Figure 22B is an enlarged view of region A of Figure 22A. Detailed Implementation

[0014] It will be understood that when a component or layer is referred to as being "on," "connected to," or "attached to" another component or layer, it can be directly on, directly connected to, or attached to the other component or layer, or there can be an intervening component or layer. Conversely, when a component or layer is referred to as being "directly on," "directly connected to," or "directly attached to" another component or layer, there is no intervening component or layer.

[0015] Figure 1 is a schematic diagram showing the semiconductor device 1 according to an embodiment. Figure 2 is a perspective view schematically showing each semiconductor die 10 of Figure 1. Figure 3 is a cross-sectional view showing region A of Figure 1. Figure 4 is a cross-sectional view schematically showing the cell array region MCA of Figure 2.

[0016] Referring to Figures 1 to 4, the semiconductor device 1 may include a plurality of semiconductor dies 10, which may be stacked in the vertical direction Z. Each of the plurality of semiconductor dies 10 may be disposed at an overlapping position in the vertical direction Z, and each of the plurality of semiconductor dies 10 may be electrically connected to a corresponding semiconductor die 10.

[0017] In one embodiment, each of the plurality of semiconductor dies 10 may include a memory chip (e.g., a dynamic random access memory (DRAM) device). In another embodiment, each of the plurality of semiconductor dies 10 may be a high-bandwidth memory (HBM) device. In yet another embodiment, the plurality of semiconductor dies 10 may not be mounted on a buffer die, and the semiconductor device 1 may be an unbuffered semiconductor device.

[0018] In other embodiments, the plurality of semiconductor dies 10 may be attached to a buffer die, which may include a logic chip. In another embodiment, the plurality of semiconductor dies 10 may be attached to a portion of an interposer layer, and the logic chip may be mounted in another portion of that interposer layer.

[0019] In one embodiment, each of the plurality of semiconductor dies 10 may include at least one through-path 12 extending through the die body 10M and in the vertical direction Z. Each of the plurality of semiconductor dies 10 may include at least one front pad 14P provided at (e.g., in or on) the uppermost surface of the corresponding semiconductor die 10 and at least one rear pad 16P provided at (e.g., in or on) the lowermost surface of the corresponding semiconductor die 10. In one embodiment, the at least one front pad 14P and the at least one rear pad 16P may be electrically connected to the at least one through-path 12.

[0020] In an embodiment, each of the plurality of semiconductor dies 10 may include a front insulating layer 14I defining the uppermost surface of the corresponding semiconductor die 10 and a rear insulating layer 16I defining the lowermost surface of the corresponding semiconductor die 10. The front insulating layer 14I may be disposed on the upper surface of the die body 10M of the semiconductor die 10, and the front insulating layer 14I may include an upper surface that can be configured to be coplanar with the upper surface of the front pad 14P. The rear insulating layer 16I may be disposed on the lower surface of the die body 10M of the semiconductor die 10, and the rear insulating layer 16I may include a lower surface that can be configured to be coplanar with the lower surface of the rear pad 16P.

[0021] In one embodiment, the plurality of semiconductor dies 10 may be attached or adhered to each other via a metal-oxide hybrid bonding process. In another embodiment, a front pad 14P included in one semiconductor die 10 may contact a rear pad 16P included in another semiconductor die 10 directly disposed on the one semiconductor die 10, and a front insulating layer 14I included in one semiconductor die 10 may contact a rear insulating layer 16I included in the other semiconductor die 10 directly disposed on the one semiconductor die 10.

[0022] In one embodiment, the plurality of semiconductor dies 10 may include a first die C1, a second die C2, a third die C3, a fourth die C4, a fifth die C5, and a sixth die C6, which may be stacked in the vertical direction Z. In another embodiment, the front pad 14P included in the first die C1 may contact the rear pad 16P included in the second die C2, and the front insulating layer 14I included in the first die C1 may contact the rear insulating layer 16I included in the second die C2. Furthermore, the front pad 14P included in the second die C2 may contact the rear pad 16P included in the third die C3, and the front insulating layer 14I included in the second die C2 may contact the rear insulating layer 16I included in the third die C3. The relationship between the third die C3, the fourth die C4, the fifth die C5, and the sixth die C6 may be the same as or similar to the relationship described above regarding the first die C2, the second die C2, and the third die C3. In this way, the plurality of semiconductor dies 10 can be stacked in the vertical Z direction by a metal-oxide hybrid bonding process.

[0023] In this embodiment, the number of semiconductor dies 10 stacked in the vertical direction Z is not limited to the number shown in FIG1. ​​For example, the number of semiconductor dies 10 can be 2 to 5 or 7 to 100.

[0024] In an implementation, each of the plurality of semiconductor dies 10 may include a DRAM device having a transistor-capacitor (1T-1C) structure, wherein a unit transistor CTR (see FIG2) is electrically connected to a unit capacitor CAP (see FIG2).

[0025] As shown in Figure 2, each of the plurality of semiconductor dies 10 may include a cell region CELL and a connection region CON. The cell region CELL of each of the plurality of semiconductor dies 10 may be a region in which a cell transistor CTR, a cell capacitor CAP, and a peripheral circuit transistor PTR are disposed, and the connection region CON of each of the plurality of semiconductor dies 10 may be a region in which the at least one through-path 12 is disposed.

[0026] In this implementation, the cell region (CELL) may include a cell array region (MCA) and a peripheral circuit region (PCA) disposed at different vertical heights relative to each other. The cell array region (MCA) and the peripheral circuit region (PCA) may overlap each other in the vertical direction Z. As shown in Figure 1, the peripheral circuit region (PCA) may be disposed on the cell array region (MCA), and each semiconductor device (e.g., semiconductor die 10) may have a cell-on-periphery (POC) structure.

[0027] In one implementation, the cell array region (MCA) can be a memory cell region of a DRAM device; for example, cell transistors (CTRs) and cell capacitors (CAPs) can be disposed within the MCA. In another implementation, the peripheral circuit region (PCA) can be the core region or the peripheral circuit region of the DRAM device. The PCA may include peripheral circuit transistors (PTRs) for transmitting signals and / or power to the cell transistors (CTRs) and cell capacitors (CAPs) (each of the CTRs and CAPs is included within the MCA). In yet another implementation, the PTRs may be configured with various circuits, such as command decoders, control logic, address buffers, row decoders, column decoders, sense amplifiers, and data input / output (I / O) circuitry.

[0028] In one embodiment, the peripheral circuit region PCA can be attached to the cell array region MCA via a bonding process. Alternatively, the peripheral circuit region PCA can be attached to the cell array region MCA via an oxide bonding process.

[0029] As shown in Figure 3, each semiconductor die 10 may include a first substrate 110, a unit capacitor CAP disposed on the first substrate 110, and a unit transistor CTR disposed on the unit capacitor CAP. Furthermore, each semiconductor die 10 may include a second substrate 210 disposed at a vertical height higher than the first substrate 110, and may include a peripheral circuit transistor PTR disposed on the second substrate 210. Each semiconductor die 10 may include at least one through-path 12, which passes through the first substrate 110 and the second substrate 210 and extends in the vertical direction Z.

[0030] Each semiconductor die 10 may include a wiring pattern WP disposed at a vertical height higher than that of the peripheral circuit transistor PTR. The wiring pattern WP may be electrically connected to the peripheral circuit transistor PTR and the second substrate 210, and may include a portion that vertically overlaps with the at least one through-path 12. This portion of the wiring pattern WP may be configured to cover the upper surface of the through-path 12. The wiring pattern WP may include multiple layers of multiple metal wiring lines. A wiring insulation layer 230 may be further disposed on the upper surface, sidewalls, and lower surface of each of the multiple metal wiring lines included in the wiring pattern WP.

[0031] Each semiconductor die 10 may include a third interlayer insulating layer 238, the at least one front pad 14P, and a front insulating layer 14I, which can be disposed on the upper surface of the wiring pattern WP.

[0032] In some embodiments, the at least one front pad 14P may comprise copper or a copper alloy. At least a portion of the sidewall of the at least one front pad 14P may be surrounded by a front insulating layer 14I and a third interlayer insulating layer 238. In one embodiment, the third interlayer insulating layer 238 may surround the lower portion of the sidewall of the at least one front pad 14P. In another embodiment, the front insulating layer 14I may be disposed on the third interlayer insulating layer 238 and may surround the upper portion of the sidewall of the at least one front pad 14P. In yet another embodiment, the front insulating layer 14I may have an upper surface coplanar with the upper surface of the at least one front pad 14P.

[0033] In some embodiments, the third interlayer insulating layer 238 may include silicon oxide, and the front insulating layer 14I may include at least one of silicon oxide, silicon nitride, silicon nitride, and silicon carbon nitride.

[0034] In some embodiments, a lower pad UWP may be further disposed between the wiring pattern WP and the at least one front pad 14P. The lower pad UWP may include at least one of aluminum, tungsten, copper, and nickel. The lower pad UWP may be formed to have a width greater than that of the front pad 14P, and the entire lower surface of the front pad 14P may be disposed on the flat upper surface of the lower pad UWP.

[0035] Each semiconductor die 10 may include at least one rear pad 16P connected to the lower end of the at least one through-path 12. In some embodiments, the at least one rear pad 16P may include copper or a copper alloy. At least a portion of the sidewall of the at least one rear pad 16P may be surrounded by a rear insulating layer 16I. The rear insulating layer 16I may include a lower surface coplanar with the lower surface of the at least one rear pad 16P. In some embodiments, the rear insulating layer 16I may include at least one of silicon oxide, silicon nitride, silicon oxide nitride, and silicon carbon nitride.

[0036] In one embodiment, the at least one through-path 12 may pass through the first substrate 110 and the second substrate 210 and may extend in the vertical direction Z. A through-path insulating layer 12I may be disposed on the sidewall of each of the at least one through-path 12. In some embodiments, the through-path insulating layer 12I may be disposed on the entire sidewall of the through-path 12.

[0037] In one embodiment, the first substrate 110 may include a first through-hole H1 passing through the first substrate 110, and the second substrate 210 may include a second through-hole H2 passing through the second substrate 210 and positioned perpendicularly to the first through-hole H1. A through-hole 12 may pass through the first through-hole H1 and the second through-hole H2 and may extend in the vertical direction Z. For example, the through-hole 12 may extend in the vertical direction Z such that a portion of the through-hole 12 is disposed within the first through-hole H1 and the second through-hole H2. A through-hole insulating layer 12I may surround the sidewall of the through-hole 12, may pass through the first through-hole H1 and the second through-hole H2, and may extend in the vertical direction Z.

[0038] In one embodiment, the through-pass 12 may include an upper surface disposed at a vertical height higher than the upper surface of the second substrate 210, and a lower surface disposed at a vertical height lower than the lower surface of the first substrate 110. In another embodiment, the through-pass insulating layer 12I may include an upper surface disposed at a vertical height higher than the upper surface of the second substrate 210, and a lower surface disposed at a vertical height lower than the lower surface of the first substrate 110. For example, a first portion of the through-pass insulating layer 12I may be disposed between the inner wall of the first through-pass hole H1 and the side wall of the through-pass 12, and a second portion of the through-pass insulating layer 12I may be disposed between the inner wall of the second through-pass hole H2 and the side wall of the through-pass 12. The side walls of the through-pass 12 may be surrounded by the through-pass insulating layer 12I, therefore, the through-pass 12 may be electrically insulated from the first substrate 110 and the second substrate 210.

[0039] In some embodiments, the first substrate 110 may include silicon (e.g., polycrystalline silicon, monocrystalline silicon, or amorphous silicon). In some other embodiments, the first substrate 110 may include at least one of germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP).

[0040] In one embodiment, the unit capacitor CAP can be disposed on the first substrate 110, and the unit capacitor CAP can be a metal-insulator-metal (MIM) type capacitor. In another embodiment, the unit capacitor CAP can include a first electrode 122, a capacitor dielectric layer 124, and a second electrode 126.

[0041] In other embodiments, instead of the unit capacitor CAP, a storage component such as a variable resistance storage device, a phase change storage device, or a magnetic storage device can be provided.

[0042] In one embodiment, an interface insulating layer 132 may be disposed between the first substrate 110 and the unit capacitor CAP, and a buried insulating layer 134 (e.g., a first buried insulating layer 134_1) may be disposed on the interface insulating layer 132 to surround the lower surface and sidewalls of the unit capacitor CAP. The buried insulating layer 134 may be configured on the first substrate 110 to cover the unit capacitor CAP, and the through-path 12 and the through-path insulating layer 12I may pass through the buried insulating layer 134 and may extend in the vertical direction Z. In another embodiment, at least a portion of the sidewall of the through-path insulating layer 12I may contact the buried insulating layer 134.

[0043] In one embodiment, the unit capacitor CAP can be attached to the first substrate 110 via a bonding process. In another embodiment, after forming the unit capacitor CAP and the first buried insulating layer 134_1 surrounding the unit capacitor CAP, an interface insulating layer 132 can be formed on the first substrate 110. The interface insulating layer 132 can be attached to the first buried insulating layer 134_1 via an oxide bonding process.

[0044] In one embodiment, the cell transistor CTR can be a vertical channel transistor (VCT). In another embodiment, the cell transistor CTR may include a channel layer AP extending in the vertical direction Z, a word line WL disposed on one sidewall of the channel layer AP, a back gate line BG disposed on the other sidewall of the channel layer AP, and a bit line BL disposed on the upper surface of the channel layer AP. A gate insulating layer GI may be disposed between the channel layer AP and the word line WL, and between the channel layer AP and the back gate line BG.

[0045] In one embodiment, the landing pad LP can be disposed on the lower surface of the channel layer AP, the first electrode 122 of the unit capacitor CAP can be configured to extend in the vertical direction Z, and the landing pad LP is between the channel layer AP and the first electrode 122.

[0046] In some embodiments, the channel layer AP may include at least one of silicon, germanium, and silicon-germanium. In some embodiments, multiple channel layer APs may be provided, and in some embodiments, the multiple channel layer APs may be arranged in a matrix in a first horizontal direction X and a second horizontal direction Y.

[0047] In one embodiment, multiple word lines WL and multiple back gate lines BG may be arranged alternately in a first horizontal direction X and may extend in a second horizontal direction Y. In another embodiment, the multiple word lines WL and the multiple back gate lines BG may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), molybdenum nitride (MoN), ruthenium (Ru), tungsten (W), tungsten nitride (WN), cobalt (Co), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), or combinations thereof.

[0048] In one embodiment, the bit line BL may be disposed on the upper surface of the channel layer AP and may extend in the first horizontal direction X. In another embodiment, the bit line BL may include Ti, TiN, Ta, TaN, Mo, MoN, Ru, W, WN, Co, TiSiN, WSiN, polysilicon, or a combination thereof.

[0049] In an embodiment, the gate insulating layer GI may include at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium nitride (HfON), hafnium silicon nitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium nitride (ZrON), zirconium silicon nitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconium titanium oxide (PbZrTiO), strontium tantalum bismuth oxide (SrTaBiO), bismuth iron oxide (BiFeO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0050] In this embodiment, the landing pad LP can be disposed between the lower surface of the channel layer AP and the first electrode 122. The landing pad LP may include Ti, TiN, Ta, TaN, Mo, MoN, Ru, W, WN, Co, TiSiN, WSiN, polysilicon or silicides thereof.

[0051] In one embodiment, the cell transistor CTR may be covered by a buried insulating layer 134. In another embodiment, the portion of the cell transistor CTR including the channel layer AP, word line WL, and back gate line BG may be covered by a second buried insulating layer 134_2 of the buried insulating layer 134, and the bit line BL may be covered by a third buried insulating layer 134_3 of the buried insulating layer 134.

[0052] In an embodiment, a unit wiring structure 136 may be provided, which can at least partially pass through the buried insulating layer 134 and be electrically connected to the unit capacitor CAP and the unit transistor CTR. The unit wiring structure 136 may include a first wiring 136_1 covered by a third buried insulating layer 134_3, a first contact 136_2 covered by a second buried insulating layer 134_2 and a third buried insulating layer 134_3 and connected to the first wiring 136_1 or the unit transistor CTR, a second wiring 136_3 covered by the first buried insulating layer 134_1, and a second contact 136_4 covered by the first buried insulating layer 134_1 and connected to the second wiring 136_3 or the unit capacitor CAP.

[0053] In one embodiment, the first wiring 136_1 and the first contact 136_2 may be electrically connected to the cell transistor CTR, for example, to the word line WL, the back gate line BG, and / or the bit line BL. In another embodiment, the second wiring 136_3 and the second contact 136_4 may be electrically connected to the cell capacitor CAP.

[0054] The first interlayer insulating layer 138 may be disposed on the lower surface of the first substrate 110. The first interlayer insulating layer 138 may surround a portion of the sidewall of the through-pass insulating layer 12I and a portion of the sidewall of the rear pad 16P. The rear insulating layer 16I may be disposed on the lower surface of the first interlayer insulating layer 138.

[0055] In one embodiment, the second substrate 210 may be disposed at a vertical height higher than that of the first substrate 110. The second substrate 210 may include silicon (e.g., polycrystalline silicon, monocrystalline silicon, or amorphous silicon). In some other embodiments, the second substrate 210 may include at least one of Ge, SiGe, SiC, GaAs, InAs, and InP.

[0056] The second interlayer insulating layer 234 can be disposed on the lower surface of the second substrate 210, and the lower surface of the second interlayer insulating layer 234 can contact the upper surface of the buried insulating layer 134 (e.g., the third buried insulating layer 134_3).

[0057] The peripheral circuit transistor (PTR) can be disposed on the upper surface of the second substrate 210. The PTR can include at least one of planar transistors, FinFET transistors, multi-bridge channel transistors, and buried channel array transistors.

[0058] Wiring pattern WP electrically connected to peripheral circuit transistor PTR and second substrate 210 can be disposed on the upper surface of second substrate 210, and wiring insulation layer 230 covering peripheral circuit transistor PTR and wiring pattern WP can be disposed on the upper surface of second substrate 210.

[0059] In one embodiment, the via 210H can be configured to pass through the second substrate 210, and the via insulating layer 222 can be disposed in the via 210H. The through-path contact 220 can pass through the through insulating layer 222 and can extend in the vertical direction Z, and the wiring pattern WP can be electrically connected to the unit wiring structure 136 through the through-path contact 220.

[0060] According to an embodiment, each semiconductor die 10 may include a unit transistor CTR disposed on a first substrate 110, a peripheral circuit transistor PTR disposed on a second substrate 210, and a through-path 12 passing through the first substrate 110 and the second substrate 210. The plurality of semiconductor dies 10 may be stacked in the vertical direction Z and connected together via a front pad 14P and a rear pad 16P. The semiconductor device 1 can have a high degree of integration and can have good electrical performance.

[0061] Figure 5 is a schematic cross-sectional view of the cell array region MCA-1 according to an embodiment.

[0062] Referring to Figure 5, a unit transistor (CTR) can be disposed in an opening portion of a molded insulating layer (MS). The unit transistor CTR may include a channel layer (AP) comprising a vertical cross-sectional surface having an inverted U-shape. Two word lines (WL) may be disposed spaced apart from each other between two vertical extensions of the channel layer (AP).

[0063] In one embodiment, the channel layer AP may include an oxide semiconductor. In another embodiment, the oxide semiconductor may include zinc tin oxide (ZnO2). x Sn y O), indium zinc oxide (In x Zn y O), zinc oxide (ZnO) x Indium gallium zinc oxide (In) x Ga y Zn z O), Indium gallium silicon oxide (In x Ga y Si z O), indium tungsten oxide (In) x W y O), indium oxide (In) x O), tin oxide (Sn) x O), titanium oxide (Ti x O), zinc nitrogen oxides (Zn) x ON z ), magnesium zinc oxide (Mg x Zn y O), zirconium indium zinc oxide (Zr) x In y Zn z O), hafnium indium zinc oxide (Hf x In y Zn z O), tin indium zinc oxide (Sn) x In y Zn z O), aluminum tin indium zinc oxide (Al) x Sn y In z Zn a O), silicon indium zinc oxide (Si) x In y Zn z O), aluminum zinc tin oxide (Al) x Zn y Sn z O), gallium zinc tin oxide (Ga x Zn y Sn z O) and zirconium zinc tin oxide (Zr) x Zny Sn z At least one of (O). In an embodiment, the channel layer AP may further include n-type impurity ions. For example, n-type impurity ions can be incorporated into the channel layer AP by an ion implantation process.

[0064] Figures 6 to 8, 9A, 9B, 10 to 21, 22A and 22B are schematic diagrams illustrating a method for manufacturing a semiconductor device 1 according to an embodiment.

[0065] Referring to FIG6, a mask pattern can be formed on the second substrate 210, and a via hole 210H can be formed by removing a portion of the second substrate 210 using the mask pattern as an etching mask. Subsequently, a via insulating layer 222 can be formed in the via hole 210H using an insulating material.

[0066] A peripheral circuit transistor (PTR) can be formed on the second substrate 210, and a first wiring insulating layer 230_1 covering the PTR can be formed. In an embodiment, the first wiring insulating layer 230_1 may include at least one of silicon oxide, silicon nitride, silicon oxide nitride, and a low-k dielectric material.

[0067] In an implementation, the peripheral circuit transistor PTR may include at least one of planar transistors, FinFET transistors, multi-bridge channel transistors, and buried channel array transistors.

[0068] Referring to FIG7, the first carrier substrate 310 may be attached to the first wiring insulating layer 230_1. In an embodiment, an interface insulating layer 312 may be formed on the first carrier substrate 310, and the interface insulating layer 312 may bond the first carrier substrate 310 to the second substrate 210 to contact the upper surface of the first wiring insulating layer 230_1.

[0069] In an embodiment, the interface insulating layer 312 may include at least one of silicon oxide, silicon nitride, silicon oxide nitride, and silicon carbon nitride.

[0070] In some embodiments, the interface insulating layer 312 can be bonded to the first wiring insulating layer 230_1 via an oxide bonding process. In some embodiments, plasma treatment can be performed on the surfaces of each of the interface insulating layer 312 and the first wiring insulating layer 230_1. In some embodiments, a chemical surface treatment can be performed on the surfaces of each of the interface insulating layer 312 and the first wiring insulating layer 230_1. In some embodiments, high-temperature annealing can be performed on the surfaces of each of the interface insulating layer 312 and the first wiring insulating layer 230_1.

[0071] Referring to Figure 8, the structure in which the second substrate 210 is bonded to the first carrier substrate 310 can be reversed.

[0072] Subsequently, a polishing process can be performed to remove a portion of the second substrate 210. The polishing process can be performed to expose the upper surface of the via insulating layer 222 (in the orientation shown in FIG. 8). The thickness of the second substrate 210 can be reduced by the polishing process.

[0073] Subsequently, a second interlayer insulating layer 234 can be formed on the upper surface of the second substrate 210. The second interlayer insulating layer 234 can be formed to cover the entire upper surface of the second substrate 210 and the entire upper surface of the via insulating layer 222.

[0074] Referring to Figures 9A and 9B, a unit transistor CTR can be formed on the second carrier substrate 320. For example, a channel layer AP, a word line WL, a back gate line BG, and a gate insulating layer GI (which are components of the unit transistor CTR) can be formed first.

[0075] In one implementation, the channel layer AP may extend in the vertical direction Z, and the gate insulating layer GI may be formed on each of the two sides of the channel layer AP. Subsequently, word lines WL may be formed on one sidewall of the channel layer AP with the gate insulating layer GI between them, and back gate lines BG may be formed on the other sidewall of the channel layer AP with the gate insulating layer GI between them.

[0076] In some embodiments, the interface insulating layer 322 may be disposed between the second carrier substrate 320 and the channel layer AP. In some embodiments, the second carrier substrate 320, the interface insulating layer 322, and the channel layer AP may be part of a silicon-on-insulator (SOI) type wafer. For example, an SOI type wafer may be provided, wherein the interface insulating layer 322 and the silicon layer are disposed on the second carrier substrate 320, and the channel layer AP may be formed by patterning the silicon layer.

[0077] In other embodiments, the second carrier substrate 320 may be provided as a bulk silicon type wafer. An interface insulating layer 322 may be formed on the second carrier substrate 320, and the channel layer AP may be formed on the interface insulating layer 322 by at least one of epitaxial processes, chemical vapor deposition (CVD) processes, and atomic layer deposition (ALD) processes.

[0078] In one embodiment, the unit transistor CTR can be formed on the second carrier substrate 320, and a second buried insulating layer 134_2 can be formed covering the unit transistor CTR.

[0079] Subsequently, a unit capacitor CAP can be formed on the unit transistor CTR and the second buried insulating layer 134_2. In an embodiment, a first electrode 122 extending in the vertical direction Z can be formed on each channel layer AP (or on a landing pad LP connected to the channel layer AP), and a capacitor dielectric layer 124 and a second electrode 126 can be formed sequentially on the first electrode 122.

[0080] Subsequently, a first buried insulating layer 134_1 covering the unit capacitor CAP can be formed. In an embodiment, the first buried insulating layer 134_1 may include a plurality of insulating layers. For example, a second wiring 136_3 may be formed on each of the plurality of insulating layers on which the first buried insulating layer 134_1 is configured, and a second contact 136_4 may be formed through at least one of the plurality of insulating layers on which the first buried insulating layer 134_1 is configured.

[0081] Here, the first buried insulation layer 134_1 and the second buried insulation layer 134_2 can be referred to as buried insulation layer 134.

[0082] Referring to FIG10, the first substrate 110 may be attached to the buried insulating layer 134. For example, the first substrate 110 may be attached to the buried insulating layer 134 such that the interface insulating layer 132 is between them.

[0083] In one embodiment, an interface insulating layer 132 may be formed on a first substrate 110, and the interface insulating layer 132 may bond a second carrier substrate 320 to the first substrate 110 to contact the upper surface of a buried insulating layer 134 (e.g., a first buried insulating layer 134_1 (see FIG. 9B)).

[0084] In an embodiment, the interface insulating layer 132 may include at least one of silicon oxide, silicon nitride, silicon nitride oxide, and silicon carbon nitride.

[0085] In some embodiments, the interface insulating layer 132 can be bonded to the buried insulating layer 134 via an oxide bonding process. In some embodiments, plasma treatment can be performed on the surfaces of each of the interface insulating layer 132 and the buried insulating layer 134. In some embodiments, a chemical surface treatment can be performed on the surfaces of each of the interface insulating layer 132 and the buried insulating layer 134. In some embodiments, high-temperature annealing can be performed on the surfaces of each of the interface insulating layer 132 and the buried insulating layer 134.

[0086] Referring to FIG11, the structure in which the first substrate 110 is bonded to the second carrier substrate 320 can be reversed.

[0087] Referring to FIG12, the second carrier substrate 320 (see FIG11) can be removed. In an embodiment, the second carrier substrate 320 can be removed by performing a polishing process and / or an etching process, thereby exposing the upper surface of the interface insulating layer 322.

[0088] Subsequently, the upper surface of the buried insulation layer 134 and each of the multiple trench layers AP can be exposed by removing the interface insulation layer 322.

[0089] In some implementations, source / drain regions can be formed on the upper side of each of the plurality of channel layers AP by implanting impurity ions into a portion of each of the plurality of channel layers AP.

[0090] Referring to FIG13, a bit line BL extending in the first horizontal direction X can be formed on the upper surface of each of the plurality of channel layers AP. The bit line BL can be electrically connected to a group of channel layers AP disposed spaced apart from each other in the first horizontal direction X.

[0091] Subsequently, a first contact 136_2 (see FIG. 4) and a wiring structure 136 electrically connected to the bit line BL, word line WL and back gate line BG (e.g., a first wiring 136_1 electrically connected to the bit line BL, word line WL and back gate line BG) can be formed (see FIG. 4), and a third buried insulating layer 134_3 covering the bit line BL, the first wiring 136_1 and the first contact 136_2 can be formed.

[0092] Referring to FIG14, the first carrier substrate 310 can be bonded to the first substrate 110.

[0093] In one embodiment, the first carrier substrate 310 may be bonded to the first substrate 110 such that the second substrate 210 is disposed at a vertical height higher than the vertical height of the unit transistor CTR disposed on the first substrate 110.

[0094] In this embodiment, the peripheral circuit transistor PTR can be disposed on the upper surface of the second substrate 210, and the second interlayer insulating layer 234 can be disposed on the lower surface of the second substrate 210. Here, the second substrate 210 can be disposed at a vertical height higher than that of the first substrate 110, such that the second interlayer insulating layer 234 is disposed on the upper surface of the buried insulating layer 134 (e.g., the third buried insulating layer 134_3). The lower surface of the second interlayer insulating layer 234 can contact the upper surface of the buried insulating layer 134.

[0095] In some embodiments, the second interlayer insulating layer 234 can be bonded to the buried insulating layer 134 using an oxide bonding process. In some embodiments, plasma treatment can be performed on the surfaces of each of the second interlayer insulating layer 234 and the buried insulating layer 134. In some embodiments, a chemical surface treatment can be performed on the surfaces of each of the second interlayer insulating layer 234 and the buried insulating layer 134. In some embodiments, high-temperature annealing can be performed on the surfaces of each of the second interlayer insulating layer 234 and the buried insulating layer 134.

[0096] Referring to FIG15, the first carrier substrate 310 (see FIG14) can be removed. In an embodiment, the first carrier substrate 310 can be removed by performing a grinding process and / or an etching process, thereby exposing the upper surface of the interface insulating layer 312 (see FIG14).

[0097] Subsequently, the upper surface of the first wiring insulation layer 230_1 can be exposed by removing the interface insulation layer 312.

[0098] Referring to FIG16, a mask pattern can be formed on the upper surface of the first wiring insulating layer 230_1, and the mask pattern can be used as an etching mask to remove a portion of the first wiring insulating layer 230_1 and a portion of the via insulating layer 222. A through-path contact 220 can then be formed by filling the regions from which the portions of the first wiring insulating layer 230_1 and the via insulating layer 222 have been removed with conductive material. The through-path contact 220 can pass through the first wiring insulating layer 230_1 and the via insulating layer 222, and can extend in the vertical direction Z. The through-path contact 220 can be disposed on the unit wiring structure 136 and can be electrically connected to the unit wiring structure 136.

[0099] Referring to FIG17, a mask pattern can be formed on the upper surface of the first wiring insulating layer 230_1, and the mask pattern can be used as an etching mask to form a through-hole H12 passing through a portion of the first wiring insulating layer 230_1, a portion of the second substrate 210, a portion of the second interlayer insulating layer 234, a portion of the buried insulating layer 134, and a portion of the first substrate 110. For example, the through-hole H12 can pass through the second substrate 210 and can extend in the vertical direction Z, and the through-hole H12 may not completely pass through the first substrate 110.

[0100] Referring to FIG18, a through-path insulating layer 12I can be formed on the inner wall of the through-path hole H12. The through-path insulating layer 12I may include silicon oxide, silicon nitride, or silicon nitride.

[0101] In an embodiment, the through-path insulating layer 12I can be formed on the through-path hole H12 to have a relatively uniform thickness.

[0102] Referring to Figure 19, a through passage 12 can be formed in the through passage hole H12.

[0103] In one embodiment, the through-pass 12 can be formed using copper or a copper alloy, either by electroplating or electroless plating. In another embodiment, prior to forming the through-pass 12, a seed layer can be further formed on the inner wall of the through-pass hole H12 using copper, titanium, silver, or platinum, via a sputtering process.

[0104] Referring to FIG20, a wiring pattern WP and a wiring insulation layer 230 may be formed on the upper surface of the through-path 12. A portion of the wiring pattern WP and a portion of the wiring insulation layer 230 may be disposed at a position that vertically overlaps with the through-path 12, and the wiring pattern WP may be electrically connected to the through-path 12.

[0105] Subsequently, a lower pad UWP electrically connected to the wiring pattern WP can be formed on the wiring insulation layer 230. A third interlayer insulation layer 238 can be formed on the lower pad UWP, and a front insulating layer 14I can be formed on the third interlayer insulation layer 238.

[0106] Subsequently, a front pad opening portion can be formed by removing a portion of each of the front insulating layer 14I and the third interlayer insulating layer 238, and a front pad 14P can be formed in the front pad opening portion.

[0107] In one embodiment, the front pad 14P can be formed using copper or a copper alloy, either by electroplating or electroless plating. In another embodiment, prior to forming the front pad 14P, a seed layer can be further formed on the inner wall of the front pad opening using copper, titanium, silver, or platinum, via a sputtering process.

[0108] In one embodiment, by performing a planarization process, such as chemical mechanical polishing, on the upper side of the front pad 14P, a portion of the upper side of the front pad 14P can be removed, such that the upper surface of the front pad 14P and the upper surface of the front insulating layer 14I are made to be coplanar with each other.

[0109] Referring to FIG21, a portion of the thickness of the first substrate 110 can be removed from the lower surface of the first substrate 110. In an embodiment, the process for removing a portion of the first substrate 110 from the lower surface of the first substrate 110 can be a polishing process. In an embodiment, a polishing process can be performed such that the lower surface of the through-path insulating layer 12I disposed on the lower surface of the through-path 12 is exposed. In other embodiments, after the lower surface of the through-path insulating layer 12I is exposed following the polishing process, an etching process can be further performed to further remove a portion of the thickness of the first substrate 110 from the lower surface of the first substrate 110.

[0110] In one embodiment, the portion of the through-path insulating layer 12I disposed at the lower surface of the through-path 12 can be removed, and the lower surface of the through-path 12 can be exposed. In another embodiment, the lower surface of the through-path 12 can be disposed at a level lower than the lower surface of the first substrate 110, and the lower surface of the through-path 12 can protrude downward relative to the lower surface of the first substrate 110.

[0111] Subsequently, the first interlayer insulating layer 138 can be formed on the lower surface of the first substrate 110 to have a sufficient thickness to cover the bottom of the through-passage 12. Subsequently, a rear insulating layer 16I can be formed on the lower surface of the first interlayer insulating layer 138.

[0112] A rear pad opening portion that re-exposes the lower surface of the through-path 12 can be formed by removing a portion of the rear insulating layer 16I and a portion of the first interlayer insulating layer 138, and a rear pad 16P can be formed in the rear pad opening portion.

[0113] In one embodiment, the rear pad 16P can be formed using copper or a copper alloy, either by electroplating or electroless plating. In another embodiment, prior to forming the rear pad 16P, a seed layer can be further formed on the inner wall of the rear pad opening using copper, titanium, silver, or platinum, via a sputtering process.

[0114] In one embodiment, by performing a planarization process (such as chemical mechanical polishing) on ​​the bottom of the rear pad 16P, a portion of the lower side of the rear pad 16P can be removed, such that the lower surface of the rear pad 16P and the lower surface of the rear insulating layer 16I are made coplanar.

[0115] By performing the above process, a semiconductor die 10 can be formed. According to an embodiment, the process can be performed multiple times to form multiple semiconductor dies 10.

[0116] Referring to Figures 22A and 22B, a semiconductor die 10 (e.g., the first die C1) can be bonded to another semiconductor die 10 (e.g., the second die C2).

[0117] The process of bonding the first die C1 to the second die C2 may include a metal-oxide hybrid bonding process. In one embodiment, the front pad 14P included in the first die C1 may contact the rear pad 16P included in the second die C2, and the front insulating layer 14I included in the first die C1 may contact the rear insulating layer 16I included in the second die C2.

[0118] In this way, multiple semiconductor dies 10 can be stacked in the vertical direction Z by a metal oxide hybrid bonding process, thus enabling the manufacture of the semiconductor device 1 described above with reference to Figures 1 to 4.

[0119] According to an embodiment, each semiconductor die 10 may include a vertical channel transistor (CTR) on a first substrate 110, a peripheral circuit transistor (PTR) on a second substrate 210, and a through-path 12 passing through the first substrate 110, the buried insulating layer 134, and the second substrate 210. The plurality of semiconductor dies 10 can be stacked in the vertical Z direction via front pads 14P and rear pads 16P. The semiconductor device 1 can have high integration density and good electrical performance.

[0120] According to an embodiment, each semiconductor die may include a vertical channel transistor disposed on a first substrate and a peripheral circuit transistor disposed on a second substrate, and may also include a through-path extending through the first and second substrates. Multiple dies may be stacked vertically and connected by front and rear pads. The semiconductor device can have high integration density and good electrical performance.

[0121] In the foregoing, non-limiting exemplary embodiments have been described with reference to the accompanying drawings. Embodiments have been described using the terminology described herein, but these terms are for illustrative purposes only and are not intended to limit their meaning or the scope of this disclosure. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments may be included within the scope of this disclosure.

[0122] Although non-limiting exemplary embodiments have been described with reference to the accompanying drawings, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure.

[0123] This application is based on and claims priority to Korean Patent Application No. 10-2024-0152967, filed on October 31, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: A plurality of dies are stacked in a vertical direction, each of the plurality of dies comprising: a first substrate; a unit capacitor on the first substrate; a unit transistor on the unit capacitor; a second substrate, wherein the vertical height of the second substrate is greater than the vertical height of the unit transistor; a peripheral circuit transistor on the second substrate; and a through-path extending through the first substrate and the second substrate in the vertical direction.

2. The semiconductor device of claim 1, wherein each of the plurality of dies further comprises: The wiring pattern at least partially overlaps vertically with the through-path, wherein the vertical height of the wiring pattern is higher than the vertical height of the peripheral circuit transistor; The front pad is on the upper surface of the wiring pattern; and the rear pad is on the lower surface of the through-path.

3. The semiconductor device of claim 2, wherein the plurality of dies includes a first die and a second die on the first die, and the through-path of the first die and the through-path of the second die are electrically connected to each other, the second die having a rear pad on the upper surface of the first die attached to the front pad of the first die.

4. The semiconductor device of claim 2, wherein each of the plurality of dies further comprises: A front insulating layer, on the upper surface of the wiring pattern, wherein the upper surface of the front insulating layer is coplanar with the upper surface of the front pad; The plurality of dies includes a first die and a second die on the first die, wherein the upper surface of the front insulating layer of the first die contacts the lower surface of the rear insulating layer of the second die.

5. The semiconductor device of claim 2, wherein each of the plurality of dies further comprises a through-path contact extending in the vertical direction through a via hole in the second substrate and electrically connecting the peripheral circuit transistor to the unit transistor.

6. The semiconductor device of claim 1, wherein the unit transistor comprises: The channel layer extends in the vertical direction; The letter line extends on one sidewall of the channel layer and in a first horizontal direction; And bit lines, on the upper surface of the channel layer, extending in a second horizontal direction intersecting the first horizontal direction.

7. The semiconductor device of claim 6, wherein the channel layer comprises silicon, germanium, silicon-germanium, or oxide semiconductor.

8. The semiconductor device of claim 1, wherein each of the plurality of dies further comprises a through-path insulating layer surrounding a sidewall of the through-path, the first substrate includes a first through-path hole through the first substrate, the second substrate includes a second through-path hole through the second substrate, the second through-path hole perpendicularly overlapping the first through-path hole, and the through-path perpendicularly overlapping the first through-path hole and the second through-path hole.

9. The semiconductor device of claim 8, wherein the through-path includes an upper surface, wherein the vertical height of the upper surface of the through-path is higher than the vertical height of the upper surface of the second substrate, and the through-path includes a lower surface, wherein the vertical height of the lower surface of the through-path is lower than the vertical height of the lower surface of the first substrate.

10. The semiconductor device of claim 8, wherein the through-path insulating layer includes an upper surface, wherein the vertical height of the upper surface of the through-path insulating layer is higher than the vertical height of the upper surface of the second substrate, and the through-path insulating layer includes a lower surface, wherein the vertical height of the lower surface of the through-path insulating layer is lower than the vertical height of the lower surface of the first substrate.

11. The semiconductor device of claim 8, wherein a first portion of the through-path insulating layer is between the sidewall of the through-path and the inner wall of the first through-path hole, a second portion of the through-path insulating layer is between the sidewall of the through-path and the inner wall of the second through-path hole, and the through-path is electrically insulated from the first substrate and the second substrate.

12. The semiconductor device of claim 8, wherein each of the plurality of dies further comprises: A buried insulating layer is located between the first substrate and the second substrate and on the unit transistor. The through-path insulating layer is located on the entire sidewall of the through-path, and at least a portion of the sidewall of the through-path insulating layer contacts the buried insulating layer.

13. A semiconductor device, comprising: First die; and a second die on the first die, wherein each of the first die and the second die includes: a first substrate; a unit capacitor on the first substrate; a unit transistor on the unit capacitor; a second substrate, wherein the vertical height of the second substrate is greater than the vertical height of the unit transistor; a peripheral circuit transistor on the second substrate; a through-path extending vertically through the first substrate and the second substrate; a wiring pattern at least partially vertically overlapping the through-path, wherein the vertical height of the wiring pattern is greater than the vertical height of the peripheral circuit transistor; a front pad on the upper surface of the wiring pattern; and a rear pad on the lower surface of the through-path.

14. The semiconductor device of claim 13, wherein each of the first die and the second die further comprises: A front insulating layer on the upper surface of the wiring pattern, wherein the upper surface of the front insulating layer is coplanar with the upper surface of the front pad; and a rear insulating layer on the lower surface of the first substrate, wherein the lower surface of the rear insulating layer is coplanar with the lower surface of the rear pad; and a buried insulating layer between the first substrate and the second substrate and on the unit transistor, wherein at least a portion of the through-path passes through the buried insulating layer.

15. The semiconductor device of claim 14, wherein the rear pad of the second die contacts the front pad of the first die, and the lower surface of the rear insulating layer of the second die contacts the upper surface of the front insulating layer of the first die.

16. The semiconductor device of claim 15, wherein the through-path of the first die is electrically connected to the through-path of the second die.

17. The semiconductor device of claim 13, wherein each of the first die and the second die further includes a through-path contact extending in the vertical direction through a via hole in the second substrate and electrically connecting the peripheral circuit transistor to the unit transistor.

18. The semiconductor device of claim 13, wherein the unit transistor comprises: The channel layer extends in the vertical direction; The letter line extends on one sidewall of the channel layer and in a first horizontal direction; And bit lines, wherein the vertical height of the bit lines is higher than the vertical height of the channel layer, and the bit lines extend in a second horizontal direction intersecting the first horizontal direction.

19. A semiconductor device, comprising: The first substrate includes a first through-hole; A unit capacitor is on the first substrate; a unit transistor is on the unit capacitor; A second substrate, wherein the vertical height of the second substrate is higher than the vertical height of the unit transistor, the second substrate includes a second through-hole that vertically overlaps with the first through-hole; a peripheral circuit transistor on the second substrate; and a through-hole contact extending vertically through the through-hole of the second substrate, the through-hole contact electrically connecting the peripheral circuit transistor to the unit transistor. A through-path, passing through the first through-path hole and the second through-path hole in the vertical direction; a through-path insulating layer on the sidewall of the through-path; a wiring pattern that at least partially overlaps the through-path vertically, wherein the vertical height of the wiring pattern is higher than the vertical height of the peripheral circuit transistor; a front pad on the upper surface of the wiring pattern; a front insulating layer on the upper surface of the wiring pattern, wherein the upper surface of the front insulating layer is coplanar with the upper surface of the front pad; Rear pads on the lower surface of the through-path; And a rear insulating layer, on the lower surface of the first substrate, wherein the lower surface of the rear insulating layer is coplanar with the lower surface of the rear pad.

20. The semiconductor device of claim 19, wherein the unit transistor comprises: The channel layer extends in the vertical direction; The letter line extends on one sidewall of the channel layer and in a first horizontal direction; And bit lines, wherein the vertical height of the bit lines is higher than the vertical height of the channel layer, and the bit lines extend in a second horizontal direction intersecting the first horizontal direction.

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