Semiconductor device and preparation method thereof, and semiconductor equipment
By arranging memory cells in three dimensions on a substrate and using interconnect structures to couple transistors, the problem of planar NAND flash memory approaching its storage density limit has been solved, achieving higher storage density and smaller device size, while reducing costs and improving reliability.
CN121968588APending Publication Date: 2026-05-01YANGTZE MEMORY TECH CO LTD
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Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2024-10-31
- Publication Date
- 2026-05-01
AI Technical Summary
Technical Problem
The storage density of existing 2D or planar NAND flash memory is nearing its limit. Planar processes and manufacturing technologies are costly and difficult to further increase storage density.
Method used
A three-dimensional memory structure is used to achieve higher storage density and control flexibility by arranging storage cells in three dimensions on a substrate and using interconnect structures to couple transistors to the semiconductor structure, including multiple interconnect structures and lead-out structures.
Benefits of technology
It increases storage density, reduces the size of semiconductor devices, lowers manufacturing costs, simplifies the process, and improves device reliability and stability.
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Smart Images
Figure CN121968588A_ABST
Abstract
The invention provides a semiconductor device and a preparation method thereof, and semiconductor equipment, and relates to the technical field of semiconductor chips. The semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a stack structure, a transistor, and a connection structure. The stacked structure comprises a core region, and the core region comprises first dielectric layers and gate layers which are alternately stacked. The transistor is located on one side of the core region, and the connecting structure penetrates through the core region of the stacked structure in the stacking direction and is coupled with the transistor. The number of the connection structures is multiple, and at least one connection structure couples the transistor and the second semiconductor structure. The semiconductor device is applied to the three-dimensional memory so as to realize data reading and writing operation.
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