Semiconductor structure, preparation method thereof and capacitor structure
By designing pillar arrays and barrier layers in the semiconductor structure, the contact area of the capacitor layer is increased, solving the problem of large size of traditional capacitors in high-voltage and high-power scenarios. This enables the integration and miniaturization of capacitors, increases capacitance, and reduces costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CSMC TECH FAB2 CO LTD
- Filing Date
- 2024-10-30
- Publication Date
- 2026-05-01
AI Technical Summary
Traditional capacitors are bulky in high-voltage, high-power applications, which cannot meet the requirements of integration and miniaturization of electronic products. Therefore, improving the storage capacity of silicon capacitors has become a research focus.
The semiconductor structure design includes a substrate, a barrier layer, and a pillar array. The pillar array consists of a first sub-pillar and a second sub-pillar. The sidewalls of the first sub-pillar have an uneven structure. By setting a barrier layer between the substrate and the pillar array, the contact area of the capacitor layer is increased and the substrate is protected.
The capacitance value of the capacitor structure was increased, the space occupied by the capacitor components was reduced, the integration and miniaturization of the capacitor were achieved, and the manufacturing cost was reduced.
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Figure CN121968599A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method, and a capacitor structure. Background Technology
[0002] Traditional capacitors are mostly discrete devices, with only one capacitance per capacitor. Their capacitance per unit volume is small, and in high-voltage, high-power applications, they occupy a significant amount of space. This fails to meet the requirements of integration and miniaturization in electronic products. Current research on integrated circuits mainly focuses on the integration of active devices, while the integration of passive devices lags behind. Capacitors, as important passive devices, have functions such as storing charge, smoothing voltage changes, blocking DC and passing AC, and bypassing high-frequency noise. Therefore, integrating capacitors is beneficial for further miniaturization and higher integration levels.
[0003] Silicon capacitors, as a novel electronic component, are manufactured using silicon materials and semiconductor processing techniques. Due to the high stability of silicon, silicon capacitors possess advantages such as good high-frequency characteristics, high-temperature resistance, and small size, making them widely used in electronic devices. Compared to traditional electrolytic capacitors, silicon capacitors have higher operating frequencies and lower equivalent series resistance, providing more stable capacitance values and lower losses. Since the semiconductor industry primarily uses silicon-based integrated circuits, integrating capacitors using silicon capacitors better meets the packaging requirements of integrated circuits. Currently, further improving the storage capacity of silicon capacitors is a key research focus. Summary of the Invention
[0004] Therefore, it is necessary to provide a semiconductor structure, its fabrication method, and a capacitor structure to address the above-mentioned problems.
[0005] To achieve the above objectives, in a first aspect, this application provides a semiconductor structure, comprising:
[0006] Base;
[0007] A barrier layer is disposed on one side of the substrate; and
[0008] A column array is disposed on the side of the barrier layer away from the substrate; the column array includes a plurality of columns arranged at intervals;
[0009] The column includes a first sub-column and a second sub-column arranged in a direction away from the base. The outer contour of the orthographic projection of the first sub-column on the base is located within the outer contour of the orthographic projection of the second sub-column on the base. The sidewall of the first sub-column has a concave-convex structure.
[0010] The semiconductor structure provided in this application embodiment includes a first sub-pillar and a second sub-pillar in the pillar array, with the outer contour of the orthographic projection of the first sub-pillar onto the substrate located within the outer contour of the orthographic projection of the second sub-pillar onto the substrate. The sidewalls of the first sub-pillar have an uneven structure. This increases the surface area of the pillar array, thereby improving the contact area of the capacitor layer in the capacitor structure and consequently increasing the capacitance value. Furthermore, by providing a barrier layer between the substrate and the pillar array, damage to the substrate during the etching process can be prevented.
[0011] In one embodiment, the sidewall of the first sub-pillar is provided with a protrusion.
[0012] In one embodiment, the protrusion is a spiky protrusion.
[0013] In one embodiment, the spike-like protrusion extends obliquely toward the side away from the column in the direction from the first sub-column to the second sub-column.
[0014] In one embodiment, the barrier layer is made of silicon oxide;
[0015] And / or, the distance between the surface of the column near the base and the surface of the column away from the base is between 6000 angstroms and 6900 angstroms.
[0016] Secondly, embodiments of this application provide a method for fabricating a semiconductor structure, including:
[0017] Provide a base;
[0018] A barrier layer is formed on the substrate;
[0019] A column array is formed on the barrier layer; the column array includes a plurality of columns arranged at intervals; the column includes a first sub-column and a second sub-column arranged in a direction away from the substrate, the outer contour of the orthographic projection of the first sub-column on the substrate is located within the outer contour of the orthographic projection of the second sub-column on the substrate; the sidewall of the first sub-column has a concave-convex structure.
[0020] The semiconductor structure fabrication method provided in this application involves making the pillar array include a first sub-pillar and a second sub-pillar, and ensuring that the outer contour of the orthographic projection of the first sub-pillar onto the substrate lies within the outer contour of the orthographic projection of the second sub-pillar onto the substrate. The sidewalls of the first sub-pillar have an uneven structure. This increases the surface area of the pillar array, thereby improving the contact area of the capacitor layer in the capacitor structure and consequently increasing the capacitance value. Furthermore, by providing a barrier layer between the substrate and the pillar array, damage to the substrate during the etching process can be prevented.
[0021] In one embodiment, forming a column array on the barrier layer includes:
[0022] A semiconductor material layer is formed on the barrier layer;
[0023] A mask layer is formed on the semiconductor material layer;
[0024] The semiconductor material layer is etched using a first etching process to form a second sub-pillar;
[0025] The semiconductor material layer is etched using a second etching process to form the first sub-pillar.
[0026] In one embodiment, the process gas for the first etching process includes chlorine, hydrogen bromide, and oxygen.
[0027] In one embodiment, the cavity pressure of the first etching process is between 8mT and 10mT, the source power is between 800W and 1000W, and the bias power is between 80V and 100V.
[0028] The flow rate ratio of chlorine, hydrogen bromide and oxygen is between 3:20:4 and 3:25:4.
[0029] In one embodiment, the process gas for the second etching process includes sulfur hexafluoride and oxygen.
[0030] In one embodiment, the flow ratio of sulfur hexafluoride to oxygen is between 7:2 and 7:5;
[0031] The cavity pressure of the second etching process is between 8mT and 10mT, the source power is between 800W and 1000W, and the bias power is between 80V and 100V.
[0032] Thirdly, embodiments of this application provide a capacitor structure, including:
[0033] The semiconductor structure described in any embodiment of the first aspect; and
[0034] A capacitor layer is disposed on the pillars of the pillar array.
[0035] The capacitor structure provided in this application embodiment includes a first sub-pillar and a second sub-pillar in the pillar array, with the outer contour of the orthographic projection of the first sub-pillar onto the substrate located within the outer contour of the orthographic projection of the second sub-pillar onto the substrate. The sidewalls of the first sub-pillar have an uneven structure. This increases the surface area of the pillar array, thereby improving the contact area of the capacitor layer and consequently increasing the capacitance value of the capacitor structure. Furthermore, by providing a barrier layer between the substrate and the pillar array, damage to the substrate during the etching process can be prevented. Attached Figure Description
[0036] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0037] Figure 1 This is a partial cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of this application.
[0038] Figure 2 for Figure 1 A top view of the semiconductor structure shown.
[0039] Figure 3 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application.
[0040] Figure 4 for Figure 3 A schematic diagram of a process for preparing S300 is shown.
[0041] Figures 5-9 for Figure 3 The diagram shows a cross-sectional view of the semiconductor structure during the fabrication process.
[0042] Figure 10 This is a partial cross-sectional schematic diagram of a capacitor structure provided in an embodiment of this application.
[0043] Explanation of reference numerals in the attached figures:
[0044] 1. Capacitor structure; 10. Semiconductor structure; 11. Substrate; 12. Barrier layer; 13. Pillar array; 131. Pillar; 1311. First sub-pillar; 1311a. Spiked protrusion; 1312. Second sub-pillar; 20. Capacitor layer; 30. Insulating layer; 2. Semiconductor material layer; 3. Mask layer. Detailed Implementation
[0045] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0047] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0048] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0049] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0050] Embodiments of the application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures), thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the application.
[0051] Firstly, referring to Figure 1 and Figure 2 As shown, this application embodiment provides a semiconductor structure 10, including a substrate 11, a barrier layer 12, and a pillar array 13. The barrier layer 12 is disposed on one side of the substrate 11. The pillar array 13 is disposed on the side of the barrier layer 12 away from the substrate 11. The pillar array 13 includes a plurality of pillars 131 arranged at intervals.
[0052] The column 131 includes a first sub-column 1311 and a second sub-column 1312 arranged in a direction away from the base 11. Specifically, the first sub-column 1311 is located at the bottom of the second sub-column 1312, and the second sub-column 1312 is located at the top of the first sub-column 1311. The outer contour of the orthographic projection of the first sub-column 1311 onto the base 11 lies within the outer contour of the orthographic projection of the second sub-column 1312 onto the base 11. In other words, the maximum outer diameter of the first sub-column 1311 is greater than the minimum outer diameter of the second sub-column 1312, and the second sub-column 1312 is equivalent to a "mushroom head". The sidewalls of the first sub-column 1311 have a concave-convex structure.
[0053] It should be noted that the materials of the substrate 11 and the pillar 131 can be monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound, silicon-on-insulator (SOI) or low-temperature polycrystalline silicon (LTPS), or other materials known to those skilled in the art.
[0054] Understandably, the general outline shape of the first sub-pillar 1311 and the second sub-pillar 1312 can be various forms, such as cylindrical, rhomboid, star-shaped, or honeycomb-shaped. Capacitive spaces are formed between adjacent pillars 131. In one example, the spacing between adjacent pillars 131 in the pillar array 13 is the same, and the height of each pillar 131 is equal. The ratio of the height to the width (or outer diameter) of the pillar 131 can be between 2:1 and 50:1.
[0055] As is well known, the capacitance of a capacitor is determined by the following formula:
[0056]
[0057] Where ε0 is the vacuum permittivity, ε r Let A be the relative permittivity, d be the effective area of the capacitor, and d be the distance between the two plates of the capacitor. To increase the capacitance, three approaches can be taken: selecting a material with a high relative permittivity; increasing the capacitor surface area; and decreasing the distance between the two conductive layers.
[0058] The semiconductor structure 10 provided in this application embodiment can form a three-dimensional capacitor structure 1 by setting a pillar array 13, thereby increasing the contact area (i.e., the capacitor surface area mentioned above) of the capacitor layer 20 of the capacitor structure 1 and thus increasing the capacitance value. Further, by making the pillars 131 of the pillar array 13 include a first sub-pillar 1311 and a second sub-pillar 1312, and ensuring that the outer contour of the orthographic projection of the first sub-pillar 1311 onto the substrate 11 is within the outer contour of the orthographic projection of the second sub-pillar 1312 onto the substrate 11, and the sidewall of the first sub-pillar 1311 has a concave-convex structure, the surface area of the pillar array 13 can be increased, which is beneficial for increasing the contact area of the capacitor layer 20 of the capacitor structure 1, and further beneficial for increasing the capacitance density (i.e., the capacitance value of the capacitor structure 1). In addition, by setting a barrier layer 12 between the substrate 11 and the pillar array 13, damage to the substrate 11 caused by the etching process can be prevented.
[0059] In one embodiment, the sidewall of the first sub-pillar 1311 is provided with protrusions. This allows the side surface of the first sub-pillar 1311 to form an uneven structure. For example, the protrusions can be toothed, spiked, spherical, or similar shapes.
[0060] In one embodiment, reference Figure 1 As shown, the protrusion is a spike-like protrusion 1311a. This allows it to be manufactured using a relatively simple, specific process, which helps reduce costs.
[0061] In one embodiment, the spike-like protrusion 1311a extends obliquely away from the column 131 in the direction from the first sub-column 1311 to the second sub-column 1312. That is, the extension direction of the spike-like protrusion 1311a intersects the extension direction (height direction) of the column 131, and the end (head) of the spike-like protrusion 1311a faces upward. In this way, the side wall of the first sub-column 1311 is provided with a "barbed" protrusion, which on the one hand helps to increase the side surface area of the column 131; on the other hand, it can be manufactured by a relatively simple specific process, which helps to reduce costs.
[0062] It should be noted that the first sub-pillar 1311 can also be considered as a cylindrical structure similar to a "mace".
[0063] In one embodiment, the spike-like protrusions 1311a are evenly distributed on the sidewall of the first sub-pillar 1311.
[0064] It is understood that the size and extension length of each spike protrusion 1311a may be the same or different. This application does not specifically limit the exact dimensions of the spike protrusions 1311a in its embodiments.
[0065] In one embodiment, the barrier layer 12 is made of silicon oxide. This allows for the use of lower-cost materials to fabricate the barrier layer 12, thereby preventing damage to the substrate 11 during the fabrication of the pillar array 13.
[0066] In one embodiment, the distance between the surface of the pillar 131 closest to the substrate 11 and the surface of the pillar 131 furthest from the substrate 11 is between 6000 angstroms and 6900 angstroms. That is, the height of the pillar 131 is between 6000 angstroms and 6900 angstroms. Exemplarily, the height of the pillar 131 can be 6000 angstroms, 6300 angstroms, 6600 angstroms, 6800 angstroms, 6900 angstroms, etc.
[0067] By keeping the height of the column 131 within the aforementioned range, the etching depth can be reduced while ensuring that the column 131 has sufficient surface area, which helps to reduce manufacturing costs.
[0068] It should be noted that, in one example, the barrier layer 12 can cover the entire substrate 11, that is, the entire surface of the substrate 11 near the column array 13 is covered with the barrier layer 12. In another example, the barrier layer 12 is only provided below the columns 131, and the barrier layer 12 in the areas not covered by the columns 131 is removed.
[0069] Secondly, referring to Figure 3 As shown in the figure, this application provides a method for fabricating a semiconductor structure 10, which specifically includes the following steps:
[0070] S100: Provides substrate 11. For example... Figure 5 As shown, the material of the substrate 11 can be monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound, silicon-on-insulator (SOI) or low-temperature polycrystalline silicon (LTPS), etc.
[0071] S200: A barrier layer 12 is formed on the substrate 11. The structure of the barrier layer 12 after its formation is as follows: Figure 6 As shown. For example, the barrier layer 12 can be made of silicon dioxide.
[0072] S300: A column array 13 is formed on the barrier layer 12. The column array 13 includes a plurality of columns 131 arranged at intervals; the column 131 includes a first sub-column 1311 and a second sub-column 1312 arranged in a direction away from the substrate 11, the outer contour of the orthographic projection of the first sub-column 1311 on the substrate 11 is located within the outer contour of the orthographic projection of the second sub-column 1312 on the substrate 11; the sidewall of the first sub-column 1311 has a concave-convex structure.
[0073] By providing a barrier layer 12 between the substrate 11 and the pillar array 13, damage to the substrate 11 can be prevented from being caused by subsequent etching processes. The pillars 131 of the pillar array 13 include a first sub-pillar 1311 and a second sub-pillar 1312, with the outer contour of the orthographic projection of the first sub-pillar 1311 onto the substrate 11 located within the outer contour of the orthographic projection of the second sub-pillar 1312 onto the substrate 11. The sidewalls of the first sub-pillar 1311 have an uneven structure. This increases the surface area of the pillar array 13, thereby improving the contact area of the capacitor layer 20 of the capacitor structure 1, and consequently, increasing the capacitance value of the capacitor structure 1.
[0074] In one embodiment, reference Figure 4 As shown, S300: Forming a column array 13 on the barrier layer 12 specifically includes the following steps:
[0075] S310: A semiconductor material layer 2 is formed on the barrier layer 12. The structure of the semiconductor material layer 2 after its formation is as follows. Figure 7 As shown, the semiconductor material layer 2 can be made of monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound, silicon-on-insulator (SOI), or low-temperature polycrystalline silicon (LTPS), etc.
[0076] S320: A mask layer 3 is formed on the semiconductor material layer 2. Specifically, refer to... Figure 8 As shown, photoresist can be coated on the semiconductor material layer 2, and after exposure and development, a patterned mask layer 3 can be defined.
[0077] S330: The semiconductor material layer 2 is etched using a first etching process to form the second sub-pillar 1312. That is: a "mushroom head" is first formed on the semiconductor material layer 2 so that a first sub-pillar 1311 with an uneven surface can be formed below the "mushroom head".
[0078] S340: The semiconductor material layer 2 is etched using a second etching process to form the first sub-pillar 1311. (Refer to...) Figure 9 As shown, a spike-like protrusion 1311a is formed on the side wall of the first sub-pillar 1311. The spike-like protrusion 1311a extends obliquely away from the pillar 131 in the direction from the first sub-pillar 1311 to the second sub-pillar 1312. That is, the extension direction of the spike-like protrusion 1311a intersects the extension direction (height direction) of the pillar 131, and the end (head) of the spike-like protrusion 1311a faces upward. In this way, the side wall of the first sub-pillar 1311 is provided with a "barbed" protrusion, which on the one hand helps to increase the side surface area of the pillar 131; on the other hand, it can be manufactured by a relatively simple specific process, which helps to reduce costs.
[0079] In one embodiment, the process gas for the first etching process includes chlorine, hydrogen bromide, and oxygen. Here, chlorine plays the primary etching role, hydrogen bromide can generate polymers and protect the sidewalls of the first sub-pillar 1311, and oxygen provides a protective function.
[0080] In one embodiment, the flow rate ratio of chlorine, hydrogen bromide, and oxygen is between 3:20:4 and 3:25:4. Exemplarily, the flow rate ratio can be 3:20:4, 3:21:4, 3:22:4, 3:23:4, 3:25:4, etc. By keeping the flow rate ratio of chlorine, hydrogen bromide, and oxygen within the above-mentioned range, it is beneficial to form a "mushroom head" shaped second sub-pillar 1312.
[0081] In one embodiment, the chamber pressure of the first etching process is between 8 mT and 10 mT. Exemplarily, the chamber pressure can be 8 mT, 8.5 mT, 9.3 mT, 10 mT, etc. The source power is between 800 W and 1000 W. Exemplarily, the source power can be 800 W, 850 W, 930 W, 980 W, 1000 W, etc. The bias power is between 80 V and 100 V. The bias power can be 80 V, 85 V, 90 V, 98 V, 100 V, etc.
[0082] Thus, using lower cavity pressure, higher source power, and lower bias power helps to form the "mushroom head" shaped second sub-pillar 1312.
[0083] In one embodiment, the process gas for the second etching process includes sulfur hexafluoride and oxygen. This facilitates the formation of a "spike-like" structure with barbed protrusions.
[0084] In one embodiment, the process gas for the second etching process also includes chlorine and hydrogen bromide.
[0085] In one embodiment, the flow ratio of sulfur hexafluoride to oxygen is between 7:2 and 7:5. Exemplarily, the flow ratio of sulfur hexafluoride to oxygen can be 7:2, 7:3, 7:4, 7:5, etc. This facilitates the formation of a "spike-like" structure with barbed protrusions.
[0086] In one embodiment, the volumetric flow rate of sulfur hexafluoride is between 32 sccm and 38 sccm, and the volumetric flow rate of oxygen is between 10 sccm and 25 sccm.
[0087] In one embodiment, the chamber pressure of the second etching process is between 8 mT and 10 mT. Exemplarily, the chamber pressure can be 8 mT, 8.5 mT, 9.3 mT, 10 mT, etc. The source power is between 800 W and 1000 W. Exemplarily, the source power can be 800 W, 850 W, 930 W, 980 W, 1000 W, etc. The bias power is between 80 V and 100 V. The bias power can be 80 V, 85 V, 90 V, 98 V, 100 V, etc.
[0088] Thus, using lower cavity pressure, higher source power, and lower bias power helps to form a "malle mace"-like structure with "barbed" protrusions.
[0089] In one embodiment, both the first and second etching processes utilize the same equipment. Specifically, both the first and second etching processes employ an inductively coupled plasma (ICP) generator. Further, after the first etching process is completed, sulfur hexafluoride is introduced, and the flow ratio of sulfur hexafluoride to oxygen is adjusted, while other process gases and parameters remain unchanged. This eliminates the need to adjust numerous process parameters, thus reducing process costs. Furthermore, it should be noted that compared to the traditional Bosch process, the fabrication process provided in this embodiment has the advantages of simplicity and shorter processing time.
[0090] In one embodiment, S300: A column array 13 is formed on the barrier layer 12, and then the following steps are included:
[0091] S400: Remove the mask layer and polymer from pillar 131. Specifically, the mask layer 3 and polymer can be removed by a dry process or a wet process.
[0092] Thirdly, referring to Figure 10 As shown, this application provides a capacitor structure 1, which includes a capacitor layer 20 and a semiconductor structure 10 of any embodiment in the first aspect. The capacitor layer 20 is disposed on the pillars 131 of the pillar array 13.
[0093] The capacitor structure 1 provided in this embodiment of the application includes a first sub-pillar 1311 and a second sub-pillar 1312 in the pillar array 13, with the outer contour of the orthographic projection of the first sub-pillar 1311 onto the substrate 11 located within the outer contour of the orthographic projection of the second sub-pillar 1312 onto the substrate 11. The sidewall of the first sub-pillar 1311 has a concave-convex structure. This increases the surface area of the pillar array 13, thereby improving the contact area of the capacitor layer 20 and consequently increasing the capacitance value of the capacitor structure 1.
[0094] In one embodiment, the capacitor structure 1 further includes an insulating layer 30 disposed between the capacitor layer 20 and the pillar 131. Exemplarily, the insulating layer 30 may be made of silicon oxide.
[0095] In one embodiment, the capacitor layer 20 includes alternating layers of electrode layers (not shown) and dielectric layers (not shown). Exemplarily, the capacitor layer 20 may include a first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer, and a third electrode layer, which are stacked sequentially. The first, second, and third electrode layers are made of conductive materials, while the first and second dielectric layers may be made of inorganic dielectrics, including, but not limited to, silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, titanium oxide, zirconium oxide, and hafnium oxide. It is understood that the capacitor layer 20 can be adapted to have more alternating electrode and dielectric layers; for simplicity, only a structure with three alternating electrode layers and two alternating dielectric layers is described.
[0096] Furthermore, the capacitor structure 1 also includes distributed electrodes (not shown in the figure), which are electrically connected to the electrode layer in the capacitor layer 20.
[0097] It should be noted that doped resistors, PiN diodes, Schottky diodes, and other semiconductor devices can be formed on the back side of the substrate 11 of capacitor structure 1 through a doping process, thereby realizing an integrated passive device. Resistors or semiconductor devices can be generated by ion implantation doping on the back side of substrate 11. The resistivity of the resistor or semiconductor device is determined by the carrier concentration and mobility; the higher the impurity concentration, the lower the resistivity.
[0098] Understandably, capacitor structure 1 is made using silicon material through semiconductor manufacturing processes, which facilitates the integration of capacitor devices. When the capacitance value of capacitor structure 1 can be guaranteed, the size of capacitor structure 1 can be reduced to achieve a high degree of integration of semiconductor devices.
[0099] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0100] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0101] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A semiconductor structure, characterized in that, include: Base; A barrier layer is disposed on one side of the substrate; as well as A column array is disposed on the side of the barrier layer away from the substrate; The column array comprises multiple columns arranged at intervals; The column includes a first sub-column and a second sub-column arranged in a direction away from the base. The outer contour of the orthographic projection of the first sub-column on the base is located within the outer contour of the orthographic projection of the second sub-column on the base. The sidewall of the first sub-column has a concave-convex structure.
2. The semiconductor structure according to claim 1, characterized in that, The side wall of the first sub-pillar has a protrusion.
3. The semiconductor structure according to claim 2, characterized in that, The protrusion is a spiky protrusion.
4. The semiconductor structure according to claim 3, characterized in that, The spike-like protrusions extend obliquely toward the side away from the column along the direction from the first sub-column toward the second sub-column.
5. The semiconductor structure according to claim 1, characterized in that, The barrier layer is made of silicon oxide; And / or, the distance between the surface of the column near the base and the surface of the column away from the base is between 6000 angstroms and 6900 angstroms.
6. A capacitor structure, characterized in that, include: The semiconductor structure as described in any one of claims 1-5; as well as A capacitor layer is disposed on the pillars of the pillar array.
7. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; A barrier layer is formed on the substrate; A column array is formed on the barrier layer; The column array includes multiple columns arranged at intervals; each column includes a first sub-column and a second sub-column arranged in a direction away from the base, wherein the outer contour of the orthographic projection of the first sub-column on the base is located within the outer contour of the orthographic projection of the second sub-column on the base; the sidewall of the first sub-column has a concave-convex structure.
8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The formation of a column array on the barrier layer includes: A semiconductor material layer is formed on the barrier layer; A mask layer is formed on the semiconductor material layer; The semiconductor material layer is etched using a first etching process to form a second sub-pillar; The semiconductor material layer is etched using a second etching process to form the first sub-pillar.
9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The process gases for the first etching process include chlorine, hydrogen bromide, and oxygen.
10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The cavity pressure of the first etching process is between 8mT and 10mT, the source power is between 800W and 1000W, and the bias power is between 80V and 100V. The flow rate ratio of chlorine, hydrogen bromide and oxygen is between 3:20:4 and 3:25:
4.
11. The method for preparing a semiconductor structure according to claim 8, characterized in that, The process gases for the second etching process include sulfur hexafluoride and oxygen.
12. The method for preparing a semiconductor structure according to claim 11, characterized in that, The flow ratio of sulfur hexafluoride to oxygen is between 7:2 and 7:5; The cavity pressure of the second etching process is between 8mT and 10mT, the source power is between 800W and 1000W, and the bias power is between 80V and 100V.