Etching method for forming smooth three-dimensional surface of semiconductor substrate and manufacturing method of deep groove capacitor

Abstract

The invention provides an etching method for forming a smooth three-dimensional surface of a semiconductor substrate and a deep groove capacitor obtained by using the method, and the method comprises the steps: S10, uniformly coating a photoresist layer on the semiconductor substrate, and carrying out the photoetching exposure of a mask plate to obtain photoresist patterns which are uniformly distributed in an array; s20, performing high-temperature curing on the photoresist pattern array to enable the upper surface of the photoresist pattern array to be a curved surface; s30, dry etching is carried out by using the curved photoresist pattern as a mask, array-distributed semiconductor patterns with curved upper surfaces are formed on the surface of the semiconductor substrate, and grooves are formed between the semiconductor patterns; according to the method, the spherical segment surface is obtained by utilizing the characteristic that the photoresist is shrunk after being cured at the temperature, and the spherical segment surface is processed by utilizing a dry etching technology by adjusting the etching rate ratio of different materials, so that the arc-shaped corner is obtained.

Description

An etching method for forming a smooth three-dimensional surface of a semiconductor substrate and a method for manufacturing deep trench capacitors. Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and in particular to an etching method for forming a smooth three-dimensional surface of a semiconductor substrate and a method for manufacturing deep trench capacitors. Background Technology

[0002] Etching is a common process step in semiconductor manufacturing. Sharp corners are easily formed on the sidewall edges of the etched area, especially in deep trench etching. For example, in capacitor manufacturing, deep trenches are often etched to increase capacitance density and thus the capacitor area. A common deep trench structure is a U-shaped morphology extending vertically downwards to the bottom. During the fabrication of high-voltage silicon capacitors, when depositing a dielectric layer (such as silicon oxide) in the deep trench, due to the interface effect between the silicon substrate and silicon oxide, sharp corners inevitably form at the concave corners on both sides of the bottom of the deep trench. The silicon oxide thickness is thinner at these corners, leading to a decrease in withstand voltage and significantly impacting the performance of the silicon capacitor. Furthermore, when filling this U-shaped deep trench with conductive materials (such as polysilicon), it is very easy to seal the top of the deep trench, creating voids inside the trench and affecting the mechanical strength and stability of the capacitor. Summary of the Invention

[0003] To address the aforementioned product performance issues, this invention provides a semiconductor substrate etching method for forming a smooth three-dimensional surface and a method for manufacturing a deep trench capacitor, thus solving the problem of concave corners at the bottom of the deep trench.

[0004] This invention provides a method for etching a semiconductor substrate to form a smooth three-dimensional surface, comprising the following steps: S10: uniformly coating a photoresist layer on a semiconductor substrate and obtaining a uniformly arrayed photoresist pattern through photolithography exposure using a mask; S20: curing the photoresist pattern array at high temperature to make its upper surface curved; S30: using the curved photoresist pattern as a mask to perform dry etching to form an arrayed semiconductor pattern with a curved upper surface on the surface of the semiconductor substrate, wherein trenches are present between the semiconductor patterns.

[0005] Optionally, step S25 is further included between steps S20 and S30: performing wet etching to form pits in the gaps between the photoresist patterns on the semiconductor substrate.

[0006] Optionally, before step S10, step S5 is further included: forming an array of pre-fabricated semiconductor patterns on the surface of a semiconductor substrate using dry etching, wherein the photoresist pattern is formed on the pre-fabricated semiconductor pattern in step S10.

[0007] Optionally, the photoresist pattern, the pre-fabricated semiconductor pattern, and the semiconductor pattern are columnar.

[0008] Optionally, the sidewalls of the preformed semiconductor pattern formed in step S5 are sloping walls.

[0009] Optionally, step S5 utilizes the anisotropy of the THAM process, which can increase the in-situ energy of the THAM pattern by up to 1.4 times.

[0010] A method for manufacturing a deep trench capacitor includes the following steps: after step S30, the method includes: S40: forming a conductive layer covering the trench and an upper electrode covering the conductive layer; S50: forming a lower electrode on the lower surface of a semiconductor substrate.

[0011] 8. The manufacturing method according to claim 7, wherein the upper electrode and the lower electrode are any one of aluminum, copper, tungsten, nickel, thallium, cobalt, titanium, silver, gold or silicon compounds or alloys thereof.

[0012] Optionally, step S25 is further included between steps S20 and S30: performing wet etching to form pits in the gaps between the photoresist patterns on the semiconductor substrate.

[0013] Optionally, before step S10, step S5 is further included: forming an array of pre-fabricated semiconductor patterns on the surface of a semiconductor substrate using dry etching, wherein the photoresist pattern is formed on the pre-fabricated semiconductor pattern in step S10.

[0014] Compared with the prior art, the technical solution of the present disclosure has the following beneficial effects: The present invention utilizes the shrinkage characteristics of photoresist after temperature curing to obtain a spherical defect (spherical defect / polygonal corresponding spherical defect / elliptical spherical defect) surface. By adjusting the etching rate ratio of PR and materials such as Si / SiO2 / SiC, the spherical defect surface is processed by dry etching technology to obtain an arc-shaped corner, which facilitates subsequent ALD and other processes and avoids sharp corners from affecting device performance.

[0015] The overall surface area is increased by adjusting the etching depth. The increase in surface area of ​​a spherical cap relative to the bottom circle (or polygon, etc.) of the cap is the increase in wafer surface area. The increase in surface area is proportional to the chord height / etch depth. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 is a flowchart of an etching method for forming a smooth three-dimensional surface of a semiconductor substrate according to an embodiment of the present invention; Figure 2 is a top view of an etching method for forming a smooth three-dimensional surface of a semiconductor substrate according to an embodiment of the present invention; Figures 3 to 5 are cross-sectional schematic diagrams of an etching method for forming a smooth three-dimensional surface of a semiconductor substrate according to an embodiment of the present invention; Figures 6 to 7 are cross-sectional schematic diagrams of an etching method for forming a smooth three-dimensional surface of a semiconductor substrate according to another embodiment of the present invention; Figures 8 to 10 are cross-sectional schematic diagrams of a method for manufacturing a deep trench capacitor according to an embodiment of the present invention; Figure 11 is a cross-sectional schematic diagram of a deep trench capacitor according to an embodiment of the present invention. Detailed Implementation

[0018] Preferred embodiments of the invention will now be described in more detail. While preferred embodiments of the invention are described below, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0019] In this invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower parts of the device in its normal operating state, while "inner" and "outer" refer to the parts relative to the outline of the device. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. Since this invention pertains to electrical devices, connection and interconnection both refer to conductive interconnections. Because the accompanying drawings describe the same device, the same reference numerals denote the same components.

[0020] As shown in Figure 1, this embodiment provides an etching method for forming a smooth three-dimensional surface of a semiconductor substrate, including the following steps: S10: uniformly coating a photoresist layer on a semiconductor substrate 110, and obtaining a uniformly arrayed photoresist pattern 120 by photolithography exposure through a mask.

[0021] Specifically, as shown in Figures 2 and 3, the semiconductor substrate 110 can be a silicon substrate, a silicon wafer on which semiconductor devices are formed, or a silicon wafer on which an insulating layer is formed. Before spin-coating the photoresist, the surface of the silicon substrate is cleaned with acetone, isopropanol, and water, and then a photoresist layer is uniformly coated. The photoresist layer can be coated using a spin-coating method. Then, exposure, development, and cleaning are performed using a mask. The photoresist can be sequentially subjected to ultraviolet lithography under a mask, followed by baking and development to form a cylindrical pattern with polygonal columnar shapes. Ultraviolet exposure is performed through a mask at an exposure dose of 200–2000 mJ / cm², followed by baking at a temperature of 90–120°C for a baking time of ≥60 s. After immersion in a developing solution, the photoresist in the exposed areas is removed, thus patterning the photoresist. As shown in Figure 3, a cylindrical or polygonal columnar pattern array can be obtained, which facilitates the formation of a near-hemispherical curved surface in the subsequent reflow process.

[0022] S20: High-temperature curing of the photoresist pattern array to make its upper surface curved.

[0023] As shown in Figure 4, a substrate with a photoresist pattern is heated to a specific temperature, causing the photoresist pattern to be uniformly distributed during thermal reflow. For example, using AZ40XT photoresist, the heating temperature is set to 140℃~180℃, and the heating time is 8 minutes, allowing the photoresist to reflow and form a curved photoresist pattern. The specific heating temperature and time can be adjusted according to the desired curvature of the photoresist pattern.

[0024] S30: Using a curved photoresist pattern 120 as a mask, dry etching is performed to form an array of semiconductor patterns 130 with curved upper surfaces on the surface of the semiconductor substrate 110, with trenches between the semiconductor patterns.

[0025] Specifically, as shown in Figure 5, reactive ion etching (RIE) is used with the patterned and thermally reflowed photoresist pattern as a mask to transfer the pattern onto the semiconductor substrate, forming a semiconductor pattern. Preferably, the etching process achieves a 1:1 etching rate between the photoresist pattern and the underlying semiconductor substrate. When the photoresist is completely etched away, the photoresist microlens pattern is successfully transferred onto the semiconductor substrate. Specifically, inductively coupled reactive ion (ICP) etching can be used, with the reactive etching gas flow rate and type being 50 sccm of CF4 and 10 sccm of Ar, an ICP power of 2000 W, an HF power of 250 W, and an etching chamber pressure of 30 mtorr.

[0026] Because the photoresist pattern has a curved or hemispherical surface, the edges of the etched trenches are relatively smooth.

[0027] In another embodiment, as shown in Figures 6 and 7, step S25 is included between steps S20 and S30: wet etching is performed to form pits 140 in the gaps between the photoresist patterns 120 on the semiconductor substrate 110. Since wet etching is isotropic etching, pits 140 are formed in the semiconductor substrate at the gaps between the photoresist patterns 120, thereby further increasing the thickness of the mask for dry etching in step S30. In other words, the photoresist pattern retained in wet etching and the semiconductor substrate below the photoresist pattern constitute the mask in dry etching, thereby further deepening the depth of the dry etching trench.

[0028] In another embodiment, as shown in Figures 8-10, step S5 is included before step S10: forming an array of pre-fabricated semiconductor patterns 150 on the surface of the semiconductor substrate 110 using dry etching, wherein the photoresist pattern is formed on the pre-fabricated semiconductor pattern 150 in step S10. The photoresist pattern 120, the pre-fabricated semiconductor pattern 150, and the semiconductor pattern are columnar. The sidewalls of the pre-fabricated semiconductor pattern 150 formed in step S5 are sloping walls. Step S5 utilizes the anisotropy of the THAM process, which can increase the size of the THAM pattern in situ by up to 1.4 times. Specifically, a photoresist mask can be formed first, and anisotropic etching can be performed under the photoresist mask. The preferred THAM process in this application forms a sloping etching, that is, the size of the opening gradually decreases, so that the size of the THAM pattern in situ increases by 1.4 times, that is, the size of the semiconductor pattern at the bottom of the photoresist mask pattern is 1.4 times that of the photoresist mask pattern. This further increases the thickness of the mask used in the dry etching process in step S30. In other words, the pre-fabricated semiconductor pattern and the photoresist pattern on it together constitute the mask in the dry etching process, thus allowing for a deeper dry etching trench. Due to its tilt angle, it can mitigate the sharp corners at the trench boundaries during the subsequent dry etching of deeper trenches, resulting in a smooth, three-dimensional surface.

[0029] In other embodiments, a photoresist pattern forming two photoresist layers can be used, for example, the bottom layer is not subjected to high-temperature shrinkage, and then another photoresist layer is formed on the first photoresist pattern, and then high-temperature shrinkage is performed, so that the top photoresist pattern has a curved surface.

[0030] This application also provides a method for manufacturing a deep trench capacitor, which includes, after step S30: S40: forming a conductive layer covering the trench and an upper electrode covering the conductive layer.

[0031] Specifically, the photoresist pattern can be removed by cleaning, and a metal layer can be formed on the sidewalls and bottom of the trench using chemical vapor deposition or physical vapor deposition. The metal layer can be continuous, covering the semiconductor substrate between the trenches, or it can be broken in certain parts as needed. It serves as one of the electrodes of a capacitor. For example, a dielectric layer 160 silicon oxide is deposited on the surface of the deep trench and the semiconductor substrate outside the deep trench using thermal oxidation, with a dielectric layer thickness of 1μm; a conductive layer polysilicon 170 is filled in the tapered deep trench and on the surface of the semiconductor substrate outside the deep trench using thermal oxidation filling; a layer of metallic gold 180 is deposited on the surface of the conductive polysilicon layer as the upper electrode, with a metal layer thickness of 5μm; and a passivation layer silicon oxide is deposited at both ends of the metal layer using LPCVD.

[0032] S50: A lower electrode is formed on the lower surface of the semiconductor substrate.

[0033] Specifically, a layer of metallic nickel is deposited on the bottom of a semiconductor substrate, such as a silicon substrate, as the lower electrode 190, with a metal layer thickness of 1.5 μm.

[0034] The upper and lower electrodes can be any one of aluminum, copper, tungsten, nickel, thallium, cobalt, titanium, silver, gold, or silicon compounds or their alloys.

[0035] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An etching method for forming a smooth three-dimensional surface of a semiconductor substrate, characterized in that, The process includes the following steps: S10: uniformly coating a photoresist layer on a semiconductor substrate and obtaining a uniformly distributed photoresist pattern through photolithography exposure using a mask; S20: curing the photoresist pattern array at high temperature to make its upper surface curved; S30: using the curved photoresist pattern as a mask for dry etching to form a semiconductor pattern with a curved upper surface distributed in an array on the surface of the semiconductor substrate, with trenches between the semiconductor patterns.

2. The etching method according to claim 1, characterized in that, Between steps S20 and S30, step S25 is also included: performing wet etching to form pits in the gaps between the photoresist patterns on the semiconductor substrate.

3. The etching method according to claim 1, characterized in that, Before step S10, there is also step S5: forming an array of pre-fabricated semiconductor patterns on the surface of a semiconductor substrate using dry etching, wherein the photoresist pattern is formed on the pre-fabricated semiconductor pattern in step S10.

4. The etching method according to claim 3, characterized in that, The photoresist pattern, pre-fabricated semiconductor pattern, and semiconductor pattern are columnar.

5. The method for forming a capacitor according to claim 3, characterized in that, The sidewalls of the preformed semiconductor pattern formed in step S5 are sloping walls.

6. The etching method according to claim 3, characterized in that, Step S5 utilizes the anisotropy of the THAM process, which can increase the in-situ energy of the THAM pattern by up to 1.4 times.

7. A method for manufacturing a deep trench capacitor using the etching method of any one of claims 1 to 6, characterized in that, The steps include: after step S30, S40: forming a conductive layer covering the trench and an upper electrode covering the conductive layer; S50: forming a lower electrode on the lower surface of the semiconductor substrate.

8. The manufacturing method as described in claim 7, characterized in that, The upper and lower electrodes are any one of aluminum, copper, tungsten, nickel, thallium, cobalt, titanium, silver, gold, or silicon compounds or their alloys.

9. The manufacturing method according to claim 7, characterized in that, Between steps S20 and S30, step S25 is also included: performing wet etching to form pits in the gaps between the photoresist patterns on the semiconductor substrate.

10. The manufacturing method according to claim 7, characterized in that, Before step S10, there is also step S5: forming an array of pre-fabricated semiconductor patterns on the surface of a semiconductor substrate using dry etching, wherein the photoresist pattern is formed on the pre-fabricated semiconductor pattern in step S10.

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