Novel high-power-density NPN device structure
By employing segmented ion implantation and ZP implantation in the NPN device structure to form a high current density path, the problem of insufficient current density in traditional NPN devices is solved, achieving high power density and excellent ESD protection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JIEFANG SEMICON (SHANGHAI) CO LTD
- Filing Date
- 2024-10-28
- Publication Date
- 2026-05-01
AI Technical Summary
Traditional NPN device structures exhibit poor current density characteristics and cannot effectively protect integrated circuits from ESD damage.
By employing segmented first conductivity type ion implantation and ZP implantation, segmented N+ buried layer regions, segmented ZP buried layer regions, and segmented ZP well regions are formed in the NPN device structure, creating a high current density current path and enhancing the device's current characteristics and area performance efficiency.
It improves the power density of devices, enhances ESD protection capabilities, improves the ESD resistance of integrated circuits, and extends the lifespan of devices and systems.
Smart Images
Figure CN121968606A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, and in particular to a novel high-power-density NPN device structure. Background Technology
[0002] ESD, or electrostatic discharge, is an ancient natural phenomenon. ESD exists in every corner of daily life. However, this seemingly commonplace electrical phenomenon poses a fatal threat to delicate integrated circuits. Electrical surges / transient voltages refer to sudden, random, and abnormally high voltages or currents exceeding normal conditions in a circuit. They are characterized by their short duration and extremely high instantaneous energy. Electrical surges are highly destructive to electronic components and integrated circuits. At best, they induce malfunctions in logic circuits; at worst, they cause secondary breakdowns of transistors, latch-up effects in Complementary Metal Oxide Semiconductors (CMOS), and other severe thermal effects that lead to device or integrated circuit failure. Electrical surges typically have two random sources: the first is instability in the power grid, such as sudden switching on / off, sudden starting of capacitive or inductive loads, hot-plugging of related equipment, and unstable operation of related power supplies. The second is sudden external interference, such as lightning or electrostatic discharge.
[0003] With advancements in integrated circuit manufacturing processes, the minimum linewidth has decreased to the submicron or even nanometer level. While this has led to improved chip performance, it has also significantly reduced the chip's resistance to ESD (Electrostatic Discharge), making electrostatic damage more severe. Most ESD incidents cause non-fatal damage to integrated circuits, reducing their lifespan and reliability, and ultimately leading to system functional degradation. This poses a significant obstacle to achieving large-scale, highly reliable integration.
[0004] TVS devices are important semiconductor protection devices. When turned on, they have extremely low resistance and can absorb transient pulse power up to several kilowatts, clamping the voltage at the port to a relatively safe preset value. This protects the corresponding circuit from damage or even irreversible damage caused by transient voltage pulses or current surges. TVS devices are characterized by fast response, low leakage current, high transient power, and small size. They are currently widely used in overvoltage protection in various fields such as electromechanical systems, power supply equipment, electromagnetic interference suppression, input / output interfaces, communication equipment, and relays, making them excellent ESD devices. However, as... Figure 1 The current density characteristics of the traditional NPN device structure shown are poor.
[0005] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0006] The purpose of this invention is to provide a novel high-power-density NPN device structure to solve the problem of poor current density characteristics in traditional NPN device structures.
[0007] To address the aforementioned technical problems, this invention provides a novel high-power-density NPN device structure, comprising a first conductivity type substrate and at least two ZP buried layers. The ZP buried layers are disposed at a predetermined depth in the first conductivity type substrate, and a first conductivity type buried layer is disposed between the ZP buried layers. A ZP well region is disposed on top of the ZP buried layers, and the ZP well regions are separated by first conductivity type ion regions. Two first conductivity type regions are arranged at intervals on top of the ZP well regions.
[0008] Preferably, the first conductivity type substrate is an N-type substrate, the first conductivity type buried layer is an N-type buried layer, the first conductivity type ion region is an N-type ion region, and the NPN device structure includes a first ZP buried layer, a second ZP buried layer, and a third ZP buried layer arranged sequentially from left to right in the N-type substrate.
[0009] Preferably, a first ZP well region is provided on the top of the first ZP buried layer, and a first N-type region and a second N-type region are arranged sequentially from left to right in the first ZP well region.
[0010] Preferably, a second ZP well region is provided on the top of the second ZP buried layer, and a third N-type region and a fourth N-type region are arranged sequentially from left to right in the second ZP well region.
[0011] Preferably, an N-type ion region is provided between the first ZP well region and the second ZP well region, and a first N-type buried layer is provided between the first ZP buried layer and the second ZP buried layer.
[0012] Preferably, a third ZP trap region is provided on the top of the third ZP buried layer, and a fifth N-type region and a sixth N-type region are arranged sequentially from left to right in the third ZP trap region.
[0013] Preferably, an N-type ion region is provided between the second ZP well region and the third ZP well region, and a second N-type buried layer is provided between the second ZP buried layer and the third ZP buried layer.
[0014] Preferably, the first N-type region is led out through a wire and serves as the anode of the NPN device structure, the second N-type region and the third N-type region are interconnected through a wire, the fourth N-type region and the fifth N-type region are connected to each other through a wire, and the sixth N-type region is led out through a wire and serves as the cathode of the NPN device structure.
[0015] Preferably, the N-type ion region is an N-type epitaxial layer formed on top of the N-type substrate.
[0016] Preferably, the ZP buried layer longitudinally spans the boundary between the N-type substrate and the N-type epitaxial layer and covers the lower edge of the corresponding ZP well region.
[0017] In the novel high-power-density NPN device structure provided by this invention, segmented first-conductivity-type ion implantation and ZP implantation are performed on a first-conductivity-type substrate to form a segmented first-conductivity-type buried layer region and a segmented ZP buried layer region. Then, segmented ZP implantation is performed in the first-conductivity-type ion region to form a segmented ZP well region. This forms a current path with high current density within the NPN device, thereby improving the overall power density of the device and achieving excellent current characteristics and area performance efficiency. Attached Figure Description
[0018] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:
[0019] Figure 1 This is a schematic diagram of a traditional NPN device structure;
[0020] Figure 2 This is a schematic diagram of a novel high-power-density NPN device structure proposed in an embodiment of the present invention;
[0021] Figure 3 This is a schematic diagram illustrating the working principle of a novel high-power-density NPN device structure proposed in an embodiment of the present invention.
[0022] In the attached image:
[0023] 111. N-type substrate; 121. First ZP buried layer; 122. Second ZP buried layer; 123. Third ZP buried layer; 131. First N-type buried layer; 132. Second N-type buried layer; 141. N-type epitaxial layer; 151. First ZP well region; 152. Second ZP well region; 153. Third ZP well region; 161. First N-type region; 162. Second N-type region; 163. Third N-type region; 164. Fourth N-type region; 165. Fifth N-type region; 166. Sixth N-type region. Detailed Implementation
[0024] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.
[0025] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; the term “at least two” is generally used to mean “two or more”; furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first," "second," and "third" may explicitly or implicitly include one or at least two of those features. The term "proximal" typically refers to the end closer to the operator, and the term "distal" typically refers to the end closer to the patient. "One end" and "the other end," as well as "proximal" and "distal," generally refer to two corresponding parts, including not only endpoints. The terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements or interactions between two elements. Furthermore, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of another element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0026] The inventors discovered that the current density characteristics of traditional NPN device structures are poor.
[0027] Based on this, the core idea of this invention is to improve the traditional NPN device structure to achieve excellent current density characteristics and excellent area performance efficiency.
[0028] For details, please refer to Figures 2-3 This is a schematic diagram of an embodiment of the present invention. Figure 2As shown, a novel high power density NPN device structure includes a first conductivity type substrate and at least two ZP buried layers. The ZP buried layers are disposed at a predetermined depth in the first conductivity type substrate. A first conductivity type buried layer is disposed between the ZP buried layers. A ZP well region is disposed on top of the ZP buried layers. The ZP well regions are separated by first conductivity type ion regions. Two first conductivity type regions are arranged at intervals on top of the ZP well regions.
[0029] Compared to traditional NPN structures, this structure employs buried layer epitaxy, performing segmented first conductivity type ion implantation and ZP implantation on a first conductivity type substrate to form segmented first conductivity type buried layer regions and segmented ZP buried layer regions. Subsequently, segmented ZP implantation is performed in the first conductivity type ion region to form segmented ZP well regions. This creates a high current density current path within the NPN device, improving the overall power density of the device and achieving excellent current characteristics and area performance efficiency.
[0030] In one embodiment, the first conductivity type substrate is an N-type substrate 111, the first conductivity type buried layer is an N-type buried layer, and the first conductivity type ion region is an N-type ion region. The NPN device structure includes a first ZP buried layer 121, a second ZP buried layer 122, and a third ZP buried layer 123 arranged sequentially from left to right in the N-type substrate 111. A first ZP well region 151 is disposed on the top of the first ZP buried layer 121, and a first N-type region 161 and a second N-type region 162 are arranged sequentially from left to right within the first ZP well region 151. A second ZP well region 152 is disposed on the top of the second ZP buried layer 122, and a third N-type region 163 and a fourth N-type region 164 are arranged sequentially from left to right within the second ZP well region 152.
[0031] Specifically, an N-type ion region is provided between the first ZP well region 151 and the second ZP well region 152, and a first N-type buried layer 131 is provided between the first ZP buried layer 121 and the second ZP buried layer 122.
[0032] Specifically, a third ZP well region 153 is provided on the top of the third ZP buried layer 123, and a fifth N-type region 165 and a sixth N-type region 166 are arranged sequentially from left to right within the third ZP well region 153. An N-type ion region is provided between the second ZP well region 152 and the third ZP well region 153, and a second N-type buried layer 132 is provided between the second ZP buried layer 122 and the third ZP buried layer 123.
[0033] The first ZP buried layer region 121, the second ZP buried layer region 122, and the third ZP buried layer region 123 are arranged sequentially from left to right, with each pair separated by the same distance, the size of which is the width of the N-type buried layer region. The width of the first ZP buried layer region 121, the second ZP buried layer region 122, and the third ZP buried layer region 123 is the same as the width of the corresponding ZP well region, and the left and right edges of the three regions are tangent to the left and right edges of the corresponding ZP well regions, respectively.
[0034] Specifically, the first N-type region 161, the second N-type region 162, the third N-type region 163, the fourth N-type region 164, the fifth N-type region 165, and the sixth N-type region 166 are located inside the first ZP well region 151, the second ZP well region 152, and the third ZP well region 153, respectively. Their upper edges are tangent to the upper edges of the ZP well regions, and their lower edges are slightly higher than the lower edges of the ZP well regions. There are slight intervals between the first N-type region 161, the second N-type region 162, the third N-type region 163, the fourth N-type region 164, the fifth N-type region 165, and the sixth N-type region 166.
[0035] The first N-type region 161 is led out through a wire and serves as the anode of the NPN device structure; the second N-type region 162 and the third N-type region 163 are interconnected through a wire; the fourth N-type region 164 and the fifth N-type region 165 are connected to each other through a wire; and the sixth N-type region 166 is led out through a wire and serves as the cathode of the NPN device structure.
[0036] For example, the N-type ion region is an N-type epitaxial layer 141 formed on top of the N-type substrate 111. The N-type epitaxial layer 141 is located on the upper part of the N-type substrate 111, with its upper edge higher than the upper edge of the N-type substrate 111 and its lower edge tangent to the lower edge of the N-type substrate 111.
[0037] like Figure 2 As shown, the first ZP well region 151, the second ZP well region 152, and the third ZP well region 153 are located inside the N-type epitaxial layer 141, arranged sequentially from left to right, with each pair separated by the same distance equal to the width of the first N-type buried layer 131 and the second N-type buried layer 132. The upper edges of the first ZP well region 151, the second ZP well region 152, and the third ZP well region 153 are tangent to the upper edge of the N-type epitaxial layer 141, and their lower edges are slightly higher than the lower edge of the N-type epitaxial layer 141.
[0038] In one embodiment, the ZP buried layer longitudinally spans the boundary between the N-type substrate 111 and the N-type epitaxial layer 141 and covers the lower edge of the corresponding ZP well region.
[0039] Correspondingly, the first ZP buried layer region 121, the second ZP buried layer region 122, and the third ZP buried layer region 123 are located between the N-type epitaxial layer 141 and the N-type substrate 111, longitudinally spanning the boundary between them and covering the lower edge of the corresponding ZP well region. The first N-type buried layer region 131 and the second N-type buried layer region 132 are located between the N-type epitaxial layer 141 and the N-type substrate 111, longitudinally spanning the boundary between them. The first N-type buried layer region 131 is to the left of the second N-type buried layer region 132, and the two are located sequentially between the first ZP buried layer region 121, the second ZP buried layer region 122, and the third ZP buried layer region 123. The left edge of the first N-type buried layer region 131 is tangent to the right edge of the first ZP buried layer region 121, and the right edge is tangent to the left edge of the second ZP buried layer region 122. The left edge of the second N-type buried layer region 132 is tangent to the right edge of the second ZP buried layer region 122, and the right edge is tangent to the left edge of the third ZP buried layer region 123.
[0040] Compared to traditional NPN device structures, the novel high-power-density NPN device structure proposed in this invention features a segmented N+ buried layer region, a segmented ZP buried layer region, and a segmented ZP well region. For example... Figure 3 The diagram illustrates the working principle of this novel high-power-density NPN device structure. When an ESD event occurs, the device rapidly initiates current discharge. In addition to the series conductive path (surface path) within the NPN device itself, a second conductive path (body path) is formed by the parasitic NPN within the device, consisting of a segmented N+ buried layer region, a segmented ZP buried layer region, and a segmented ZP well region. Due to the depth of the ZP well region, the junction area of the body parasitic NPN is very large, resulting in a large current discharge through the body path. This creates a high-current-density region within the device. Consequently, the overall current density of the device is significantly increased, thereby enhancing the overall power density.
[0041] The device structure and accompanying drawings presented in this invention are merely a demonstration and illustration of a novel high-power-density NPN device. Apart from the structure shown in the drawings, any person skilled in the art may modify or change the above structure without departing from the spirit and scope of this invention. For example, the NPN structure described above may be changed to a PNP structure, SCR structure, diode structure, MOS structure, etc., or the number of stacked series connections or the form of stacked packaging may be changed according to different application scenarios. These structures should obviously be within the protection scope of this invention.
[0042] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.
Claims
1. A novel high-power-density NPN device structure, characterized in that, It includes a first conductivity type substrate and at least two ZP buried layers, the ZP buried layers are disposed at a predetermined depth in the first conductivity type substrate, the first conductivity type buried layers are disposed between the ZP buried layers, the top of the ZP buried layers is provided with ZP well regions, the ZP well regions are separated by first conductivity type ion regions, and two first conductivity type regions are arranged at intervals on the top of the ZP well regions.
2. The novel high-power-density NPN device structure according to claim 1, characterized in that, The first conductivity type substrate is an N-type substrate, the first conductivity type buried layer is an N-type buried layer, the first conductivity type ion region is an N-type ion region, and the NPN device structure includes a first ZP buried layer, a second ZP buried layer, and a third ZP buried layer arranged from left to right in the N-type substrate.
3. The novel high-power-density NPN device structure according to claim 2, characterized in that, The top of the first ZP buried layer is provided with a first ZP well region, and the first N-type region and the second N-type region are arranged sequentially from left to right in the first ZP well region.
4. The novel high-power-density NPN device structure according to claim 2, characterized in that, The top of the second ZP buried layer is provided with a second ZP well region, and the second ZP well region is arranged from left to right with a third N-type region and a fourth N-type region.
5. The novel high-power-density NPN device structure according to claim 3 or 4, characterized in that, An N-type ion region is provided between the first ZP well region and the second ZP well region, and a first N-type buried layer is provided between the first ZP buried layer and the second ZP buried layer.
6. The novel high-power-density NPN device structure according to claim 2, characterized in that, The top of the third ZP buried layer is provided with a third ZP well region, and the fifth N-type region and the sixth N-type region are arranged sequentially from left to right in the third ZP well region.
7. The novel high-power-density NPN device structure according to claim 4 or 6, characterized in that, An N-type ion region is provided between the second ZP well region and the third ZP well region, and a second N-type buried layer is provided between the second ZP buried layer and the third ZP buried layer.
8. The novel high-power-density NPN device structure according to claim 3, 4, or 6, characterized in that, The first N-type region is led out through a wire and serves as the anode of the NPN device structure. The second N-type region and the third N-type region are interconnected through a wire. The fourth N-type region and the fifth N-type region are connected to each other through a wire. The sixth N-type region is led out through a wire and serves as the cathode of the NPN device structure.
9. The novel high-power-density NPN device structure according to claim 2, characterized in that, The N-type ion region is an N-type epitaxial layer formed on top of the N-type substrate.
10. The novel high-power-density NPN device structure according to claim 9, characterized in that, The ZP buried layer longitudinally spans the boundary between the N-type substrate and the N-type epitaxial layer and covers the lower edge of the corresponding ZP well region.