Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, and belongs to the technical field of power semiconductors, and the semiconductor device comprises a semiconductor substrate of a first conduction type, in which a multi-type gate structure is formed, and the semiconductor substrate comprises at least one first gate structure for a gate and at least one second gate structure for a virtual gate; and the first floating region of the first conduction type is located between the first gate structure and the second gate structure, and the doping concentration close to the first gate structure is larger than that close to the second gate structure. The beneficial effects are that by arranging the first floating region of the first conductive type, the hole accumulation effect is weakened, and displacement current is reduced; meanwhile, the doping concentration difference is utilized, so that the hole is far away from the capacitance between the first floating region and the first gate structure, the charging process is reduced, the displacement current is reduced, and the control of the gate structure on EMI and opening loss is enhanced; moreover, saturation current can be reduced, short-circuit capability can be improved, Miller capacitance of the device can be reduced, and switching loss can be reduced.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] Insulated-gate bipolar transistors (IGBTs) power devices, with their advantages of high input impedance and low on-state voltage drop, have become one of the core components in modern power electronic circuits, widely used in transportation, energy, industry, home appliances, and many other fields. However, with the continuous expansion of the application range of IGBT devices and the continuous improvement of their performance requirements, current IGBT device design faces the significant challenge of balancing electromagnetic interference (EMI) and turn-on losses.

[0003] In existing technologies, such as Figure 1 The conventional IGBT semiconductor device shown has the problem of high on-state voltage drop and insufficient withstand voltage. To improve the short-circuit withstand capability of the device, the channel density is usually reduced, thus a floating p-base region is incorporated. Figure 2 In the IGBT semiconductor device with a floating P-type region shown, the P-type region 20' collects a large number of holes, causing its potential to rise. This results in a large displacement current between the floating P-type region 20' and the gate structure 30', making the gate structure uncontrollable by the externally applied voltage and further worsening the relationship between EMI and turn-on losses. Furthermore, the device has a high current density and weak short-circuit capability; simultaneously, the device has a large Miller capacitance, increasing switching losses. Summary of the Invention

[0004] To address the above technical problems, this invention provides a semiconductor device; furthermore, it also provides a method for fabricating the semiconductor device. By distancing holes away from the capacitance between the floating region and the gate structure, the charging process is reduced, thereby reducing the displacement current and enhancing the gate structure's control over electromagnetic interference (EMI) and turn-on losses.

[0005] The technical problem solved by this invention can be achieved by the following technical solutions:

[0006] A semiconductor device, comprising:

[0007] Semiconductor substrate of the first conductivity type;

[0008] Multiple types of gate structures are formed in the semiconductor substrate, the gate structure including at least one first gate structure and at least one second gate structure, the first gate structure being used as a gate of the semiconductor device, and the second gate structure being used as a dummy gate of the semiconductor device;

[0009] A first floating region of a first conductivity type is formed in a semiconductor substrate and located between the first gate structure and the second gate structure; within the first floating region, the doping concentration near the first gate structure is greater than the doping concentration near the second gate structure.

[0010] Preferably, it further includes:

[0011] A second floating region, having a second conductivity type opposite to the first conductivity type, is formed in a semiconductor substrate and located between two adjacent second gate structures.

[0012] Preferably, within the second floating region, the doping concentration near the second gate structure is less than the doping concentration away from the second gate structure.

[0013] Preferably, the doping concentration of the first floating region is higher than the doping concentration of the semiconductor substrate.

[0014] Preferably, the doping concentration of the second floating region is higher than the doping concentration of the semiconductor substrate.

[0015] Preferably, the connection between the first floating region and the semiconductor substrate has a connection surface, which is an arc surface extending toward the surface of the semiconductor substrate.

[0016] Preferably, it further includes:

[0017] An insulating dielectric layer is formed on the upper surface of the semiconductor substrate;

[0018] A first metal layer is formed on the upper surface of the insulating dielectric layer.

[0019] Preferably, it further includes:

[0020] A base region is formed in the semiconductor substrate and is located on the side of the first gate structure away from the floating region, and the base region has the second conductivity type;

[0021] An emitter region is formed in the base region and is in contact with the sidewall of the first gate structure, the emitter region having the first conductivity type;

[0022] The base region and the emitter region are in ohmic contact with the first metal layer.

[0023] Preferably, it further includes:

[0024] A buffer layer is formed on the lower surface of the semiconductor substrate, the buffer layer having the first conductivity type;

[0025] A collector layer is formed on the lower surface of the buffer layer, and the collector layer has the second conductivity type;

[0026] A second metal layer is formed on the lower surface of the collector layer, and the second metal layer is in ohmic contact with the collector layer.

[0027] On the other hand, a method for fabricating a semiconductor device is also provided, for fabricating the semiconductor device as described above, comprising:

[0028] Provide a semiconductor substrate of a first conductivity type;

[0029] Multiple types of gate structures are formed in the semiconductor substrate, the gate structures including at least one first gate structure and at least one second gate structure, the first gate structure being used as a gate of the semiconductor device, and the second gate structure being used as a dummy gate of the semiconductor device;

[0030] A floating region of a first conductivity type is formed between the first gate structure and the second gate structure. Within the first floating region, the doping concentration near the first gate structure is greater than the doping concentration near the second gate structure.

[0031] The advantages or beneficial effects of the technical solution of this invention are as follows:

[0032] This invention weakens the hole accumulation effect and reduces displacement current by setting a first floating region of a first conductivity type. At the same time, the doping concentration near the first gate structure is greater than that near the second gate structure, thereby concentrating the holes in the first floating region near the second gate, making the holes away from the capacitance between the first floating region and the first gate structure, thus reducing the charging process, thereby reducing displacement current and enhancing the gate structure's control over EMI and turn-on losses. Moreover, it can reduce saturation current, improve short-circuit capability, and reduce Miller capacitance of the device, thereby reducing switching losses. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the structure of a conventional IGBT semiconductor device in the prior art 1;

[0034] Figure 2 This is a schematic diagram of the structure of an IGBT semiconductor device with a floating P-type region in the prior art 2;

[0035] Figure 3 This is a schematic diagram of the semiconductor device structure in a preferred embodiment 1 of the present invention;

[0036] Figure 4 In a preferred embodiment of the present invention, a lateral doping concentration distribution diagram of a semiconductor device is shown; in the diagram, abs netdoping represents the net doping concentration.

[0037] Figure 5 In a preferred embodiment of the present invention, a lateral band structure diagram of a semiconductor device is shown; in the diagram, EC represents the conduction band bottom, EF represents the Fermi level, and EV represents the valence band top.

[0038] Figure 6 A preferred embodiment of the present invention shows the vertical doping concentration distribution of the semiconductor device;

[0039] Figure 7 A longitudinal band structure diagram of a semiconductor device, as shown in a preferred embodiment of the present invention;

[0040] Figure 8 This is a schematic flowchart of a semiconductor device fabrication method in a preferred embodiment of the present invention.

[0041] Figure 9-15 This is a schematic diagram of the structure of each step in the semiconductor device fabrication method in a preferred embodiment of the present invention;

[0042] Figure 16 This is a schematic diagram of the structure of the semiconductor device in a preferred embodiment 2 of the present invention.

[0043] Explanation of reference numerals in the attached figures:

[0044] 10. Semiconductor substrate; 11. Buffer layer; 12. Collector layer; 20. First gate structure; 21. First gate oxide layer; 22. First polygate; 200. Second gate structure; 210. Second gate oxide layer; 220. Second polygate; 30. First floating region; 300. Second floating region; 40. Insulating dielectric layer; 50. First metal layer; 60. Base region; 70. Emitter region; 80. Second metal layer. Detailed Implementation

[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0046] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0047] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0048] Example 1

[0049] In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a semiconductor device is now provided, such as... Figure 3 As shown, it includes:

[0050] Semiconductor substrate 10 of the first conductivity type;

[0051] Multiple types of gate structures are formed in a semiconductor substrate, and the gate structure includes at least one first gate structure 20 for serving as a device gate and at least one second gate structure 200 for serving as a device dummy gate.

[0052] A first floating region 30 of a first conductivity type is formed in a semiconductor substrate 10 and is located between a first gate structure 20 and a second gate structure 200; within the first floating region 30, the doping concentration near the first gate structure 20 is greater than the doping concentration near the second gate structure 200.

[0053] Furthermore, the first gate structure 20 can be used to form the gate G of a semiconductor device. The first gate structure 20 is a trench gate structure, including a first gate oxide layer 21 and a first polygate 22. The first polygate 22 is located within the first gate oxide layer 21, and the gate G is connected to the first polygate 22.

[0054] Furthermore, the second gate structure 200 can be used to form a dummy gate of a semiconductor device and connected to the emitter E. The second gate structure 200 is a trench gate structure, including a second gate oxide layer 210 and a second polygate 220. The second polygate 220 is located within the second gate oxide layer 210, and the dummy gate is connected to the second polygate 220.

[0055] In some embodiments, the first conductivity type can be N-type and the second conductivity type can be P-type. In other embodiments, the first conductivity type can be P-type and the second conductivity type can be N-type. This invention will be described using an example where the first conductivity type is N-type and the second conductivity type is P-type.

[0056] Furthermore, the semiconductor substrate 10 of the first conductivity type is used to form the drift layer. The semiconductor substrate 10 of the first conductivity type can be a single semiconductor material substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.; it can also be a composite semiconductor material substrate, which is composed of two or more elements, such as a germanium silicon (SiGe) substrate, a silicon carbide (SiC) substrate, etc.; or it can be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0057] In the semiconductor device of the present invention, the doping concentration of the first floating region 30 is higher than that of the semiconductor substrate 10.

[0058] Specifically, within the first floating region 30, the doping concentration near the first gate structure 20 is greater than the doping concentration near the second gate structure 200, and is also greater than the doping concentration of the semiconductor substrate 10.

[0059] In this embodiment, the first floating region 30 can be an N+ type or an N type floating region, and the doping concentration range of the first floating region 30 is 1×10¹⁵ cm⁻³ to 1×10¹⁸ cm⁻³.

[0060] For example Figure 3 Taking the first floating region 30 as an example, when the majority carriers in the first floating region 30 are holes, such as Figure 4 and Figure 5 As shown, in the lateral direction, since the doping concentration near the first gate structure 20 is greater than the doping concentration near the second gate structure 200, therefore, as Figure 5 As shown, the distance between the Fermi level EF near the first gate structure 20 and the conduction band bottom EC is smaller than the distance between the Fermi level EF near the second gate structure 200 and the conduction band bottom EC.

[0061] The potential energy of holes near the valence band top EV of the first gate structure 20 is higher than that of holes near the valence band top EV of the second gate structure 200. Because of this potential energy difference between the holes near the valence band top EV of the first gate structure 20 and those near the valence band top EV of the second gate structure 200, this promotes the movement of holes near the first gate structure 20 towards the second gate structure 200, while simultaneously hindering the movement of holes near the second gate structure 200 towards the first gate structure 20. This, in turn, facilitates the accumulation of holes near the second gate structure 200.

[0062] like Figure 6 and Figure 7 As shown, in the vertical direction, since the doping concentration of the first floating region 30 is greater than that of the semiconductor substrate 10, the distance between the Fermi level EF of the first floating region 30 and the conduction band bottom EC of the first floating region 30 is smaller than the distance between the Fermi level EF of the semiconductor substrate 10 and the conduction band bottom EC of the semiconductor substrate 10.

[0063] The potential energy of holes located near the top EV of the 0-valence band in the first floating region 30 is higher than that of holes near the top EV of the decimal band in the semiconductor substrate 10. Because of this potential energy difference between the holes near the top EV of the 0-valence band in the first floating region 30 and those near the top EV of the decimal band in the semiconductor substrate 10, this promotes the movement of more holes from the first floating region 30 towards the semiconductor substrate 10, while simultaneously hindering the movement of holes from the semiconductor substrate 10 towards the first floating region 30. This, in turn, facilitates the accumulation of holes below the first floating region 30.

[0064] In summary, the semiconductor device of the present invention reduces the hole accumulation effect and is located away from the capacitance between the first floating region 30 and the first gate structure 20, thereby reducing the charging process, reducing the displacement current, and enhancing the control of the first gate structure 20 over EMI and turn-on losses.

[0065] According to the semiconductor device of the present invention, by setting the doping concentration near the first gate structure 20 in the first floating region 30 to be greater than the doping concentration near the second gate structure 200, and both being greater than the doping concentration of the substrate, holes are concentrated near the second gate structure 200, thus moving the holes away from the capacitance between the first floating region 30 and the first gate structure 20. This reduces the charging process, thereby reducing the displacement current and enhancing the control of the first gate structure 20 over EMI and turn-on losses. The second gate structure reduces the current density of the device, lowers the saturation current, and improves the short-circuit capability; it also reduces the Miller capacitance of the device, thus reducing switching losses.

[0066] The semiconductor device of the present invention has a connection surface at the connection between the first floating region 30 and the semiconductor substrate 10, and the connection surface is an arc surface extending toward the upper surface of the semiconductor substrate 10.

[0067] The semiconductor device of the present invention, such as Figure 3 As shown, it also includes an insulating dielectric layer 40 and a first metal layer 50. The insulating dielectric layer 40 is formed on the first gate structure 20, the second gate structure 200 and the first floating region 30; the first metal layer 50 is formed on the insulating dielectric layer 40.

[0068] Specifically, the insulating dielectric layer 40 is used to achieve electrical isolation between the first metal layer 50 and the first gate structure 20, the second gate structure 200, and the first floating region 30. The first metal layer 50 can be used to form the emitter E of the semiconductor device.

[0069] The semiconductor device of the present invention further includes a base region 60 and an emitter region 70. The base region 60 is formed in a semiconductor substrate and is located on the side of the first gate structure 20 away from the first floating region 30. The base region 60 has a second conductivity type. The emitter region 70 is formed in the base region 60 and is in contact with the sidewall of the first gate structure 20. The emitter region 70 has a first conductivity type. Both the base region 60 and the emitter region 70 are in ohmic contact with the first metal layer 50.

[0070] Furthermore, the base region 60 can be a P-type base region, and the emitter region 70 can be an N+ type emitter region. An NPN structure is formed below the first metal layer 50 by the P-type base region 60, the N+ type emitter region 70, and the semiconductor substrate 10. The first gate structure 20 is used to provide current to the base region 60, thereby turning on the NPN structure so that the current can sequentially pass through the semiconductor substrate 10, the base region 60, and the emitter region 70 to reach the first metal layer 50.

[0071] The semiconductor device of the present invention further includes a buffer layer 11, a collector layer 12, and a second metal layer 80. The buffer layer 11 is formed on the lower surface of the semiconductor substrate 10 and has a first conductivity type. The collector layer 12 is formed on the lower surface of the buffer layer 11 and has a second conductivity type. The second metal layer 80 is formed on the lower surface of the collector layer 12 and is in ohmic contact with the collector layer 12.

[0072] Specifically, the second metal layer 80 can form the collector C of the semiconductor device. The collector layer 12, buffer layer 11, and base region 60 form a PNP structure above the second metal layer 80. The first gate structure 20 can provide current to the semiconductor substrate 10, thereby turning on the PNP structure so that current can flow from the second metal layer 80, and then sequentially pass through the collector layer 12, buffer layer 11, semiconductor substrate 10, base region 60, and emitter region 70 to reach the first metal layer 50.

[0073] Furthermore, the semiconductor device in this embodiment of the invention can be a field-stop IGBT device; in other embodiments, the semiconductor device can also be a through-type IGBT device, a non-through-type IGBT device, or a MOSFET device. The basic conduction principle of semiconductor devices is based on mature technologies, and will not be elaborated further in this embodiment.

[0074] This invention reduces hole accumulation by setting a first floating region 30 of a first conductivity type. Simultaneously, the doping concentration near the first gate structure 20 is greater than the doping concentration near the second gate structure 200, and both are greater than the substrate doping concentration. This concentrates holes in the first floating region 30 near the second gate 200, moving them away from the capacitance between the first floating region 30 and the first gate structure 20. This reduces the charging process, thereby reducing displacement current and enhancing the gate structure's control over EMI and turn-on losses. This invention reduces saturation current, improves short-circuit capability, and reduces Miller capacitance, thus lowering switching losses.

[0075] Example 2

[0076] This invention provides a method for fabricating a semiconductor device, used to fabricate the semiconductor device as described in Example 1 above, such as... Figure 8 As shown, it includes:

[0077] Step S100: Provide a semiconductor substrate 10 of a first conductivity type;

[0078] Step S200: As Figure 9 As shown, trench structures are formed on a semiconductor substrate through photomask and etching;

[0079] Step S300: As Figure 10 As shown, through a thermal process, silicon is oxidized to form an oxide layer, and then a polycrystalline silicon layer is deposited.

[0080] Step S400: As Figure 11 As shown, the base region is formed by implanting high-energy boron ions (B) and annealing at high temperature;

[0081] Step S500: As Figure 12 As shown, by injecting high-energy ions of arsenic (As) or phosphorus (P) and annealing at high temperature, an emission region and a floating region are formed.

[0082] Step S600: As Figure 13 As shown, an insulating dielectric layer is deposited, and then lead holes are formed by photolithography;

[0083] Step S700: As Figure 14 As shown, the front metal is deposited to complete the front process;

[0084] Step S800: As Figure 15 As shown, the back side is thinned, and a buffer layer and a collector layer are formed by ion implantation, respectively. Finally, the back side metal is deposited and alloyed. This completes the entire process.

[0085] Furthermore, the first gate structure 20 and the second gate structure 200 can be deposited on the semiconductor substrate 10 by plasma chemical vapor deposition (PCVD) process and then patterned using photolithography.

[0086] Furthermore, the semiconductor substrate 10 can be etched using photolithography to form a gate trench; then a first gate structure 20 and a second gate structure 200 can be deposited in the gate trench.

[0087] Furthermore, the first floating region 30 and the base region 60 can be formed simultaneously by injecting particles of a first conductivity type above the first floating region 30 and the base region 60. Through annealing, a doping concentration closer to the first gate can be formed in the first floating region 30 that is greater than the doping concentration closer to the second gate.

[0088] Example 3

[0089] The semiconductor device of the present invention, such as Figure 16 As shown, it also includes:

[0090] The second floating region 300, having a second conductivity type opposite to the first conductivity type, is formed in the semiconductor substrate 10 and is located between two adjacent second gate structures 200.

[0091] Specifically, in this embodiment, a first floating region 30 of a first conductivity type is formed between adjacent first gate structures 20 and second gate structures 200; and a second floating region 300 of a second conductivity type is formed between two adjacent second gate structures 200.

[0092] In the semiconductor device of the present invention, the doping concentration near the second gate structure 200 in the second floating region 300 is less than the doping concentration away from the second gate structure 200.

[0093] In the semiconductor device of the present invention, the doping concentration of the second floating region 300 is higher than that of the semiconductor substrate 10.

[0094] like Figure 16 As shown, in addition to the first gate structure 20 and the second gate structure 200 being spaced apart, multiple second gate structures 200 can also be provided. The floating region between two adjacent second gate structures 200 can be set to a second conductivity type, such as P-type, which serves as a storage layer for holes, enhancing the carrier injection effect of the device.

[0095] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor substrate of the first conductivity type; Multiple types of gate structures are formed in the semiconductor substrate, the gate structure including at least one first gate structure and at least one second gate structure, the first gate structure being used as a gate of the semiconductor device, and the second gate structure being used as a dummy gate of the semiconductor device; A first floating region of a first conductivity type is formed in a semiconductor substrate and located between the first gate structure and the second gate structure; within the first floating region, the doping concentration near the first gate structure is greater than the doping concentration near the second gate structure.

2. The semiconductor device according to claim 1, characterized in that, Also includes: A second floating region, having a second conductivity type opposite to the first conductivity type, is formed in a semiconductor substrate and located between two adjacent second gate structures.

3. The semiconductor device according to claim 2, characterized in that, Within the second floating region, the doping concentration near the second gate structure is lower than the doping concentration away from the second gate structure.

4. The semiconductor device according to claim 1, characterized in that, The doping concentration of the first floating region is higher than that of the semiconductor substrate.

5. The semiconductor device according to claim 1, characterized in that, The doping concentration of the second floating region is higher than that of the semiconductor substrate.

6. The semiconductor device according to claim 1, characterized in that, The connection between the first floating region and the semiconductor substrate has a connection surface, which is an arc surface extending toward the surface of the semiconductor substrate.

7. The semiconductor device according to claim 1 or 2, characterized in that, Also includes: An insulating dielectric layer is formed on the upper surface of the semiconductor substrate; A first metal layer is formed on the upper surface of the insulating dielectric layer.

8. The semiconductor device according to claim 7, characterized in that, Also includes: A base region is formed in the semiconductor substrate and is located on the side of the first gate structure away from the floating region, and the base region has the second conductivity type; An emitter region is formed in the base region and is in contact with the sidewall of the first gate structure, the emitter region having the first conductivity type; The base region and the emitter region are in ohmic contact with the first metal layer.

9. The semiconductor device according to claim 1 or 2, characterized in that, Also includes: A buffer layer is formed on the lower surface of the semiconductor substrate, the buffer layer having the first conductivity type; A collector layer is formed on the lower surface of the buffer layer, and the collector layer has the second conductivity type; A second metal layer is formed on the lower surface of the collector layer, and the second metal layer is in ohmic contact with the collector layer.

10. A method for fabricating a semiconductor device, characterized in that, For fabricating the semiconductor device as described in any one of claims 1-9, comprising: Provide a semiconductor substrate of a first conductivity type; Multiple types of gate structures are formed in the semiconductor substrate, the gate structures including at least one first gate structure and at least one second gate structure, the first gate structure being used as a gate of the semiconductor device, and the second gate structure being used as a dummy gate of the semiconductor device; A floating region of a first conductivity type is formed between the first gate structure and the second gate structure. Within the first floating region, the doping concentration near the first gate structure is greater than the doping concentration near the second gate structure.

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