Power field effect transistor and forming method thereof
By forming the hard mask layer and gate material layer in a single process, the problem of complex power MOSFET process flow is solved, and the process steps are simplified and production efficiency is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2026-01-27
- Publication Date
- 2026-05-01
AI Technical Summary
The existing power MOSFET process is complex, requiring multiple steps to form the hard mask layer and gate material layer, resulting in wasted equipment.
The hard mask layer and gate material layer are formed in one process, and the target thickness is achieved in one step, which simplifies the process flow and reduces equipment waste.
It reduces process steps, improves production efficiency, and reduces machine waste.
Smart Images
Figure CN121968618A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a power field-effect transistor and a method for forming the same. Background Technology
[0002] A power MOSFET is a voltage-controlled semiconductor device primarily used for power amplification and switching applications. Power MOSFETs are a type of metal-oxide-semiconductor field-effect transistor, characterized by simple drive circuitry, fast switching speed, and high operating frequency.
[0003] The existing process flow for power MOSFETs involves growing the gate material layer in two steps. First, a first hard mask layer is formed, followed by a field oxide layer. After forming the field oxide layer, the first hard mask layer is removed. Then, the first gate material layer and the second hard mask layer are formed, followed by the formation of a JFET structure. Next, an isolation layer is formed on the JFET structure, the second hard mask layer is removed, and then the second gate material layer is formed. Both the hard mask layer and the gate material layer require two separate process steps to form, and both the first and second hard mask layers need to be removed, meaning there are two steps required to remove the hard mask layer. This makes the process flow for power MOSFETs complex and results in wasted equipment. Summary of the Invention
[0004] The purpose of this invention is to provide a power field-effect transistor and a method for forming the same, so as to solve the problem of complex process flow of power field-effect transistors.
[0005] To solve the above-mentioned technical problems, the present invention provides a method for forming a power field-effect transistor, comprising:
[0006] Provide a substrate;
[0007] A hard mask layer is formed, the hard mask layer covering the substrate and the thickness of the hard mask layer being a first target thickness;
[0008] A field oxide layer is formed, the field oxide layer extending from the substrate to the substrate;
[0009] A JFET structure is formed, wherein the JFET structure is located within the substrate;
[0010] An isolation layer is formed on the JFET structure, and the top surface of the isolation layer is flush with the top surface of the hard mask layer and the top surface of the field oxide layer.
[0011] A gate material layer is formed, which covers the isolation layer and the substrate, and the thickness of the gate material layer is a second target thickness.
[0012] Optionally, a dielectric layer is formed before forming the hard mask layer, the dielectric layer covering the substrate.
[0013] Optionally, the step of forming the field oxide layer includes:
[0014] A patterned first photoresist layer is formed, the patterned first photoresist layer exposing a hard mask layer of the defined region of the field oxide layer;
[0015] Perform the first etching process, using the patterned first photoresist layer as a mask, to etch the hard mask layer and dielectric layer of the defined region of the field oxide layer, thereby exposing the substrate of the defined region of the field oxide layer;
[0016] An oxidation process is performed to form a field oxide layer in an exposed substrate, the field oxide layer extending from the substrate to the substrate.
[0017] Optionally, the steps for forming the JFET structure include:
[0018] A patterned second photoresist layer is formed, which exposes the hard mask layer of the definition region of the JFET structure;
[0019] A second etching process is performed, using the patterned second photoresist layer as a mask, to etch the hard mask layer and dielectric layer of the definition region of the JFET structure to form a trench. The trench penetrates the hard mask layer and the dielectric layer and exposes the substrate of the definition region of the JFET structure.
[0020] An ion implantation process is performed to form a JFET structure within the exposed substrate.
[0021] Optionally, the step of forming the isolation layer includes:
[0022] Remove the patterned second photoresist layer remaining on the hard mask layer and the field oxide layer;
[0023] A deposition process is performed to form an isolation layer material layer on the JFET structure, the isolation layer material layer also covering the hard mask layer and the field oxide layer;
[0024] A chemical mechanical polishing process is performed to remove the isolation layer material layer on the hard mask layer and the field oxide layer. The remaining isolation layer material layer on the JFET structure constitutes the isolation layer, and the top surface of the isolation layer is flush with the top surface of the hard mask layer and the field oxide layer.
[0025] Optionally, the ion type in the ion implantation process is the same as the type of doped ions in the substrate.
[0026] Optionally, the step of forming the gate material layer includes:
[0027] Remove the hard mask layer on the dielectric layer;
[0028] A gate material layer is formed, which covers the isolation layer and the dielectric layer, and the thickness of the gate material layer is a second target thickness.
[0029] Optionally, the thickness of the first target ranges from 2,500 angstroms to 2,700 angstroms.
[0030] Optionally, the second target thickness ranges from 4400 angstroms to 4600 angstroms.
[0031] Based on the same inventive concept, the present invention also provides a power field-effect transistor, which is fabricated using the power field-effect transistor formation method described in any of the above claims.
[0032] In a method for forming a power field-effect transistor (FET) provided by the present invention, a substrate is provided; a hard mask layer is formed, the hard mask layer covering the substrate and the thickness of the hard mask layer being a first target thickness; a field oxide layer is formed, the field oxide layer extending from the substrate to the substrate; a JFET structure is formed, the JFET structure being located within the substrate; an isolation layer is formed, the isolation layer being located on the JFET structure and the top surface of the isolation layer being flush with the top surface of the hard mask layer and the top surface of the field oxide layer; a gate material layer is formed, the gate material layer covering the isolation layer and the substrate, the thickness of the gate material layer being a second target thickness. In this invention, the gate material layer and the hard mask layer only require one process step to achieve their target thickness, reducing process steps and thus reducing equipment waste. Attached Figure Description
[0033] Figure 1 This is a flowchart of a method for forming a power field-effect transistor according to an embodiment of the present invention.
[0034] Figures 2 to 10 This is a schematic diagram of the structure corresponding to the steps of the method for forming a power field-effect transistor according to an embodiment of the present invention.
[0035] In the picture,
[0036] 10-Substrate; 10a-Definition region of field oxide layer; 10b-Definition region of JFET structure; 11-Dielectric layer; 12-Hard mask layer; 13-Patterned first photoresist layer; 14-Field oxide layer; 15-Patterned second photoresist layer; 16-JFET structure; 16a-Trench; 17-Isolation layer; 17a-Isolation material layer; 18-Gate material layer. Detailed Implementation
[0037] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the power field-effect transistor and its formation method proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, used only to facilitate and clarify the illustration of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales.
[0038] Figure 1 This is a flowchart illustrating a method for forming a power field-effect transistor according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for forming a power field-effect transistor, including:
[0039] Step S10: Provide a substrate;
[0040] Step S20: Form a hard mask layer, the hard mask layer covering the substrate and the thickness of the hard mask layer being a first target thickness;
[0041] Step S30: Forming a field oxide layer that extends from the substrate to the substrate;
[0042] Step S40: Form a JFET structure, wherein the JFET structure is located within the substrate;
[0043] Step S50: Form an isolation layer, the isolation layer being located on the JFET structure and the top surface of the isolation layer being flush with the top surface of the hard mask layer and the top surface of the field oxide layer;
[0044] Step S60: Form a gate material layer, the gate material layer covering the isolation layer and the substrate, the thickness of the gate material layer being a second target thickness.
[0045] Figures 2 to 10 This is a schematic diagram of the structural steps corresponding to the formation method of the power field-effect transistor according to an embodiment of the present invention. To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the following description is provided in conjunction with the appendix to the specification. Figures 2 to 10 Specific embodiments of the present invention will be described in detail below.
[0046] like Figure 2As shown, a substrate 10 is provided. The substrate 10 provides an operating platform for subsequent processes. It can be any substrate known to those skilled in the art for supporting semiconductor integrated circuit components, such as a bare die or a wafer processed by epitaxial growth. Specifically, the substrate is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate. In this embodiment, the substrate 10 includes a silicon substrate and an epitaxial layer (EPI). The doping type of the substrate 10 is a first type, such as N-type.
[0047] like Figure 3 As shown, a dielectric layer 11 is formed. The dielectric layer 11 is made of a material such as silicon oxide and can be formed using a chemical vapor deposition process. The dielectric layer 11 covers the substrate 10 and is located between the hard mask layer 12 and the substrate 10, serving as a buffer layer between the hard mask layer 12 and the substrate 10.
[0048] Please continue to refer to this. Figure 3 A hard mask layer 12 is formed, which covers the substrate 10, and the thickness of the hard mask layer 12 is a first target thickness. The first target thickness ranges from 2500 angstroms to 2700 angstroms, and for example, is 2600 angstroms. The thickness of the hard mask layer 12 is the first target thickness to ensure that the thickness of the subsequently formed isolation layer meets the target requirements. The material of the hard mask layer 12 is, for example, silicon nitride (NIT). In existing fabrication processes, the hard mask layer usually requires multiple depositions; this embodiment saves process steps by using a single process.
[0049] like Figure 4 and Figure 5 As shown, a field oxide layer 14 is formed, the field oxide layer 14 extending from the substrate 10 to the substrate 10. Further, the step of forming the field oxide layer 14 includes: as shown... Figure 4 As shown, a patterned first photoresist layer 13 is formed, which exposes the hard mask layer 12 on the defined region 10a of the field oxide layer; a first etching process is performed, using the patterned first photoresist layer 13 as a mask, to etch the hard mask layer 12 and the dielectric layer 11 on the defined region 10a of the field oxide layer, exposing the substrate of the defined region 10a of the field oxide layer. Figure 5As shown, an oxidation process is performed to form a field oxide layer 14 in the exposed substrate, the field oxide layer 14 extending from the substrate 10 to the substrate 10. The oxidation process is, for example, a thermal oxidation process, to oxidize a portion of the substrate (the substrate of the defined region 10a of the field oxide layer) to silicon oxide, and then continue to grow silicon oxide above the top surface of the substrate to form the field oxide layer 14. In other embodiments, before forming the field oxide layer, a photolithography process for the active region (ACT PH) is performed, followed by a photolithography process for the ring isolation region (Ring PH), and then an ion implantation process is performed to form a ring isolation structure. Those skilled in the art will know the above processes, and this embodiment will not elaborate further.
[0050] like Figure 6 As shown, a JFET structure 16 is formed within the substrate 10. Further, the steps for forming the JFET structure 16 include: forming a patterned second photoresist layer 15, which exposes the hard mask layer 12 of the definition region 10b of the JFET structure; performing a second etching process, using the patterned second photoresist layer 15 as a mask, etching the hard mask layer 12 and the dielectric layer 11 of the definition region 10b of the JFET structure to form a trench 16a, which penetrates the hard mask layer 12 and the dielectric layer 11 and exposes the substrate of the definition region 10b of the JFET structure; and performing an ion implantation process to form the JFET structure 16 within the exposed substrate. The type of doped ions in the JFET structure 16 is the same as the type of doped ions in the substrate 10. The type of doped ions in the JFET structure 16 is also N-type. The JFET structure 16 is formed by ion implantation. The ion doping concentration in the JFET structure 16 is greater than that in the substrate 10. Therefore, the resistance of the JFET structure 16 is smaller, so as to concentrate the current.
[0051] like Figure 7 and Figure 8 As shown, an isolation layer 17 is formed, which is located on the JFET structure 16, and the top surface of the isolation layer 17 is flush with the top surface of the hard mask layer 12. Further, the step of forming the isolation layer 17 includes removing the remaining patterned second photoresist layer 15 from the hard mask layer 12 and the field oxide layer 14. That is, after the step of forming the JFET structure, if the patterned second photoresist layer 15 is not completely consumed, a photoresist removal process is required, typically using an ashing process or a stripping method to remove the remaining patterned second photoresist layer 15. Figure 7 As shown, a deposition process is performed to form an isolation layer material layer 17a on the JFET structure 16, the isolation layer material layer 17a also covering the hard mask layer 12 and the field oxide layer 14; as Figure 8As shown, a chemical mechanical polishing process is performed to remove the isolation layer material layer 17a on the hard mask layer 12 and the field oxide layer 14. The remaining isolation layer material layer 17a on the JFET structure 16 constitutes the isolation layer 17, and the top surface of the isolation layer 17 is flush with the top surfaces of the hard mask layer 12 and the field oxide layer 14. The material of the isolation layer 17 is, for example, silicon oxide, and the raw materials for preparing the isolation layer 17 include TEOS, formed using a chemical vapor deposition process. The thickness of the hard mask layer 12 determines the thickness of the isolation layer 17. It is worth noting that the thickness of the isolation layer 17 is the sum of the thicknesses of the hard mask layer 12 and the dielectric layer 11. However, since the thickness of the dielectric layer 11 is relatively small, the thickness of the hard mask layer 12 determines the thickness of the isolation layer 17. The isolation layer 17 is used to isolate the JFET structure 16 from the subsequently formed gate; therefore, the thickness of the isolation layer 17 needs to meet certain requirements to achieve the isolation effect.
[0052] like Figure 9 and Figure 10 As shown, a gate material layer 18 is formed, which covers the isolation layer 17, the dielectric layer 11, and the field oxide layer 14. The thickness of the gate material layer 18 is a second target thickness. The second target thickness ranges from 4400 angstroms to 4600 angstroms, and for example, is 4500 angstroms. Further, the step of forming the gate material layer 18 includes: as... Figure 9 As shown, the hard mask layer 12 on the dielectric layer 11 can be removed by an etching process, such as a dry etching process or a wet etching process. The etching solution for a wet etching process is, for example, phosphoric acid. Figure 10 As shown, a gate material layer 17 is formed, which covers the isolation layer 17, the dielectric layer 11, and the field oxide layer 14. The gate material layer 17 is made of, for example, polysilicon and can be formed using a chemical vapor deposition process. In the prior art, the gate material layer 18 is formed through a multi-step process, while in this embodiment, the gate material layer 18 of the target thickness is formed in a single process, simplifying the process flow, reducing equipment waste, and improving production efficiency.
[0053] Please continue to refer to this. Figure 10 This embodiment also provides a power field-effect transistor, fabricated using the power field-effect transistor formation method described in any one of the above embodiments, comprising:
[0054] Substrate 10, on which a dielectric layer 11 is formed;
[0055] A field oxide layer 14 extends from the substrate 10 onto the substrate 10;
[0056] JFET structure 16, wherein the JFET structure 16 is located within the substrate 10;
[0057] An isolation layer 17 is located on the JFET structure 16, and the top surface of the isolation layer 17 is flush with the top surface of the field oxide layer 14.
[0058] A gate material layer 18 covers the isolation layer 17 and the dielectric layer 11, and the thickness of the gate material layer 18 is a second target thickness.
[0059] In summary, the method for forming a power field-effect transistor (FET) provided in this embodiment of the invention includes: providing a substrate; forming a hard mask layer covering the substrate with a thickness of a first target thickness; forming a field oxide layer extending from the substrate to the substrate; forming a JFET structure located within the substrate; forming an isolation layer on the JFET structure with its top surface flush with the top surfaces of the hard mask layer and the field oxide layer; and forming a gate material layer covering the isolation layer and the substrate with a thickness of a second target thickness. In this invention, the gate material layer and the hard mask layer both require only one process step to achieve their target thickness, reducing process steps and thus minimizing equipment waste.
[0060] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.
[0061] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for forming a power field-effect transistor, characterized in that, include: Provide a substrate; A hard mask layer is formed, the hard mask layer covering the substrate and the thickness of the hard mask layer being a first target thickness; A field oxide layer is formed, the field oxide layer extending from the substrate to the substrate; A JFET structure is formed, wherein the JFET structure is located within the substrate; An isolation layer is formed on the JFET structure, and the top surface of the isolation layer is flush with the top surface of the hard mask layer and the top surface of the field oxide layer. A gate material layer is formed, which covers the isolation layer and the substrate, and the thickness of the gate material layer is a second target thickness.
2. The method for forming a power field-effect transistor as described in claim 1, characterized in that, Prior to the formation of the hard mask layer, a dielectric layer is also formed, which covers the substrate.
3. The method for forming a power field-effect transistor as described in claim 2, characterized in that, The steps for forming the field oxide layer include: A patterned first photoresist layer is formed, the patterned first photoresist layer exposing a hard mask layer of the defined region of the field oxide layer; Perform the first etching process, using the patterned first photoresist layer as a mask, to etch the hard mask layer and dielectric layer of the defined region of the field oxide layer, thereby exposing the substrate of the defined region of the field oxide layer; An oxidation process is performed to form a field oxide layer in the exposed substrate, the field oxide layer extending from the substrate to the substrate.
4. The method for forming a power field-effect transistor as described in claim 2, characterized in that, The steps for forming the JFET structure include: A patterned second photoresist layer is formed, which exposes the hard mask layer of the definition region of the JFET structure; A second etching process is performed, using the patterned second photoresist layer as a mask, to etch the hard mask layer and dielectric layer of the definition region of the JFET structure to form a trench. The trench penetrates the hard mask layer and the dielectric layer and exposes the substrate of the definition region of the JFET structure. An ion implantation process is performed to form a JFET structure within the exposed substrate.
5. The method for forming a power field-effect transistor as described in claim 4, characterized in that, The steps for forming the isolation layer include: Remove the patterned second photoresist layer remaining on the hard mask layer and the field oxide layer; A deposition process is performed to form an isolation layer material layer on the JFET structure, the isolation layer material layer also covering the hard mask layer and the field oxide layer; A chemical mechanical polishing process is performed to remove the isolation layer material layer on the hard mask layer and the field oxide layer. The remaining isolation layer material layer on the JFET structure constitutes the isolation layer, and the top surface of the isolation layer is flush with the top surface of the hard mask layer and the field oxide layer.
6. The method for forming a power field-effect transistor as described in claim 1, characterized in that, The ion type used in the ion implantation process is the same as the type of doped ions in the substrate.
7. The method for forming a power field-effect transistor as described in claim 2, characterized in that, The step of forming the gate material layer includes: Remove the hard mask layer on the dielectric layer; A gate material layer is formed, which covers the isolation layer and the dielectric layer, and the thickness of the gate material layer is a second target thickness.
8. The method for forming a power field-effect transistor as described in claim 1, characterized in that, The thickness of the first target ranges from 2,500 angstroms to 2,700 angstroms.
9. The method for forming a power field-effect transistor as described in claim 1, characterized in that, The second target thickness ranges from 4400 angstroms to 4600 angstroms.
10. A power field-effect transistor, characterized in that, It is fabricated using the method for forming a power field-effect transistor as described in any one of claims 1 to 9.