Thin film transistor and manufacturing method thereof, array substrate and display panel

Abstract

The invention provides a thin film transistor and a manufacturing method thereof, an array substrate and a display panel. The manufacturing method of the thin film transistor comprises the steps of providing a substrate; preparing a metal oxide active layer on one side of the substrate; preparing a first insulating layer on one side, far away from the substrate, of the metal oxide active layer; preparing a gate on one side, away from the substrate, of the first insulating layer; and injecting ions at least comprising fluorine elements into the first injection region and the second injection region. The fluorine-containing ions are injected into the first injection region and the second injection region to form the source region and the drain region respectively, and the carrier concentration is improved and the conductor resistance of the source and the drain is reduced by utilizing the strong electronegativity of the fluorine element, so that the on-state driving current of the thin film transistor is improved, and the device performance is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a thin-film transistor and its fabrication method, an array substrate, and a display panel. Background Technology

[0002] In a display panel composed of multiple pixel units, each pixel unit or sub-pixel unit is equipped with at least one thin-film transistor (TFT). The core function of the TFT is to turn on in precise timing in response to a scan signal, and to write the voltage or current corresponding to the data signal onto the pixel electrode electrically connected to the TFT. After the scan signal is removed, the TFT turns off, and the voltage or current written onto the pixel electrode is substantially maintained for one frame, thereby controlling the light emission brightness or light transmission state of the pixel unit during display, thus achieving image display.

[0003] However, the performance of thin-film transistors still needs improvement. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a thin-film transistor and its fabrication method, array substrate and display panel, which are beneficial to improving the performance of thin-film transistors.

[0005] To achieve the above objectives, one embodiment of this application provides a method for fabricating a thin-film transistor, comprising: providing a substrate; fabricating a metal oxide active layer on one side of the substrate; fabricating a first insulating layer on the side of the metal oxide active layer away from the substrate; fabricating a gate on the side of the first insulating layer away from the substrate; implanting ions comprising at least fluorine into two first implantation regions and a second implantation region; wherein the metal oxide active layers corresponding to the two sides of the orthographic projection of the gate onto the metal oxide active layer are respectively the first implantation region and the second implantation region.

[0006] In some embodiments, the ions comprising at least fluorine are positively charged.

[0007] In some embodiments, the step of injecting ions comprising at least fluorine into the first injection region and the second injection region includes: injecting boron difluoride ions into the first injection region and the second injection region.

[0008] In some implementations, the material of the metal oxide active layer includes at least one of indium gallium zinc oxide, indium zinc oxide, and indium tin zinc oxide.

[0009] In some embodiments, the step of injecting ions comprising at least fluorine into the first and second injection regions includes: injecting ions into the first and second injection regions at a concentration of 5 × 10⁻⁶.14 ~2×10 per square centimeter 15 Each square centimeter.

[0010] In some embodiments, the step of injecting ions comprising at least fluorine into the first injection region and the second injection region includes: the injection energy for injecting the ions into the first injection region and the second injection region is in the range of 35 keV to 45 keV.

[0011] In some embodiments, after the step of implanting ions comprising at least fluorine into the first implantation region and the second implantation region, the method further includes: forming a second insulating layer on the side of the gate away from the substrate; etching through the first and second insulating layers to form two vias; the two vias exposing at least a portion of the first implantation region and at least a portion of the second implantation region, respectively; forming a metal trace layer on the side of the two insulating layers away from the substrate; the metal trace layer overlapping the first implantation region and the second implantation region through the two vias, respectively.

[0012] In some embodiments, the step of preparing a metal oxide active layer on one side of the substrate includes: depositing a metal oxide thin film on one side of the substrate; annealing the metal oxide thin film at a temperature of 300°C to 400°C; and patterning the annealed metal oxide thin film to form the metal oxide active layer.

[0013] One embodiment of this application provides a thin-film transistor, comprising: a substrate; a metal oxide active layer disposed on one side of the substrate; the metal oxide active layer including a first implantation region and a second implantation region; the first implantation region and the second implantation region including ions of at least fluorine element; a first insulating layer disposed on the side of the metal oxide active layer away from the substrate; a gate disposed on the side of the first insulating layer away from the substrate; the metal oxide active layers corresponding to the orthographic projection of the gate onto the metal oxide active layer are respectively the first implantation region and the second implantation region.

[0014] One embodiment of this application provides an array substrate, including the thin-film transistor fabricated according to any of the above-described fabrication methods or the thin-film transistor as described above.

[0015] One embodiment of this application is a display panel, characterized in that it includes: a light-emitting device; a thin-film transistor as described above; and the light-emitting device is electrically connected to the thin-film transistor.

[0016] One embodiment of this application provides a method for fabricating a thin-film transistor, which, compared with the prior art, has the following advantages: by injecting ions including at least fluorine into the first and second injection regions to form source and drain regions respectively, the strong electronegativity of fluorine effectively increases the carrier concentration in the region, thereby reducing the conductivity resistance of the formed source and drain regions, thereby increasing the drive current of the thin-film transistor in the on state and improving device performance. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A flowchart illustrating a method for fabricating a thin-film transistor according to one embodiment of this application; Figure 2 A related thin-film transistor fabrication process diagram is provided for one embodiment of this application; Figure 3 A schematic diagram of a related thin-film transistor is provided for one embodiment of this application; Figure 4 A schematic diagram of a related thin-film transistor is provided for one embodiment of this application; Figure 5 A schematic diagram of a related thin-film transistor is provided for one embodiment of this application; Figure 6 This is a schematic diagram of a related thin-film transistor provided for one embodiment of this application.

[0019] Marker explanation: 100 Thin-film transistor; 110 Substrate; 120 Metal oxide active layer; 121 First implantation region; 122 Second implantation region; 123 First region; 125 Metal oxide thin film; 130 First insulating layer; 140 Gate; 150 Second insulating layer; 151 Through-hole; 152 Metal trace layer. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0021] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0022] In related technologies, metal-oxide-slim thin-film transistors (MOSFETs) have become core components of high-performance display panels due to their high mobility and good uniformity. However, during the manufacturing process, the conductor formation of their source and drain electrodes typically relies on methods such as boron ion implantation or plasma treatment. While these methods can achieve conductor formation, the electron concentration in the resulting source and drain regions is limited, leading to persistently high resistance, usually maintained at the 1KΩ~2KΩ level. This high source-drain resistance directly limits the maximum current that the light-emitting device can pass through when it is turned on, resulting in a smaller on-state current. This, in turn, affects the pixel charging speed, brightness uniformity, and overall power consumption performance of the display panel.

[0023] Please see Figure 1 and Figure 2 To address the aforementioned problems, one embodiment of this application provides a method for fabricating a thin-film transistor 100, which may include the following steps: S110: Provides substrate 110.

[0024] In this embodiment, the substrate 110 provides a physical foundation and process initiation platform for the fabrication of the thin-film transistor 100. The substrate 110 can serve as the base for subsequent functional layer structures to be stacked sequentially, and must possess good surface flatness, chemical stability, and thermal stability. Specifically, the substrate 110 can be a rigid substrate 110. For example, a rigid substrate can be a glass substrate 110, a quartz substrate 110, or a silicon substrate 110 covered with an insulating structure. The substrate 110 can also be a flexible substrate 110. For example, a flexible substrate 110 can be a polyimide substrate 110, a polyethylene terephthalate substrate 110, or other high-temperature resistant polymer substrates 110. When using a flexible substrate 110, a buffer layer is typically formed on the flexible substrate 110 first to improve surface properties and block impurities. Furthermore, the substrate 110 can be transparent or opaque.

[0025] S120: A metal oxide active layer 120 is prepared on one side of the substrate 110.

[0026] In this embodiment, a metal oxide active layer 120 may be formed on one side of the substrate 110. Specifically, after completing the processes provided for the substrate 110, a functional layer with semiconductor properties can be formed on the surface of the substrate 110 through film deposition and patterning processes. The functional layer may be the metal oxide active layer 120, which refers to a thin film made of a metal oxide semiconductor material. The metal oxide active layer 120 forms the basis for the carrier transport channel and electrode contact region in the thin film transistor 100.

[0027] S130: A first insulating layer 130 is disposed on the side of the metal oxide active layer 120 away from the substrate 110.

[0028] In this embodiment, a first insulating layer 130 with good insulating properties is covered on the metal oxide active layer 120. Part of the first insulating layer 130 is formed between adjacent metal oxide active layers 120 to electrically isolate adjacent metal oxide active layers 120. The first insulating layer 130 may be an insulating dielectric layer for electrically isolating the subsequently formed gate 140 from the underlying metal oxide active layer 120.

[0029] Through this step, a first insulating layer 130 is disposed on the side of the metal oxide active layer 120 away from the substrate 110, that is, directly covering the upper surface of the metal oxide active layer 120, thereby establishing the necessary insulating isolation between the gate 140 and the metal oxide active layer 120. The placement of the first insulating layer 130 is crucial for the normal function of the thin-film transistor 100. It ensures that the electric field applied to the gate 140 can effectively act on the underlying metal oxide active layer 120 (especially its first region 123, i.e., the future channel region) through the first insulating layer 130 to control the conduction and turn-off of the channel, while avoiding a direct electrical short circuit between the gate 140 and the metal oxide active layer 120. This step is the basis for constructing the gate 140 of the thin-film transistor 100, providing the necessary insulating interface for the subsequent formation of the gate 140.

[0030] Specifically, the material of the first insulating layer 130 can be at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material, and its thickness is usually in the range of tens to hundreds of nanometers. It can be formed by processes such as chemical vapor deposition or atomic layer deposition.

[0031] S140: A gate 140 is formed on the side of the first insulating layer 130 away from the substrate 110.

[0032] In this embodiment, a gate 140 can be disposed on the side of the first insulating layer 130 away from the substrate 110. That is, the gate 140 for applying a control electric field can be formed on the already formed first insulating layer 130 by deposition and patterning processes. The gate 140 is an electrode made of conductive material for receiving scan signals and generating a control electric field.

[0033] Specifically, on the side of the first insulating layer 130 away from the substrate 110, a continuous gate 140 material layer is first deposited over the entire surface using a physical vapor deposition or chemical vapor deposition process. The gate 140 material layer may comprise at least one conductive material selected from molybdenum, aluminum, copper, titanium, or alloys thereof. Subsequently, a photoresist mask corresponding to the target gate 140 pattern is formed on this gate 140 material layer using a photolithography process. Next, using the photoresist mask as a shield, the exposed gate 140 material layer is selectively etched to remove the portions not covered by the mask. After etching, the photoresist mask is removed, thereby leaving a patterned gate 140 on the first insulating layer 130.

[0034] S150: Ions including at least fluorine are injected into the two first injection regions 121 and the second injection region 122; the metal oxide active layers 120 on both sides of the orthogonal projection of the gate 140 onto the metal oxide active layer 120 are the first injection region 121 and the second injection region 122, respectively.

[0035] In this embodiment, after the gate 140 is formed, ion implantation can be performed on the first implantation region 121 and the second implantation region 122, thereby forming source and drain regions in the first implantation region 121 and the second implantation region 122 respectively.

[0036] The first implantation region 121 and the second implantation region 122 are located on either side of the region of the metal oxide active layer 120 covered by the orthogonal projection of the gate 140 onto the metal oxide active layer 120. The metal oxide active layer 120 may include the first implantation region 121 and the second implantation region 122, with the first implantation region 121 and the second implantation region 122 located between them. The metal oxide active layer 120 may also include a first region 123, through which the first implantation region 121 and the second implantation region 122 are connected. The orthogonal projection of the gate 140 onto the substrate 110 lies between the orthogonal projections of the first implantation region 121 and the second implantation region 122 onto the substrate 110, that is, the orthogonal projection of the gate 140 onto the substrate 110 overlaps with the orthogonal projection of the first region 123 onto the substrate 110.

[0037] The source / drain regions can be highly conductive regions formed in the first implantation region 121 and the second implantation region 122 of the metal oxide active layer 120 through selective ion implantation, with the first region 123 forming the channel region. Specifically, the source / drain regions can be obtained by ion implantation of the first implantation region 121 or the second implantation region 122 with fluorine-containing elements. The implanted fluorine acts as an electron donor in the lattice of the metal oxide active layer 120, thereby increasing the free electron concentration in the corresponding region and endowing it with excellent low resistance characteristics.

[0038] During the operation of the thin-film transistor 100, one of the implanted regions, after being conductiveized by ion implantation, serves as the carrier injection terminal, i.e., the source region. The other implanted region, after being conductiveized by ion implantation, serves as the carrier collection terminal, i.e., the drain region. The source and drain regions together constitute the main path for current to flow through the channel region. After the thin-film transistor 100 is integrated, the source and drain regions are electrically connected to the corresponding metal trace layer 152 through independent contact holes to connect to external circuits and perform signal input and output functions.

[0039] The two source and drain regions are located on both sides of the channel region and are directly connected to it, and their formation positions can be precisely defined by the self-aligned masking effect of the gate 140.

[0040] Specifically, using the gate 140 as an ion implantation mask, selective ion implantation is performed on the first implantation region 121 and the second implantation region 122 of the metal oxide active layer 120 exposed outside the gate 140. The implanted ions may include at least fluorine. Specifically, fluorine may be introduced into the first implantation region 121 and the second implantation region 122 in the form of boron difluoride ions or other fluorine-containing ions. During the implantation process, ions are implanted into the lattice of the metal oxide active layer 120 with a certain energy and dose.

[0041] Because fluorine atoms are more electronegative than oxygen atoms in metal oxides, they can act as effective electron donors after entering the crystal lattice, increasing the free electron concentration in the first injection region 121 and the second injection region 122 to a certain extent. This transforms the semiconductor regions of the first injection region 121 and the second injection region 122 into two source-drain regions with high conductivity. Through this process, the first injection region 121 and the second injection region 122 are transformed into low-resistance conductive regions, thus forming two source-drain regions.

[0042] In this embodiment, source and drain regions are formed by injecting ions containing at least fluorine into the first injection region 121 and the second injection region 122, respectively. The strong electronegativity of fluorine effectively increases the free electron concentration in the source and drain regions, thereby reducing the resistance of the formed source and drain regions, thereby increasing the drive current of the thin film transistor 100 in the on state and improving device performance.

[0043] In some embodiments, at least fluorine ions are included and are positively charged.

[0044] In this embodiment, the fluorine-containing ions used during ion implantation are positively charged. Positive charge means that the ions physically exhibit a net charge state. Specifically, positively charged ions can be produced using a semiconductor ion implantation setup and given sufficient kinetic energy to be implanted into the first and second implantation regions. The positive charge of these ions ensures that they meet the physical requirements of standard ion implantation processes.

[0045] In some embodiments, the step of injecting ions comprising at least fluorine into the first injection region 121 and the second injection region 122 includes: injecting boron difluoride ions into the first injection region 121 and the second injection region 122.

[0046] In this embodiment, ions including boron difluoride ions can be injected into the first injection region 121 and the second injection region 122, thereby injecting ions including fluorine into the first injection region 121 and the second injection region 122.

[0047] Boron difluoride ions are positively charged ion groups composed of a boron atom and two fluorine atoms, and their chemical symbol is usually represented as boron difluoride ion. During ion implantation, the ion type used is boron difluoride ions, or an ion beam containing at least one of the above. Boron difluoride ions utilize the characteristic of fluorine as an electron donor to dope the first implantation region 121 and the second implantation region 122 through the ion implantation process. This results in a high concentration of free electrons within the first implantation region 121 and the second implantation region 122, ultimately transforming the first implantation region 121 and the second implantation region 122 from semiconductor regions into low-resistance conductive regions, i.e., forming source and drain regions.

[0048] In some embodiments, the material of the metal oxide active layer 120 includes one of indium gallium zinc oxide, indium zinc oxide, indium tin zinc oxide, or a combination of two or more of them.

[0049] In this embodiment, the material of the metal oxide active layer 120 may include at least one of indium gallium zinc oxide, indium zinc oxide, and indium tin zinc oxide.

[0050] Indium gallium zinc oxide (IGaZO) can be an amorphous or crystalline semiconductor oxide material containing indium, gallium, zinc, and oxygen. Indium zinc oxide (IZO) can also be a semiconductor oxide material containing indium, zinc, and oxygen. Indium tin zinc oxide (IZO) can be a semiconductor oxide material containing indium, tin, zinc, and oxygen. These materials all belong to the metal-oxide-semiconductor system, possessing high carrier mobility, good uniformity, and optical transparency in the visible light range, making them suitable active layer materials for thin-film transistors 100 in high-performance display panels.

[0051] The metal oxide active layer 120 formed using these materials is well compatible with the subsequent fluorine ion implantation step, enabling effective control of the electrical properties of its first implantation region 121 and second implantation region 122.

[0052] In some embodiments, the step of implanting ions comprising at least fluorine into the first implantation region 121 and the second implantation region 122 includes: implanting ions into the first implantation region 121 and the second implantation region 122 at a concentration of 5 × 10⁻⁶ ions. 14 ~2×10 per square centimeter 15 One square centimeter.

[0053] In this embodiment, 5×10 is used. 14 ~2×10 per square centimeter 15 Implanting ions into the first implantation region 121 and the second implantation region 122 at an ion concentration of 1 ion per square centimeter can ensure that the resistance of the source and drain regions corresponding to the first implantation region 121 and the second implantation region 122 is effectively reduced while maintaining good performance and process stability of the thin film transistor 100.

[0054] Ion concentration refers to the number of ions implanted per unit area of ​​the metal oxide active layer 120 surface during the ion implantation process, and its unit is ions per square centimeter.

[0055] Specifically, when implanting ions into the two first implantation regions 121 and the second implantation region 122, the ion concentration can be 5 × 10⁻⁶. 14 Each square centimeter, 6×10 14 Each square centimeter, 7×10 14 Each square centimeter, 8×10 14 Each square centimeter, 9×10 14 Each square centimeter, 1×10 15 Each square centimeter or 2×10 15 Each square centimeter, etc.

[0056] If using less than 5×10 14Implanting ions at a concentration of 1 per square centimeter may result in insufficient fluorine elements being introduced into the first implantation region 121 and the second implantation region 122, which may not be enough to increase the free electron concentration in the region, resulting in an insignificant decrease in the conductivity resistance of the source and drain regions.

[0057] If using a value higher than 2×10 15 Implanting ions at a concentration of 1 ion per square centimeter may lead to excessive lattice damage or introduce unnecessary defects, which may degrade the electrical properties of the metal oxide active layer 120.

[0058] In some embodiments, the step of injecting ions comprising at least fluorine into the first injection region 121 and the second injection region 122 includes: the injection energy used to inject ions into the first injection region 121 and the second injection region 122 is in the range of 35 keV to 45 keV.

[0059] In this embodiment, the implantation energy used to implant ions into the first implantation region 121 and the second implantation region 122 can be in the range of 35 keV to 45 keV, which can ensure that fluorine ions are accurately and effectively doped to the expected depth position in the first implantation region 121 and the second implantation region 122, thereby optimizing the vertical doping distribution and conductivity characteristics of the source and drain regions.

[0060] Implantation energy refers to the kinetic energy carried by a single ion in an ion beam during ion implantation, and its common unit is keV. In ion implantation, the ion beam containing fluorine is used, and its implantation energy is controlled within the range of 35 keV to 45 keV. The magnitude of the implantation energy directly determines the depth to which ions can penetrate and remain within the metal oxide active layer 120. Setting the implantation energy between 35 keV and 45 keV is a specially selected process window.

[0061] Specifically, for example, the injected energy can be 35 keV, 36 keV, 37 keV, 38 keV, 39 keV, 40 keV, 41 keV, 42 keV, 43 keV, 44 keV, or 45 keV, etc.

[0062] If the implantation energy is below 35 keV, the ions may not be able to obtain enough kinetic energy to be effectively implanted to the target depth of the first implantation region 121 and the second implantation region 122, resulting in a shallow doping distribution and failure to form an effective low-resistance conductive region.

[0063] If the injected energy exceeds 45 kiloelectron volts, the ions may penetrate too deeply, and may even penetrate the metal oxide active layer 120. This will not only fail to form an effective conductive layer in the target area, but may also cause unnecessary damage to the underlying substrate 110 or other film layers, affecting the overall performance and reliability of the thin film transistor 100.

[0064] Please see Figures 3-5 In some embodiments, after implanting ions comprising at least fluorine into the first implantation region 121 and the second implantation region 122, the method further includes: forming a second insulating layer 150 on the side of the gate 140 away from the substrate 110; etching through the second insulating layer 150 and the first insulating layer 130 to form two vias 151; the two vias 151 exposing at least a portion of the first implantation region 121 and at least a portion of the second implantation region 122; forming a metal wiring layer 152 on the side of the second insulating layer 150 away from the substrate 110; the metal wiring layer 152 overlapping the first implantation region 121 and the second implantation region 122 through the two vias 151, respectively.

[0065] In this embodiment, after the fabrication of the source and drain regions of the thin-film transistor 100 is completed, the back-end process for interconnecting the thin-film transistor 100 with external circuitry is realized.

[0066] First, a second insulating layer 150 is deposited all over the side of the gate 140 away from the substrate 110, and this second insulating layer 150 at least partially covers the first insulating layer 130. The second insulating layer 150 serves as an interlayer dielectric, and its main function is to provide electrical isolation for the subsequently formed metal wiring layers 152 of different levels, preventing short circuits, and to provide mechanical protection and a surface planarization basis for the entire thin-film transistor 100. Specifically, the material of the second insulating layer 150 may include silicon oxide, silicon nitride, or organic insulating materials.

[0067] Next, two vias 151 can be fabricated by etching the second insulating layer 150 and the first insulating layer 130. These two vias 151 penetrate the first insulating layer 130 and the second insulating layer 150, respectively exposing at least a portion of the first injection region 121 and at least a portion of the second injection region 122. Specifically, through a patterning process combining photolithography and dry / wet etching, vertically penetrating holes, i.e., vias 151, are etched in the second insulating layer 150 and the portion of the first insulating layer 130 located above the first and second injection regions 121 and 122. The purpose of forming the vias 151 is to establish vertical electrical connection channels. For example, the positions of the two vias 151 are set to correspond to the lower first injection region 121 and the second injection region 122, respectively, so that the two vias 151 can expose at least a portion of the upper surfaces of the first and second injection regions 121 and 122, providing a contact interface for the subsequent fabrication of the metal wiring layer 152.

[0068] Subsequently, conductive material is filled into the via 151 by depositing and patterning a thin metal film, while a specific wiring pattern is formed on the surface of the second insulating layer 150. The metal trace layer 152 thus achieves the dual function of vertical interconnection and horizontal extension. Crucially, the metal portion located within the via 151 is in direct contact with the exposed first injection region 121 and second injection region 122, thereby establishing a robust electrical connection and bringing out the electrodes of the thin-film transistor 100.

[0069] Please see Figure 6 In some embodiments, the step of preparing a metal oxide active layer 120 on one side of the substrate 110 includes: depositing a metal oxide thin film 125 on one side of the substrate 110; annealing the metal oxide thin film 125 at a temperature of 300°C to 400°C; and patterning the annealed metal oxide thin film 125 to form the metal oxide active layer 120.

[0070] In this embodiment, the step of fabricating a metal oxide active layer 120 on one side of the substrate 110 provides a specific and implementable process breakdown.

[0071] First, a non-patterned initial thin film with the designed composition and thickness can be formed on the prepared substrate 110 surface using physical or chemical deposition processes. Deposition can refer to the process of depositing a film, which can be achieved, for example, through sputtering, atomic layer deposition, chemical vapor deposition, or spin coating. The formed metal oxide thin film 125 serves as a material precursor for the subsequent metal oxide active layer 120.

[0072] Next, the metal oxide thin film 125 is heat-treated in a temperature range of 300°C to 400°C. Limiting the annealing temperature to between 300°C and 400°C is sufficient to achieve effective film modification while avoiding damage to the substrate 110 (especially for flexible substrates 110), over-crystallization of the film, or adverse reactions with the underlying structure that may occur due to excessively high temperatures.

[0073] Specifically, for example, the annealing temperature can be 300℃, 305℃, 310℃, 315℃, 320℃, 325℃, 333℃, 340℃, 350℃, 360℃, 370℃, 375℃, 380℃, or 400℃, etc.

[0074] If the annealing temperature is less than 300℃, the atoms inside the metal oxide film 125 cannot obtain enough energy for sufficient diffusion and recombination under these conditions. As a result, lattice defects, dangling bonds, and oxygen vacancies formed during film deposition cannot be effectively repaired or passivated. Consequently, the metal oxide film 125 exhibits insufficient densification, poor microstructural stability, and high bulk defect and interface state density.

[0075] If the annealing temperature is greater than 400°C, the excessively high annealing temperature will introduce excessive heat energy into the metal oxide film 125 and the substrate 110 below, which may cause irreversible thermal damage, deformation or decomposition of the substrate 110.

[0076] Finally, the annealed, large-area metal oxide film 125 can be processed into a specific planar pattern as required by the design through photolithography and etching processes. The patterning process may include coating photoresist, exposure, and development to form a photoresist pattern, and then selectively etching the underlying metal oxide film 125 using this pattern as a mask to remove unwanted parts. The patterned film islands that remain are the metal oxide active layer 120. This patterning process precisely defines the contour of the active layer, including the shape and size of its first implantation region 121 and second implantation region 122, providing a basis for subsequent gate 140 alignment and ion implantation regions.

[0077] By depositing a metal oxide thin film 125, performing annealing and patterning, a complete process from material deposition and performance optimization to precise configuration is achieved, thereby forming the metal oxide active layer 120, which serves as the core of the thin film transistor 100.

[0078] One embodiment of this application provides a thin-film transistor 100, comprising: a substrate 110; a metal oxide active layer 120 disposed on one side of the substrate 110; the metal oxide active layer 120 including a first implantation region 121 and a second implantation region 122; the first implantation region 121 and the second implantation region 122 including ions of at least fluorine element; a first insulating layer 130 disposed on the side of the metal oxide active layer 120 away from the substrate 110; a gate 140 disposed on the side of the first insulating layer 130 away from the substrate 110; the metal oxide active layers 120 corresponding to the two sides of the orthographic projection of the gate 140 on the metal oxide active layer 120 are the first implantation region 121 and the second implantation region 122, respectively.

[0079] In this embodiment, the thin-film transistor 100 may include a substrate 110, a metal oxide active layer 120, a first insulating layer 130, and a gate 140. The substrate 110 can serve as the mechanical support and physical foundation of the entire thin-film transistor 100.

[0080] A metal oxide active layer 120 is disposed on one side of the substrate 110. This metal oxide active layer 120 can serve as a core functional layer. The portions of the metal oxide active layer 120 corresponding to the gate 140 on either side of the orthographic projection of the metal oxide active layer 120 are respectively a first implantation region 121 and a second implantation region 122. The first implantation region 121 and the second implantation region 122 are spaced apart. While separated from each other, they are interconnected through a first region 123, thereby forming a continuous semiconductor thin film island. Both the first implantation region 121 and the second implantation region 122 contain ions containing at least fluorine. Specifically, ions containing at least fluorine can be implanted into the first implantation region 121 and the second implantation region 122 using an ion implantation method, transforming them from their original semiconductor regions into regions with high conductivity, thereby forming source and drain regions respectively.

[0081] On the side of the metal oxide active layer 120 away from the substrate 110, a first insulating layer 130 and a gate 140 are sequentially stacked. The first insulating layer 130 covers the metal oxide active layer 120 to achieve electrical isolation. The first insulating layer 130 at least partially covers the substrate 110 and is located between adjacent metal oxide active layers 120 to electrically isolate adjacent metal oxide active layers. The gate 140 is located on the side of the first insulating layer 130 away from the substrate 110. In a direction perpendicular to the substrate 110, the gate 140 is precisely positioned to cover a first region 123 between the first implantation region 121 and the second implantation region 122. Since the first region 123 connects the two source and drain regions and is an undoped semiconductor region, this overlap ensures that the electric field generated by the gate 140 can most effectively act on the first region 123, thereby forming a conductive channel in the region that can be controlled by the gate voltage.

[0082] In this embodiment, the source and drain regions of the thin-film transistor 100 can be formed directly in the metal oxide active layer 120 by fluorine ion implantation, resulting in extremely low contact resistance; at the same time, the self-aligned overlap between the gate 140 and the channel region optimizes the gate control efficiency. This thin-film transistor 100 combines high performance with high process compatibility.

[0083] One embodiment of this application is an array substrate, including a thin-film transistor 100 fabricated according to any of the above-described fabrication methods or a thin-film transistor 100 as described above.

[0084] In this embodiment, the array substrate can be a core component constituting a display panel, image sensor or other electronic device, specifically referring to a substrate assembly on a common substrate 110 in which multiple thin-film transistors 100 and their related circuits and electrodes are integrated in a regular array.

[0085] The thin-film transistor 100 constituting the array substrate may be a thin-film transistor 100 implanted with ions including at least fluorine to form a low-resistance source-drain region.

[0086] Specifically, thin-film transistors 100 are integrated in an array on the same substrate 110 to form an array substrate, enabling the large-scale application of the invention. Each thin-film transistor 100 can serve as a switching element or driving element for a pixel. Because the thin-film transistors 100 constituting the array substrate have lower source-drain contact resistance, the entire array substrate achieves superior overall electrical performance. For example, faster pixel charging speed, higher display uniformity, lower power consumption, and better high-current driving capability. The array substrate can be a backplane for an active-matrix organic light-emitting diode display panel, a TFT array substrate for a liquid crystal display panel, or a driving backplane for a micro-LED display panel, etc.

[0087] One embodiment of this application provides a display panel, characterized in that it includes: a light-emitting device; a thin-film transistor 100 as described above; and the light-emitting device is electrically connected to the thin-film transistor 100.

[0088] In this embodiment, the display panel can be a functional module or final product capable of converting electrical signals into visual images.

[0089] The display panel may include at least a light-emitting device and a thin-film transistor 100 as described above. The light-emitting device may be a photoelectric conversion element capable of generating visible light under the drive of an external electrical signal. Specifically, the light-emitting device may be an organic light-emitting diode, a quantum dot light-emitting diode, a micro light-emitting diode, or a liquid crystal cell composed of pixel electrodes and a common electrode in a liquid crystal display unit.

[0090] When the display panel directly incorporates the thin-film transistor 100, the light-emitting device and the drain region of the thin-film transistor 100 are electrically connected through conductive structures such as electrodes and metal wiring layers 152. This electrical connection enables the thin-film transistor 100 to act as a driving switch or driving current source, precisely controlling the current or voltage flowing to or applied to the light-emitting device based on the scan signal and data signal received by its gate 140, thereby regulating the brightness of the light-emitting device in each display frame and ultimately achieving image display.

[0091] In this embodiment, the display panel can achieve more efficient and precise pixel driving by employing thin-film transistors 100 with source and drain regions possessing excellent conductivity, or an array substrate containing such thin-film transistors 100, thereby improving the overall performance of the display panel. Specifically, this display panel exhibits higher brightness uniformity, faster dynamic response speed, lower overall power consumption, and superior display quality. This display panel can be a screen component for various electronic devices such as mobile phones, tablets, televisions, laptops, and smart wearable devices.

[0092] It should be noted that some embodiments of this application have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. In addition, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired result.

[0093] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the above embodiments of this application, which are not provided in detail for the sake of brevity.

[0094] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a thin-film transistor, characterized in that, include: Provide substrate; An active metal oxide layer is prepared on one side of the substrate; A first insulating layer is formed on the side of the metal oxide active layer away from the substrate; A gate is formed on the side of the first insulating layer away from the substrate; Ions containing at least fluorine are injected into the first and second injection regions; The metal oxide active layers corresponding to the two sides of the orthogonal projection of the gate onto the metal oxide active layer are the first injection region and the second injection region, respectively.

2. The manufacturing method according to claim 1, characterized in that, The ions, which include at least fluorine, are positively charged.

3. The manufacturing method according to claim 1, characterized in that, The step of injecting ions comprising at least fluorine into the first injection region and the second injection region includes: injecting boron difluoride ions into the first injection region and the second injection region; Preferably, the material of the metal oxide active layer includes at least one of indium gallium zinc oxide, indium zinc oxide, and indium tin zinc oxide.

4. The manufacturing method according to claim 1, characterized in that, The step of injecting ions, including at least fluorine, into the first and second injection regions includes: injecting ions into the first and second injection regions at a concentration of 5 × 10⁻⁶. 14 ~2×10 per square centimeter 15 Each square centimeter.

5. The manufacturing method according to claim 1, characterized in that, The step of injecting ions containing at least fluorine into the first injection region and the second injection region includes: the injection energy for injecting the ions into the first injection region and the second injection region is in the range of 35 keV to 45 keV.

6. The manufacturing method according to claim 1, characterized in that, After the step of injecting ions comprising at least fluorine into the first injection region and the second injection region, the method further includes: A second insulating layer is formed on the side of the gate away from the substrate; The first insulating layer and the second insulating layer are etched to form two vias; the two vias respectively expose at least a portion of the first injection region and at least a portion of the second injection region. A metal trace layer is prepared on the side of the second insulating layer away from the substrate; the metal trace layer overlaps with the first injection region and the second injection region through two vias, respectively.

7. The manufacturing method according to claim 1, characterized in that, The step of fabricating a metal oxide active layer on one side of the substrate includes: A metal oxide thin film is deposited on one side of the substrate; The metal oxide film is annealed at a temperature of 300℃~400℃; The annealed metal oxide film is patterned to form the active metal oxide layer.

8. A thin-film transistor, characterized in that, include: Substrate; A metal oxide active layer is disposed on one side of the substrate; the metal oxide active layer includes a first implantation region and a second implantation region; the first implantation region and the second implantation region include ions containing at least fluorine. A first insulating layer is disposed on the side of the metal oxide active layer away from the substrate; A gate is disposed on the side of the first insulating layer away from the substrate; the metal oxide active layers corresponding to the orthogonal projection of the gate onto the metal oxide active layer are the first implantation region and the second implantation region, respectively.

9. An array substrate, characterized in that, This includes the thin-film transistor fabricated by the method according to any one of claims 1 to 7, or the thin-film transistor as described in claim 8.

10. A display panel, characterized in that, include: Light-emitting devices; The thin-film transistor as described in claim 8; The light-emitting device is electrically connected to the thin-film transistor.

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