Semiconductor structure and method of manufacturing the same

Abstract

The embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate and a plurality of memory cell transistors on the substrate. Each memory cell transistor comprises a nanosheet group, the nanosheet group comprising a plurality of nanosheets arranged at intervals and extending along a first direction, the nanosheet comprising a channel region; a gate layer covering a plurality of channel regions of the nanosheet group; the first direction is parallel to a surface of the substrate; and a plurality of data storage elements are located on one side of the nanosheet group along the first direction, each data storage element being electrically connected to the plurality of nanosheets of one memory cell transistor.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in electronic devices such as computers. The array area of ​​a DRAM chip typically consists of a 3D stacked array of memory cells.

[0003] DRAM access transistors need to have low leakage characteristics and high conduction current. As semiconductor structures continue to develop and their key dimensions continue to shrink, how to improve gate control capability is an urgent problem to be solved. Summary of the Invention

[0004] This disclosure provides a semiconductor structure, including:

[0005] A substrate, and a plurality of memory cell transistors located on the substrate, each of the memory cell transistors comprising: a nanosheet group comprising a plurality of spaced nanosheets extending along a first direction, the nanosheets comprising a channel region; a gate layer covering the plurality of channel regions of the nanosheet group; the first direction being parallel to the surface of the substrate;

[0006] Multiple data storage elements are located on one side of the nanosheet group along the first direction, and each of the data storage elements is electrically connected to multiple of the nanosheets of a memory cell transistor.

[0007] In some embodiments, the memory cell transistor further includes an epitaxial layer that at least covers the sidewalls of a plurality of nanosheets in the nanosheet group near the data storage element, and the data storage element is in contact with the epitaxial layer.

[0008] In some embodiments, each nanosheet group includes two or three nanosheets; and / or, a plurality of nanosheets in each nanosheet group are spaced apart along a second direction; the second direction is perpendicular to the surface of the substrate.

[0009] In some embodiments, the plurality of memory cell transistors are arranged in a plurality of transistor rows and a plurality of transistor columns, the transistor rows extending along a third direction, each transistor row including a plurality of memory cell transistors spaced apart along the third direction; the third direction intersects the first direction and is parallel to the surface of the substrate;

[0010] The transistor columns extend along a second direction, and each transistor column includes a plurality of memory cell transistors spaced apart along the second direction; the second direction is perpendicular to the surface of the substrate.

[0011] In some embodiments, the gate layer extends along the second direction, and a plurality of gate layers of each transistor column are sequentially connected along the second direction to form a word line. The number of word lines is plurality, and the plurality of word lines extend along the second direction and are arranged along the third direction.

[0012] The nanosheet further includes a first source / drain region located along the first direction on the side of the channel region away from the data storage element; the semiconductor structure further includes: a plurality of bit lines, each bit line extending along the third direction, and the plurality of bit lines arranged along the second direction, each bit line corresponding to a transistor row, and each bit line electrically connected to a plurality of first source / drain regions in its corresponding transistor row.

[0013] In some embodiments, the gate layer extends along the third direction, and a plurality of gate layers in each transistor row are sequentially connected along the third direction to form word lines. The number of word lines is plurality, and the plurality of word lines extend along the third direction and are arranged along the second direction.

[0014] The nanosheet further includes a first source / drain region located along the first direction on the side of the channel region away from the data storage element; the semiconductor structure further includes: a plurality of bit lines, each bit line extending along the second direction and the plurality of bit lines arranged along the third direction, each bit line corresponding to a transistor column, and each bit line electrically connected to a plurality of first source / drain regions in its corresponding transistor column.

[0015] This disclosure also provides a method for manufacturing a semiconductor structure, including:

[0016] A substrate is provided, and a plurality of memory cell transistors are formed on the substrate; wherein forming the memory cell transistors includes: forming a nanosheet group, the nanosheet group including a plurality of spaced nanosheets extending along a first direction, the nanosheets including channel regions; forming a gate layer, the gate layer covering the plurality of channel regions of the nanosheet group; the first direction is parallel to the surface of the substrate;

[0017] Multiple data storage elements are formed, the data storage elements are located on one side of the nanosheet group along the first direction, and each data storage element is electrically connected to multiple nanosheets of a memory cell transistor.

[0018] In some embodiments, forming the nanosheet assembly includes:

[0019] An initial stacked structure is formed on the substrate, the initial stacked structure comprising first dielectric layers and stacked layers alternately stacked along a second direction, the stacked layers comprising a plurality of first semiconductor layers stacked along the second direction, and a second dielectric layer located at least between two adjacent first semiconductor layers; the second direction is perpendicular to the surface of the substrate;

[0020] The initial stacked structure is graphically represented to form a plurality of stacked structures extending along the first direction and arranged along a third direction, and a first trench located between the stacked structures; wherein, the first semiconductor layer in the stacked structure is defined as an initial nanosheet; the third direction intersects the first direction and is parallel to the surface of the substrate;

[0021] Fill the first trench with an isolation layer;

[0022] A portion of the initial nanosheets and a portion of the second dielectric layer are removed along the first direction to form a second trench extending along the first direction between adjacent first dielectric layers; the remaining initial nanosheets constitute nanosheets, and a plurality of nanosheets located between adjacent first dielectric layers constitute a nanosheet group; the second trench is located on one side of the nanosheet group in the first direction and exposes the sidewalls of a plurality of nanosheets in the nanosheet group.

[0023] Forming the data storage element includes: forming the data storage element at least partially located within the second trench, the data storage element being electrically connected to a plurality of nanosheets of the nanosheet group.

[0024] In some embodiments, prior to forming the data storage element, the method further includes performing an epitaxial process from the second trench to form an epitaxial layer, the epitaxial layer at least covering the sidewalls of a plurality of nanosheets in the nanosheet group exposed by the second trench, the data storage element being contacted and connected to the epitaxial layer.

[0025] In some embodiments, the plurality of nanosheet groups are arranged as a plurality of nanosheet rows and a plurality of nanosheet columns, the nanosheet rows extending along the third direction, each nanosheet row including a plurality of nanosheet groups spaced apart along the third direction; the nanosheet columns extending along the second direction, each nanosheet column including a plurality of nanosheet groups spaced apart along the second direction; forming the gate layer includes:

[0026] Multiple character lines are formed, each character line extending along the second direction, and the multiple character lines are arranged along the third direction; wherein...

[0027] Each word line corresponds to a nanosheet column, and each word line covers a portion of the surface of a plurality of nanosheets in its corresponding nanosheet column. The word line covers a portion of a plurality of nanosheets in each nanosheet group, forming the gate layer of the memory cell transistor. The plurality of gate layers in each nanosheet column are sequentially connected along the second direction to form the word line, and the portion of the nanosheet covered by the word line forms the channel region.

[0028] In some embodiments, the nanosheet further includes a first source / drain region located along the first direction on a side of the channel region opposite to the data storage element; the method further includes:

[0029] Multiple bit lines are formed, each bit line extending along the third direction, and the multiple bit lines are arranged along the second direction; wherein each bit line corresponds to a nanosheet row, and each bit line is electrically connected to multiple first source / drain regions in its corresponding nanosheet row.

[0030] In some embodiments, the plurality of nanosheet groups are arranged as a plurality of nanosheet rows and a plurality of nanosheet columns, the nanosheet rows extending along the third direction, each nanosheet row including a plurality of nanosheet groups spaced apart along the third direction; the nanosheet columns extending along the second direction, each nanosheet column including a plurality of nanosheet groups spaced apart along the second direction; forming the gate layer includes:

[0031] Multiple character lines are formed, each character line extending along the third direction, and the multiple character lines are arranged along the second direction; wherein...

[0032] Each word line corresponds to a row of nanosheets, and each word line covers a portion of the surface of a plurality of nanosheets in its corresponding row of nanosheets. The word line covers a portion of a plurality of nanosheets in each group of nanosheets, forming the gate layer of the memory cell transistor. The plurality of gate layers in each row of nanosheets are sequentially connected along the third direction to form the word line, and the portion of the nanosheet covered by the word line forms the channel region.

[0033] In some embodiments, the nanosheet further includes a first source / drain region located along the first direction on a side of the channel region opposite to the data storage element; the method further includes:

[0034] Multiple bit lines are formed, each bit line extending along the second direction, and the multiple bit lines are arranged along the third direction; wherein each bit line corresponds to a nanosheet column, and each bit line is electrically connected to multiple first source / drain regions in the corresponding nanosheet column.

[0035] In some embodiments, forming the initial stacked structure on the substrate includes:

[0036] A stacked material layer is formed on the substrate, the stacked material layer comprising second semiconductor layers and an initial stacked layer alternately stacked along the second direction, the initial stacked layer comprising a plurality of first semiconductor layers stacked along the second direction, and a third semiconductor layer located at least between two adjacent first semiconductor layers;

[0037] At least a portion of the second semiconductor layer is removed to form a first gap;

[0038] The first dielectric layer is filled into the first gap;

[0039] At least a portion of the third semiconductor layer is removed to form a second gap;

[0040] The second dielectric layer is filled into the second gap.

[0041] In some embodiments, both the second semiconductor layer and the third semiconductor layer are made of silicon-germanium, wherein the atomic percentage of germanium atoms in the second semiconductor layer is between 0.2 and 0.5, and the atomic percentage of germanium atoms in the third semiconductor layer is between 0.1 and 0.2; and / or,

[0042] In the step of removing at least a portion of the second semiconductor layer, the etch selectivity ratio of the second semiconductor layer to the third semiconductor layer is greater than or equal to 100; and / or,

[0043] In the step of removing at least a portion of the third semiconductor layer, the etching selectivity ratio of the third semiconductor layer to the first semiconductor layer is greater than or equal to 100.

[0044] The semiconductor structure provided in this disclosure includes a memory cell transistor and a data storage element, which can constitute a memory cell for storing data. The memory cell transistor includes multiple nanosheets and a gate layer that simultaneously controls the multiple nanosheets. The arrangement of multiple nanosheets is equivalent to paralleling multiple conductive channels in the channel region, increasing the current conduction path and thereby increasing the drive current (Idsat) of the memory cell transistor. This, in turn, improves the switching speed of the memory cell transistor. When the memory cell transistor is in the off state, the conductive channels in the channel region can be more thoroughly "pinched off," effectively blocking the leakage path between the source and drain of the memory cell transistor, significantly reducing the turn-off leakage current (Ioff) of the memory cell transistor, thereby improving the electrical performance of the memory cell.

[0045] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification and the drawings. Attached Figure Description

[0046] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 A perspective view of a semiconductor structure provided in some embodiments of this disclosure;

[0048] Figure 2 Some embodiments of this disclosure follow Figure 3 A schematic diagram of the cross-sectional structure taken from line C1C2 in the diagram;

[0049] Figure 3 Some embodiments of this disclosure follow Figure 2 A schematic diagram of the cross-sectional structure taken from lines A1A2 and B1B2 in the diagram;

[0050] Figure 4 for Figures 1 to 3 The schematic diagram of the memory cell transistor provided in the document;

[0051] Figure 5 A perspective view of a semiconductor structure provided for other embodiments of this disclosure;

[0052] Figure 6 Some embodiments of this disclosure follow Figure 7 A schematic diagram of the cross-sectional structure taken from line C1C2 in the diagram;

[0053] Figure 7 Some embodiments of this disclosure follow Figure 6 A schematic diagram of the cross-sectional structure taken by line B1B2 in the diagram;

[0054] Figure 8 for Figures 5 to 7 The schematic diagram of the memory cell transistor provided in the document;

[0055] Figure 9 A flowchart illustrating a semiconductor structure in a manufacturing method according to some embodiments of this disclosure;

[0056] Figure 10 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 3 Schematic diagram of the cross-sectional structure taken from line C1C2 in the middle. Figure 1 ;

[0057] Figure 11 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 2 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 2 ;

[0058] Figure 12 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 3 Schematic diagram of the cross-sectional structure taken from line C1C2 in the middle. Figure 3 ;

[0059] Figure 13 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 2 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 4 ;

[0060] Figure 14 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 2 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 5 ;

[0061] Figure 15 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 3 Schematic diagram of the cross-sectional structure taken from line C1C2 in the middle. Figure 6 ;

[0062] Figure 16 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 2 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 7 ;

[0063] Figure 17 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 3 Schematic diagram of the cross-sectional structure taken from line C1C2 in the middle. Figure 8 ;

[0064] Figure 18 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 2 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 9 ;

[0065] Figure 19 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 2 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 10 ;

[0066] Figure 20 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 2 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 10 one;

[0067] Figure 21 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 2 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 10 two;

[0068] Figure 22 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 2 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 10 three;

[0069] Figure 23 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 2 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 10 Four;

[0070] Figure 24 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 2 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 10 five;

[0071] Figure 25 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 2 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 10 six;

[0072] Figure 26 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 3 Schematic diagram of the cross-sectional structure taken from line C1C2 in the middle. Figure 10 seven;

[0073] Figure 27 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 2 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 10 eight;

[0074] Figure 28 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 3 Schematic diagram of the cross-sectional structure taken from line C1C2 in the middle. Figure 10 Nine;

[0075] Figure 29 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 2 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 2 ten;

[0076] Figure 30 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 3 Schematic diagram of the cross-sectional structure taken from line C1C2 in the middle. Figure 2 eleven;

[0077] Figure 31 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 2 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 2 twelve;

[0078] Figure 32 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 2 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 2 Thirteen;

[0079] Figure 33 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 3 Schematic diagram of the cross-sectional structure taken from line C1C2 in the middle. Figure 2 fourteen;

[0080] Figure 34 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 2 Schematic diagram of the cross-sectional structure taken by lines A1A2 and B1B2. Figure 2 fifteen;

[0081] Figure 35 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 6 Schematic diagram of the cross-sectional structure taken by line B1B2 in the middle. Figure 2 sixteen;

[0082] Figure 36 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 6 Schematic diagram of the cross-sectional structure taken by line B1B2 in the middle. Figure 2 Seventeen;

[0083] Figure 37 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 7 Schematic diagram of the cross-sectional structure taken from line C1C2 in the middle. Figure 2eighteen;

[0084] Figure 38 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 6 Schematic diagram of the cross-sectional structure taken by line B1B2 in the middle. Figure 2 nineteen;

[0085] Figure 39 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 7 Schematic diagram of the cross-sectional structure taken from line C1C2 in the middle. Figure 3 ten;

[0086] Figure 40 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 6 Schematic diagram of the cross-sectional structure taken by line B1B2 in the middle. Figure 3 eleven;

[0087] Figure 41 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 7 Schematic diagram of the cross-sectional structure taken from line C1C2 in the middle. Figure 3 twelve;

[0088] Figure 42 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 6 Schematic diagram of the cross-sectional structure taken by line B1B2 in the middle. Figure 3 Thirteen;

[0089] Figure 43 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 7 Schematic diagram of the cross-sectional structure taken from line C1C2 in the middle. Figure 3 fourteen;

[0090] Figure 44 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 7 Schematic diagram of the cross-sectional structure taken from line C1C2 in the middle. Figure 3 fifteen;

[0091] Figure 45 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 6 Schematic diagram of the cross-sectional structure taken by line B1B2 in the middle. Figure 3 sixteen;

[0092] Figure 46 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 7 Schematic diagram of the cross-sectional structure taken from line C1C2 in the middle. Figure 3 Seventeen;

[0093] Figure 47 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 6 Schematic diagram of the cross-sectional structure taken by line B1B2 in the middle. Figure 3 eighteen;

[0094] Figure 48 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 6 Schematic diagram of the cross-sectional structure taken by line B1B2 in the middle. Figure 3 nineteen;

[0095] Figure 49 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 6 Schematic diagram of the cross-sectional structure taken by line B1B2 in the middle. Figure 4 ten. Detailed Implementation

[0096] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0097] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0098] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0099] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as a second element, component, area, layer, or part. And the discussion of a second element, component, area, layer, or part does not imply that the first element, component, area, layer, or part necessarily exists in this disclosure.

[0100] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0101] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0102] The semiconductor structure provided in this disclosure includes a memory cell transistor and a data storage element, which can constitute a memory cell for storing data. The memory cell transistor includes multiple nanosheets and a gate layer that simultaneously controls the multiple nanosheets. The arrangement of multiple nanosheets is equivalent to paralleling multiple conductive channels in the channel region, increasing the current conduction path and thereby increasing the drive current (Idsat) of the memory cell transistor. This, in turn, improves the switching speed of the memory cell transistor. When the memory cell transistor is in the off state, the conductive channels in the channel region can be more thoroughly "pinched off," effectively blocking the leakage path between the source and drain of the memory cell transistor, significantly reducing the turn-off leakage current (Ioff) of the memory cell transistor, thereby improving the electrical performance of the memory cell.

[0103] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0104] The semiconductor structure provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0105] like Figures 1 to 8 As shown, the semiconductor structure includes: a substrate 10, and a plurality of memory cell transistors 20 located on the substrate 10. Each memory cell transistor 20 includes: a nanosheet group 18, the nanosheet group 18 including a plurality of spaced nanosheets 181 extending along a first direction, the nanosheets 181 including a channel region 231; a gate layer 13 covering the plurality of channel regions 231 of the nanosheet group 18; the first direction being parallel to the surface of the substrate 10; and a plurality of data storage elements 24 located on one side of the nanosheet group 18 along the first direction, each data storage element 24 being electrically connected to the plurality of nanosheets 181 of a memory cell transistor 20.

[0106] The semiconductor structure provided in this disclosure can be a three-dimensional dynamic random access memory (3D DRAM), but is not limited thereto. The semiconductor structure can also be any semiconductor device with a floating transistor.

[0107] In some embodiments, the materials of the substrate 10 and the nanosheet 181 can be semiconductor materials. The materials of the substrate 10 and the nanosheet 181 can each independently include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In some embodiments, the substrate 10 can be a silicon substrate, which may be doped or undoped, and the nanosheet 181 can be made of silicon, which may be doped or undoped.

[0108] like Figure 1 or Figure 5 As shown, in some embodiments, the plurality of memory cell transistors 20 may be arranged in an array along a second direction and a third direction. In some embodiments, the plurality of memory cell transistors 20 are arranged as a plurality of transistor rows M and a plurality of transistor columns N, wherein the transistor rows M extend along a third direction, and each transistor row M includes a plurality of memory cell transistors 20 spaced apart along the third direction; the transistor columns N extend along a second direction, and each transistor column N includes a plurality of memory cell transistors 20 spaced apart along the second direction.

[0109] In some embodiments, multiple nanosheet groups 18 may be arranged in an array along a second direction and a third direction, and multiple data storage elements 24 may also be arranged in an array along the second direction and a third direction, and the multiple data storage elements 24 are electrically connected to the multiple nanosheet groups 18 of the multiple memory cell transistors 20 in a one-to-one correspondence.

[0110] Here, the third direction may intersect (including perpendicular or oblique) the first direction and be parallel to the surface of the substrate 10, and the second direction may be perpendicular to the surface of the substrate 10.

[0111] like Figure 2 or Figure 6 As shown, in some embodiments, in the third direction, two adjacent memory cell transistors 20 and two adjacent data storage elements 24 are separated by an isolation layer 19. For example... Figure 3 or Figure 7 As shown, in some embodiments, in the second direction, two adjacent memory cell transistors 20 and two adjacent data storage elements 24 are separated by a first dielectric layer 16. In some embodiments, the materials of the isolation layer 19 and the first dielectric layer 16 may each independently include one or more of oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), oxynitrides (e.g., silicon oxynitride), etc.

[0112] like Figures 1 to 4 or Figures 5 to 8As shown, in some embodiments, the plurality of nanosheets 181 in each nanosheet group 18 may be arranged at intervals along the second direction.

[0113] In some embodiments, two adjacent nanosheets 181 in each nanosheet group 18 in the second direction may be separated by a second dielectric layer 15.

[0114] In some embodiments, the material of the second dielectric layer 15 may include one or more of oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), oxynitrides (e.g., silicon oxynitride), etc., and the materials of the first dielectric layer 16 and the second dielectric layer 15 may be different. The material of the first dielectric layer 16 may include, but is not limited to, silicon nitride, and the material of the second dielectric layer 15 may include, but is not limited to, silicon oxide.

[0115] However, this is not the only one. In some other embodiments of this disclosure, the multiple nanosheets 181 of each nanosheet group 18 may also be arranged at intervals along a third direction to increase the applicability of different scenarios.

[0116] like Figure 3 or Figure 7 As shown, in some embodiments, the data storage element 24 may include a capacitor structure 22, which may include a first electrode layer 221. The capacitor structure 22 is electrically connected to a plurality of nanosheets 181 in the nanosheet group 18 through the first electrode layer 221. In some embodiments, the first electrode layer 221 is a cup-shaped structure extending along a first direction, and the opening of the first electrode layer 221 is opposite to the nanosheet group 18 electrically connected to the first electrode layer 221 along the first direction. In some embodiments, the capacitor structure 22 may further include: a capacitor dielectric layer 222 and a second electrode layer 223. The capacitor dielectric layer 222 at least covers the inner wall of the first space T21 defined by the first electrode layer 221; the second electrode layer 223 covers the capacitor dielectric layer 222 and at least fills the second space T22 defined by the capacitor dielectric layer 222. In some embodiments, the second electrode layers 223 of the plurality of capacitor structures 22 that are respectively electrically connected to the plurality of nanosheet groups may be electrically connected to each other, and the second electrode layers 223 may be a common electrode layer.

[0117] In some embodiments, the memory cell transistor 20 may further include an epitaxial layer 21, which at least covers the sidewalls of a plurality of nanosheets 181 in the nanosheet group 18 near the data storage element 24. The data storage element 24 is in contact with the epitaxial layer 21, thereby achieving electrical connection between the data storage element 24 and the plurality of nanosheets 181 in the nanosheet group 18 through the epitaxial layer 21. In some embodiments, the data storage element 24 includes a capacitor structure 22, the first electrode layer 221 of which is in contact with the epitaxial layer 21.

[0118] In some embodiments, the material of the epitaxial layer 21 may include a semiconductor material, and the material of the epitaxial layer 21 may be the same as or different from the material of the nanosheet 181. The epitaxial layer 21 may be doped or undoped. When the epitaxial layer 21 is doped, the doping type of the epitaxial layer 21 may be opposite to the doping type of the channel region 231.

[0119] In some embodiments, the epitaxial layer 21 may be heavily doped at the end near the data storage element 24, thereby reducing the contact resistance between the epitaxial layer 21 and the data storage element 24.

[0120] like Figure 3 and Figure 4 or Figure 7 and Figure 8 As shown, in some embodiments, in each memory cell transistor 20, a portion of nanosheets 181 are located between the channel region 231 and the data storage element 24. A third gap S3 is formed between the portion of nanosheets 181 located between the channel region 231 and the data storage element 24. The opening of the third gap S3 faces the data storage element 24. The epitaxial layer 21 also fills the third gap S3 and covers the opening of the third gap S3. The epitaxial layer 21 covers the portion of the multiple nanosheets 181 in the nanosheet group 18 that is close to the sidewall of the data storage element 24 and is connected to the portion of the epitaxial layer 21 that fills the third gap S3 and covers the opening of the third gap S3. In this way, the contact area between the epitaxial layer 21 and the data storage element 24 can be increased, and the contact resistance between the two can be further reduced.

[0121] like Figure 4 or Figure 8 As shown, in some embodiments, the portion of nanosheet 181 located in front of the channel region 231 and the data storage element 24, as well as the epitaxial layer 21, can serve as the second source / drain region 233 of the memory cell transistor 20.

[0122] like Figures 1 to 4 As shown, in some embodiments, the gate layer 13 extends along a third direction, and multiple gate layers 13 of each transistor row M are sequentially connected along a third direction to form word lines WL. There are multiple word lines WL, which extend along a third direction and are arranged along a second direction.

[0123] like Figure 2 and Figure 3As shown, in some embodiments, the semiconductor structure may further include a third dielectric layer 14, which may penetrate the isolation layer 19 along the second direction. The third dielectric layer 14 and the gate layer 13 are alternately distributed in the third direction. A portion of the word line WL also covers a portion of the outer wall of the third dielectric layer 14. The multiple gate layers 13 of each transistor row M in the third direction are connected to each other through the portion of the word line WL covering the outer wall of the third dielectric layer 14 to form a word line WL extending along the third direction. In the second direction, adjacent word lines WL are spaced apart.

[0124] like Figure 2 As shown, in some embodiments, a portion of the word line WL covering the third dielectric layer 14 on the third direction sidewall also covers the channel region 231 on the third direction sidewall, which can be part of the gate layer 13. Adjacent gate layers 13 on the third direction can be connected to each other by the portion of the word line WL covering the third dielectric layer 14 on the sidewall in the first direction.

[0125] In some embodiments, for any channel region 231 in the nanosheet group 18, the word line WL can surround the channel region 231 along a third direction, or it can only cover a portion of the surface of the channel region 231 to increase scene applicability. For example... Figures 1 to 4 As shown, for example, the word line WL can fill the gap between adjacent channel regions 231 in each memory cell transistor 20 and cover the sidewalls of the channel regions 231 in the third direction. However, it is not limited to this; the word line WL can also surround each channel region 231 of a transistor row M in the third direction to improve the gate control capability of the word line WL.

[0126] like Figures 1 to 4 As shown, in some embodiments, the nanosheet 181 further includes a first source / drain region 232, which is located along a first direction on the side of the channel region 231 away from the data storage element 24; the semiconductor structure may also include: a plurality of bit lines BL, each bit line BL extending along a second direction and the plurality of bit lines BL arranged along a third direction, each bit line BL corresponding to a transistor column N, and each bit line BL being electrically connected to the plurality of first source / drain regions 232 in its corresponding transistor column N.

[0127] like Figure 3 As shown, in some embodiments, a bit line BL can pass through multiple nanosheet groups 18 of a corresponding transistor column N along a second direction, thereby achieving electrical connection with the first source / drain region 232 of the nanosheet 181.

[0128] like Figures 5 to 8As shown, in some other embodiments of this disclosure, the gate layer 13 may extend along a second direction, and multiple gate layers 13 of each transistor column N are sequentially connected along the second direction to form word lines WL. There are multiple word lines WL, which extend along the second direction and are arranged along a third direction. In some embodiments, the word lines WL may surround each channel region 231 of a transistor column N along the second direction to improve the gate control capability of the word lines WL.

[0129] like Figures 5 to 8 As shown, in some embodiments, the nanosheet 181 may further include a first source / drain region 232, which is located along a first direction on the side of the channel region 231 away from the data storage element 24; the semiconductor structure may further include: a plurality of bit lines BL, each bit line BL extending along a third direction and the plurality of bit lines BL arranged along a second direction, each bit line BL corresponding to a transistor row M, and each bit line BL being electrically connected to the plurality of first source / drain regions 232 in its corresponding transistor row M.

[0130] like Figure 6 and Figure 7 As shown, in some embodiments, bit lines BL may be located on the side of nanosheet group 18 away from data storage element 24 along a first direction, and in a second direction, adjacent bit lines BL may be separated by a first dielectric layer 16.

[0131] In some embodiments, the materials of the word line WL and the bit line BL may each independently include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys.

[0132] In some embodiments, the memory cell transistor 20 may further include a gate dielectric layer (not shown), which is located at least between the gate layer 13 and the channel region 231.

[0133] In some embodiments, a portion of the gate dielectric layer may also cover the sidewall of the gate layer 13 in the second direction. The gate layer 13 and the epitaxial layer 21 may be separated by the gate dielectric layer to avoid direct contact between the epitaxial layer 21 and the gate layer 13, which could cause a short circuit.

[0134] In some embodiments, a portion of the second dielectric layer 15 may be retained between the gate layer 13 and the third gap S3, and the gate layer 13 and the epitaxial layer 21 may be separated by a portion of the second dielectric layer 15 to avoid direct contact between the epitaxial layer 21 and the gate layer 13, which could cause a short circuit.

[0135] In this embodiment of the present disclosure, a memory cell transistor 20 and a data storage element 24 can constitute a memory cell for storing data. The memory cell transistor 20 includes multiple nanosheets 181 and a gate layer 13 that controls the multiple nanosheets 181 simultaneously. The arrangement of the multiple nanosheets 181 is equivalent to paralleling the conductive channels in multiple channel regions 231, increasing the current conduction path, thereby increasing the drive current (Idsat) of the memory cell transistor 20, and thus improving the switching speed of the memory cell transistor 20. When the memory cell transistor 20 is in the off state, the conductive channels in the channel region 231 can be more thoroughly "pinched off", so that the leakage path between the source and drain of the memory cell transistor 20 (i.e., the first source / drain region 232 and the second source / drain region 233) is effectively blocked, significantly reducing the turn-off leakage current (Ioff) of the memory cell transistor 20, thereby improving the electrical performance of the memory cell.

[0136] In some embodiments, each nanosheet group 18 may include two or three nanosheets 181. This configuration can effectively increase the drive current of the memory cell transistor 20 and reduce the turn-off leakage current of the memory cell transistor 20.

[0137] In some embodiments, the thickness of each nanosheet 181 in the second direction can range from 5 nm to 6 nm; when multiple nanosheets 181 of the nanosheet group 18 are arranged at intervals along the second direction, the multiple nanosheets 181 of the nanosheet group 18 can be distributed at equal or approximately equal intervals in the second direction, and in a nanosheet group 18, the distance between the upper surface of the uppermost nanosheet 181 and the lower surface of the lowermost nanosheet 181 can be around 40 nm.

[0138] This disclosure also provides a method for manufacturing a semiconductor structure, such as... Figure 9 As shown, the manufacturing method includes:

[0139] Step S101: Provide a substrate and form a plurality of memory cell transistors on the substrate; forming the memory cell transistors includes: forming a nanosheet group, the nanosheet group including a plurality of spaced nanosheets extending along a first direction, the nanosheets including channel regions; forming a gate layer, the gate layer covering the plurality of channel regions of the nanosheet group; the first direction is parallel to the surface of the substrate;

[0140] Step S102: Form multiple data storage elements. The data storage elements are located on one side of the nanosheet group along the first direction. Each data storage element is electrically connected to multiple nanosheets of a storage cell transistor.

[0141] The manufacturing method of the semiconductor structure provided in the embodiments of this application will be further described in detail below with reference to the accompanying drawings.

[0142] First, execute step S101, as follows: Figures 10 to 32 As shown, a substrate 10 is provided, and a plurality of memory cell transistors 20 are formed on the substrate 10 (see Figure 10). Figure 4 The formation of the memory cell transistor 20 includes: forming a nanosheet group 18, the nanosheet group 18 including a plurality of spaced nanosheets 181 extending along a first direction, the nanosheets 181 including a channel region 231; forming a gate layer 13, the gate layer 13 covering the plurality of channel regions 231 of the nanosheet group 18; the first direction is parallel to the surface of the substrate 10.

[0143] The material of substrate 10 has been described previously and will not be repeated here.

[0144] In some embodiments, forming the nanosheet assembly 18 includes:

[0145] An initial stacked structure ST' is formed on substrate 10. The initial stacked structure ST' includes first dielectric layers 16 and stacked layers 17 alternately stacked along a second direction. The stacked layers 17 include a plurality of first semiconductor layers 121 stacked along the second direction, and a second dielectric layer 15 located at least between two adjacent first semiconductor layers 121. The second direction is perpendicular to the surface of substrate 10 (e.g., ...). Figures 10 to 11 , Figure 14 , Figure 20 , Figure 21 as well as Figures 23 to 25 );

[0146] A patterned initial stacked structure ST' is formed, creating a plurality of stacked structures ST extending along a first direction and arranged along a third direction, and a first trench T1 located between the stacked structures ST; wherein, the first semiconductor layer 121 in the stacked structure ST is defined as an initial nanosheet 181'; the third direction intersects (e.g., perpendicular or obliquely) the first direction and is parallel to the surface of the substrate (e.g., ...). Figures 26 to 27 );

[0147] The first trench T1 is filled with an isolation layer 19 (such as... Figures 28 to 29 );

[0148] A portion of the initial nanosheets 181' and a portion of the second dielectric layer 15 are removed along the first direction to form a second trench T2 extending along the first direction between adjacent first dielectric layers 16; the remaining initial nanosheets 181' constitute nanosheets 181, and multiple nanosheets 181 located between adjacent first dielectric layers 16 constitute a nanosheet group 18. The second trench T2 is located on one side of the nanosheet group 18 in the first direction and exposes the sidewalls of multiple nanosheets 181 in the nanosheet group 18 (e.g., ...). Figures 30 to 31 ).

[0149] See you again Figures 10 to 11In some embodiments, forming an initial stacked structure ST' on the substrate 10 may include: forming a stacked material layer ST'' on the substrate 10, the stacked material layer ST'' including a second semiconductor layer 122 and an initial stacked layer 12 alternately stacked along a second direction, the initial stacked layer 12 including a plurality of first semiconductor layers 121 stacked along the second direction, and a third semiconductor layer 123 located at least between two adjacent first semiconductor layers 121.

[0150] See you again Figure 14 , Figure 20 , Figure 24 and Figure 25 The process of forming an initial stacked structure ST' may further include: removing at least a portion of the third semiconductor layer 123 to form a second gap S2; and filling the second gap S2 with a second dielectric layer 15.

[0151] See you again Figure 21 and Figure 23 The process of forming an initial stacked structure ST' may further include: removing at least a portion of the second semiconductor layer 122 to form a first gap S1, and filling the first gap S1 with a first dielectric layer 16.

[0152] Thus, a stacked material layer ST'' can be formed first by an epitaxial growth process, and then at least a portion of the second semiconductor layer 122 and at least a portion of the third semiconductor layer 123 in the stacked material layer ST'' can be replaced with a first dielectric layer 16 and a second dielectric layer 15, respectively, to form an initial stacked structure ST'. In some embodiments, in the stacked material layer ST'', the third semiconductor layer 123 may also be located between adjacent first semiconductor layers 121 and second semiconductor layers 122 in the second direction; in the initial stacked structure ST', the second dielectric layer 15 may also be located between adjacent first dielectric layers 16 and first semiconductor layers 121 in the second direction.

[0153] In some embodiments, the material of the first semiconductor layer 121 is different from the materials of the second semiconductor layer 122 and the third semiconductor layer 123 to avoid damage to the first semiconductor layer 121 during the removal of the second semiconductor layer 122 and the third semiconductor layer 123. The material of the first semiconductor layer 121 may include semiconductor materials as described above, such as silicon.

[0154] In some embodiments, the materials of the second semiconductor layer 122 and the third semiconductor layer 123 may both include silicon and germanium, wherein the atomic percentage of germanium atoms in the second semiconductor layer 122 is between 0.2 and 0.5 (including endpoint values, such as 0.2, 0.3, 0.4, 0.5, etc.), and the atomic percentage of germanium atoms in the third semiconductor layer 123 is between 0.1 and 0.2 (including endpoint values, such as 0.1, 0.15, 0.2, etc.). In this way, the etching selectivity ratio of the second semiconductor layer 122 and the third semiconductor layer 123 can be controlled in the same etching step, avoiding or reducing damage to the third semiconductor layer 123 when etching the second semiconductor layer 122, or avoiding or reducing damage to the second semiconductor layer 122 when etching the third semiconductor layer 123.

[0155] In some embodiments, during the step of removing at least a portion of the second semiconductor layer 122, the etching selectivity ratio of the second semiconductor layer 122 to the third semiconductor layer 123 is greater than or equal to 100 (e.g., 100, 120, 150, 200, 500, 1000, etc.). In some embodiments, during the step of removing at least a portion of the second semiconductor layer 122, the etching selectivity ratio of the second semiconductor layer 122 to the first semiconductor layer 121 is greater than or equal to 100 (e.g., 100, 120, 150, 200, 500, 1000, etc.). This avoids or reduces damage to the third semiconductor layer 123 or the first semiconductor layer 121 during the etching of the second semiconductor layer 122.

[0156] In some embodiments, during the step of removing at least a portion of the third semiconductor layer 123, the etching selectivity ratio of the third semiconductor layer 123 to the first semiconductor layer 121 is greater than or equal to 100 (e.g., 100, 120, 150, 200, 500, 1000, etc.). In some embodiments, when at least a portion of the second semiconductor layer 122 is still retained, during the step of removing at least a portion of the third semiconductor layer 123, the etching selectivity ratio of the third semiconductor layer 123 to the second semiconductor layer 122 is greater than or equal to 100 (e.g., 100, 120, 150, 200, 500, 1000, etc.). This avoids or reduces damage to the first semiconductor layer 121 or the second semiconductor layer 122 during the etching of the third semiconductor layer 123.

[0157] See you again Figures 12 to 13 , Figures 15 to 19 as well as Figure 22 In some embodiments, a gate layer 13 is formed (see Figure 4 This includes: forming multiple word lines WL, each word line WL extending along a third direction, and multiple word lines WL arranged along a second direction.

[0158] The following is combined Figures 12 to 22The method for replacing the second semiconductor layer 122 and the third semiconductor layer 123 and forming the word line WL provided in the embodiments of this disclosure will be described in detail.

[0159] like Figure 12 and Figure 13 As shown, the stacked material layer ST'' can enclose the first region 101, the second region 102, and the third region 103 arranged along the first direction.

[0160] First, such as Figure 12 and Figure 13 As shown, after forming the stacked material layer ST'', a plurality of first openings K1 can be formed in the second region 102 of the stacked material layer ST'' at intervals along the third direction. The first openings K1 can extend from the top surface of the stacked material layer ST'' along the second direction and at least penetrate the plurality of first semiconductor layers 121 in the stacked material layer ST''. The first openings K1 can penetrate or not penetrate the second semiconductor layer 122 located at the bottom layer in the stacked material layer ST''.

[0161] Figure 12 As shown, the distance between the first opening K1 and the first region 101 in the first direction, and the distance between the first opening K1 and the third region 103 in the first direction, are 0. However, it is not limited to this; the distance between the first opening K1 and the first region 101 in the first direction, and the distance between the first opening K1 and the third region 103 in the first direction, can also be greater than 0.

[0162] Next, as Figure 14 As shown, in some embodiments, the third semiconductor layer 123 located in the first region 101 and the second region 102 may be removed to form a first sub-gap S21.

[0163] Next, as Figure 15 and Figure 16 As shown, a conductive material layer 13'' can be formed, which can cover the inner wall of the first sub-gap S21 (e.g., can completely fill the first sub-gap S21) and the inner wall of the first opening K1.

[0164] In some embodiments, prior to forming the conductive material layer 13'', a gate oxide layer (not shown) may be formed that at least covers the surface of the first semiconductor layer 121 exposed by the first sub-gap S21 and the first opening K1, with the conductive material layer 13'' covering the gate oxide layer. In some embodiments, the gate oxide layer may cover the inner walls of the first sub-gap S21 and the first opening K1, with the conductive material layer 13'' covering the gate oxide layer.

[0165] Next, as Figure 17 and Figure 18As shown, a third dielectric layer 14 can be filled within the first opening K1. The material of the third dielectric layer 14 can be, but is not limited to, oxides, such as silicon oxide.

[0166] Next, as Figure 19 As shown, the conductive material layer 13'' located in the first region 101 can be removed to reopen the first sub-gap S21 located in the first region 101. The remaining conductive material layer 13'' forms a preset word line WL'. The preset word line WL' is located in the second region 102, extends along a third direction between adjacent second semiconductor layers 122, and extends continuously along a second direction within the first opening K1.

[0167] Next, as Figure 20 As shown, the first dielectric sublayer 151 can be filled within the reopened first sub-gap S21.

[0168] Next, as Figure 21 As shown, the remaining second semiconductor layer 122 can be removed to form a first gap S1, which surrounds the third dielectric layer 14 and exposes a portion of the preset word line WL' located on the sidewall of the third dielectric layer 14.

[0169] Next, as Figure 22 As shown, the exposed preset word line WL' is removed from the first gap S1 to break the preset word line WL' in the second direction, forming a plurality of word lines WL distributed at intervals in the second direction, and the word lines WL extend along the third direction.

[0170] Next, as Figure 23 As shown, the first dielectric layer 16 is filled in the first gap S1 and the gap formed by removing part of the preset word line WL'. In this way, the second semiconductor layer 122 remaining after the formation of the first opening K1 is replaced with the first dielectric layer 16. The first dielectric layer 16 also serves to isolate adjacent word lines WL in the second direction.

[0171] Next, as Figure 24 As shown, the remaining third semiconductor layer 123 located in the third region 103 can be removed to form a second sub-gap S22, and the first sub-gap S21 and the second sub-gap S22 constitute the second gap S2.

[0172] Next, as Figure 25 As shown, a second dielectric sublayer 152 is filled within the second sub-gap S22. The first dielectric sublayer 151 and the second dielectric sublayer 152 constitute the second dielectric layer 15, and the materials of the first dielectric sublayer 151 and the second dielectric sublayer 152 can be the same or different. In this way, the third semiconductor layer 123 remaining after the formation of the first opening K1 is replaced with the second dielectric layer 15.

[0173] The materials of the first dielectric layer 16 and the second dielectric layer 15 have been described previously and will not be repeated here.

[0174] Thus, the initial stacked structure ST' and word line WL can be formed through the above steps.

[0175] In some embodiments, the second semiconductor layer 122 may be removed before forming the first opening K1 to form a first gap S1, and the first dielectric layer 16 may be filled in the first gap S1. In some embodiments, the third semiconductor layer 123 may be removed before forming the first opening K1 to form a second gap S2, and the second dielectric layer 15 may be filled in the second gap S2.

[0176] See you again Figure 26 and Figure 27 The initial stacked structure ST' located on both sides of the third dielectric layer 14 along the first direction can be removed to form a first trench T1, and a plurality of stacked structures ST arranged in the third direction, with adjacent stacked structures ST separated by the first trench T1 and the third dielectric layer 14.

[0177] Figures 30 to 34 as well as Figures 2 to 3 The nanosheet group 18 referred to in the middle refers to a plurality of nanosheets 181 located between adjacent first dielectric layers 16 in the second direction.

[0178] See you again Figures 30 to 31 In some embodiments, the plurality of nanosheets 181 in each nanosheet group 18 may be arranged at intervals along a second direction, and the plurality of nanosheet groups 18 may be arranged in a row along the second direction and a third direction. Specifically, the plurality of nanosheet groups 18 may be arranged into a plurality of nanosheet rows L and a plurality of nanosheet columns H. The nanosheet rows L extend along a third direction, and each nanosheet row L includes a plurality of nanosheet groups 18 arranged at intervals along the third direction. The nanosheet columns H extend along the second direction, and each nanosheet column H includes a plurality of nanosheet groups 18 arranged at intervals along the second direction.

[0179] like Figures 30 to 31 as well as Figure 4 As shown, in some embodiments, each word line WL corresponds to a nanosheet row L, and each word line WL covers a portion of the surface of a plurality of nanosheets 181 in its corresponding nanosheet row L. The word line WL covers a portion of the plurality of nanosheets 181 in each nanosheet group 18, constituting a memory cell transistor 20 (see [link to documentation]). Figure 4 Gate layer 13 (see) Figure 4 Each nanosheet row L has multiple gate layers 13 connected sequentially along a third direction to form a word line WL, and the portion of the nanosheet 181 covered by the word line WL forms a channel region 231.

[0180] In some embodiments, a plurality of gate layers 13 in the third direction are interconnected by a partial word line WL covering the outer sidewall of the third dielectric layer 14 to form a word line WL extending in the third direction.

[0181] In some embodiments, a portion of the word line WL covering the third dielectric layer 14 on the third-direction sidewall also covers the channel region 231 on the third-direction sidewall, which may be part of the gate layer 13. Adjacent gate layers 13 on the third-direction sidewall can be connected to each other by the portion of the word line WL covering the sidewall of the third dielectric layer 14 in the first direction.

[0182] In some embodiments, for any channel region 231 in the nanosheet group 18, the word line WL may surround the channel region 231 along a third direction, or may only cover a portion of the surface of the channel region 231 to increase scenario applicability. For example, 30 to Figure 31 As shown, for example, the word line WL can fill the gap between adjacent channel regions 231 in each storage nanosheet group 18 and cover the sidewalls of the channel region 231 in the third direction.

[0183] However, this is not the only limitation. The word line WL can also surround each channel region 231 of a nanosheet row L along a third direction to improve the gate control capability of the word line WL. Specifically, a third semiconductor layer 123 can also be formed between the second semiconductor layer 122 and the first semiconductor layer 121 adjacent along the second direction. Subsequently, after the word line WL is formed, the word line WL can fill the gaps between adjacent channel regions 231 in each memory cell transistor 20, as well as the gaps between adjacent first dielectric layers 16 and channel regions 231, and cover the sidewalls of channel regions 231 in the third direction.

[0184] like Figure 32 As shown, in some embodiments, after forming the second trench T2, the method may further include performing an epitaxial process from the second trench T2 to form an epitaxial layer 21, the epitaxial layer 21 at least covering the sidewalls of the plurality of nanosheets 181 in the nanosheet group 18 exposed by the second trench T2.

[0185] In some embodiments, the material of the epitaxial layer 21 may include a semiconductor material, and the material of the epitaxial layer 21 may be the same as or different from the material of the nanosheet 181. The epitaxial layer 21 may be doped or undoped. When the epitaxial layer 21 is doped, the doping type of the epitaxial layer 21 may be opposite to the doping type of the channel region 231.

[0186] Next, proceed to step S102, as follows: Figure 33 and Figure 34As shown, a plurality of data storage elements 24 are formed, and the data storage elements 24 are located on one side of the nanosheet group 18 along a first direction. Each data storage element 24 is electrically connected to a plurality of nanosheets 181 of a storage cell transistor 20.

[0187] Specifically, forming a data storage element 24 includes forming a data storage element 24 that is at least partially located within a second trench T2, and the data storage element 24 is electrically connected to a plurality of nanosheets 181 of the nanosheet group 18.

[0188] In some embodiments, the data storage element 24 may include a capacitor structure 22, which may include a first electrode layer 221. The capacitor structure 22 is electrically connected to a plurality of nanosheets 181 in the nanosheet group 18 through the first electrode layer 221. In some embodiments, the first electrode layer 221 is a cup-shaped structure extending along a first direction, and the opening of the first electrode layer 221 is opposite to the nanosheet group 18 electrically connected to the first electrode layer 221 along the first direction. In some embodiments, the capacitor structure 22 may further include a capacitor dielectric layer 222 and a second electrode layer 223. The capacitor dielectric layer 222 at least covers the inner wall of the first space T21 defined by the first electrode layer 221; the second electrode layer 223 covers the capacitor dielectric layer 222 and at least fills the second space T22 defined by the capacitor dielectric layer 222. In some embodiments, the second electrode layers 223 of the plurality of capacitor structures 22 that are respectively electrically connected to the plurality of nanosheet groups may be electrically connected to each other, and the second electrode layers 223 may be a common electrode layer.

[0189] In some embodiments, the epitaxial layer 21 may be formed before the data storage element 24 is formed, and the data storage element 24 is contacted and connected to the epitaxial layer 21. In some embodiments, the epitaxial layer 21 may be heavily doped at the end near the data storage element 24, thereby reducing the contact resistance between the epitaxial layer 21 and the data storage element 24.

[0190] In some embodiments, after the second trench T2 is formed, a portion of the nanosheet 181 remains between the channel region 231 and the second trench T2, and a portion of the second dielectric layer 15 remains between the gate layer 13 and the second trench T2; see again Figure 31 After forming the second trench T2 and before forming the data storage element 24, a portion of the second dielectric layer 15 located between the gate layer 13 and the second trench T2 may be removed to form a third gap S3 between the gate layer 13 and the second trench T2. The third gap S3 is located between adjacent nanosheets 181. See again Figure 32In some embodiments, the epitaxial layer 21 may also fill the third gap S3 and cover the opening of the third gap S3. The epitaxial layer 21 covers the portion of the sidewalls of the multiple nanosheets 181 in the nanosheet group 18 exposed by the second trench T2 and is connected to the portion of the epitaxial layer 21 that fills the third gap S3 and covers the opening of the third gap S3. In this way, the contact area between the epitaxial layer 21 and the data storage element 24 can be increased, and the contact resistance between the two can be further reduced.

[0191] In some embodiments, the gate dielectric layer may also cover the sidewall of the gate layer 13 in the first direction, and the gate layer 13 and the epitaxial layer 21 may be separated by the gate dielectric layer to avoid direct contact between the epitaxial layer 21 and the gate layer 13, which could cause a short circuit.

[0192] In some embodiments, a portion of the second dielectric layer 15 may be retained between the gate layer 13 and the third gap S3, and the gate layer 13 and the epitaxial layer 21 may be separated by a portion of the second dielectric layer 15 to avoid direct contact between the epitaxial layer 21 and the gate layer 13, which could cause a short circuit.

[0193] like Figure 4 As shown, in some embodiments, the portion of nanosheet 181 located in front of the channel region 231 and the data storage element 24, as well as the epitaxial layer 21, can serve as the second source / drain region 233 of the memory cell transistor 20.

[0194] Next, as Figures 1 to 3 As shown, the method may further include: forming multiple bit lines BL, each bit line BL extending along a second direction, and the multiple bit lines BL being arranged along a third direction.

[0195] In some embodiments, the nanosheet 181 further includes a first source / drain region 232, which is located on the side of the channel region 231 away from the data storage element 24 along a first direction. Each bit line BL corresponds to a nanosheet column H, and each bit line BL is electrically connected to a plurality of first source / drain regions 232 in its corresponding nanosheet column H.

[0196] See you again Figures 1 to 3In some embodiments, the bit line BL can be formed by the following method: First, after forming the data storage element 24, at least the first dielectric layer 16, the second dielectric layer 15, and the nanosheet 181 can be etched along the second direction to form a plurality of second openings K2 spaced apart along the third direction and extending along the second direction. The second openings K2 penetrate a plurality of nanosheet groups 18 of a nanosheet column H along the second direction. The second openings K2 may not penetrate the first dielectric layer 16 located at the bottom layer to avoid the bit line BL formed subsequently from contacting the substrate 10 and causing a short circuit. Then, the bit line BL is formed in the second opening. A bit line BL can penetrate a plurality of nanosheet groups 18 of a corresponding nanosheet column H along the second direction, thereby achieving electrical connection with the first source / drain region 232 of the nanosheet 181.

[0197] However, it is not limited to this. A similar method can be used to form the bit line BL after forming the stacked structure ST and before forming the data storage element 24 to increase the applicability of the scenario.

[0198] In this embodiment of the present disclosure, a memory cell transistor 20 and a data storage element 24 can constitute a memory cell for storing data. The memory cell transistor 20 includes multiple nanosheets 181 and a gate layer 13 that controls the multiple nanosheets 181 simultaneously. The arrangement of the multiple nanosheets 181 is equivalent to paralleling the conductive channels in multiple channel regions 231, increasing the current conduction path, thereby increasing the drive current (Idsat) of the memory cell transistor 20, and thus improving the switching speed of the memory cell transistor 20. When the memory cell transistor 20 is in the off state, the conductive channels in the channel region 231 can be more thoroughly "pinched off", so that the leakage path between the source and drain of the memory cell transistor 20 (i.e., the first source / drain region 232 and the second source / drain region 233) is effectively blocked, significantly reducing the turn-off leakage current (Ioff) of the memory cell transistor 20, thereby improving the electrical performance of the memory cell.

[0199] In some embodiments, each nanosheet group 18 may include two or three nanosheets 181. This configuration can effectively increase the drive current of the memory cell transistor 20 and reduce the turn-off leakage current of the memory cell transistor 20.

[0200] In some embodiments, the thickness of each nanosheet 181 in the second direction can range from 5 nm to 6 nm; when multiple nanosheets 181 of the nanosheet group 18 are arranged at intervals along the second direction, the multiple nanosheets 181 of the nanosheet group 18 can be distributed at equal or approximately equal intervals in the second direction, and in a nanosheet group 18, the distance between the upper surface of the uppermost nanosheet 181 and the lower surface of the lowermost nanosheet 181 can be around 40 nm.

[0201] Figures 12 to 34 ,as well as Figures 1 to 3 The resulting word line WL extends along the third direction, and the bit line BL extends along the second direction. However, this is not the only variation; see [link to relevant documentation]. Figures 35 to 49 ,as well as Figures 5 to 7 In other embodiments of this disclosure, word lines WL extending along a second direction and bit lines BL extending along a third direction may also be formed.

[0202] Specifically, such as Figure 35 As shown, in the formation of Figures 10 to 11 After the stacked material layer ST'' shown, the method may further include: removing the second semiconductor layer 122 to form a first gap S1, and filling the first gap S1 with a first dielectric layer 16.

[0203] Next, as Figure 36 As shown, the method may further include: removing the third semiconductor layer 123 to form a second gap S2, and filling the second gap S2 with a second dielectric layer 15.

[0204] Thus, the initial stacked structure ST' is formed.

[0205] Next, as Figures 37 to 40 As shown, after forming the initial stacked structure ST', the method may further include: forming a plurality of bit lines BL, each bit line BL extending along a third direction, and the plurality of bit lines BL being arranged along a second direction.

[0206] Specifically, multiple bit lines (BLs) can be formed using the following method: First, as... Figures 37 to 38 As shown, one end of the stacked layer 17 in the first direction can be removed to form a third trench T3 extending in the third direction between adjacent first dielectric layers 16; the number of third trenches T3 is multiple, the multiple third trenches T3 are arranged along the second direction, and adjacent third trenches T3 in the second direction are spaced apart by the first dielectric layer 16; then, as Figures 39 to 40 As shown, bit lines BL are formed in the third trench T3, and each bit line BL is electrically connected to a plurality of first semiconductor layers 121 located between adjacent first dielectric layers 16.

[0207] Next, as Figure 41 and Figure 42 As shown, after forming bit lines BL, the method may further include: etching the remaining initial stacked structures ST' to form a plurality of stacked structures ST arranged along a third direction, and a first trench T1 located between two adjacent stacked structures ST, defining a first semiconductor layer 121 in the stacked structure ST as an initial nanosheet 181', and electrically connecting each bit line BL to the end of the plurality of initial nanosheets 181' located between adjacent first dielectric layers 16.

[0208] Next, as Figure 43 As shown, the method also includes forming an isolation layer 19 within the first trench T1.

[0209] Next, as Figures 44 to 47 As shown, the method also includes: forming multiple word lines WL, each word line WL extending along a second direction, and the multiple word lines WL being arranged along a third direction.

[0210] Specifically, the word line WL can be formed using the following method: First, as... Figure 44 and Figure 45 As shown, after forming the stacked structure ST and the isolation layer 19, the first dielectric layer 16, the second dielectric layer 15, and the isolation layer 19 are etched along the second direction to form a plurality of third openings K3 arranged along the third direction and extending along the second direction. The edge of the third opening K3 in the third direction extends beyond the edge of the initial nanosheet 181' in the third direction, thus facilitating the removal of the first dielectric layer 16 and the second dielectric layer 15 located within the range of the third opening K3 to expose the surface of the initial nanosheet 181'.

[0211] Next, as Figure 46 and Figure 47 As shown, the character line WL is formed within the third opening K3.

[0212] In some embodiments, the third opening K3 may extend along the second direction into the bottom first dielectric layer 16, thereby surrounding the plurality of initial nanosheets 181' along the second direction, and the word line WL formed therein also surrounds the plurality of initial nanosheets 181' along the second direction to improve the gate control capability of the word line WL. In some embodiments, the third opening K3 may not completely penetrate the bottom first dielectric layer 16 to avoid short circuits caused by contact between the word line WL and the substrate 10.

[0213] Next, as Figure 48 As shown, the method further includes: removing a portion of the initial nanosheets 181' and a portion of the second dielectric layer 15 along the first direction to form a second trench T2 extending along the first direction between adjacent first dielectric layers 16, the remaining initial nanosheets 181' constituting nanosheets 181, and a plurality of nanosheets 181 located between adjacent first dielectric layers 16 constituting a nanosheet group 18.

[0214] Next, as Figure 49 As shown, the method further includes performing an epitaxial process from the second trench T2 to form an epitaxial layer 21, the epitaxial layer 21 at least covering the sidewalls of the plurality of nanosheets 181 in the nanosheet group 18 exposed by the second trench T2.

[0215] Next, as Figures 5 to 8 As shown, a data storage element 24 is formed that is at least partially located within the second trench T2.

[0216] In some embodiments, after forming the nanosheet assembly 18, the following methods may also be employed: Figures 44 to 47 A similar method is used to form the word line WL.

[0217] like Figures 5 to 8 As shown, in some embodiments, each word line WL corresponds to a nanosheet column H, and each word line WL covers a portion of the surface of a plurality of nanosheets 181 in its corresponding nanosheet column H. The word line WL covers a portion of the plurality of nanosheets 181 in each nanosheet group 18, forming the gate layer 13 of the memory cell transistor 20. The plurality of gate layers 13 in each nanosheet column H are sequentially connected along the second direction to form the word line WL, and the portion of the nanosheets 181 covered by the word line forms the channel region 231.

[0218] In some embodiments, the nanosheet 181 further includes a first source / drain region 232, wherein a portion of the nanosheet 181 located between the channel region 231 and the bit line BL constitutes the first source / drain region 232, and the first source / drain region 232 is located on the side of the channel region 231 away from the data storage element 24 along a first direction; wherein each bit line BL corresponds to a nanosheet row L, and each bit line BL is electrically connected to a plurality of first source / drain regions 232 in its corresponding nanosheet row L.

[0219] The technical features described in the above embodiments can be arbitrarily combined without conflict. Those skilled in the art can change the order of the above-described forming method steps without departing from the protection scope of this disclosure. In the embodiments of this disclosure, some steps can be executed simultaneously or sequentially without conflict.

[0220] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, and a plurality of memory cell transistors are formed on the substrate; wherein forming the memory cell transistors includes: forming an initial stacked structure on the substrate, the initial stacked structure including first dielectric layers and stacked layers alternately stacked along a second direction, the stacked layers including a plurality of first semiconductor layers stacked along the second direction, and a second dielectric layer located at least between two adjacent first semiconductor layers; patterning the initial stacked structure to form a plurality of stacked structures extending along a first direction and arranged along a third direction, defining the first semiconductor layers in the stacked structures as initial nanosheets; removing a portion of the initial nanosheets and a portion of the second dielectric layer along the first direction to form a second trench extending along the first direction between adjacent first dielectric layers, the remaining initial nanosheets constituting nanosheets, the plurality of nanosheets being spaced apart and extending along the first direction, the plurality of nanosheets located between adjacent first dielectric layers constituting a nanosheet group, the nanosheets including channel regions; forming a gate layer, the gate layer covering the plurality of channel regions of the nanosheet group; the third direction intersects the first direction and is parallel to the surface of the substrate, the second direction being perpendicular to the surface of the substrate; Multiple data storage elements are formed, the data storage elements are located on one side of the nanosheet group along the first direction and are at least partially located in the second trench, and each of the data storage elements is electrically connected to a plurality of the nanosheets of a memory cell transistor.

2. The manufacturing method according to claim 1, characterized in that, The stacked structures have a first trench between them, and the second trench is located on one side of the nanosheet group in the first direction and exposes the sidewalls of a plurality of the nanosheets in the nanosheet group. Before forming the second trench, the method further includes filling the first trench with an isolation layer.

3. The manufacturing method according to claim 1, characterized in that, Prior to forming the data storage element, the method further includes performing an epitaxial process from the second trench to form an epitaxial layer, the epitaxial layer at least covering the sidewalls of a plurality of nanosheets in the nanosheet group exposed by the second trench, the data storage element being contacted and connected to the epitaxial layer.

4. The manufacturing method according to claim 1 or 3, characterized in that, The nanosheet groups are arranged into multiple nanosheet rows and multiple nanosheet columns. The nanosheet rows extend along the third direction, and each nanosheet row includes multiple nanosheet groups spaced apart along the third direction. The nanosheet columns extend along the second direction, and each nanosheet column includes multiple nanosheet groups spaced apart along the second direction. Forming the gate layer includes: Multiple character lines are formed, each character line extending along the second direction, and the multiple character lines are arranged along the third direction; wherein... Each word line corresponds to a nanosheet column, and each word line covers a portion of the surface of a plurality of nanosheets in its corresponding nanosheet column. The word line covers a portion of a plurality of nanosheets in each nanosheet group, forming the gate layer of the memory cell transistor. The plurality of gate layers in each nanosheet column are sequentially connected along the second direction to form the word line, and the portion of the nanosheet covered by the word line forms the channel region.

5. The manufacturing method according to claim 4, characterized in that, The nanosheet further includes a first source / drain region located along the first direction on the side of the channel region away from the data storage element; the method further includes: forming a plurality of bit lines, each bit line extending along the third direction, and the plurality of bit lines arranged along the second direction; wherein each bit line corresponds to a row of nanosheets, and each bit line is electrically connected to a plurality of the first source / drain regions in the corresponding row of nanosheets.

6. The manufacturing method according to claim 1 or 3, characterized in that, The nanosheet groups are arranged into multiple nanosheet rows and multiple nanosheet columns. The nanosheet rows extend along the third direction, and each nanosheet row includes multiple nanosheet groups spaced apart along the third direction. The nanosheet columns extend along the second direction, and each nanosheet column includes multiple nanosheet groups spaced apart along the second direction. Forming the gate layer includes: Multiple character lines are formed, each character line extending along the third direction, and the multiple character lines are arranged along the second direction; wherein... Each word line corresponds to a row of nanosheets, and each word line covers a portion of the surface of a plurality of nanosheets in its corresponding row of nanosheets. The word line covers a portion of a plurality of nanosheets in each group of nanosheets, forming the gate layer of the memory cell transistor. The plurality of gate layers in each row of nanosheets are sequentially connected along the third direction to form the word line, and the portion of the nanosheet covered by the word line forms the channel region.

7. The manufacturing method according to claim 6, characterized in that, The nanosheet further includes a first source / drain region located along the first direction on the side of the channel region away from the data storage element; the method further includes: forming a plurality of bit lines, each bit line extending along the second direction, and the plurality of bit lines arranged along the third direction; wherein each bit line corresponds to a nanosheet column, and each bit line is electrically connected to a plurality of the first source / drain regions in the nanosheet column corresponding to it.

8. The manufacturing method according to claim 1, characterized in that, Forming the initial stacked structure on the substrate includes: A stacked material layer is formed on the substrate, the stacked material layer comprising second semiconductor layers and an initial stacked layer alternately stacked along the second direction, the initial stacked layer comprising a plurality of first semiconductor layers stacked along the second direction, and a third semiconductor layer located at least between two adjacent first semiconductor layers; At least a portion of the second semiconductor layer is removed to form a first gap; The first dielectric layer is filled into the first gap; At least a portion of the third semiconductor layer is removed to form a second gap; The second dielectric layer is filled into the second gap.

9. The manufacturing method according to claim 8, characterized in that, Both the second and third semiconductor layers are made of silicon-germanium, wherein the atomic percentage of germanium atoms in the second semiconductor layer is between 0.2 and 0.5, and the atomic percentage of germanium atoms in the third semiconductor layer is between 0.1 and 0.2; and / or, In the step of removing at least a portion of the second semiconductor layer, the etch selectivity ratio of the second semiconductor layer to the third semiconductor layer is greater than or equal to 100; and / or, In the step of removing at least a portion of the third semiconductor layer, the etching selectivity ratio of the third semiconductor layer to the first semiconductor layer is greater than or equal to 100.

10. A semiconductor structure, characterized in that, The semiconductor structure is manufactured using the method described in any one of claims 1-9, and the semiconductor structure comprises: A substrate, and a plurality of memory cell transistors located on the substrate, each of the memory cell transistors comprising: a nanosheet group comprising a plurality of spaced nanosheets extending along a first direction, the nanosheets comprising a channel region; a gate layer covering the plurality of channel regions of the nanosheet group; the first direction being parallel to the surface of the substrate; Multiple data storage elements are located on one side of the nanosheet group along the first direction, and each of the data storage elements is electrically connected to multiple of the nanosheets of a memory cell transistor.

11. The semiconductor structure according to claim 10, characterized in that, The memory cell transistor further includes an epitaxial layer that covers at least one of the nanosheets in the nanosheet group near the sidewall of the data storage element, and the data storage element is in contact with the epitaxial layer.

12. The semiconductor structure according to claim 10, characterized in that, Each of the nanosheet groups comprises two or three nanosheets; and / or, a plurality of nanosheets in each of the nanosheet groups are spaced apart along a second direction; the second direction is perpendicular to the surface of the substrate.

13. The semiconductor structure according to any one of claims 10-12, characterized in that, The plurality of memory cell transistors are arranged in a plurality of transistor rows and a plurality of transistor columns, the transistor rows extending along a third direction, and each transistor row including a plurality of memory cell transistors spaced apart along the third direction; The third direction intersects the first direction and is parallel to the surface of the substrate; The transistor columns extend along a second direction, and each transistor column includes a plurality of memory cell transistors spaced apart along the second direction; the second direction is perpendicular to the surface of the substrate.

14. The semiconductor structure according to claim 13, characterized in that, The gate layer extends along the second direction, and multiple gate layers of each transistor column are sequentially connected along the second direction to form word lines. The number of word lines is multiple, and the multiple word lines extend along the second direction and are arranged along the third direction. The nanosheet further includes a first source / drain region, which is located along the first direction on the side of the channel region opposite to the data storage element; The semiconductor structure further includes: a plurality of bit lines, each bit line extending along the third direction and the plurality of bit lines arranged along the second direction, each bit line corresponding to a transistor row, and each bit line electrically connected to a plurality of first source / drain regions in the corresponding transistor row.

15. The semiconductor structure according to claim 13, characterized in that, The gate layer extends along the third direction, and the multiple gate layers of each transistor row are sequentially connected along the third direction to form a word line. The number of word lines is multiple, and the multiple word lines extend along the third direction and are arranged along the second direction. The nanosheet further includes a first source / drain region, which is located along the first direction on the side of the channel region opposite to the data storage element; The semiconductor structure further includes: a plurality of bit lines, each bit line extending along the second direction and the plurality of bit lines arranged along the third direction, each bit line corresponding to a transistor column, and each bit line electrically connected to a plurality of first source / drain regions in the corresponding transistor column.

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