Split gate MOSFET with reduced on-resistance

Abstract

The invention relates to a split gate MOSFET with reduced on resistance. The electronic device includes: a semiconductor body; a trench extending within the semiconductor body from a first side toward a second side of the semiconductor body and terminating within the semiconductor body; an insulating field plate region in each of the trenches; a conductive gate region in each of the trenches on the respective insulating field plate region, electrically insulated from the semiconductor body by the respective insulating field plate region, respectively; a field plate region in each of the trenches, buried in the respective insulating field plate region and electrically insulated from the respective conductive gate region and the semiconductor body; a gate interconnect extends within the semiconductor body transversely to the trench from the first side toward the second side and terminates in the semiconductor body.

Description

Split-gate MOSFET with reduced on-resistance Technical Field

[0001] This invention relates to split-gate MOSFETs with reduced on-resistance, and more particularly to an electronic device with a gate interconnect that increases the channel perimeter and conductive area without requiring adjustments to the manufacturing process dimensions or high lithographic resolution. Furthermore, this invention relates to the manufacturing process of the electronic device. Background Technology

[0002] MOSFET ("Metal-Oxide-Semiconductor Field-Effect Transistor") technology is now widely recognized as an excellent option for several applications, such as switches in power management circuits.

[0003] Vertically diffused MOSFETs (VDMOS), which have been commercially available for decades, have seen significant commercial adoption due to their improved electrical performance. However, the high on-resistance of VDMOSFETs has long limited their current handling capabilities.

[0004] This problem has been overcome with "trench gate" MOSFETs. Due to the vertical channel, these devices allow for reduced cell pitch without negatively impacting current diffusion. Specifically, the introduction of devices using a field plate insulated from the gate electrode and connected to the source potential as an extension of the gate electrode achieves lateral depletion of the off-state drift region. Because the field plate is electrically insulated from the gate electrode, this structure is also known as a "shielded gate" or "split gate" structure.

[0005] Compared to previous MOSFETs, split-gate technology offers significant advantages, such as improved on-resistance relative to the active region extension and reduced gate-drain capacitance. In fact, the split-gate structure allows for the use of high doping concentrations, thereby significantly improving MOSFET performance.

[0006] As is well known, one of the main goals in developing split-gate power MOSFET devices is to reduce on-resistance.

[0007] This can be achieved in existing technologies by reducing the main resistance contribution and / or by increasing the ratio between the conductive area and the channel perimeter relative to the total device area.

[0008] However, since the basic cell in the known technical solutions is strip-shaped, the main limitation of these solutions is reducing the size of the MOSFET's basic cell. This requires adjusting the size of the diffusion process and increasing the lithography resolution to reduce the lateral dimension of the strip. Clearly, this means significant additional costs and difficulties during the manufacturing process. Summary of the Invention

[0009] Embodiments of this disclosure provide an electronic device and a manufacturing process for the electronic device that overcome the shortcomings of the prior art, particularly achieving a significant increase in channel perimeter and conductive area without requiring adjustments to process dimensions or high lithography resolution. According to this disclosure, an electronic device and a manufacturing process for the electronic device are provided.

[0010] In some embodiments, an electronic device includes: a semiconductor body having a first side and a second side opposite to each other along a first axis; a plurality of trenches extending from the first side toward the second side within the semiconductor body and terminating within the semiconductor body; and a corresponding insulating field plate region in each of the trenches, covering the lower wall and sidewalls of the corresponding trench. The device includes a corresponding conductive gate region in each of the trenches on the corresponding insulating field plate region, each conductive gate region being made of a conductive material and electrically insulated from the semiconductor body by the corresponding insulating field plate region. The device includes a corresponding field plate region in each of the trenches, each field plate region being embedded in the corresponding insulating field plate region and electrically insulated from the corresponding conductive gate region and the semiconductor body by the corresponding insulating field plate region. The device includes a plurality of gate interconnects extending laterally through the trenches from the first side toward the second side within the semiconductor body and terminating within the semiconductor body, the gate interconnects being made of a conductive material, electrically insulated from the semiconductor body, and electrically connected to the conductive gate regions to electrically interconnect the conductive gate regions with each other.

[0011] In some embodiments, a process for manufacturing an electronic device includes forming a plurality of trenches within a semiconductor body having a first side and a second side opposite to each other along a first axis, the trenches extending from the first side toward the second side and terminating within the semiconductor body. The process includes forming a respective insulating field plate region in each of the trenches, covering the lower wall and sidewalls of the respective trench, and forming a respective field plate region in each of the trenches, each field plate region being embedded within and electrically insulated from the semiconductor body by the respective insulating field plate region. The process includes forming a respective conductive gate region on the respective insulating field plate region, in each of the trenches, each conductive gate region being made of a conductive material and electrically insulated from the semiconductor body and the respective field plate region by the respective insulating field plate region. The process includes forming a plurality of gate interconnects extending laterally through the trenches from the first side toward the second side within the semiconductor body and terminating within the semiconductor body, the gate interconnects being made of a conductive material, electrically insulated from the semiconductor body, and electrically connected to the conductive gate regions to electrically interconnect the conductive gate regions with each other.

[0012] In some embodiments, a method includes forming a semiconductor body of a first conductivity type, forming a plurality of trenches extending and terminating within the semiconductor body, forming a plurality of insulating field plate regions, each in a respective trench, and forming a plurality of respective conductive gate regions, each in a respective trench. The method further includes forming a plurality of field plate regions, each in a respective trench and electrically insulated from the respective conductive gate regions and the semiconductor body via the respective insulating field plate regions, and forming a plurality of gate interconnects extending adjacent to the trenches within the semiconductor body, terminating within the semiconductor body, electrically insulated from the semiconductor body, and electrically interconnecting the conductive gate regions. Attached Figure Description

[0013] To better understand the invention, preferred embodiments will now be described by way of non-limiting example with reference to the accompanying drawings, in which:

[0014] Figure 1 shows a schematic perspective view along two different cross-sectional lines of an electronic device according to one embodiment;

[0015] Figures 2A to 2C show top views of the electronic device of Figure 1 according to corresponding embodiments;

[0016] Figure 3 shows schematic perspective views along two different cross-sectional lines of an existing electronic device according to different embodiments;

[0017] Figures 4A to 4M show schematic perspective views along two different cross-sectional lines of the manufacturing steps of the electronic device of Figure 1 according to one embodiment; and

[0018] Figures 5A to 5S show schematic perspective views of two different cross-sectional lines along the manufacturing steps of the electronic device in Figure 3 according to different embodiments.

[0019] In particular, these figures are illustrated with reference to a three-axis Cartesian system defined by mutually orthogonal X, Y, and Z axes.

[0020] In the following description, elements common to different embodiments are indicated by the same reference numerals. Detailed Implementation

[0021] Figure 1 shows an electronic device 10, specifically a power MOSFET. In particular, electronic device 10 is of the "split-gate" type, also known as the "shielded-gate" type. Electronic device 10 will be more simply referred to below as MOSFET 10.

[0022] MOSFET 10 is shown in Figure 1 in cross-sectional view along two different profile lines. Specifically, the left profile in Figure 1 is taken along profile line AA shown in Figure 2A, while the right profile in Figure 1 is taken along profile line BB shown in Figure 2A.

[0023] In detail, the MOSFET 10 includes a semiconductor body 12 having a first side and a second side (or upper side and lower side) 12a, 12b opposite to each other along the Z-axis direction and a first conductivity type (illustratively N in the following text).

[0024] On the first side 12a, the MOSFET 10 also includes multiple trenches (or "field plates" or "trenches") 13 in the semiconductor body 12.

[0025] As shown in Figures 2A to 2C and better described below, in the top view (i.e., parallel to the XY plane defined by axes X and Y), the groove 13 has a closed polygonal shape (such as a hexagonal shape, a square shape, etc.) and is arranged in a matrix.

[0026] Referring again to Figure 1, the MOSFET 10 includes a corresponding oxide region (or insulating field plate region) 14 extending at the lower wall and sidewall of the trench 13 for each trench 13.

[0027] For each trench 13, the MOSFET 10 also includes a corresponding conductive gate region (or more simply, a gate region) 15 within the trench 13. Specifically, an oxide region 14 extends below and around the gate region 15 such that the gate region 15 is electrically insulated from the semiconductor body 12 via the oxide region 14.

[0028] For each trench 13, the MOSFET 10 also includes a corresponding field plate region 16 made of a conductive material, such as N-doped polysilicon. The field plate region (more simply referred to as the field plate below) 16 extends within the corresponding trench 13 and is buried within an oxide region 14 to electrically insulate it from the conductive gate region 15 via a portion of the oxide region 14. A first portion 16a of the field plate 16 extends below the conductive gate region 15 without making electrical or physical contact with it.

[0029] In the embodiment of FIG1, in addition, the second portion 16b of the field plate 16, which is continuous with the first portion 16a and stacked on the first portion 16a along the Z-axis direction, extends within the conductive gate region 15 to traverse the conductive gate region 15 along the Z-axis direction, and is physically and electrically separated from the conductive gate region 15 by a portion of the oxide region 14.

[0030] The field plate 16 is used to reduce the electric field in the semiconductor body 12 near the trench 13 and reduce parasitic capacitance.

[0031] Each component of the conductive gate region 15 and the oxide region 14 forms a corresponding gate structure 22 of the MOSFET 10. Since the field plate 16 is electrically insulated from the conductive gate region 15, the gate structure 22 of the MOSFET 10 is referred to as a “shielded gate” or “split gate” structure.

[0032] For each trench 13, the MOSFET 10 also includes a corresponding upper oxide region 18 extending over the trench 13 and over the conductive gate region 15. In particular, the upper oxide region 18 is not vertically stacked with the second portion 16b of the field plate 16 (i.e., aligned along the Z-axis); in other words, the upper oxide region 18 has a through opening 18' that runs through it along the Z-axis and is vertically stacked on the second portion 16b of the field plate 16.

[0033] For each trench 13, the MOSFET 10 also includes a corresponding plurality of body regions 17 having a second conductivity type (illustratively P-type here). In particular, the number of body regions 17 for each trench 13 is equal to the number of sides of the closed polygonal shape of the trench 13 in a top view, such that each body region 17 is associated with a corresponding side of the trench 13, as better described below.

[0034] Body regions 17 are housed within semiconductor bodies 12, transverse to the corresponding trenches 13, and extend around the trenches 13 to surround them without maintaining continuity, and face the first side 12a of the semiconductor body 12. For example, in the cross-section of FIG1, two body regions 17 are shown adjacent to the opposite (along the Y-axis) sides of the trenches 13. As better shown in FIG2A, thus, in the top view, at the level of the first side 12a of the semiconductor body 12, each body region 17 is inserted between the two trenches 13 that are closest to each other in the matrix arrangement.

[0035] In detail, a portion of the oxide region 14 extends between the body region 17 and the corresponding conductive gate region 15, such that the conductive gate region 15 is electrically insulated from the corresponding body region 17.

[0036] For each trench 13, the MOSFET 10 also includes a corresponding plurality of source regions 20 having a first conductivity type (illustratively N-type here). In particular, the number of source regions 20 for each trench 13 is equal to the number of sides of the closed polygonal shape of the trench 13 in a top view, such that each source region 20 is associated with a corresponding side of the trench 13, as better described below.

[0037] Each source region 20 extends over a corresponding body region 17, located at the radially outer portion of the latter. In other words, each source region 20 has a through opening 20' that traverses the source region 20 along the Z-axis and is vertically stacked on the radially inner (or central) portion of the corresponding body region 17 to expose it. More specifically, in the top view, the source region 20 is annular in type and is vertically stacked on the radially outer portion of the corresponding body region 17, while the radially inner portion of the corresponding body region 17 is exposed through the through opening 20'.

[0038] Therefore, the source region 20 is housed within the semiconductor body 12, transverse to the corresponding trench 13, and extends around the trench 13 to surround the trench 13 without maintaining continuity, and is located on the first side 12a of the semiconductor body 12. For example, in the cross-section of FIG1, two source regions 20 are shown for each trench 13, adjacent to the opposite (along the Y-axis) sides of the trench 13. As better shown in FIG2A, thus, in the top view, at the level of the first side 12a of the semiconductor body 12, each source region 20 is inserted between the two trenches 13 that are closest to each other in the matrix arrangement.

[0039] In detail, the portion of oxide region 14 extending between body region 17 and corresponding conductive gate region 15 also extends between source region 20 and corresponding conductive gate region 15, such that conductive gate region 15 is electrically insulated from corresponding source region 20.

[0040] The MOSFET 10 also includes a source metallization portion 24 extending over the upper oxide region 18, over the body region 17 exposed by the through-opening 20' of the source region 20, and over a second portion 16b of the field plate 16 exposed by the through-opening 18' of the upper oxide region 8. More specifically, the source metallization portion 24 includes a body 24a extending over the upper oxide region 18, a corresponding first metallization portion 24b extending over the corresponding body region 17 exposed by the through-opening 20' of the source region 20, and a corresponding second metallization portion 24c extending over the second portion 16b of the field plate 16 exposed by the through-opening 18' of the upper oxide region 18; in particular, the body 24a extends continuously with the first metallization portion 24b and the second metallization portion 24c. Therefore, the source metallization portion 24 is in direct electrical contact with the body region 17, the source region 20, and the field plate 16.

[0041] In use, the source metallization section 24 operates as a source electrode and can be biased to the source voltage V. S (For example, ground voltage), the source voltage can be used to bias the body region 17, the source region 20 and the field plate 16.

[0042] In addition, the MOSFET 10 also includes a drain metallization 26 that extends in contact with the semiconductor body 12 on the second side 12b.

[0043] In use, the drain metallization section 26 operates as the drain electrode and can be biased to the drain voltage V. D The semiconductor body 12 can be biased using this drain voltage.

[0044] In addition, the MOSFET 10 also includes a gate metallization that extends in contact with the gate region 15, as not shown.

[0045] In use, the gate metallization operates as the gate electrode and can be biased to the gate voltage V. G The gate region 15 can be biased using this gate voltage.

[0046] In detail, Figure 1 shows the active region 11 of the MOSFET 10, which comprises multiple cells, each defined by a corresponding trench 13. Outside the active region 11, i.e., beyond the edge termination region (not shown as is known), there are side surfaces of the semiconductor body, extending substantially orthogonally to the first side, for example. These side surfaces are formed after a dicing step of the SiC wafer, in which multiple MOSFETs 10 are formed. The dicing step serves to separate the MOSFET 10 from another MOSFET 10 on the same wafer. The dicing occurs at a scribe line (not shown) on the SiC wafer from which the MOSFETs 10 are obtained. This scribe line surrounds the active region 11 at a distance in the XY plane and extends, for example, from the outside to a guard ring (not shown), which surrounds the active region 11 in the top view.

[0047] Referring to Figure 1, the MOSFET 10 also includes a gate interconnect 28 that extends between the gate regions 15 and is in physical and electrical contact with the gate regions 15 so that they are in electrical contact with each other.

[0048] In this way, the gate metallization can be made to directly contact only a portion of the gate region 15 (e.g., those portions placed on the outer periphery of the active region 11 of the MOSFET 10 in the top view), while still allowing all gate regions 15 to be biased via the gate interconnect 28.

[0049] Specifically, gate interconnects 28 connect gate regions 15 arranged side by side, and in detail, in the matrix arrangement in the top view, gate regions 15 are closest to each other.

[0050] In detail, the MOSFET 10 has interconnect trenches 31 that extend in the semiconductor body 12 from a first side 12a toward a second side 12b without reaching the latter. The interconnect trenches 31 communicate with trenches 13, that is, they are open in the trenches 13 to define an interconnect network that joins the trenches 13 together at the level of the first side 12a.

[0051] More specifically, the lower surface of the interconnect trench 31 is substantially flush with the lower surface of the gate region 15 along the Z-axis. The shape of the interconnect trench 31 is shown in the top view and will be discussed more in detail below with reference to Figures 2A to 2C.

[0052] Gate interconnects 28 are housed in interconnect trenches 31 and are electrically insulated from semiconductor bodies 12, source regions 20, and body regions 17 by insulating interconnect portions 29 of insulating material, which also extend within interconnect trenches 31. Specifically, each insulating interconnect portion 29 extends laterally below the corresponding gate interconnect 28 to be inserted between the gate interconnect 28 and the semiconductor body 12. In detail, the insulating interconnect portions 29 extend continuously with the oxide regions 14 to which they are connected.

[0053] Therefore, each gate interconnect 28 together with the corresponding insulating interconnect portion 29 forms a corresponding insulating interconnect structure 30 that is accommodated in the corresponding interconnect trench 31.

[0054] As shown in Figure 1, the gate interconnect 28 extends on the first side 12a of the semiconductor body 12, particularly flush with the gate region 15.

[0055] The gate interconnects 28 are continuous with the gate regions 15 to which they are coupled, and are made of the same material as the gate regions 15 in detail, so as to extend in a continuous manner relative to the latter.

[0056] In particular, the thickness of the gate interconnect 28, measured along the Z-axis, can be approximately equal to the thickness of the gate region 15.

[0057] For purely illustrative and non-limiting purposes, the thickness of the gate interconnect 28 may be between about 0.5 µm and about 0.7 µm, and its width, measured in the XY plane along a direction orthogonal to the main extension of the gate interconnect 28, may be between about 0.15 µm and about 0.25 µm. The length of the gate interconnect 28, measured in the XY plane along the main extension of the gate interconnect 28, depends, in a manner that is self-evident, on the mutual distance between the trenches 13, as can be better envisioned by reference to Figures 2A to 2C below.

[0058] Similarly, and also for purely illustrative and non-limiting purposes, the thickness of the interconnect trench 31 along the Z-axis may be between approximately 0.6 µm and approximately 0.8 µm, and the width measured in the XY plane along a direction orthogonal to the main extension of the interconnect trench 31 may be between approximately 0.25 µm and approximately 0.35 µm (in other words, the oxide thickness of the insulating interconnect portion 29 is approximately 50 nm). The length of the interconnect trench 31, measured in the XY plane along the main extension of the interconnect trench 31, depends in a manner that is inherently obvious on its own on the relative distances between the trenches 13, as can be better envisioned by reference to Figures 2A to 2C below.

[0059] The shape and arrangement of the gate interconnect 28 can vary, as shown in Figures 2A to 2C.

[0060] In detail, Figures 2A to 2C show top views of the corresponding embodiments of the MOSFET 10, which are considered to be at the layer of the first side 12a of the semiconductor body 12.

[0061] In the embodiment of FIG2A, the trench 13, as well as the gate region 15 and the gate structure 22, generally have a hexagonal shape parallel to the XY plane.

[0062] In Figure 2A, each vertex of each gate region 15 is connected to a corresponding gate interconnect 28, such that each gate interconnect 28 connects the three gate regions 15 to each other, and in the view of Figure 2A, these gate regions 15 are arranged in a triangle.

[0063] In detail, each gate interconnect 28 has three arms, each arm having a corresponding first end and a second end opposite to each other. In each gate interconnect 28, the first ends of the three arms are joined together to form a joint portion of the gate interconnect 28. In a top view, the three arms extend radially from the joint portion and are spaced apart from each other at equal angles. The second end of each arm is connected to a corresponding vertex of one of the three gate regions 15, which, in a top view, surrounds the gate interconnect 28 under consideration.

[0064] In this way, each mesa region (defined in the top view of FIG2A by the corresponding source region 20, which also has a hexagonal shape in the view of FIG2A) has: two sides opposite to each other, which contact the two sides of the two corresponding gate structures 22 that are first adjacent in the matrix arrangement; and four sides that contact the two corresponding insulated interconnect structures 30 in a two-to-two manner (specifically, a first pair of adjacent sides that contact the two corresponding arms of the insulated interconnect structure 30, and a second pair of adjacent sides that are opposite to the first pair of sides and contact the two corresponding arms of the other insulated interconnect structure 30).

[0065] In other words, in Figure 2A, the gate interconnects 28 are not directly coupled to each other, but are coupled to each other through the gate regions 15 to define the interconnect network of the gate regions 15 and the gate interconnects 28.

[0066] In the embodiment of FIG2B, the trench 13, as well as the gate region 15 and the gate structure 22, generally have a square shape parallel to the XY plane and are arranged in a manner that is parallel to both the X-axis and the Y-axis and aligned with each other.

[0067] In Figure 2B, each vertex of each gate region 15 is connected to a corresponding gate interconnect 28. The gate interconnects 28 are grouped into four groups of gate interconnects, and each group defines a corresponding square annular closed path that connects the four corresponding gate regions 15, which are arranged in a 2x2 configuration in the matrix under consideration.

[0068] In detail, each group of gate interconnects 28 includes two gate interconnects 28 having a main extension along the X-axis and two gate interconnects 28 having a main extension along the Y-axis. In each group, the ends of the gate interconnects 28 are engaged with each other by alternating horizontal gate interconnects 28 and vertical gate interconnects 28 to define a square annular closed path. For each group, four corresponding gate regions 15 are respectively coupled to the corresponding vertices of the gate interconnect group 28.

[0069] In other words, in Figure 2B, the different groups of gate interconnects 28 are not directly coupled to each other, but are coupled to each other through gate regions 15 to define the interconnect network of gate regions 15 and gate interconnects 28.

[0070] In the embodiment of FIG2C, the trench 13, as well as the gate region 15 and gate structure 22, generally have a square shape parallel to the XY plane and are arranged such that one axis parallel to the XY plane (illustratively parallel to the X-axis here) is aligned with each other and the other axis parallel to the XY plane is alternately aligned with each other (illustratively parallel to the Y-axis here). In other words, the gate region 15 has a checkerboard arrangement in the top view.

[0071] In Figure 2C, each vertex of each gate region 15 is connected to a corresponding gate interconnect 28, and the gate interconnects 28 are connected to each other in a manner that forms a serpentine path (more specifically, a square zigzag path).

[0072] Each serpentine path has a main extension parallel to the X-axis and extends parallel to the Y-axis between two corresponding rows of gate regions 15 so that the two rows of gate regions 15 are electrically in contact with each other, specifically, so that they are electrically in contact one after another along the serpentine path.

[0073] Specifically, in each serpentine path, the gate interconnect 28 includes a gate interconnect 28 having a main extension along the X-axis direction and a gate interconnect 28 having a main extension along the Y-axis direction, which alternate with each other in a manner that defines this square serpentine path. Specifically, for each serpentine path, the ends of the gate interconnects 28 that are continuous with each other are joined and coupled to the apex of the corresponding gate region 15.

[0074] In other words, in Figure 2C, gate interconnects 28 along the same serpentine path are directly coupled to each other, while gate interconnects 28 along different serpentine paths are not directly coupled to each other, but are coupled to each other through gate regions 15, thereby defining the interconnect network of gate regions 15 and gate interconnects 28.

[0075] Based on what has been described so far and returning to Figure 1, it is to be understood that each oxide region 14 includes a body 14a, a first oxide portion 14b, and a second oxide portion 14c. The body 14a extends below the corresponding gate region 15 and around the corresponding field plate 16. The first oxide portion 14b extends laterally and around the corresponding gate region 15 (particularly between the gate region 15 and the semiconductor body 12 and body region 17 and source region 20). The second oxide portion 14c extends laterally and is located inside the corresponding gate region 15 (particularly between the gate region 15 and the second portion 16b of the corresponding field plate 16 and the corresponding second metallized portion 24c of the source metallization portion 24). In particular, in each oxide region 14, the corresponding body 14a, the corresponding first oxide portion 14b, and the corresponding second oxide portion 14c extend continuously to each other.

[0076] Furthermore, the insulated interconnect portion 29 extends laterally below the gate interconnect 28, insulating the gate interconnect 28 from the semiconductor body 12, the source region 20, and the body region 17, and allowing it to be electrically coupled to the gate region 15. In particular, the insulated interconnect portion 29 extends continuously from the oxide region 14.

[0077] Clearly, in use, MOSFET 10 forms vertical conductive channels at the interface between body region 17 and gate region 15, and at the interface between body region 17 and gate interconnect 28, along which charge carriers move. Specifically, this second contribution is absent in currently known techniques, and when added to the first contribution, it results in a significant increase in the overall channel perimeter and channel area. This significantly reduces the on-resistance of MOSFET 10, as discussed more thoroughly below.

[0078] Figure 3 shows a MOSFET 10 according to different embodiments.

[0079] The MOSFET 10 in Figure 3 is similar to the MOSFET 10 in Figure 1, so it will not be described in detail here except to highlight its differences from the MOSFET 10 in Figure 1.

[0080] In detail, in FIG3, each upper oxide region 18 includes a body 18a and an insulating portion 18b that are continuous with each other. In the embodiment of FIG3, the body 18a is similar to the entire upper oxide region 18 of the embodiment of FIG1.

[0081] In Figure 3, each through-hole 18' extends through the body 18a of the upper oxide region 18, the gate region 15, and a portion of the body 14a of the oxide region 14 (e.g., up to approximately 0.45 µm below the lower surface of the gate region 15). In this way, the second metallization portion 24c contacts the corresponding field plate 16 at a level along the z-axis, located below the gate region 15 and situated at the body 14a of the oxide region 14.

[0082] Furthermore, for each trench 13, an insulating portion 18b extends below the body 18a of the upper oxide region 18 to traverse the gate region 15 and a portion of the body 14a of the oxide region 14. The insulating portion 18b has an annular shape in the top view and laterally surrounds the corresponding second metallized portion 24c through the entire gate region 15 and through a portion of the body 14a of the oxide region 14.

[0083] Specifically, the insulating portion 18b has a minimum width measured parallel to the XY plane (e.g., along the Y-axis), which is greater than about 50 nm, more specifically, greater than about 0.1 µm, and even more specifically, between about 0.1 µm and about 0.2 µm. This minimum width substantially corresponds to the width of the circular crown defined by the insulating portion 18b in a cross-section along the XY plane, i.e., the difference between the radius of the outer periphery (in contact with the gate region 15) and the radius of the inner periphery (in contact with the second metallization portion 24c).

[0084] The minimum width of the insulating portion 18b of the insulating material is greater than the similar minimum width of the second oxide portion 14c of the insulating material in FIG1. ​​Therefore, in FIG3, greater electrical insulation can be obtained between the source metallization portion 24 and the gate region 15, ensuring more reliable and robust operation of the MOSFET 10, and also reducing the gate-source capacitance.

[0085] Figures 4A to 4M illustrate the process for manufacturing MOSFET 10, with reference to the embodiment in Figure 1 for details.

[0086] In Figure 4A, a semiconductor substrate is provided on which an optional epitaxial layer is grown. The substrate and the epitaxial layer together form a semiconductor body 12. The substrate and the epitaxial layer are, for example, made of silicon with N-type doping.

[0087] Then, as shown in Figure 4B, the trench 13 is formed by etching the semiconductor body 12 from the upper side 12a. The etching is performed using known techniques such as RIE (Reactive Ion Etching) or DRIE (Deep Reactive Ion Etching). In the figures, the trench 13 has vertical sidewalls; depending on the process used to fabricate the trench, they may also have sloping sidewalls, for example, a truncated V-shape or a truncated inverted pyramid shape in the side view. The teachings of the invention also apply similarly to cases where the sidewalls of the trench 13 are not perfectly parallel to the Z-axis.

[0088] Then, as shown in Figure 4C, the trench 13 portion is filled with an insulating electrical material to form an insulating fill region 51, which is intended to form the body 14a of the oxide region 14. For example, in the case where the semiconductor body 12 is silicon, this step is performed by growing or depositing silicon oxide (SiO2); another insulating material can be grown or deposited based on the material of the semiconductor body 12.

[0089] Then, as shown in FIG. 4D, the step of filling trench 13 with a conductive material is performed to form a conductive region 52 in trench 13 and on semiconductor body 12. The conductive material is, for example, N-doped polysilicon, and completely fills trench 13. The conductive region 52 is intended to form field plate 16.

[0090] Then, in FIG4E, a step for removing a selective portion of the conductive region 52 is performed above the upper side 12a of the semiconductor body 12, leaving the conductive region 52 within the trench 13.

[0091] This step can be performed using CMP (chemical mechanical polishing) technology, followed by an etching step to partially etch the conductive regions 52 within the trenches 13. The conductive regions 52 are then recessed in each trench 13 until they are located below the upper side 12a. For example, the recesses of the conductive regions 52 in the trenches 13 may have a depth between approximately 50 nm and approximately 150 nm, measured from the upper side 12a.

[0092] Then, in Figure 4F, the insulating fill region 51 is partially etched on the upper side 12a to form a recess 54 in each trench 13. The material etched toward the insulating fill region 51 is selective, and the material of the conductive region 52 is retained in the trench 13. The portion of the insulating fill region 51 retained after this etching forms the body 14a of the oxide region 14.

[0093] In detail, the etching exposes a portion of the sidewall of the trench 13 between the upper side 12a of the semiconductor body 12 and the upper side of the body 14a of the oxide region 14.

[0094] Then, as shown in FIG. 4G, a mask 55 is formed on the upper side 12a of the semiconductor body 12. For example, a polymer material mask 55 covers the trench 13 and the region of the upper side 12a of the semiconductor body 12 that is not intended to accommodate the gate interconnect 28. Furthermore, the mask 55 has an opening 55' that traverses the mask 55 and exposes the region of the upper side 12a of the semiconductor body 12 intended to accommodate the gate interconnect 28. In other words, the opening 55' is vertically aligned relative to the location where the gate interconnect 28 is intended to be formed; therefore, the shape and arrangement of the opening 55' are exactly similar to those described previously with reference to the gate interconnect 28.

[0095] Then, as shown in FIG. 4H, an etching step is performed to remove selective portions of the semiconductor body 12, starting from the upper side 12a. This etching step is performed through a mask 55, and interconnect trenches 31 extending into the semiconductor body 12 from the upper side 12a are formed in the area exposed by the mask 55. Therefore, the interconnect trenches 31 are vertically aligned with the opening 55', and thus have a shape and arrangement completely similar to the opening 55'. Specifically, the ends of the interconnect trenches 31 face the trenches 13 to form an interconnect network connecting the trenches 13 to each other.

[0096] Etching is interrupted when the depth of interconnect trench 31 is similar to (more precisely, approximately equal to) the depth of recess 54. In this way, the lower wall of interconnect trench 31 is substantially at the same level as the upper wall of the body 14a of oxide region 14.

[0097] Then, as shown in Figure 4I, an oxidation step (e.g., exposing the wafer to an O2 environment) is performed to form an insulating layer 57 on the exposed surface of the semiconductor material.

[0098] This oxidation step allows the portion of the conductive region 52 that protrudes from and is therefore unprotected by the insulating fill region 51 in the trench 13 to be oxidized. This step is self-limiting and allows for the formation of embedded conductive regions in each trench 13. Each of these embedded conductive regions forms one of the field plates 16 discussed previously. Specifically, for each trench 13, the portion of the conductive region 52 protected by the insulating fill region 51 forms a first portion 16a of the field plate 16, while the portion of the conductive region 52 that protrudes from the insulating fill region 51 and remains after oxidation forms a second portion 16b of the field plate 16. Furthermore, for each trench 13, the portion of the conductive region 52 that protrudes from the insulating fill region 51 and is oxidized is intended to form a second oxide portion 14c.

[0099] This same oxidation step also results in the oxidation of the semiconductor material in the interconnect trench 31 and the remaining exposed portion of the semiconductor material on the upper side 12a of the semiconductor body 12, specifically, the oxidation of the semiconductor material on the exposed areas of the sidewalls of the trench 13. In particular, the oxidized regions of the interconnect trench 31 form the previously described insulating interconnect portion 29, while the oxidized regions of the sidewalls of the trench 13 form the previously described first oxide portion 14b.

[0100] Then, as shown in FIG4J, the steps of forming gate region 15 and gate interconnect 28 are performed. Gate region 15 is formed by depositing a conductive material (e.g., n-doped polysilicon) in recess 54, while gate interconnect 28 is formed by depositing the same conductive material (e.g., n-doped polysilicon) in interconnect trench 31.

[0101] Then, in Figure 4K, the bulk region 17 and the source region 20 are formed by implanting known P-type and N-type dopants, respectively, into the semiconductor region between the trenches 13.

[0102] Then, in Figure 4L, an upper oxide region 18 is formed on the gate region 15 and the gate interconnect 28.

[0103] In detail, firstly, for example, an upper oxide layer is formed by deposition to uniformly cover the gate region 15, gate interconnect 28, source region 20, and field plate 16. Then, the upper oxide layer is etched between trenches 13 to form a contact opening 58 in which a first metallization portion 24b will extend, and extends over the field plate 16 to form a through opening 18' in which a second metallization portion 24c will extend. Furthermore, referring again to FIG. 4L, the through opening 20' is also formed, exposing a radially inner portion of the body region 17; this is achieved by further etching toward a semiconductor material that selectively etches the upper oxide layer. Specifically, the contact opening 58 is stacked on the through opening 20'. Furthermore, the through opening 18' exposes the upper surface of the second portion 16b of the field plate 16.

[0104] Then, as shown in FIG4M, the source metallization portion 24 is formed, for example, by depositing a conductive material. Specifically, a conductive material layer is uniformly deposited on the upper oxide region 18 to form a body 24a, a first metallization portion 24b in the contact opening 58, and a second metallization portion 24c in the through opening 18'. Thus, the first metallization portion 24b contacts the body region 17 and the source region 20, while the second metallization portion 24c contacts the field plate 16.

[0105] Other steps may be performed to complete the fabrication of MOSFET 10, but these steps are not part of this invention and will not be described further.

[0106] Figures 5A to 5S illustrate the process for manufacturing MOSFET 10, with reference to the embodiment in Figure 3 for details.

[0107] In Figure 5A, a semiconductor substrate is provided on which an optional epitaxial layer is grown. The substrate and the epitaxial layer together form a semiconductor body 12. The substrate and the epitaxial layer are, for example, made of silicon with N-type doping.

[0108] Then, as shown in Figure 5B, the trench 13 is formed by etching the semiconductor body 12 from the upper side 12a. The etching is performed using known techniques such as RIE (Reactive Ion Etching) or DRIE (Deep Reactive Ion Etching). In the figures, the trench 13 has vertical sidewalls; depending on the process used to fabricate the trench, they may also have sloping sidewalls, for example, a truncated V-shape or a truncated inverted pyramid shape in the side view. The teachings of the invention also apply similarly to cases where the sidewalls of the trench 13 are not perfectly parallel to the Z-axis.

[0109] Then, in Figure 5C, trench 13 is partially filled with an electrically insulating material to form a first insulating filling region 51, which is intended to form the body 14a of oxide region 14. For example, if the semiconductor body 12 is silicon, this step is performed by growing or depositing silicon oxide (SiO2); another insulating material can be grown or deposited based on the material of the semiconductor body 12.

[0110] Next, as shown in FIG. 5D, the step of filling trench 13 with a conductive material is performed to form a conductive region 52 in trench 13 and on semiconductor body 12. The conductive material is, for example, N-doped polysilicon, and completely fills trench 13. The conductive region 52 is intended to form field plate 16.

[0111] Then, in FIG5E, a step is performed to selectively remove a portion of the conductive region 52 above the upper side 12a of the semiconductor body 12 and partially within the trench 13.

[0112] This step can be performed using CMP (chemical mechanical polishing) technology, followed by an etching step to partially etch the conductive region 52 within the trench 13. The conductive region 52 is then recessed in each trench 13 until it is located below the upper side 12a. Specifically, the recesses of the conductive region 52 in the trench 13 can have a depth between approximately 0.7 µm and approximately 0.9 µm, measured from the upper side 12a; therefore, the recesses of the conductive region 52 in the trench 13 of FIG. 5E are generally larger than similar recesses in FIG. 4E.

[0113] The portion of the conductive region 52 retained after the recess in Figure 5E forms the previously described field plate 16.

[0114] Then, in FIG. 5F, the first insulating fill region 51 is partially etched on the upper side 12a to form a first recess 54 in each trench 13. The etching of the material toward the first insulating fill region 51 is selective, and the material of the conductive region 52 is retained in the trench 13. The portion of the first insulating fill region 51 retained after this etching forms the body 14a of the oxide region 14.

[0115] Specifically, the depth of the first recess 54 is greater than the depth of the recess in the conductive region 52, such that the recessed conductive region 52 partially protrudes relative to the body 14a of the oxide region 14. In particular, the depth of the first recess 54 can be between about 0.6 µm and about 1.1 µm, especially when measured starting from the upper side 12a, between about 0.6 µm and about 0.8 µm near the semiconductor body 12, and between about 0.9 µm and about 1.1 µm at the recessed conductive region 52.

[0116] Then, as shown in Figure 5G, the first recess 54 is filled with an insulating electrical material to form a second insulating filling region 60. For example, if the semiconductor body 12 is silicon, this step is performed by growing or depositing silicon oxide (SiO2); another insulating material can be grown or deposited based on the material of the semiconductor body 12.

[0117] Then, in Figure 5H, the second insulating fill region 60 is partially etched on the upper side 12a to form a second recess 61 in each trench 13. The etching of the material toward the first insulating fill region 51 is selective, and the material of the semiconductor body 12 is retained. The portion of the second insulating fill region 60 retained after this etching contributes to the formation of the body 14a of the oxide region 14.

[0118] Specifically, the depth of the second recess 61 is less than the depth of the recess in the conductive region 52, such that the recessed conductive region 52 is partially covered by the second insulating filling region 60 left after etching, and is therefore buried in the body 14a of the oxide region 14. In particular, the second recess 61 may have a depth between approximately 0.6 µm and approximately 0.8 µm, measured from the upper side 12a, i.e., they may have a similar depth to the recess 54 in FIG. 4F.

[0119] Therefore, the etching exposes a portion of the sidewall of the trench 13 between the upper side 12a of the semiconductor body 12 and the upper side of the body 14a of the oxide region 14.

[0120] Then, in FIG. 5I, the interconnect trench 31 is formed in a manner completely similar to that described previously with reference to FIGS. 4G and 4H, and therefore will not be described in detail again. In particular, the depth of the interconnect trench 31 is substantially equal to the depth of the second recess 61, such that the lower wall of the interconnect trench 31 is substantially flush with the upper wall of the portion of the second insulating fill region 60 retained after the etching in FIG. 5H.

[0121] Then, as shown in Figure 5J, an oxidation step is performed (e.g., exposing the wafer to an O2 environment) to form an insulating layer 57 on the exposed surface of the semiconductor material.

[0122] This oxidation step results in the oxidation of the semiconductor material in the interconnect trench 31 and the remaining exposed portion of the semiconductor material on the upper side 12a of the semiconductor body 12, specifically, the oxidation of the semiconductor material on the exposed areas of the sidewalls of the trench 13. In particular, the oxidized regions of the interconnect trench 31 form the previously described insulating interconnect portion 29, while the oxidized regions of the sidewalls of the trench 13 form the previously described first oxide portion 14b.

[0123] Then, as shown in FIG. 5K, the steps of forming gate region 15 and gate interconnect 28 are performed. Gate region 15 is formed by depositing a conductive material (e.g., n-doped polysilicon) in the second recess 61, while gate interconnect 28 is formed by depositing the same conductive material (e.g., n-doped polysilicon) in the interconnect trench 31.

[0124] Then, in Figure 5L, the bulk region 17 and the source region 20 are formed by implanting P-type and N-type dopants, respectively, into the semiconductor region between the trenches 13.

[0125] Then, as shown in Figure 5M, an upper oxide layer 63 is formed, for example, by deposition, which uniformly covers the gate region 15, the gate interconnect 28, and the source region 20.

[0126] Then, as shown in FIG. 5N, starting from the upper oxide layer 63, an upper oxide region 18 is formed on the gate region 15 and the gate interconnect 28. Specifically, the upper oxide layer 63 is etched between the trenches 13 to form a first contact opening 58 in which the first metallization portion 24b will extend, and etched over the field plate 16 to form a through opening 18' in which the second metallization portion 24c will extend. Specifically, the through opening 18' here exposes a portion of the gate region 15 extending on the field plate 16.

[0127] Then, as in 5O, a first field plate contact trench 65 is formed, which is vertically aligned with the through opening 18' and extends through the gate region 15 and the second insulating fill region 60 until the upper surface of the field plate 16 is exposed.

[0128] In detail, this occurs through a series of selective etchings that first selectively recess the material of the gate region 15, and then recess the material of the second insulating fill region 60. For example, these etchings are performed via a mask 66, the opening of which is stacked over the through opening 18', and the mask 66 is removed after etching.

[0129] Then, as shown in FIG. 5P, an oxide deposition step (e.g., by TEOS deposition) is performed to cover the exposed surfaces of the semiconductor material with oxide. Specifically, this oxide step covers the semiconductor material of the gate region 15 and field plate 16 exposed by the first field plate contact trench 65, and the semiconductor material of the source region 20 exposed by the first contact opening 58 with oxide. In other words, the oxide region 18 serves as a mask operation for this deposition step. In particular, the oxide layer on the semiconductor material of the gate region 15 at the first field plate contact trench 65 is intended to form the previously described insulating portion 18b.

[0130] Then, in FIG. 5Q, a second field plate contact trench 67 is formed, which extends through the oxide portion on the field plate 16 formed in the deposition of FIG. 5P until the upper surface of the field plate 16 is exposed. In addition, a second contact opening 68 is formed, which extends through the oxide portion on the source region 20 formed in the deposition of FIG. 5P until the upper surface of the source region 20 is exposed.

[0131] In detail, this occurs through selective etching, which causes the oxide material to be recessed without etching the material of the field plate 16 and the source region 20.

[0132] Then, as shown in FIG5R, a third contact opening 69 is formed, which is vertically aligned with the second contact opening 68 and extends through the source region 20 until the upper surface of the radially inner portion of the body region 17 is exposed.

[0133] Then, as shown in FIG. 5S, the source metallization portion 24 is formed, for example, by depositing a conductive material. Specifically, a conductive material layer is uniformly deposited on the upper oxide region 18 to form the body 24a, deposited in the third contact opening 69 to form the first metallization portion 24b, and deposited in the field plate contact trench 67 to form the second metallization portion 24c. Thus, the first metallization portion 24b contacts the body region 17 and the source region 20, while the second metallization portion 24c contacts the field plate 16.

[0134] Other steps may be performed to complete the fabrication of MOSFET 10, but these steps are not part of this invention and will not be described further.

[0135] In detail, compared with the technical solutions of Figures 4A to 4M, the manufacturing process of Figures 5A to 5S allows for more precise control of the insulation of the gate region 15 relative to the source metallization 24 at the point where the source metallization 24 contacts the field plate 16, and also reduces the gate-source capacitance due to the greater thickness of the insulating portion 18b.

[0136] The advantages it offers become apparent from the study of the characteristics of the invention as described in this invention.

[0137] In particular, the split-gate MOSFET 10 allows for reduced on-resistance without adjusting the size of the diffusion process or increasing the lithography resolution, thus saving costs and difficulties during the manufacturing process.

[0138] In particular, this is due to a significant increase in the channel perimeter (e.g., an increase of about 130%) obtained by using the gate interconnect 28 and a significant increase in the conductive area (e.g., an increase of about 60%) obtained by using a cellular matrix shape instead of a strip-shaped trench 13.

[0139] Finally, it is obvious that modifications and variations may be made to the invention described and illustrated herein without departing from the scope of the invention as defined in the appended claims.

[0140] For example, the different embodiments described can be combined with each other to provide other technical solutions.

[0141] Furthermore, this technical solution can be applied to any type of trench gate vertical conductive device, such as, but not limited to, VDMOS transistors or trench-based power MOSFET devices.

[0142] In addition, other shapes and arrangements can be used as alternatives to those illustratively shown in Figures 2A to 2C. For example, the square shape in Figures 2A to 2C can be replaced by a more general quadrilateral shape, such as, for example, a rectangle or a rhombus.

[0143] In one embodiment, an electronic device (10) includes a semiconductor body (12) having a first side and a second side (12a, 12b) opposite to each other along a first axis (Z); a plurality of trenches (13) extending from the first side (12a) toward the second side (12b) within the semiconductor body (12) and terminating within the semiconductor body (12); a corresponding insulating field plate region (14) in each of the trenches (13) covering the lower wall and sidewall of the corresponding trench (13); a corresponding conductive gate region (15) in each of the trenches (13) on the corresponding insulating field plate region (14), each conductive gate region (15) being made of a conductive material and passing through the corresponding insulating field plate region (14). The trench (13) is electrically insulated from the semiconductor body (12); each field plate region (16) in each trench (13) is buried in a corresponding insulating field plate region (14) and electrically insulated from the corresponding conductive gate region (15) and the semiconductor body (12) through the corresponding insulating field plate region (14); a plurality of gate interconnects (28) extend laterally from a first side (12a) toward a second side (12b) in the semiconductor body (12) and terminate in the semiconductor body (12), the gate interconnects (28) being made of conductive material, electrically insulated from the semiconductor body (12), and electrically connected to the conductive gate regions (15) so that the conductive gate regions (15) are electrically interconnected with each other.

[0144] In one embodiment, the electronic device further includes a plurality of interconnect trenches (31), each interconnect trench (31) extending from a first side (12a) toward a second side (12b) within a semiconductor body (12) and terminating within the semiconductor body (12), wherein the interconnect trenches (31) are orthogonally inserted between trenches (13) and communicating with the trenches (13), wherein gate interconnects (28) extend within the interconnect trenches (31) to electrically contact conductive gate regions (15) with each other, and the electronic device (10) further includes insulating interconnect portions (29) of insulating material extending in the interconnect trenches (31) to be inserted between the gate interconnects (28) and the semiconductor body (12) to electrically insulate the gate interconnects (28) from the semiconductor body (12).

[0145] In one embodiment, the groove (13) is orthogonal to the first axis (Z) and has a closed polygonal shape and matrix arrangement.

[0146] In one embodiment, the trench (13) and the conductive gate region (15) have a hexagonal shape orthogonal to the first axis (Z), wherein each gate interconnect (28) connects the three adjacent gate regions (15) in a matrix arrangement to each other, wherein each gate interconnect (28) has three corresponding arms, each arm having a corresponding first end and a corresponding second end opposite to each other in a direction relative to the main extension of the arm, the first ends of the arms of each gate interconnect (28) engaging with each other to form an engagement portion of the gate interconnect (28), from the engagement portion, the corresponding three arms extend radially to be equally spaced apart from each other orthogonal to the first axis (Z), wherein the second end of each arm of each gate interconnect (28) is coupled to a corresponding vertex of the corresponding gate region in the three gate regions (15), in a matrix arrangement, the three gate regions surrounding the corresponding gate interconnect (28).

[0147] In one embodiment, in a matrix arrangement, trenches (13) are aligned with each other along a second axis (X) orthogonal to the first axis (Z) and along a third axis (Y) orthogonal to the first axis (Z) and the second axis (X), wherein the trenches (13) and conductive gate regions (15) have quadrilateral shapes, particularly square shapes, wherein gate interconnects (28) are grouped in groups, each having four corresponding gate interconnects (28), each group of gate interconnects (28) connecting the four corresponding gate regions (15) that are closest to each other in the matrix arrangement, wherein each group of gate interconnects (28) forms a conductive path orthogonal to the first axis (Z), the conductive path being of the ring type and having a quadrilateral shape, particularly square shape, wherein each vertex of the quadrilateral shape of each conductive path is connected to a corresponding vertex of the corresponding gate region in the four gate regions (15), the four gate regions surrounding the corresponding group of gate interconnects (28) in the matrix arrangement.

[0148] In one embodiment, in a matrix arrangement, trenches (13) are aligned with each other along a second axis (X) orthogonal to a first axis (Z) and alternately aligned with each other along a third axis (Y) orthogonal to the first axis (Z) and the second axis (X), wherein the trenches (13) and conductive gate regions (15) are quadrilateral in shape, particularly square in shape, wherein gate interconnects (28) are grouped to form serpentine paths of gate interconnects (28), each serpentine path having a main extension along the direction of the second axis (X) and extending between conductive gate regions (15) in two corresponding rows along the direction of the third axis (Y), each row comprising corresponding conductive gate regions (15) aligned with each other along the direction of the second axis (X), each serpentine path being coupled to the apex of the corresponding conductive gate region (15) to be continuously coupled with each other, the serpentine paths being inserted between the conductive gate regions (15) in the two corresponding rows.

[0149] In one embodiment, the electronic device further includes a gate metallization located on a first side (12a) of the semiconductor body (12) and directly electrically connected to a portion of the conductive gate region (15).

[0150] In one embodiment, the semiconductor body (12) has a first conductivity type (N), and the electronic device further includes: a plurality of body regions (17) extending between trenches (13) on a first side (12a), the body regions (17) having a second conductivity type (P) opposite to the first conductivity type (N); a plurality of source regions (20) respectively in the corresponding body regions of the body regions (17); a source metallization (24) located on the first side (12a) of the semiconductor body (12) and electrically connected to the source regions (20) and the field plate region (16); and a drain metallization (26) located on the second side (12b) of the semiconductor body (12).

[0151] In one embodiment, the source metallization (24) has a corresponding metallization portion (24c) for each trench (13), each metallization portion (24c) extending along a first axis (Z) through a corresponding conductive gate region (15) until reaching a corresponding field plate region (16), wherein each metallization portion (24c) is electrically insulated relative to the corresponding conductive gate region (15) by a corresponding insulating portion (18b) of insulating material, wherein, orthogonal to the first axis (Z), each insulating portion (18b) has an annular shape, surrounds the corresponding metallization portion (24c), and is inserted between the corresponding metallization portion (24c) and the corresponding conductive gate region (15) to be orthogonal to the first axis (Z), spacing the corresponding metallization portion (24c) and the corresponding conductive gate region (15) apart by a minimum distance of at least 50 nm.

[0152] In one embodiment, the electronic device is of the vertical conductivity type.

[0153] In one embodiment, a process for manufacturing an electronic device (10) includes the following steps: forming a plurality of trenches (13) within a semiconductor body (12), the semiconductor body (12) having a first side and a second side (12a, 12b) opposite to each other along a first axis (Z), the trenches (13) extending from the first side (12a) toward the second side (12b) and terminating within the semiconductor body (12); forming a corresponding insulating field plate region (14) in each of the trenches (13), covering the lower wall and sidewalls of the corresponding trench (13); forming a corresponding field plate region (16) in each of the trenches (13), each field plate region (16) being embedded in the corresponding insulating field plate region (14) and passing through the corresponding insulating field plate region (14). 4) Electrically insulated from the semiconductor body (12); forming a corresponding conductive gate region (15) in each of the trenches (13) on the corresponding insulating field plate region (14), each conductive gate region (15) being made of conductive material and electrically insulated from the semiconductor body (12) and the corresponding field plate region (16) through the corresponding insulating field plate region (14); forming a plurality of gate interconnects (28) extending laterally from a first side (12a) toward a second side (12b) in the semiconductor body (12) and terminating in the semiconductor body (12), the gate interconnects (28) being made of conductive material, electrically insulated from the semiconductor body (12), and electrically connected to the conductive gate regions (15) so that the conductive gate regions (15) are electrically interconnected with each other.

[0154] In one embodiment, after the step of forming the field plate region (16), the manufacturing process further includes the following steps: partially etching a corresponding insulating fill region (51) in each trench (13) on a first side (12a) to form a recess (54) in each trench (13) and define a body (14a) of each insulating field plate region (14); selectively removing portions of the semiconductor body (12) starting from the first side (12a) to form interconnect trenches (31), each interconnect trench (31) extending from the first side (12a) toward a second side (12b) within the semiconductor body (12) and terminating within the semiconductor body (12), the interconnect trenches (31) The first axis (Z) is orthogonally inserted between the trenches (13) and communicates with the trenches (13); and an insulating layer (57) is formed in the interconnect trenches (31) and the recesses (54), the portion of the insulating layer (57) present in the interconnect trenches (31) defining an insulating interconnect portion (29) extending in the interconnect trenches (31), and wherein the steps of forming the conductive gate region (15) and forming the gate interconnect (28) are performed simultaneously by depositing conductive materials in the recesses (54) and the interconnect trenches (31), respectively, such that the insulating interconnect portion (29) is inserted between the gate interconnect (28) and the semiconductor body (12) in the interconnect trenches (31).

[0155] In one embodiment, after the step of forming the field plate region (16), the manufacturing process further includes the following steps: partially removing a corresponding insulating fill region (51) in each trench (13) on a first side (12a) to form a first recess (54) in each trench (13), the field plate region (16) partially protruding into the first recess (54); forming a second insulating fill region (60) in the trench (13) on the first side (12a); partially removing the second insulating fill region (60) on the first side (12a) to form a second recess (61) in each trench (13), thereby leaving the covered field plate region (16); selectively removing portions of the semiconductor body (12) starting from the first side (12a) to form interconnect trenches (31), each interconnect trench (31) in the semiconductor body (12) 12) Extending from the first side (12a) toward the second side (12b) and terminating within the semiconductor body (12), the interconnect trench (31) is orthogonally inserted between the trenches (13) and communicates with the trenches (13); an insulating layer (57) is formed in the interconnect trench (31) and the second recess (61), the portion of the insulating layer (57) present in the interconnect trench (31) defining an insulating interconnect portion (29) extending in the interconnect trench (31), and wherein the steps of forming the conductive gate region (15) and forming the gate interconnect (28) are performed simultaneously by depositing conductive materials in the second recess (61) and the interconnect trench (31), respectively, such that the insulating interconnect portion (29) is inserted between the gate interconnect (28) and the semiconductor body (12) in the interconnect trench (31).

[0156] In one embodiment, after the steps of forming the conductive gate region (15) and forming the gate interconnect (28), the manufacturing process further includes the following steps: forming an upper oxide layer (63) on the gate region (15) and the gate interconnect (28); partially removing the upper oxide layer (63) to form a through opening (18') extending through the upper oxide layer (63) to the conductive gate region (15) and aligned with the field plate region (16) along a first axis (Z); forming a first field plate contact trench (65) through the through opening (18') extending through the gate region (15) and a second insulating fill region (60) to the exposed field plate region (16); depositing an oxide layer in the first field plate contact trench (65) comprising a portion present on the field plate region (16) and an insulating portion (18b), the insulating portion having an annular shape orthogonal to the first axis (Z) and each covering the corresponding first field plate contact. The contact trench (65) exposes the wall of the corresponding gate region (15); a second field plate contact trench (67) is formed by the first field plate contact trench (65), the second field plate contact trench (67) extending through the oxide layer portion present on the field plate region (16) until the field plate region (16) is exposed; and a source metallization portion (24) is formed having a metallization portion (24c), the metallization portion extending in the field plate contact trench (67) to contact the field plate region (16), wherein each metallization portion (24c) is electrically insulated relative to the corresponding conductive gate region (15) by a corresponding insulating portion (18b) of insulating material, and wherein, orthogonal to the first axis (Z), each insulating portion (18b) surrounds the corresponding metallization portion (24c) and is inserted between the corresponding metallization portion (24c) and the corresponding conductive gate region (15) orthogonal to the first axis (Z), spacing the corresponding metallization portion (24c) and the corresponding conductive gate region (15) apart by at least 50°. The minimum distance in nm.

[0157] In view of the detailed description above, these and other changes may be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in this specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents to which such claims are conferred. Therefore, the claims are not limited to this disclosure.

Claims

1. An electronic device, comprising: The semiconductor body has a first side and a second side that are opposite to each other along a first axis; Multiple trenches extend from the first side toward the second side within the semiconductor body and terminate within the semiconductor body; a corresponding insulating field plate region in each trench covers the lower wall and sidewall of the corresponding trench; A corresponding conductive gate region in each trench of the trench on the corresponding insulating field plate region, each conductive gate region being made of conductive material and electrically insulated from the semiconductor body through the corresponding insulating field plate region; In each of the trenches, a corresponding field plate region is embedded in the corresponding insulating field plate region and electrically insulated from the corresponding conductive gate region and the semiconductor body through the corresponding insulating field plate region; The semiconductor body includes a plurality of gate interconnects extending laterally through the trench from the first side toward the second side and terminating within the semiconductor body. The gate interconnects are made of a conductive material, electrically insulated from the semiconductor body, and electrically connected to the conductive gate regions, thereby electrically interconnecting the conductive gate regions with each other.

2. The electronic device of claim 1, further comprising a plurality of interconnect trenches, each interconnect trench extending from the first side toward the second side and terminating within the semiconductor body, wherein the interconnect trenches are orthogonally inserted between the trenches and in communication with the trenches, wherein the gate interconnects extend within the interconnect trenches to electrically contact each other with the conductive gate regions, the electronic device further comprising an insulating interconnect portion of insulating material extending in the interconnect trenches to be inserted between the gate interconnects and the semiconductor body to electrically insulate the gate interconnects from the semiconductor body.

3. The electronic device of claim 1, wherein the trench has a closed polygonal shape and matrix arrangement orthogonal to the first axis.

4. The electronic device of claim 3, wherein the channel and the conductive gate region have a hexagonal shape orthogonal to the first axis, wherein each gate interconnect connects three adjacent gate regions in the matrix arrangement to each other, wherein each gate interconnect has three corresponding arms, each arm having a corresponding first end and a corresponding second end opposite to each other in a direction relative to the main extension of the arm, the first ends of the arms of each gate interconnect engaging with each other to form a engagement portion of the gate interconnect, from the engagement portion, the corresponding three arms extending radially such that they are orthogonal to the first axis and equiangularly spaced from each other, wherein the second end of each arm of each gate interconnect is coupled to a corresponding vertex of the corresponding gate region in the three gate regions, wherein the three gate regions surround the corresponding gate interconnect in the matrix arrangement.

5. The electronic device of claim 3, wherein in the matrix arrangement, the trenches are aligned with each other along a second axis orthogonal to the first axis and along a third axis orthogonal to both the first and second axes, wherein the trenches and the conductive gate regions have quadrilateral shapes, particularly square shapes, orthogonal to the first axis, wherein the gate interconnects are grouped into groups, each having four corresponding gate interconnects, each group of gate interconnects connecting the four nearest adjacent gate regions in the matrix arrangement, wherein each group of gate interconnects forms a conductive path, the conductive path being annular in shape orthogonal to the first axis and having a quadrilateral shape, particularly square shape, wherein each vertex of the quadrilateral shape of each conductive path is connected to a corresponding vertex of the corresponding gate region in the four gate regions, the four gate regions surrounding the corresponding group of gate interconnects in the matrix arrangement.

6. The electronic device of claim 3, wherein in the matrix arrangement, the trenches are aligned with each other along a second axis orthogonal to the first axis and alternately aligned with each other along a third axis orthogonal to both the first and second axes, wherein the trenches and the conductive gate regions have a quadrilateral shape, particularly a square shape, orthogonal to the first axis, wherein the gate interconnects are grouped to form serpentine paths of gate interconnects, each serpentine path having a main extension along the direction of the second axis and extending between conductive gate regions in two corresponding rows along the direction of the third axis, each row comprising corresponding conductive gate regions aligned with each other along the direction of the second axis, each serpentine path being coupled to the vertex of the corresponding conductive gate region, thereby being continuously coupled with each other, the serpentine paths being inserted between the conductive gate regions in the two corresponding rows.

7. The electronic device of claim 1 further includes a gate metallization located on the first side of the semiconductor body and directly electrically connected to a portion of the conductive gate region.

8. The electronic device of claim 1, wherein the semiconductor body has a first conductivity type, and the electronic device further comprises: Multiple body regions extend between the trenches on the first side, the body regions having a second conductivity type opposite to the first conductivity type; Multiple source regions, each in a corresponding body region of the body region; a source metallization portion, located on the first side of the semiconductor body, and electrically connected to the source regions and the field plate region; And a drain metallization portion, located on the second side of the semiconductor body.

9. The electronic device of claim 8, wherein the source metallization has a corresponding metallization portion for each trench, each metallization portion extending along the first axis through the corresponding conductive gate region until reaching the corresponding field plate region, wherein each metallization portion is electrically insulated relative to the corresponding conductive gate region by a corresponding insulating portion of an insulating material, wherein... Each insulating portion has an annular shape orthogonal to the first axis, surrounds the corresponding metallized portion, and is inserted between the corresponding metallized portion and the corresponding conductive gate region, thereby orthogonal to the first axis to space the corresponding metallized portion and the corresponding conductive gate region apart by a minimum distance of at least 50 nm.

10. The electronic device according to claim 1 is of the vertical conductivity type.

11. A method for manufacturing an electronic device, comprising: Multiple trenches are formed within a semiconductor body, the semiconductor body having a first side and a second side opposite to each other along a first axis, the trenches extending from the first side toward the second side and terminating within the semiconductor body; In each of the trenches, a corresponding insulating field plate area is formed, covering the lower wall and sidewalls of the corresponding trench; A corresponding field plate region is formed in each of the trenches, each field plate region is buried in the corresponding insulating field plate region, and is electrically insulated from the semiconductor body through the corresponding insulating field plate region; A corresponding conductive gate region is formed on the corresponding insulating field plate region and in each trench of the trench. Each conductive gate region is made of conductive material and is electrically insulated from the semiconductor body and the corresponding field plate region through the corresponding insulating field plate region. A plurality of gate interconnects are formed, the plurality of gate interconnects extending laterally through the trench from the first side toward the second side within the semiconductor body and terminating within the semiconductor body, the gate interconnects being made of a conductive material, electrically insulated from the semiconductor body, and electrically connected to the conductive gate regions, thereby electrically interconnecting the conductive gate regions with each other.

12. The manufacturing method according to claim 11, further comprising the following step after forming the field plate region: On the first side, the corresponding insulating fill area is partially etched in each trench to form a recess in each trench and define the body of each insulating field plate area; Starting from the first side, a portion of the semiconductor body is selectively removed to form interconnect trenches. Each interconnect trench extends from the first side toward the second side within the semiconductor body and terminates within the semiconductor body. The interconnect trenches are orthogonally inserted between the trenches and communicate with the trenches. An insulating layer is formed in the interconnect trench and the recess, the portion of the insulating layer present in the interconnect trench defining an insulating interconnect portion extending in the interconnect trench, and wherein the steps of forming the conductive gate region and forming the gate interconnect are performed simultaneously by depositing conductive material in the recess and the interconnect trench respectively, such that the insulating interconnect portion is inserted between the gate interconnect and the semiconductor body in the interconnect trench.

13. The manufacturing method of claim 11, further comprising, after forming the field plate region: partially removing a corresponding insulating fill region in each trench on the first side to form a first recess in each trench, wherein the field plate region partially protrudes into the first recess; A second insulating filling region is formed in the trench on the first side; The second insulating fill area is removed from the first side portion to form a second recess in each trench, thereby leaving the covered field plate area. Starting from the first side, a portion of the semiconductor body is selectively removed to form interconnect trenches. Each interconnect trench extends from the first side toward the second side within the semiconductor body and terminates within the semiconductor body. The interconnect trenches are orthogonally inserted between the trenches and communicate with the trenches. An insulating layer is formed in the interconnect trench and the second recess, the portion of the insulating layer present in the interconnect trench defining an insulating interconnect portion extending in the interconnect trench, and wherein the formation of the conductive gate region and the formation of the gate interconnect are performed simultaneously by depositing conductive material in the second recess and the interconnect trench respectively, such that the insulating interconnect portion is inserted between the gate interconnect and the semiconductor body in the interconnect trench.

14. The manufacturing method of claim 13, further comprising, after the steps of forming the conductive gate region and forming the gate interconnect: An upper oxide layer is formed on the gate region and the gate interconnect; The upper oxide layer is partially removed to form a through opening that extends through the upper oxide layer to the conductive gate region and is aligned with the field plate region along the direction of the first axis. A first field plate contact trench is formed through the through opening, and the first field plate contact trench extends through the gate region and the second insulating fill region until the field plate region is exposed. An oxide layer is deposited in the first field plate contact trench. The oxide layer includes a portion present on the field plate region and an insulating portion. The insulating portion has an annular shape orthogonal to the first axis and each covers the wall of the corresponding gate region exposed by the corresponding first field plate contact trench. A second field plate contact groove is formed through the first field plate contact groove, and the second field plate contact groove extends through a portion of the oxide layer present on the field plate region until the field plate region is exposed. And forming a source metallization portion having a metallization portion extending in the field plate contact trench to contact the field plate region, wherein each metallization portion is electrically insulated relative to the corresponding conductive gate region by a corresponding insulating portion of insulating material, and wherein each insulating portion orthogonally surrounds the corresponding metallization portion with respect to the first axis and is inserted between the corresponding metallization portion and the corresponding conductive gate region, thereby orthogonally separating the corresponding metallization portion and the corresponding conductive gate region by a minimum distance of at least 50 nm with respect to the first axis.

15. A method comprising: Forming a semiconductor body of the first conductivity type; Multiple trenches are formed, which extend and terminate within the semiconductor body; Multiple insulating field plate regions are formed, each in its respective trench; Each of the corresponding conductive gate regions is formed in its respective trench; Multiple field plate regions are formed, each of which is located in a corresponding trench and is electrically insulated from the corresponding conductive gate region and the semiconductor body through the corresponding insulating field plate region; And forming a plurality of gate interconnects that extend adjacent to the trench within the semiconductor body, terminate within the semiconductor body, are electrically insulated from the semiconductor body, and electrically interconnect the conductive gate regions.

16. The method of claim 15, further comprising, after forming the field plate region: partially etching a corresponding insulating fill region in each trench on the first side to form a recess in each trench and define a body of each insulating field plate region; and selectively removing a portion of the semiconductor body starting from the first side to form interconnect trenches, each interconnect trench terminating in the semiconductor body, the interconnect trenches being orthogonally inserted between the trenches and communicating with the trenches.

17. The method of claim 16, further comprising, after selectively removing portions of the semiconductor body, forming an insulating layer in the interconnect trench and the recess, wherein a portion of the insulating layer present in the interconnect trench defines an insulated interconnect portion extending in the interconnect trench.

18. The method of claim 17, wherein forming the conductive gate region and forming the gate interconnect are performed simultaneously by depositing conductive materials in the recess and the interconnect trench, respectively, such that the insulating interconnect portion is inserted between the gate interconnect and the semiconductor body in the interconnect trench.

19. The method of claim 15, further comprising, after forming the field plate region: partially removing a corresponding insulating fill region in each trench on the first side to form a first recess in each trench, the field plate region partially protruding into the first recess; A second insulating filling region is formed in the trench on the first side; The second insulating fill area is removed from the first side portion to form a second recess in each trench, thereby leaving the covered field plate area. And selectively removing portions of the semiconductor body starting from the first side to form interconnect trenches, each interconnect trench extending from the first side toward the second side within the semiconductor body and terminating within the semiconductor body, the interconnect trenches being orthogonally inserted between the trenches and communicating with the trenches.

20. The method of claim 19, further comprising: An insulating layer is formed in the interconnect trench and the second recess, the portion of the insulating layer present in the interconnect trench defining an insulating interconnect portion extending in the interconnect trench, wherein the steps of forming the conductive gate region and forming the gate interconnect are performed simultaneously by depositing conductive materials in the second recess and the interconnect trench respectively, such that the insulating interconnect portion is inserted between the gate interconnect and the semiconductor body in the interconnect trench.

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