Method of manufacturing electronic device and corresponding electronic device

Abstract

The invention relates to a method of manufacturing an electronic device and a corresponding electronic device. The present specification relates to a method of manufacturing an electronic device comprising a first FinFET transistor in a second region and a second MOSFET transistor in the second region, the method comprising: forming a first sacrificial gate of a first length along a first fin of a semiconductor substrate in a first region, and forming a second sacrificial gate of a second length greater than the first length on the semiconductor substrate in the second region, including forming a first spacer of a first thickness on a side of the first sacrificial gate, and forming a second spacer of a second thickness greater than the first thickness on a side of the second sacrificial gate; forming a first semiconductor region on either side of the first sacrificial gate and a second semiconductor region on either side of the second sacrificial gate in the semiconductor substrate; each first sacrificial gate is replaced with a first gate structure and each second sacrificial gate is replaced with a second gate structure.

Description

Methods for manufacturing electronic devices and corresponding electronic devices Cross-reference to related applications

[0001] This application claims priority to French patent application number FR2411824, filed on October 29, 2024, entitled “Procédé de fabrication d'un dispositif éelectronique, et dispositif éelectronique associé”, which is incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0002] This invention generally relates to electronic devices, and more particularly to the manufacture of electronic devices.

[0003] This disclosure relates in particular to the manufacture of electronic devices comprising one or more metal-oxide-semiconductor field-effect transistors (MOSFETs) (e.g., high-voltage MOSFETs) integrated with one or more FinFETs. Background Technology

[0004] During the manufacture of electronic devices comprising different electronic components inside and on top of the same semiconductor substrate, manufacturers may wish to use the same manufacturing methods for all or some of the electronic components, particularly for manufacturing cost reasons. For example, the electronic components of an electronic device may be manufactured on the same production line. However, if the manufacturing method is implemented entirely on the entire semiconductor substrate without separate processes, such as providing protection through masks, then any implemented processes are applicable to all electronic components. However, processes used to form one electronic component may not be applicable to another, and protection through masks is often required, making some processes unsuitable for all electronic components.

[0005] Depending on the electronic device to be manufactured, and particularly the different electronic components to be formed on the inside and top of the same semiconductor substrate, manufacturing different electronic components on the same production line can be complex or even impossible. For example, in FinFET transistor manufacturing technology, specific process steps may be required to form MOSFET transistors, such as high-voltage MOSFET transistors. The voltage considered is the maximum voltage that can be applied to the transistor without the risk of damaging it; high voltage is typically above 3 volts.

[0006] In addition, it is generally desirable to use as few protective masks as possible. Summary of the Invention

[0007] There are uses for at least partial improvement of certain aspects of known electronic devices and known methods of manufacturing electronic devices.

[0008] The embodiments overcome all or part of the disadvantages of known electronic devices and known methods of manufacturing electronic devices.

[0009] One embodiment provides a method of fabricating an electronic device inside and on top of a semiconductor substrate, the electronic device including a first fin field-effect transistor in a first region and at least one second field-effect transistor having a metal-oxide-semiconductor structure in at least one second region, the method comprising: forming a first sacrificial gate having a first length along a first fin of the semiconductor substrate in the first region, the first fin having a first width at a first surface of the semiconductor substrate and being isolated by a first trench in the semiconductor substrate; and forming a second sacrificial gate having a second length greater than the first length on the first surface of the semiconductor substrate in each second region, the first sacrificial gate and the second sacrificial gate being made of a sacrificial material; forming the first sacrificial gate and the second sacrificial gate. The gate includes a first spacer of a first thickness formed on the side of the first sacrificial gate, and a second spacer of a second thickness greater than the first thickness formed on the side of the second sacrificial gate; in the semiconductor substrate, a first semiconductor region is formed in a first region on either side of the first sacrificial gate having the first spacer, thereby forming the drain region and source region of the first transistor; in the semiconductor substrate, a second semiconductor region is formed in each second region on either side of the second sacrificial gate having the second spacer, thereby forming the drain region and source region of at least one second transistor; and each first sacrificial gate is replaced with a first gate structure and each second sacrificial gate is replaced with a second gate structure.

[0010] According to one embodiment, the sacrificial material is polycrystalline silicon.

[0011] According to one embodiment, forming a first sacrificial gate and a second sacrificial gate includes: forming a first portion of a first layer made of sacrificial material in a first region and a second portion of the first layer in each second region on a semiconductor substrate, the first portion extending substantially over the entire length of the first region and the second portion extending over a second length shorter than the length of the second region, thereby forming all or part of the second sacrificial gate; forming a stack of layers made of dielectric material on the sidewalls of the first portion and the sidewalls of the second portion of the first layer; and forming all or part of the stack of layers made of dielectric material on the sidewalls of the second portion of the first layer.

[0012] According to one embodiment, the formation of the stack of layers includes: forming a first L-shaped portion of a second layer made of a dielectric material on the side surface of a first portion of a first layer and on a semiconductor substrate; forming a second L-shaped portion of the second layer made of a dielectric material on the side surface of a second portion of the first layer and on a semiconductor substrate, wherein the dielectric material is preferably made of a low dielectric constant material; forming a third layer made of a dielectric material such as a nitride, such as silicon nitride, on the first L-shaped portion of the first D-shaped portion and the second L-shaped portion of the second D-shaped portion, respectively; and forming a fourth layer made of a dielectric material such as silicon nitride on the first D-shaped portion of the first layer and the second D-shaped portion of the second layer, respectively.

[0013] According to one embodiment, forming the first and second portions of the fourth layer includes depositing and then etching the fourth layer to form: in a first region: the first and third portions of the fourth layer on the first portion of the first layer, the third portions being arranged in a row and each extending over a length substantially equal to the first length; and in each second region: the second and fourth portions of the fourth layer on the second portion of the first layer.

[0014] According to one embodiment, the method includes etching a first portion of a first layer to form a third portion of the first layer, the third portions being arranged in rows and each extending over a length substantially equal to the first length, thereby forming all or part of a first sacrificial gate.

[0015] According to one embodiment, etching of a first portion of a first layer is performed by a third portion of a fourth layer forming an etching mask, the third portion of the first layer extending between a semiconductor substrate and a third portion of the fourth layer.

[0016] According to one embodiment, after forming a third portion of the first layer, forming the first and second spacers includes: forming a first portion of a fifth layer, preferably a dielectric material having a low dielectric constant, on the side surface of the first sacrificial gate, forming the first spacer, and forming a second portion of the fifth layer on the side surface of each second sacrificial gate covered by the stack of layers, the second spacer comprising the second portion of the fifth layer.

[0017] According to one embodiment, the fifth layer includes a fourth portion that extends the second portion of the fifth layer so as to cover the fourth portion of the fourth layer.

[0018] According to one embodiment, the formation of the second semiconductor region is performed simultaneously with the formation of the first semiconductor region.

[0019] According to one embodiment, the formation of a second semiconductor region is performed before or after the formation of a first semiconductor region.

[0020] According to one embodiment, the fifth layer includes a third portion extending on either side of the second sacrificial gate and the second spacer in each second region, so as to mask the semiconductor substrate in the second region during the formation of the first semiconductor region.

[0021] According to one embodiment, forming a first semiconductor region and optionally forming a second semiconductor region includes forming a cavity in a semiconductor substrate from a first surface, and then filling the cavity by epitaxy and implantation of dopant atoms.

[0022] One embodiment provides an electronic device comprising, on the interior and top of a semiconductor substrate, a first fin field-effect transistor in a first region and at least one second field-effect transistor having a metal-oxide-semiconductor structure in at least one second region; each of the first transistors includes a first gate structure along a first length of a first fin on the semiconductor substrate, the first fin having a first width at a first surface of the semiconductor substrate and being isolated by a first trench in the semiconductor substrate, each first gate structure having a first spacer having a first thickness on its side; each second transistor includes a second gate structure on the first surface of the semiconductor substrate with a second length greater than the first length, each second gate structure having a second spacer having a second thickness greater than the first thickness on its side.

[0023] According to one embodiment, in a third region of at least one second region, a third transistor of at least one second transistor is formed on top of and inside a mesa flush with a first surface of the semiconductor substrate.

[0024] According to one embodiment, a fourth transistor in at least one second transistor is formed in a fourth region of at least one second region along a second fin of a semiconductor substrate. The second fin has a second width at a first surface of the semiconductor substrate and is isolated by a second trench in the semiconductor substrate. The second width is greater than a first width; for example, the second width is at least twice the size of the first width; and / or the first width is less than 15 nm, for example, less than or equal to 10 nm; and / or the second width is greater than 20 nm, for example, greater than or equal to 30 nm.

[0025] According to one embodiment, a plurality of second transistors are formed in a plurality of second regions; in a third region of at least one second region, a third transistor of at least one second transistor is formed on top of and inside a mesa flush with a first surface of the semiconductor substrate; and in a fourth region of at least one second region, a fourth transistor of at least one second transistor is formed on top of and inside a second fin flush with a first surface of the semiconductor substrate and isolated by a second trench in the semiconductor substrate, the second fin having a second width greater than a first width, for example, being at least twice the first width or equal to the first width.

[0026] According to one embodiment, the method includes forming the first fin in the first region and the second fin in the fourth region. The formation of the first and second fins includes: forming a first pillar in the first region and a second pillar in the fourth region on a first surface of a semiconductor substrate, the first and second pillars being arranged side-by-side and made of a first material, such as amorphous silicon, the first pillars being spaced apart by a first distance and the second pillars being spaced apart by a second distance; depositing a sixth layer made of a second material (e.g., silicon oxide) selectively etchable relative to the first material on the first and second pillars, the sixth layer having a third thickness on the sides of the first and second pillars; removing the sixth layer from the first region, the sixth layer remaining on the sides of the second pillars in the fourth region; and depositing a second material on the first and second pillars. A seventh layer is formed, the seventh layer having a fourth thickness, the fourth thickness being defined to form first posts separated from each other between the first posts on the side surface of the first posts; the sixth and seventh layers form second bodies on the side surface of the second posts, the third and fourth thicknesses being defined such that the second posts are connected between the second posts, the connected second posts forming a third post coupling two adjacent second posts; and, for example, the first and second posts made of a first material are removed by etching; the semiconductor substrate is etched from the first surface by forming the first, second and third posts made of a second material using an etching mask; the etching of the semiconductor substrate forms a first trench in the semiconductor substrate, defining a first fin between the first trenches in a first region, and forms a second trench in the semiconductor substrate, defining a second fin between the second trenches in a fourth region.

[0027] According to one embodiment, the fourth thickness is less than the third thickness.

[0028] According to one embodiment, the fourth thickness is less than half of the first distance.

[0029] According to one embodiment, the third thickness is greater than or equal to half of the second distance.

[0030] According to one embodiment, the first distance is substantially equal to the second distance.

[0031] According to one embodiment, the first thickness is less than or equal to 15 nm and the second thickness is greater than or equal to 30 nm.

[0032] According to one embodiment, the first length is less than or equal to 30 nm and the second length is greater than or equal to 150 nm.

[0033] One embodiment provides a method for fabricating at least one first fin and at least one second fin inside and on top of a semiconductor substrate, wherein the at least one first fin is used for a first fin field-effect transistor (FinFET) in a first region of an electronic device, and the at least one second fin is used for at least one second field-effect transistor (MOSFET) having a metal-oxide-semiconductor structure in a second region of the electronic device. The method includes: forming a first pillar in the first region and a second pillar in the second region on a first surface of the semiconductor substrate, the first and second pillars being arranged side-by-side and made of a first material, the first pillars being spaced apart by a first distance, and the second pillars being spaced apart by a second distance; depositing a sixth layer on the first and second pillars, the sixth layer being made of a second material selectively etchable relative to the first material, the sixth layer having a third thickness on the sides of the first and second pillars; removing the sixth layer from the first region, the sixth layer remaining in the second region. On the side surface of the second pillar; depositing a seventh layer made of a second material on the first and second pillars, the seventh layer having a fourth thickness, the fourth thickness being defined to form first pillars separated from each other between the first pillars on the side surface of the first pillars; the sixth and seventh layers forming second pillars on the side surface of the second pillars, the third and fourth thicknesses being defined such that the second pillars are connected between the second pillars, the connected second pillars forming a third pillar coupling two adjacent second pillars; and removing the first and second pillars, for example, by etching; etching the semiconductor substrate from the first surface by forming the first, second, and third pillars of an etching mask; etching the semiconductor substrate, forming a first trench in the semiconductor substrate, the first trench defining at least one first fin having a first width between the first trenches in the first region, and forming a second trench in the semiconductor substrate, the second trench defining at least one second fin having a second width between the second trenches in the second region, the second width being greater than the first width.

[0034] According to one embodiment, the second material can also be selectively etched relative to the semiconductor substrate.

[0035] According to one embodiment, the first material includes, for example, amorphous silicon, and the second material includes, for example, an oxide, such as silicon oxide.

[0036] According to one embodiment, the fourth thickness is less than the third thickness.

[0037] According to one embodiment, the fourth thickness is less than half of the first distance.

[0038] According to one embodiment, the third thickness is greater than or equal to half of the second distance.

[0039] According to one embodiment, the first distance is substantially equal to the second distance.

[0040] According to one embodiment, all the first columns are arranged with the same first pitch, and all the second columns are arranged with the same second pitch.

[0041] According to one embodiment, the first pitch is substantially equal to the second pitch.

[0042] According to one embodiment, a first distance, a first pitch, and a fourth thickness are determined such that the first columns are arranged with the same third pitch.

[0043] According to one embodiment, the third pitch is essentially half the first pitch.

[0044] According to one embodiment, the second width is at least twice the size of the first width or equal to the first width.

[0045] According to one embodiment, the first width is less than 15 nm, for example, less than or equal to 10 nm, and the second width is greater than 20 nm, for example, greater than or equal to 30 nm.

[0046] According to one embodiment, an eighth layer made of an oxide, such as silicon oxide, is disposed on a semiconductor substrate, and a ninth layer made of a nitride, such as silicon nitride, is disposed on the eighth layer. A first pillar and a second pillar are formed on the ninth layer, and the eighth and ninth layers are removed, for example, after etching the semiconductor substrate. Attached Figure Description

[0047] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which: FIG1 is a partially simplified cross-sectional view of an example of an electronic device according to one embodiment; FIGS. 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, and 13 are cross-sectional views or top views illustrating steps of a first example of a method of manufacturing an electronic device according to one embodiment; FIGS. 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25A, 25B, 26, 27, 28, 29, and 30 are cross-sectional views or top views illustrating steps of a second example of a method of manufacturing an electronic device according to one embodiment, the electronic device corresponding to the electronic device of FIG. 1; and FIGS. 31A and 31B are partial and simplified cross-sectional views of another example of an electronic device according to one embodiment. Detailed Implementation

[0048] In the various figures, the same features are indicated by the same reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0049] For clarity, only those steps and elements useful for understanding the described embodiments are shown and described in detail. In particular, not all steps of the manufacturing method are detailed, and the described embodiments are compatible with all or most electronic device manufacturing methods, especially FinFET technology manufacturing methods, and may be modified to the extent that those skilled in the art are capable of reading this disclosure.

[0050] Unless otherwise stated, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled through one or more other elements.

[0051] In the following description, reference will be made to absolute positional qualifiers (e.g., terms “front”, “back”, “top”, “bottom”, “left”, “right”, etc.) or relative positional qualifiers (e.g., terms “top”, “bottom”, “up”, “down”, etc.) or orientational qualifiers (e.g., “horizontal”, “numerical”, etc.) unless the orientation of the figures is otherwise specified.

[0052] Unless otherwise stated, the expressions “about,” “approximately,” “substantially,” and “on the order of…” indicate plus or minus 10% or 10°, preferably plus or minus 5% or 5°.

[0053] Throughout the specification, the term "on" is used without distinguishing the spatial orientation of the element referred to by the term. For example, in the description or feature "on the surface of a layer," the surface is not necessarily oriented upwards, but can correspond to a surface oriented in any direction. For example, when a layer is deposited on an element, this means that when the layer is deposited, it is deposited on all exposed portions of the element. Furthermore, the arrangement of the first element on the second element should be understood to correspond to an arrangement in which the first element directly abuts the second element and there are no intermediate elements between the first and second elements, or it may correspond to an arrangement in which the first element is on the second element and there are one or more intermediate elements between the first and second elements.

[0054] In the following description, unless otherwise stated, the modifiers “insulating” and “conductive” refer to electrical insulation and electrical conduction, respectively.

[0055] In the following description, when referring to a substrate, unless otherwise stated, it refers to a semiconductor substrate.

[0056] In the following description, the channel length of a transistor essentially corresponds to the distance between the source and drain regions of the transistor. The gate length or gate structure is defined along the channel length direction.

[0057] In the following description, the term "fin" refers to a generally elongated, protruding rib. The fin is made of a semiconductor material of the substrate and is defined by trenches formed in the substrate on either side of the fin.

[0058] Figure 1 is a partially simplified cross-sectional view of an example of an electronic device 100 according to one embodiment.

[0059] The electronic device 100 in Figure 1 is, for example, an electronic chip, or a part of an electronic chip.

[0060] Electronic device 100 includes a semiconductor substrate 101. As an example, substrate 101 is made of or based on silicon.

[0061] Figure 1 shows two regions (a) and (b) of an electronic device 100, where three FinFET transistors 10 and one MOSFET transistor 20 are formed, respectively. The FinFET transistors 10 are formed along thin fins on a semiconductor substrate 101. The MOSFET transistor 20 may be formed on top of and inside islands (also called mesas) on the semiconductor substrate 101, or on top of and inside wide fins (wider than the thin fins of the FinFET transistors 10) on the semiconductor substrate 101. Examples of fins and mesas are described later in this disclosure. The fins and mesas are structures of the semiconductor substrate 101 that are flush with the upper surface 101A of the substrate 101 and isolated from the upper surface 101A by trenches formed in the substrate 101.

[0062] It should be understood that, in practice, region (a) may include multiple FinFET transistors, not just three, while region (b) may include multiple MOSFET transistors, not just one. Furthermore, electronic device 100 may include other electronic components, such as other transistors like bipolar transistors, diodes, and / or resistors.

[0063] Region (a) is isolated from region (b) by one or more isolation trenches 151. The MOSFET transistor is also isolated by another isolation trench 152 on the side opposite to region (a). The isolation trenches 151, 152 are, for example, shallow trench isolation (STI) trenches. The isolation trenches 151, 152 extend from the upper surface 101A of the semiconductor substrate 101, or extend from or slightly above the upper surface 101A into the layer 103 described below.

[0064] In region (a), semiconductor region 11 extends in substrate 101 on either side of gate structure 110. Similarly, in region (b), semiconductor region 12 extends in substrate 101 on either side of gate structure 120. Semiconductor regions 11 and 12 are, for example, epitaxial layers or regions, formed, for example, by epitaxy in a cavity (e.g., a shallow cavity or trench) formed in substrate 101 from upper surface 101A. Semiconductor regions 11 and 12 are flush with upper surface 101A and preferably extend downward to a depth smaller than or even smaller than the thickness of substrate 101.

[0065] For example, at least the upper portion 101S of the substrate 101, having a depth greater than or equal to the depth of the semiconductor regions 11 and 12, is doped with a first conductivity type or a doped well including the first conductivity type (e.g., N-type), and the semiconductor regions 11 and 12 are doped with a second conductivity type (e.g., P-type) to form a P-type transistor (PMOS and PMOS FinFET). For example, the semiconductor regions 11 and 12 include germanium and boron atoms in silicon (SiGeB).

[0066] In the remainder of this disclosure, the first conductivity type is considered to be N-type and the second conductivity type is P-type, although it can be the other way around, i.e., the first conductivity type is P-type and the second conductivity type is N-type.

[0067] As a variant, semiconductor region 11 and / or semiconductor region 12 may be N-type doped, for example including phosphorus atoms in silicon (SiP) to form N-type transistors (NMOS and FinFET NMOS), and then the well in substrate 101 will be modified accordingly, depending on the conductivity type of substrate 101.

[0068] Those skilled in the art may consider forming an N-type FinFET transistor inside and on top of another thin fin, and / or forming an NMOS transistor (wide fin or mesa) inside and on top of the semiconductor substrate 101. More broadly, the electronic device 100 may include a PMOS FinFET transistor and / or an NMOS FinFET transistor co-integrated with a PMOS MOSFET transistor and / or an NMOS MOSFET transistor, the MOSFET transistor being disposed on top of and inside the mesa of the semiconductor substrate 101 and / or on top of and inside the wide fin of the semiconductor substrate 101.

[0069] Semiconductor region 11 corresponds to the source and drain regions of FinFET transistor 10. In this structure, the drain of one FinFET transistor corresponds to the source of an adjacent FinFET transistor, and / or conversely, the source of one FinFET transistor corresponds to the drain of an adjacent FinFET transistor.

[0070] Semiconductor region 12 corresponds to the source region and drain region of MOSFET transistor 20.

[0071] Each gate structure 110, 120 is positioned on the upper surface 101A of the substrate 101, and is typically insulated from the substrate by a gate insulating layer or gate insulator 111, 121. The gate insulator is, for example, silicon oxide such as SiO2 or oxide nitride.

[0072] In region (b), the gate insulator 121 also covers at least a portion of the height of the gate structure 120, the height of which corresponds to the lower portion 120A described above. Furthermore, the thickness e2 of the gate insulator 121 of the MOSFET 20 is greater than the thickness e1 of the gate insulator 111 of the FinFET transistor 10; for example, thickness e2 is at least twice the thickness e1. This allows for the presence of a high-voltage MOSFET transistor or an HV transistor in region (b). The HV transistor 20 operates, for example, at at least 3.3 volts (V). The FinFET transistor 10 typically operates at voltages less than about 1 V.

[0073] For example, thickness e2 is in the range of 5nm to 8nm, for example equal to about 6.5nm (corresponding to GO2, "Gate Oxide 2" transistor), and thickness e1 is in the range of 0.6nm to 1.5nm, for example equal to about 0.8nm (corresponding to GO1, "Gate Oxide 1" transistor).

[0074] Each gate structure 110, 120 includes a single-layer or multi-layer structure, typically including at least one metallic material, such as titanium nitride (TiN), tantalum nitride (TaN), and / or tungsten (W).

[0075] For example, each gate structure 110, 120 includes a lower portion 110A, 120A, the lower portion 110A, 120A including: a high permittivity or dielectric constant (high k) material layer 112, 122, such as hafnium oxide (HfO2), on the bottom of the gate insulating layers 111, 121 and the sidewalls of the gate structures 110, 120; layers 113, 123 on layers 112, 122 made of a metallic material such as titanium nitride (TiN); and layers 114, 124 on layers 113, 123 made of a metallic material different from layers 113, 123 (e.g., made of tungsten (W)).

[0076] It should be noted that high dielectric constant materials or high-k materials are materials whose dielectric constant is greater than that of silicon dioxide.

[0077] In region (a), the high-k layer 112 directly covers the sidewall of each gate structure 110, while in region (b), the high-k layer 122 covers the gate insulator 121 on the sidewall of the gate structure 120.

[0078] Layers 112, 122 and 113, 123 are, for example, U-shaped, and layers 114, 124 each correspond to fill layers that fill the spaces of gate structures 110, 120 that are not filled by other layers.

[0079] In the illustrated example, each gate structure 110, 120 includes an upper portion 110B, 120B on a lower portion 110A, 120A, the upper portion including a silicon nitride layer 115, 125. This layer 115, 125 forms a protective layer during the removal of the oxide layer 104 described below to deposit silicide contact layers over the drain and source regions.

[0080] This example of a gate structure is not limiting, and other gate structures may be considered by those skilled in the art.

[0081] The length L2 of the gate structure 120 of MOSFET 20 is greater than the length L1 of the gate structure 110 of each FinFET 10. It should be noted that the length of the gate structure is obtained in the direction of the channel length of the transistor under consideration, as shown in Figure 1.

[0082] For example, the length L1 is less than or equal to 30 nm, and the length L2 is greater than or equal to 150 nm.

[0083] Layers 131 and 141 made of dielectric material are positioned on the side surfaces of each gate structure 110 and 120, forming spacer layers or spacers on either side of the gate structures 110 and 120. Advantageously, the dielectric material of the spacers 131 and 141 is a material with low permittivity or low dielectric constant (low k), such as SiOCN or SiBCN. When applied to spacers, low dielectric constant or low k materials are materials with a dielectric constant lower than that of silicon nitride, typically with a dielectric constant lower than 7, but typically higher than that of silicon oxide (which is approximately equal to 3.9).

[0084] For example, the thickness e8 (first thickness) of spacer 131 is in the range of 3 nm to 10 nm or less than 15 nm, and the thickness of spacer 141 is in the range of 3 nm to 10 nm or less than 15 nm.

[0085] The given thickness of all spacers is obtained at the upper surface 101A of the substrate 101.

[0086] In region (a), spacer 131 is mainly on the side of gate structure 110.

[0087] In region (b), the gate insulating layer 121 includes an insulating portion 126 or is coupled to the insulating portion 126 (e.g., a portion of an oxide such as SiO2) on either side of the gate structure 120, and spacers 141 also extend over this insulating portion 126. The spacers 141 are therefore L-shaped.

[0088] In region (b), each spacer 141 is part of a spacer structure 140, which includes a plurality of other spacers made of a dielectric material. Thus, spacer structures 140 are present on each side of the gate structure 120. In the example shown, in addition to spacers 141, each spacer structure 140 includes: a spacer 142 positioned on the L-shaped spacer 141, which is semi-D-shaped or a triangle with a curved bevel (hereinafter referred to as D); a curved spacer 143 on the spacer 142, following the curved shape of the spacer 142; the spacer 143 does not necessarily extend along the entire height of the spacer 142 and may extend over the insulating portion 126; and a curved spacer 144 on the spacer 143, following the curved shape of the spacer 143 and not extending over the insulating portion 126.

[0089] For example, the materials of the various spacers in spacer structure 140 are not all the same.

[0090] For example, spacer 141 is made of a low-k material, spacer 142 is made of a nitride (e.g., silicon nitride), spacer 143 is made of silicon nitride, and spacer 144 is made of a low-k material.

[0091] For example, the thickness of spacer 142 is in the range of 15 nm to 40 nm. For example, the thickness of spacer 143 is in the range of 10 nm to 20 nm. For example, the thickness of spacer 144 is in the range of 3 nm to 10 nm.

[0092] For example, the thickness e9 (second thickness) of the spacer structure 140 obtained at the upper surface 101A of the substrate 101 is in the range of 30 nm to 60 nm, or greater than 30 nm.

[0093] Therefore, the thickness e9 of the spacer structure 140 of the MOSFET transistor 20 is much greater than the thickness e8 of the spacer 131 of the FinFET transistor 10. This large thickness of the spacer structure 140 of the MOSFET transistor 20 allows the source and drain regions 12 to be spaced apart from the gate 120 of the MOSFET transistor 20. This prevents the transistor from breaking down when operating at high voltages typically above 3V, making the MOSFET transistor 20 suitable for operation at such high voltages. In fact, during the formation of these regions, the spacer is specifically adjusted to regulate the spacing between the source and drain regions.

[0094] A layer 103 made of a dielectric material (e.g., silicon nitride) covers the uncovered portion of the upper surface 101A of the substrate 101, as well as the sides of the gate structures 110 and 120 covered by spacers 131 and 140, following the shape of these spacers.

[0095] For example, an oxide layer 104 made of SiO2 fills the space between the portion of the upper surface 101A covered by layer 103 and the gate structures 110 and 120, the spacers 131 and 141, and the side surfaces covered by layer 103. Thus, the oxide layer 104 includes multiple oxide portions within these spaces.

[0096] Figures 2 through 30 below illustrate several examples of methods for fabricating FinFET transistors and, for example, MOSFET transistors adjacent to FinFET transistors in the same electronic device in a co-integrated manner.

[0097] Figures 2 through 30 below show a first region (a) and a second region (b) of substrate 101, in which FinFET transistors are formed inside and on top of the first region (a), and MOSFET transistors are formed inside and on top of the second region (b).

[0098] Figures 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, and 13 are simplified cross-sectional or top views illustrating the steps of a first example of a method for manufacturing an electronic device according to an embodiment.

[0099] The cross-sectional views in Figures 2 to 12 were obtained along the cross-sectional plane A'A' shown by the dashed line in Figure 13, which is a top view of Figure 12 after the etch mask has been removed.

[0100] Figures 2 to 13 show a first example of a first stage of a manufacturing method, which is followed by a second stage, which may be similar to or adapted from the steps shown in Figures 20 to 30.

[0101] Figure 2 shows the initial structure including the semiconductor substrate 101 (SUB(Si)) in a partial cross-sectional view.

[0102] An oxide layer 202, such as silicon oxide (SiO2), is located on the substrate 101.

[0103] A protective (or etch-stop) layer 203, made of a dielectric material such as silicon nitride (SiN), is located on the oxide layer 202.

[0104] As a variant, layer 202 can be a silicon nitride layer, and layer 203 can be a silicon oxide layer. However, in this case, layers 210 and 220, which are deposited on layer 203 and selectively etched over layer 203 as described below, are not made of silicon oxide, but rather, for example, silicon nitride. More generally, those skilled in the art will know how to adjust the materials of the layers while taking into account at least the etch selectivity criteria.

[0105] Multiple columnar elements 204 (referred to as "mandrels") are located on layer 203. The columnar elements 204 can extend in a direction perpendicular to FIG. 2, and therefore can be in the form of arms. The columnar elements 204 are arranged in rows, i.e., side by side in the same direction.

[0106] In the example of Figure 2, the pillars are made of amorphous silicon (aSi). Multiple pillars include pillar 204A in region (a) and pillar 204B in region (b). In the example of Figure 2, the width l1 and pitch p1 of pillar 204 are substantially the same for all pillars 204A and 204B. In other words, the spacing D1 or distance D1 between two adjacent pillars 204A in region (a) is substantially equal to the distance D1 between two adjacent pillars 204B in region (b). This is not limiting; for example, the distance between pillars 204A can be greater than the distance between pillars 204B. Furthermore, the width of pillar 204A can be different from the width of pillar 204B. Pillars 204A and 204B located between the two regions (a) and (b) have a spacing D2 that is preferably larger than the distance D1.

[0107] The pitch p1 of the column 204 is, for example, in the range of 60 nm to 120 nm, such as approximately 80 nm. The width l1 of the column 204 is, for example, in the range of 20 nm to 40 nm, such as approximately 30 nm.

[0108] The column 204 can be obtained by performing photolithography, for example by depositing an amorphous silicon layer on layer 203 and then obtaining it by etching a mask that includes a pattern of serrations and protrusions suitable for forming the column 204 (specifically suitable for the desired column width and the desired distance between the columns), and then etching the amorphous silicon layer by etching the mask.

[0109] Figure 3 shows, in partial cross-sectional view, the structure obtained at the end of the step of depositing an oxide layer 210, such as SiO2, on the structure shown in Figure 2.

[0110] The thickness e3 of the oxide layer 210 is preferably suitable for filling the space between two adjacent pillars 204A in region (a) and the space between two adjacent pillars 204B in region (b), substantially along the entire height h1 of the pillars 204, thereby forming the portion between the pillars (posts) 211. The thickness e3 is, for example, in the range of 15 nm to 30 nm, for example, equal to about 20 nm for a pitch p1 of about 80 nm.

[0111] The oxide layer 210 further includes: a substantially horizontal portion 212 on the pillars 204A and 204B; a substantially horizontal portion 213 covering the layer 203 between the two regions (a) and (b); and a substantially vertical portion (pillar) 217 ​​abutting the side of the pillars 204A at the edge of the plurality of pillars 204A in region (a) and abutting the side of the pillars 204B at the edge of the plurality of pillars 204B in region (b).

[0112] The oxide layer 210 follows a serrated shape of multiple pillars 204. Therefore, the oxide layer 210 has a U-shaped portion 214 between the two regions (a) and (b), and may exhibit recesses 215, typically a few nanometers in size, in the portion between the pillars (columns) 211, which generally extend to the level of the upper surface 204S of the pillars 204. In a variant, the recesses 215 are absent.

[0113] Figure 4 shows, in partial cross-sectional view, the structure obtained at the end of the etching step (preferably dry etching) of oxide layer 210, in order to remove horizontal portions 212 and 213 while retaining the portion between pillars (body) 211 (with recess 216 that can be deeper than recess 215 before etching, below the level of the upper surface 204S of pillar 204), and simultaneously leaving vertical portions (pillars) 217 ​​in regions (a) and (b).

[0114] The etching in Figure 4 is preferably performed on a thickness substantially equal to the thickness e3 of the oxide layer 210. This etching exposes the columnar structures 204A and 204B.

[0115] Figure 5 shows the structure obtained at the end in a partial cross-sectional view: an etching mask 205 (PR1) is formed, which covers the portion between pillars 211 and vertical portion 217 in region (b) of pillar 204B, while exposing the portion between pillars 211 and vertical portion 217 in region (a) of pillar 204A; then an etching step is performed to remove the portion between pillars 211 and vertical portion 217 in region (a): wet etching is used, which is capable of removing oxides in multiple directions (isotropic etching), and the etching is selective relative to the silicon of pillar 204A and the material (resin) of etching mask 205.

[0116] Then remove the etch mask 205.

[0117] Figure 6 shows, in partial cross-sectional view, the structure obtained at the end of the step of depositing another oxide layer 220 on the structure shown in Figure 5, which is made of the same material as oxide layer 210, such as SiO2.

[0118] The oxide layer 220 has a thickness e4 that is smaller than the thickness e3 of the oxide layer 210, and such that it does not fill the space between two adjacent pillars 204A in region (a). Preferably, the thickness e4 is less than half the distance D1 between the two pillars 204A. The thickness e4 is, for example, in the range of 5 nm to 15 nm, and for example, for a pitch p1 of about 80 nm, the thickness e4 is equal to about 10 nm.

[0119] The oxide layer 220 includes: a substantially horizontal portion 222 on pillars 204A and 204B in regions (a) and (b); a substantially vertical portion (pillar) 227 on the side of pillar 204A in region (a); and substantially vertical portions (pillars) 228 formed together with the vertical portions (pillars) 217 ​​on the side of two pillars 204B at the edges of a plurality of pillars 204B in region (b). Adjacent vertical portions (pillars) 227 in region (a) are separated from each other by a non-zero distance. Between the two regions (a) and (b), the oxide layer 220 includes a substantially horizontal portion 223 of the capping layer 203. The vertical portions (pillars) 227 and 228 between the two regions (a) and (b) are also separated. In region (a), oxide layer 220 follows a serrated shape of a plurality of pillars 204A, thereby forming a U-shaped portion 225 between two adjacent pillars 204A. Oxide layer 220 also includes a U-shaped portion 224 between the two regions (a) and (b). In region (b), oxide layer 220 at least partially fills the recesses 216 in the portion between pillars 221, thus enabling the formation of recesses 225 having a depth substantially the same as the depth of recesses 215. As a variant, recesses 225 are absent. As a variant, the portion between pillars 221 fills the space between two adjacent pillars 204B in region (b). For example, the portion between pillars 221 corresponds to a vertical portion (pillar) 228 joined together between two pillars 204B.

[0120] Figure 7 shows a partial cross-sectional view of the structure obtained at the end of the etching (preferably dry etching) step of oxide layer 220, in order to remove horizontal portions 222 and 223 while retaining the portion between columnar sections 221 in region (b), vertical sections 227 in region (a), and vertical sections 228 in region (b). The etching in Figure 7 is preferably performed on a thickness substantially equal to the thickness e4 of oxide layer 220 in order to expose columnar sections 204A and 204B.

[0121] Figure 8 shows a partial cross-sectional view of the structure obtained at the end of the step of removing pillars 204A and 204B by etching, leaving only the portion between pillars 221, vertical portions 227, and vertical portions 228 on layer 203. Preferably, wet etching is used, which is capable of unidirectionally removing the silicon of pillar 204A (anisotropic etching), and this etching is selective relative to the silicon oxide of portions 221, 227, 228 and the silicon nitride of layer 203.

[0122] The portion between column (column) 221 and vertical portions (columns) 227 and 228 typically extends in the form of an arm in a direction perpendicular to Figure 8.

[0123] The portion between the columns (pillars) 221 in region (b) has a width l3 that is substantially equal to the distance D1 between the two columns 204B, and their pitch p1 is substantially equal to the pitch between the columns 204B.

[0124] The width l2 of the vertical portion (pillar) 227 in region (a) is substantially equal to the thickness e4 of the oxide layer 220, or even smaller due to the etching in FIG. 7. The width l2 of the vertical portion (pillar) 227 is less than half the distance D1 between the two pillars 204A, and therefore much smaller than the width l3 of the portion between the pillars 221. Furthermore, since each pillar 204A is replaced by two vertical portions (pillars) 227, the pitch p2 of the vertical portions (pillars) 227 is much smaller than the pitch p1 between the pillars 204A, for example, about half the pitch p1. For example, for a pitch p1 that is substantially equal to 80 nm, a pitch p2 that is substantially equal to 40 nm can be obtained.

[0125] The values ​​of distance D1, width d1 of column 204 and thickness e4 of oxide layer 220 can be advantageously defined such that the vertical portions (columns) 227 all have the same pitch p2.

[0126] Due to the etching in Figures 4 and 7, the width l4 of the vertical portion (pillar) 228 in region (b) is substantially equal to or may be less than the sum of the thicknesses e3 and e4 of oxide layers 210 and 220.

[0127] The portion between the columnar section (pillar) 221 and the vertical portions (pillars) 227 and 228 will be used as an etching mask during the etching of the semiconductor substrate 101 in the next step to form fins separated by trenches in the substrate 101, as explained below. Given that the vertical portion (pillar) 227 in region (a) has a width l2 smaller than the width l3 of the portion between the columnar sections (pillars) 221 in region (b) and a pitch p2 smaller than its pitch p1, fins that are thinner and denser in region (a) than in region (b) can be formed.

[0128] The portion between the column (column) 221 and the vertical portions (columns) 227 and 228 can be called a "fin spacer".

[0129] By forming oxide layers 210 and 220 in two steps, it is possible to form fin spacers with different widths and pitches in two regions (a) and (b), and thus fins with different widths and pitches in two regions (a) and (b), wherein a thick oxide layer 210 fills the space between the pillars, which is removed from region (a), and then another thin oxide layer 220 does not fill the space between the pillars in region (a). As a variation, the gaps between the pillars in region (b) can be filled by combining the thicknesses of the two oxide layers 210 and 220, rather than necessarily by oxide layer 210 alone. The difference is that once the pillars are removed, a pattern of thin, dense fin spacers is obtained in region (a), and a pattern of wider, less dense fin spacers is obtained in region (b). These fin spacers form the pattern for forming the etch mask for forming trenches and thus fins, as described below.

[0130] Figure 9 shows, in partial cross-sectional view, the structure obtained at the end of the step of etching semiconductor substrate 101 through layers 203 and 202, which are also etched.

[0131] As described above, the etching is performed using an etching mask formed by the portion between the column (pillar) 221 and the vertical portions (pillars) 227 and 228.

[0132] To obtain the structure of Figure 9 from Figure 8, a mask can be formed that at least covers the central region between two vertical portions (pillars) 227 and 228 positioned opposite each other between regions (a) and (b) so as not to etch the substrate 101 between regions (a) and (b). This mask can surround the two opposing vertical portions 227 and 228. The distance between regions (a) and (b) is generally greater than the distance shown in the figures. In other words, regions (a) and (b) are generally farther apart from each other.

[0133] The etching step forms trench 231 in region (a) and trench 232 in region (b) in substrate 101. Trench 231, 232 extend downward from the upper surface 101A of substrate 101 to a depth e5 less than the thickness of substrate 101.

[0134] The formation of trenches 231 and 232 allows fins 233 and 234 to be defined between trenches 231 and 232. Fins 233 and 234 correspond to unetched portions of semiconductor substrate 101, which are protected during etching by portions between pillars 221 and vertical portions 227.

[0135] In region (a), fin 233 has a width l2 measured at the upper surface 101A of substrate 101, which is substantially equal to the width l2 of the vertical portions (pillars) 227, and fin 233 has a pitch p2 substantially equal to the pitch p2 between the vertical portions (pillars) 227. Similarly, in region (b), fin 234 has a width l3 measured at the upper surface 101A of substrate 101, which is substantially equal to the width l3 of the portions between pillars (pillars) 221, and fin 234 has a pitch p1 substantially equal to the pitch p1 between the portions between pillars (pillars) 221. Therefore, as described above, fin 233 (thin fin) in region (a) is thinner and more compact than fin 234 (wide fin) in region (b). For example, width l3 is greater than or equal to twice the width l2. Thin fins 233 form the fins of the FinFET transistor 10. Wide fins 234 can form fins for one or more transistors (e.g., MOSFET transistors, e.g., HV transistors).

[0136] The advantage of forming a finned MOSFET transistor is that it provides a larger transistor width than planar or mesa transistors. In fact, because the transistor gate surrounds the fin, the gate includes a vertical portion surrounding the fin that participates in conduction. Now, in a top view, for the same surface area, a larger transistor width gives the transistor better performance, for example, a 30% increase in transistor width from 80nm in planar mode to 110nm in finned mode.

[0137] As an example, trenches 231 and 232 do not have a rectangular shape with the bottom orthogonal to the side surfaces in a cross-sectional view. Trenches 231 and 232 have a trapezoidal shape, for example, in a cross-sectional view, wherein the width of trenches 231 and 232 at the upper surface 101A of substrate 101 is greater than the width of trenches 231 and 232 at the bottom of these trenches.

[0138] For example, the width l2 of the thin fin 233 cut off at the upper surface 101A of the substrate 101 is less than 15 nm, for example less than or equal to 10 nm.

[0139] For example, the width l3 of the wide fin 234 at the upper surface 101A of the substrate 101 is greater than or equal to 20 nm, for example, equal to about 30 nm.

[0140] Then remove layers 202 and 203.

[0141] Figure 10 shows, in partial cross-sectional view, the structure obtained at the end of the step of depositing another oxide layer 240 (e.g., SiO2) on the structure shown in Figure 9. More specifically, during this step, the oxide layer 240 is deposited in trenches 231 and 232 and on fins 233 and 234, i.e., covering the upper surface 101A of the substrate 101.

[0142] Figure 11 shows a partially simplified cross-sectional view of the structure obtained at the end of the step of removing the oxide layer 240 from the upper part of the structure shown in Figure 10.

[0143] More specifically, in the first step, the oxide layer 240 is removed from the upper surface 101A of the substrate 101. This removal is performed, for example, by chemical mechanical polishing (CMP). The removal of the oxide layer 240 stops, for example, when the upper surface 101A of the substrate 101 is exposed.

[0144] In the second step, the oxide layer 240 is removed from the upper portion of trenches 231, 232, so that only the oxide portions 241, 242 of the oxide layer 240 are retained in the lower portions of trenches 231, 232. This removal proceeds, for example, to a depth in the range of 10 nm to 100 nm, on the order of 50 nm. After this step, thin fins 233 and wide fins 234 are formed on which various transistors will be fabricated.

[0145] Figure 12 shows, in a partial and simplified cross-section, the structure obtained at the end of the following operations: forming an isolation trench 250 (STI) between two regions (a) and (b) in substrate 101; then forming an etch mask 206 (PR2) covering region (a) but exposing region (b): more specifically, the etch mask 206 is deposited in a trench 231 on oxide portion 241, on fin 233, and may be partially deposited on isolation trench 250; then the step of implanting a well 207 in the region (b) of substrate 101 not covered by etch mask 206 is performed.

[0146] The etch mask 206 is then removed, as shown in the top view of Figure 13. It should be noted that, for simplicity, the oxide portions 241 and 242 in trenches 231 and 232 are not shown in Figure 13. Therefore, Figure 13 shows the thin fin 233 in region (a) and the wide fin 234 in region (b), as well as the isolation trench 250 between regions (a) and (b).

[0147] As described above, the first stage of the manufacturing method shown in Figures 2 to 13 is followed by a second stage, which may be similar to or derived from the steps shown in Figures 20 to 30 below.

[0148] Figures 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25A, 25B, 26, 27, 28, 29, and 30 are cross-sectional and top views illustrating steps of a second example of a method for manufacturing an electronic device according to one embodiment, corresponding to the electronic device 100 of Figure 1.

[0149] Figures 14 to 19 show a second example of the first stage of the manufacturing method, followed by the second stage, the steps of which are shown in Figures 20 to 30.

[0150] The cross-sectional views in Figures 14 to 18 were obtained along the cross-sectional plane AA shown by the dashed line in Figure 19 after the etch mask was removed. Figure 19 is a top view of Figure 18.

[0151] The cross-sectional views of Figures 20 to 30 are obtained along the cross-sectional plane BB shown by the dashed line in Figure 19. Specifically, cross-section BB is obtained along the thin fins 233 of the semiconductor substrate 101 and corresponds to the channel length direction of the FinFET (“fin field-effect transistor”) formed inside and on top of the fins 233. Cross-section BB is also obtained along the channel length direction of the MOSFET (metal-oxide-semiconductor field-effect transistor) formed inside and on top of the semiconductor substrate 101 (inside and on top of the mesa 235). The cross-sectional views of Figures 20 to 30 can be obtained along the cross-sectional plane B'B' shown by the dashed line in Figure 13, which then follows the thin fins 233 and the wide fins 234 of the semiconductor substrate 101.

[0152] The second example of the first stage shown in Figures 14 to 19 differs from the first example shown in Figures 2 to 13 in that it does not include the formation of wide fins in region (b). Therefore, the MOSFET transistor will be formed in region (b) on a planar portion of the semiconductor substrate 101, which can be a mesa, i.e., a planar portion surrounded by isolation trenches. The term "mesa" refers to the form of an island.

[0153] Figure 14 shows a partial and simplified cross-sectional view of an initial structure similar to that shown in Figure 6, but without pillars 204B and portions 221, 222, 228 in region (b). Therefore, the initial structure comprises: a semiconductor substrate 101 (SUB(Si)); an oxide layer 202 of silicon oxide (SiO2) on the substrate 101; a protective layer 203 made of a dielectric material such as silicon nitride (SiN) on the oxide layer 202; and pillars 204A made of amorphous silicon (aSi) in region (a). An oxide layer 320 of SiO2, for example, is deposited on pillars 204A and layer 203. The oxide layer 320 is similar to the oxide layer 220 described with respect to Figure 6, and specifically, it has a similar thickness e4 such that it does not fill the space between two adjacent pillars 204A in region (a). Preferably, the thickness e4 is less than half the distance D1 between the two pillars 204A.

[0154] The oxide layer 320 includes: a substantially horizontal portion 322 on the column 204A; a substantially horizontal portion 323 on the layer 203 in region (b), between the two regions (a) and (b), and between the column 204A in region (a); and a substantially vertical portion (column) 227 on the side of the column 204A, similar to the vertical portion (column) 227 described with respect to FIG6.

[0155] In region (a), the oxide layer 320 follows a serrated shape of a plurality of pillars 204A, thereby forming a U-shaped portion 225 between two adjacent pillars 204A, which is similar to the U-shaped portion 225 described with respect to FIG6.

[0156] Figure 15 shows, in a partial and simplified cross-sectional view, the structure obtained at the end of the etching (preferably dry etching) step of oxide layer 320, in order to remove the horizontal portions 322 and 323 while leaving the vertical portions (pillars) 227 in region (a). The etching in Figure 15 is preferably performed on a thickness substantially equal to the thickness e4 of oxide layer 220 in order to expose the pillars 204A.

[0157] Figure 16 illustrates, in a partial and simplified cross-sectional view, the structure obtained at the end of the step of removing the columnar structure 204A by anisotropic wet etching, leaving only the vertical portion (column) 227 on layer 203. The vertical portion (column) 227 typically extends in the form of an arm in a direction perpendicular to Figure 16.

[0158] Similar to the vertical portion (pillar) 227 described in conjunction with Figure 8, the vertical portion (pillar) 227 of Figure 16 has a width l2 that is substantially equal to the thickness e4 of the oxide layer 320, or even smaller due to the etching in Figure 15. Therefore, the width l2 of the vertical portion (pillar) 227 is less than half the distance D1 between the two pillars 204A. Furthermore, since each spindle 204A is replaced by two vertical portions (pillars) 227, the pitch p2 of the vertical portions (pillars) 227 is much smaller than the pitch p1 between the pillars 204A, for example, approximately half the pitch p1. For example, for a pitch p1 that is substantially equal to 80 nm, a pitch p2 that is substantially equal to 40 nm can be obtained.

[0159] The values ​​of distance D1, width d1 of column 204A and thickness e4 of oxide layer 320 can be advantageously defined so that vertical portions (columns) 227 have the same pitch p2.

[0160] Then, after the removal step, an etch mask 305 (PR3) is formed on region (b).

[0161] Figure 17 shows, in a partial and simplified cross-sectional view, the structure obtained at the end of etching the semiconductor substrate 101 through layers 203 and 202, which are also etched. The etching in Figure 17 is similar to the etching described in conjunction with Figure 9, except that it is performed in region (a), but the semiconductor substrate 101 is not etched in region (b), which is protected by the etching mask 305.

[0162] The etching is performed through the vertical portion (pillar) 227, which also forms an etching mask in region (a).

[0163] The etching step forms trenches 231 in the substrate 101 in region (a) similar to the trenches 231 shown in FIG. 9. The trenches 231 extend downward from the upper surface 101A of the substrate 101 to a depth e5 less than the thickness of the substrate 101. The formation of the trenches 231 allows for the definition of fins 233 between the trenches 231. The fins 233 correspond to the unetched portions of the semiconductor substrate 101 in region (a) protected by vertical portions (pillars) 227. The trenches 231 and fins 233 are formed only in region (a), while region (b) remains substantially flat.

[0164] The fin 233 has a width measured at the upper surface 101A of the substrate 101, which is substantially equal to the width l2 of the vertical portion (pillar) 227, and its pitch p2 is substantially equal to the pitch between the vertical portions (pillars) 227.

[0165] Fins 233 form the fins of FinFET transistor 10.

[0166] For example, the width of the fin 233 at the upper surface 101A of the substrate 101 is less than 15 nm, for example, less than or equal to 10 nm.

[0167] Then remove layers 202 and 203.

[0168] Then, another oxide layer can be deposited in trench 231 and on fin 233, followed by the removal of this oxide layer from the top of fin 233 and over the upper portion of trench 231, so that only a portion of oxide 241 remains in the lower portion of trench 231, similar to that described with respect to Figures 10 and 11, but only in region (a). In this case, a new mask is provided on the upper surface 101A of substrate 101 in region (b). This can be done before or after forming isolation trenches 151 and 152 as described below.

[0169] Figure 18 shows a partially simplified cross-sectional view of the structure obtained at the end of forming an isolation trench 151 (STI) between two regions (a) and (b) in the substrate 101 and forming an isolation trench 152 (STI) on the other side of region (b) opposite to the isolation trench 151. Trench 151 and 152 form a mesa 235 of the semiconductor substrate 101 in region (b).

[0170] Then, similar to that described in conjunction with FIG12, an etch mask 306 (PR4) is formed, covering region (a) but exposing region (b): more specifically, the etch mask 306 is deposited in the trench 231 on the oxide portion 241, on the fin 233, and may be partially deposited on the isolation trench 151; then, the step of implanting a 307 well in the region (b) of the substrate 101 not covered by the etch mask 306 is performed.

[0171] The etch mask 306 is then removed, as shown in the top view of Figure 19. It should be noted that, for simplicity, Figure 19 does not show the oxide portion 241 in the trench 231.

[0172] As previously stated, the second stage of the manufacturing method is described below with reference to Figures 20 to 30, based on the cross section BB shown in Figure 19. This second stage is particularly capable of forming the sacrificial gates of FinFET and MOSFET transistors to form semiconductor regions 11 corresponding to the source and drain regions of FinFET transistor 10, and semiconductor regions 12 corresponding to the source and drain regions of MOSFET transistor 20, and then completing the gate structures 110 and 120 of the FinFET and MOSFET transistors (the so-called "gate replacement" step).

[0173] The described sacrificial gate includes a sacrificial material, typically a semiconductor material, which in the described example is polycrystalline silicon. The described sacrificial gate may also include a dielectric layer, for example, made of silicon nitride, on the sacrificial material, but this example is not limiting.

[0174] The steps described below (Phase Two) are based on FinFET transistor fabrication technology and are suitable for co-integrating with FinFET transistors to form MOSFET transistors, which may be HV transistors. It should be noted that the steps described above (Phase One) are also based on FinFET transistor fabrication technology.

[0175] Figure 20 shows a partial simplified cross-sectional view of the structure obtained at the end of deposition on the structure of Figure 19: a protective or etch stop layer 402 on the upper surface 101A of the substrate 101; a polysilicon or polysilicon layer 403 (Poly) on layer 402; and a protective layer 404 or a hard mask (nitride HM) formed on the polysilicon layer 403.

[0176] The etch stop layer 402 is advantageously made of an oxide, such as silicon oxide, for example SiO2. More specifically, the etch stop layer 402 is made of a material capable of performing selective etching relative to polysilicon. This selective etching step is described in the following description in conjunction with Figures 25A and 25B.

[0177] The protective layer 404 can be made of nitrides (such as silicon nitride) or even oxides (such as silicon oxide).

[0178] Figure 21 shows the structure obtained at the end of the following steps in a partially simplified cross-sectional view.

[0179] The stack 405 of layers 403 and 404 in region (b) is etched.

[0180] Prior to performing the etching, an etching mask (not shown) is deposited on layer 404. The etching mask is configured to mask the entire area (a), for example up to a portion above the isolation trench 151 and substantially the central portion of area (b), while exposing the rest of area (b).

[0181] After etching through the etch mask, the stack 405 of the etched layers 403 and 404 forms a stack 405a of unetched portions 403a and 404a in region (a), and a stack 405b of unetched portions 403b and 404b in region (b), which can plot the location of the future sacrificial gate structure of the MOSFET transistor 20.

[0182] A layer 406 of low-k dielectric material is deposited on the upper and side surfaces of stacks 405a and 405b, as well as on the exposed portions of layer 402. In other words, layer 406 follows the shape of the structure obtained at the end of etching stack 405. The low-k material is, for example, SiOCN or SiBCN.

[0183] For example, the thickness e6 of layer 406 is in the range of 3nm to 10nm, for example, approximately 5nm.

[0184] Then, a mask 407 (PR5) is formed on the stack 405a, extending along the side of the stack 405a to a portion of the layer 406 between the stacks 405a and 405b. During the ion implantation step of the substrate 101 in region (b), the mask 407 is able to mask a portion of region (a) and possible region (b) from the upper surface 101A and on either side of the stack 405b to form an LDD (lightly doped drain) semiconductor region.

[0185] The low-k layer 406 enables a framework structure (low-k spacer 406b) to be formed around the polysilicon 403b in region (b) of the MOSFET transistor. This framework structure is identical to the framework structure (low-k spacer 421 described below) that is formed later in this method around the polysilicon 403c in region (a) for the FinFET transistor (see Figures 25A and 25B and the corresponding description). Therefore, when the sacrificial gate is removed, i.e., the polysilicon 403c and 403b in regions (a) and (b) respectively (see Figure 28 and the corresponding description), etching can be selective relative to the same low-k material on the sides of the FinFET and MOSFET transistors.

[0186] Then remove mask 407.

[0187] Figure 22 shows the structure obtained at the end of the following steps in a partially simplified cross-sectional view.

[0188] After mask 407 is removed, a nitride layer 408, for example made of silicon nitride, is deposited on the stack 405a and 405b and on layer 406. Then, a nitride etching is performed, comprising layer 408, low-k layer 406, portions 404a and 404b of nitride layer 404, stopping on portions 403a and 403b of polysilicon layer 403 and on layer 402. This results in spacers being formed on the sides of polysilicon portions 403a and 403b.

[0189] In region (b), the spacers formed include: L-shaped portions 406b of layer 406: each L-shaped portion 406b includes a vertical portion abutting a side of the polysilicon portion 403b, the vertical portion extending in the horizontal portion on layer 402; and D-shaped spacers 408b contacting the L-shaped spacers 406b.

[0190] Part 406b forms, for example, spacer 141 as shown in FIG1. ​​Spacer 408b corresponds, for example, to spacer 142 as shown in FIG1.

[0191] In region (a), the spacers formed include: another L-shaped portion 406a of layer 406: the other portion 406a includes a vertical portion (only one side is visible in FIG. 22, but there are usually two sides) abutting the side of polysilicon portion 403a, the vertical portion extending in the horizontal portion on layer 402; and a D-shaped spacer 408a in contact with the L-shaped spacer 406a in region (a).

[0192] Once spacers 406b and 408b have been formed, a substrate 101 implantation step can be performed in region (b) from the upper surface 101A and on both sides of the polysilicon portion 403b by spacers 406b and 408b to form the drain region and source region (SD) of the MOSFET transistor 20.

[0193] The implantation step is preferably performed after a mask is formed on region (a). Although only one MOSFET transistor is shown in region (b), there can be multiple MOSFET transistors, such as NMOS and PMOS types. In this case, one or more masks can also be provided on region (b) to mask future PMOS transistors during N-type implantation and similarly to mask future NMOS transistors during P-type implantation.

[0194] However, this injection step is optional at this stage of the method and can be performed in subsequent steps, as described later in this disclosure with respect to Figures 25A and 25B.

[0195] Figure 23 shows a partially simplified cross-sectional view of the structure obtained at the end of the step of depositing a protective layer 410 or hard mask (SIN HM) made of a dielectric material (e.g., nitride, such as silicon nitride) on the structure shown in Figure 22.

[0196] Layer 410 has a thickness e7, for example greater than 30 nm, measured from the upper surface of polysilicon portion 403a.

[0197] Figure 24 illustrates, through a partially simplified cross-sectional view, the structure obtained at the end of the step of etching layer 410 through an etch mask (not shown), the etch mask being configured to form: in region (a): multiple portions 411 of layer 410 on polysilicon portion 403a and portion 412 of layer 410 forming another spacer on spacer 408a; and in region (b): portion 413 of layer 410 on polysilicon portion 403b and portion 414 of layer 410 forming another spacer on spacer 408b.

[0198] Parts 411 are arranged in rows, that is, side by side in the same direction, and appear as columns in Figure 24, but they usually extend in a direction perpendicular to Figure 24, for example, forming arms.

[0199] Spacer 414 corresponds, for example, to spacer 143 shown in Figure 1.

[0200] The length L5 of portion 413 is greater than the length L4 of polysilicon portion 403b. Preferably, portion 413 extends on either side of polysilicon portion 403b to extend above spacer 406b or even above spacer 408b.

[0201] For example, portion 413 is able to protect polysilicon portion 403b during the etching operation described below.

[0202] Figures 25A and 25B show two variant structures of the semiconductor region 11 (source and drain) for forming the FinFET transistor 10 in two partial and simplified cross-sectional views.

[0203] Prior to the formation of these semiconductor regions 11, in a manner common to both variations, the polysilicon portion 403a in region (a) is etched, while the polysilicon portion 403b in region (b) is protected from this etching by portion 413 of layer 410 and spacers 406b, 408b, 414. Furthermore, pillars 411 on the polysilicon portion 403a form a pattern of the etching mask in region (a), while simultaneously preventing etching of the polysilicon portion located beneath these pillars 411. Thus, etching is capable of forming polysilicon pillars 403c aligned beneath the pillars 411.

[0204] In region (a), each of the sacrificial gates 430 comprises a stack of dielectric material pillars 411 on a polysilicon pillar 403c.

[0205] In region (b), the sacrificial gate 440 includes a polysilicon portion 403b, which is covered on its side surfaces by spacers 406b, 408b, 414 made of dielectric material, and on its upper surface by a portion 413 made of dielectric material.

[0206] The sacrificial gate 440 has a length L4, and the sacrificial gate 430 has a length L3 that is less than the length L4. The length L3 of the sacrificial gate 430 substantially corresponds to the length L1 of the gate structure 110 in FIG1. ​​The length L4 of the sacrificial gate 440 substantially corresponds to the length L2 of the gate structure 120 in FIG1.

[0207] The polysilicon etching stops on the oxide layer 402, which forms the etch stop layer. Then, another etching removes all portions of the oxide layer 402 exposed in regions (a) and (b). A portion 402a of the oxide layer 402 is retained below the sacrificial gate 430, and a portion 402b of the oxide layer is retained below the sacrificial gate 440 and the spacers 406b, 408b, 414. The portions 402b of the oxide layer 402, for example, form all or part of the insulating portion 126 shown in FIG. 1.

[0208] Spacers 406a, 408a and 412 in region (a) are typically maintained, although this is not shown in Figures 25A, 25B and below: these spacers can be used as a transition between FinFET transistors and (one or more) MOSFET transistors.

[0209] Then, a low-k dielectric material layer 420 is deposited on the sacrificial gates 430 and 440 and on the upper surface 101A of the substrate 101. Preferably, the low-k material of layer 420 is the same as the low-k material of layer 406.

[0210] Then, the layer 420 is etched in region (a) to remove the portion of layer 420 located on substrate 101 and above sacrificial gate 430, and only the portion 421 on the side of sacrificial gate 430 is retained in region (a).

[0211] A portion 421 in region (a) forms a spacer, which will be particularly able to maintain the shape of the sacrificial gate 430 during the gate replacement steps described below with respect to Figures 28 to 30. The portion 421 forms a spacer 131, for example, as shown in Figure 1, and has a thickness e8, for example, in the range of 3 nm to 10 nm or less than 15 nm.

[0212] An etching mask (not shown) is formed to mask all or part of region (b) while exposing region (a). The etching mask is configured differently according to variations of Figures 25A and 25B.

[0213] After the deposition and etching of layer 420, at least in region (a), in substrate 101, a semiconductor region 11 is formed on either side of the sacrificial gate 430 coated with spacer 421.

[0214] Preferably, a semiconductor region 11 is formed in the substrate 101 by epitaxy. Specifically, a cavity 409a is formed in region (a) of the substrate 101 from the upper surface 101 on either side of the sacrificial gate 430 coated with spacer 421, and then these cavities 409a are filled by in-situ doped epitaxial P-type (e.g., SiGeB) to form a PMOS type FinFET transistor, and / or these cavities 409a are filled by in-situ doped epitaxial N-type (e.g., SiP) to form an NMOS type FinFET transistor.

[0215] In a variant of FIG. 25A, the etch mask covers the entire region (b), or even extends further over the isolation trench 151, such that layer 420 is completely contained within region (b). Specifically, the horizontal portion 423 of layer 420 is contained on the upper surface 101A of substrate 101 on either side of the sacrificial gate 440. Furthermore, portions 422 of layer 420 are contained within region (b) on spacers 414, such as forming other spacers, and portions 424 cover portions 413.

[0216] Spacer 422 corresponds, for example, to spacer 144 shown in Figure 1.

[0217] In this variant, layer 420 protects the entire region (b) from the etching and epitaxial operations performed in region (a). Therefore, the semiconductor region 12 of the MOSFET transistor 20 is not formed simultaneously with the semiconductor region 11 of the FinFET transistor 10.

[0218] The variant of Figure 25A enables the formation of semiconductor region 12, which need not be identical to semiconductor region 11, and for example, semiconductor region 12 is closer to the drain and source regions conventionally formed for MOSFET transistors than semiconductor regions formed for FinFET transistors. Semiconductor region 12 can be formed in an earlier step by ion implantation, for example during the steps shown with respect to Figure 24 or Figure 22, or even after the formation of semiconductor region 11. As a variant, similar to semiconductor region 11 but in an earlier or later step, semiconductor region 12 can be formed by epitaxy.

[0219] In the variant of Figure 25B, the etched mask does not cover the area (b).

[0220] In this variant, semiconductor region 12 of MOSFET transistor 20 is formed simultaneously with semiconductor region 11. Preferably, semiconductor region 12 is formed in substrate 101 by epitaxy. Specifically, on either side of the sacrificial gate 440 covered with spacers 406b, 408b, 414 (or even 422), cavities 409b are formed from the upper surface 101A in substrate 101 in region (b), and these cavities 409b are then filled by epitaxy and implantation of P-type (e.g., SiGe) and / or N-type (e.g., SiP) dopant atoms to form a PMOS type MOSFET transistor. These operations of forming and filling cavities 409b can advantageously be performed simultaneously with those operations for cavity 409a.

[0221] Since no masking region (a) is required during the formation of semiconductor region 12 in region (b), and no masking region (b) is required during the formation of semiconductor region 11 in region (a), the variant of FIG25B can reduce the number of masks, thereby reducing manufacturing costs.

[0222] As shown in Figure 25B, after etching the thin layer 420 on the sacrificial gate 440, the following can be retained: for example, a thin portion 422 of the layer 420 on the spacer 414, which may form other spacers, and a thin portion 424 covering the sides of the portion 413. As a variation, etching can remove the entire layer 420 in region (b) such that the layer 420 does not cover the sacrificial gate 440 at all.

[0223] Spacers 406b, 408b, 414 and optional 422 form a multilayer dielectric spacer structure similar to spacer structure 140 shown in FIG1.

[0224] For example, the thickness of spacer 406b (141) is in the range of 3 nm to 10 nm, or less than 15 nm. For example, the thickness of spacer 408b (142) is in the range of 15 nm to 40 nm. For example, the thickness of spacer 414 (143) is in the range of 10 nm to 20 nm. For example, the thickness of spacer 422 (144) is in the range of 3 nm to 10 nm. For example, the total thickness e9 of the spacer structure (140) obtained at the level of the upper surface 101A of substrate 101 is in the range of 30 nm to 60 nm, or greater than 30 nm.

[0225] Due to the stacking of these spacers, the resulting spacer structure has a significant thickness. This large thickness can be used to form the drain and source regions of the MOSFET transistor 20, as it increases the channel length between the drain and source regions. This, in particular, increases the operating voltage of the MOSFET transistor 20, making it especially suitable for operation at high voltages. For example, the channel length of the MOSFET transistor 20 is greater than or equal to 200 nm.

[0226] The remainder of this disclosure begins with FIG25B, but those skilled in the art can easily modify the steps described below by starting with FIG25A.

[0227] Figure 26 shows a partially simplified cross-sectional view of the structure obtained at the end of the following steps: on the structure shown in Figure 25B, i.e., on the substrate 101 and on the sacrificial gates 430 and 440 coated with their spacers, an etch stop layer 451, such as a nitride layer, is deposited; an oxide layer 452, such as SiO2, is deposited on layer 451.

[0228] For example, the upper portion of layer 452 extending beyond the upper surfaces of sacrificial gates 430 and 440 may be removed by chemical mechanical polishing (CMP).

[0229] Layer 452 fills the space between the portion of the upper surface 101A covered by layer 451 and the spacers 421 and 406b, 408b, 414, 422 of the sacrificial gates 430 and 440, as well as the side surfaces covered by layer 451. Therefore, layer 452 includes multiple portions of these spaces.

[0230] In addition, the upper portions of the sacrificial gates 430 and 440, as well as the upper portions of the spacers 421 and 406b, 408b, 414, 422 of these sacrificial gates, and the upper portion of layer 451 (the upper portion of layer 451 located on the side of the sacrificial gate) are removed to allow access to at least portions 411 and 413 in the sacrificial gate.

[0231] Therefore, sacrificial gates 431 and 441 with reduced thickness or height are obtained.

[0232] Preferably, these removals are performed such that the sacrificial gates 431 and 441, spacers 421 and 406b, 408b, 414, 422, layers 451 and 452 are flush with the same upper layer.

[0233] Figure 27 shows the structure obtained at the end of the following steps in a partially simplified cross-sectional view: another upper portion of layer 452 is removed by etching, preferably at height h2, such that the etched layer 452 is substantially flush with, or even below, the upper surfaces of the polysilicon portions 403c and 403b: this removal is performed without etching the sacrificial gates 431 and 441, spacers 421 and 406b, 408b, 414, 422, and layer 451; then a protective nitride layer 453, such as SiN, is deposited on the etched layer 452 and the sacrificial gates 431 and 441; the nitride layer 453 is planarized, for example by CMP, to remove the nitride on the sacrificial gates 431, 441: a thickness of layer 453 substantially equal to the etch height h2 of layer 452 is obtained.

[0234] Figure 28 shows the structure obtained at the end of the following steps in a partially simplified cross-sectional view: for example, by selectively removing portions 411 and 413 of polysilicon layers 403c, 403b, sacrificial gates 431 and 441, layer 453, and portions of spacers 421, 406b, 408b, 414, 422, and layer 451 (the removal of these layers and spacers essentially corresponds to the removal at height h3 of portions 431 and 441) relative to the polysilicon: for example, height h2 is greater than height h3, such that the height of layer 453 (h2 minus h3) can be kept flush with sacrificial gates 431 and 441, spacers 421, 406b, 408b, 414, 422, and layer 451; then the removal is performed by etching the polysilicon portions 403c and 403b in sacrificial gates 431 and 441.

[0235] Layer 451 with reduced height forms, for example, layer 103 as shown in FIG1.

[0236] The reduced thickness layer 452 forms, for example, layer 104 as shown in FIG1.

[0237] Sacrificial gates 432 and 442 are obtained with further reductions in thickness or height.

[0238] Figure 29 shows a partially simplified cross-sectional view of the structure obtained at the end of the following steps.

[0239] An oxide layer 454, such as SiO2, is deposited on the structure shown in Figure 28. Layer 454 follows the shape of the structure in Figure 28 and is deposited particularly on the interior, bottom, and sidewalls of the sacrificial gates 432 and 442.

[0240] Then, an etching mask 455 (PR6) is formed on the oxide layer 454 in region (b). The etching mask 455 leaves the exposed portion of the oxide layer 454 in region (a), which is then removed.

[0241] Then remove the etch mask 455.

[0242] Figure 30 shows a partially simplified cross-sectional view of the structure obtained at the end of the filling steps of sacrificial gates 432 and 442. The filling materials are, for example, those described in the description of Figure 1, and will not be described again here.

[0243] The structure of Figure 30 corresponds to the electronic device 100 in Figure 1, and will not be described here.

[0244] After the gate is filled with a metallic material, a portion of the oxide layer 454 on layer 453 in region (b) outside the sacrificial gate 442 is removed, typically followed by CMP planarization. The reduced-thickness layer 453 is also removed at the same stage of the process.

[0245] Unetched portions of oxide layer 454 are retained on the bottom and sidewalls within the sacrificial gate 442. These unetched portions of oxide layer 454 form, for example, the gate insulating layer 121 shown in FIG1.

[0246] Those skilled in the art will be able to modify the second stage of the manufacturing method by starting with the structures of Figures 12 and 13 instead of Figures 18 and 19. In other words, instead of forming the MOSFET transistors on the mesa (or as a supplement below), the MOSFET transistors can be formed along the wide fin 234.

[0247] The advantage of forming MOSFET transistors on a mesa is that it limits the risk of hot carriers, while the advantage of forming MOSFET transistors on a wide fin is that it improves performance, especially if the variant described in Figure 25B is chosen to form the drain and source regions of the MOSFET transistor.

[0248] Figures 31A and 31B are partial and simplified cross-sectional views of another example of an electronic device 300 according to one embodiment. Figure 31A is a cross-sectional view through the isolation trench and the semiconductor substrate 101. Figure 31B is a cross-sectional view along the cross-sectional plane CC shown in Figure 31A.

[0249] The electronic device 300 of Figures 31A and 31B differs from the electronic device 100 of Figures 1 and 30 in that it includes three regions (a), (b1), and (b2): a thin fin region (a), a platform region (b1), and a wide fin region (b2).

[0250] The thin fin 233 in region (a) is similar to the fin 233 described with respect to Figures 9 to 13 or Figures 18 and 19. The platform 235 in region (b1) is similar to the platform 235 described in conjunction with Figures 18 and 19. The wide fin 234 in region (b2) is similar to the fin 234 described in conjunction with Figures 9 to 13.

[0251] Figure 31B shows a FinFET transistor 10 along the thin fin 233 in region (a), a MOSFET transistor 20-1 on top of and inside the mesa 235 in region (b1), and a MOSFET transistor 20-2 along the wide fin 234 in region (b2).

[0252] Region (a) is insulated from region (b1) by isolation trench 351, and region (b2) is insulated from region (b1) by another isolation trench 352. Region (b2) is also insulated by another isolation trench 353 on the side opposite to isolation trench 352.

[0253] For example, transistors 10, 20-1 and 20-2 are formed by employing the described method in the same manufacturing process, which may be similar to the method described with respect to Figures 20 to 30.

[0254] It should be understood that, in practice, replacing region (b1) between regions (a) and (b2) can be replacing region (b2) between regions (a) and (b1), or region (a) between regions (b1) and (b2). Other regions may also exist, and / or other orientations or configurations of the regions, and more generally, any other configuration of the regions may exist, wherein at least one region comprises one or more FinFET transistors, and at least another region comprises one or more MOSFET transistors, such as one or more HVMOSFET transistors. The MOSFET transistors and / or FinFET transistors may comprise at least one PMOS transistor and one NMOS transistor.

[0255] The advantage of these embodiments is that they enable the integration of FinFET transistors and high-voltage MOSFET transistors within the same electronic device on wide fins and / or mesas, while remaining compatible with standard FinFET transistor fabrication methods. In particular, the embodiments are able to form spacers in the MOSFET transistors using steps present in typical FinFET transistor fabrication methods.

[0256] Many applications may benefit from the advantages offered by the electronic device according to one embodiment, which can therefore be integrated into various types of devices. In particular, the above embodiments are applicable to any type of device that provides analog and logic functions in the same electronic chip, such as a microcontroller.

[0257] As an example, electronic devices can be integrated into equipment used in the automotive industry, such as in the field of automotive electrification or in the field of advanced driver assistance systems.

[0258] For example, electronic devices can be integrated into equipment used in industry.

[0259] As an example, electronic devices can be integrated into devices used for personal electronic devices.

[0260] As an example, electronic devices can be integrated into devices designed for use in communication equipment or computers and peripherals.

[0261] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to those skilled in the art.

[0262] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

[0263] A method for fabricating an electronic device (100; 300) inside and on top of a semiconductor substrate (101), the electronic device (100; 300) being summarized as including a first fin field-effect transistor (10) in a first region (a) and at least one second field-effect transistor (20; 20-1, 20-2) in at least one second region (b; b1, b2), the method comprising: forming, in the first region, a first sacrificial gate (430) having a first length (L3) along a first fin (233) of the semiconductor substrate (101), the first fin having a first width (12) at a first surface (101A) of the semiconductor substrate and being isolated by a first trench (231) in the semiconductor substrate; and in each second region, forming a second sacrificial gate (440) having a second length (L4) greater than the first length (L3) on the first surface (101A) of the semiconductor substrate, the first sacrificial gate and the second sacrificial gate being made of a sacrificial material. The formation of the first sacrificial gate and the second sacrificial gate includes forming a first spacer (421) of a first thickness (e8) on the side of the first sacrificial gate (430) and forming a second spacer (406b, 408b, 414, 422) of a second thickness (e9) greater than the first thickness (e8) on the side of the second sacrificial gate (440); in the semiconductor substrate, forming the first semiconductor region (11) in a first region on either side of the first sacrificial gate (430) having the first spacer, forming the drain region and source region of the first transistor; in the semiconductor substrate, forming the second semiconductor region (12) in each second region on either side of the second sacrificial gate (440) having the second spacer, forming the drain region and source region of the at least one second transistor; and replacing each first sacrificial gate (430) with a first gate structure (110) and replacing each second sacrificial gate (440) with a second gate structure (120).

[0264] The formation of the first sacrificial gate and the second sacrificial gate includes: forming a first portion (403a) of a first layer (403) made of the sacrificial material in the first region (a) on the semiconductor substrate (101), and forming a second portion (403b) of the first layer in each second region (b; b1, b2), the first portion extending substantially over the entire length of the first region, and the second portion extending over a second length (L4) shorter than the length of the second region, thereby forming all or part of the second sacrificial gate (440); forming a stack of multiple layers made of a dielectric material on the sides of the first portion (403a) and the second portion (403b) of the first layer (403); and forming all or part of the stack of layers made of the dielectric material on the sides of the second portion (403b) of the first layer (403) to form the second spacers (406b, 408b, 414, 422).

[0265] The formation of the stack of layers includes: forming a first L-shaped portion (406a) of a second layer (406) made of a dielectric material on the side surface of a first portion (403a) of a first layer (403) and on the semiconductor substrate (101); forming a second L-shaped portion (406b) of a second layer (406) made of a dielectric material on the side surface of a second portion (403b) of a first layer (403) and on the semiconductor substrate (101), wherein the dielectric material is preferably made of a low dielectric constant material; forming a third layer made of a dielectric material (e.g., a nitride, such as silicon nitride) on the first D-shaped portion (408a) of the first L-shaped portion (406a) and on the second D-shaped portion (408b) of the second L-shaped portion (406b); and forming a fourth layer (410) made of a dielectric material such as silicon nitride on the first D-shaped portion (408a) of the first portion (412) and on the second D-shaped portion (408b) of the second portion (414).

[0266] The formation of the first portion (412) and the second portion (414) of the fourth layer (410) includes depositing and subsequently etching the fourth layer to form: in the first region: the first portion (412) and the third portion (411) of the fourth layer on the first portion (403a) of the first layer (403), the third portions being arranged in a row and each extending over a length substantially equal to the first length (L3); and in each of the second regions: the second portion (414) and the fourth portion (413) of the fourth layer on the second portion (403b) of the first layer (403).

[0267] A method includes etching a first portion (403a) of a first layer (403) to form a third portion (403c) of the first layer, the third portions (403c) being arranged in rows and each extending over a length substantially equal to a first length (L3) to form all or part of a first sacrificial gate (430).

[0268] Etching of the first portion (403a) of the first layer (403) is performed by the third portion (411) of the fourth layer (410) forming the etching mask, the third portion (403c) of the first layer (403) extending between the semiconductor substrate (101) and the third portion (411) of the fourth layer (410).

[0269] After forming the third portion (403c) of the first layer (403), forming the first spacer and the second spacer includes: forming a first portion (421) of a fifth layer (420) preferably having a low dielectric constant dielectric material on the side surface of the first sacrificial gate (430), forming the first spacer, and forming a second portion (422) of the fifth layer on the side surface of each second sacrificial gate (440) covered by the stack of layers, the second spacer including the second portion of the fifth layer.

[0270] The formation of the second semiconductor region (12) is carried out simultaneously with the formation of the first semiconductor region (11).

[0271] The formation of the second semiconductor region (12) is carried out before or after the formation of the first semiconductor region (11).

[0272] The fifth layer (420) includes a third portion (423) that extends on either side of the second sacrificial gate (440) and the second spacer in each second region to mask the semiconductor substrate (101) in the second region during the formation of the first semiconductor region (11).

[0273] An electronic device (100; 300) is summarized to include: a first fin field-effect transistor (10) comprising a first region (a) on the interior and top of a semiconductor substrate (101), and at least one second field-effect transistor (20; 20-1, 20-2) of a metal-oxide-semiconductor structure (MOSFET) in at least one second region (b; b1, b2); each of the first transistors includes a first gate structure (110) of a first length (L1) along a first fin (233) of the semiconductor substrate (101), the first fin being in the semiconductor substrate. The first surface (101A) of the conductor substrate has a first width (l2) and is isolated by a first trench (231) in the semiconductor substrate. Each first gate structure (110) has a first spacer (131) on its side, and the first spacer (131) has a first thickness (e8). Each second transistor includes a second gate structure (120) of a second length (L2) on the first surface (101A) of the semiconductor substrate, the second length being greater than the first length. The side of each second gate structure is a second spacer (140) having a second thickness (e9) greater than the first thickness (e8).

[0274] A third transistor (20; 20-1) in at least one second transistor is formed on top of and inside a mesa (235) flush with a first surface (101A) of the semiconductor substrate (101), in a third region (b; b1) of at least one second region.

[0275] A fourth transistor (20-2) of at least one second transistor is formed in a fourth region (b-2) of at least one second region along a second fin (234) of the semiconductor substrate (101). The second fin (234) has a second width (13) at the level of a first surface (101A) of the semiconductor substrate and is isolated by a second trench (232) in the semiconductor substrate. The second width (13) is greater than the first width (12). For example, the second width is at least twice the size of the first width; and / or the first width is less than 15 nm, for example, less than or equal to 10 nm; and / or the second width is greater than 20 nm, for example, greater than or equal to 30 nm.

[0276] The method includes: forming a first fin (233) in a first region (a) and forming a second fin (234) in a fourth region (b2). The formation of the first and second fins includes: forming a first pillar (204A) in the first region (a) and a second pillar (204B) in the fourth region (b2) on a first surface (101A) of a semiconductor substrate (101). The first and second pillars are arranged side by side and are made of a first material, such as amorphous silicon. The first pillars are separated from each other by a first distance (D1), and the second pillars are arranged side by side. Separate them by a second distance (D1); deposit a sixth layer (210) on the first and second pillars, the sixth layer (210) being made of a second material (e.g., silicon oxide) and selectively etchable relative to the first material, the sixth layer having a third thickness (e3) on the sides of the first and second pillars; remove the sixth layer (210) from the first region (a), the sixth layer remaining on the sides of the second pillar (204B) in the fourth region (b2); deposit the second material on the first and second pillars. A seventh layer (220) made of material, the seventh layer having a fourth thickness (e4), the fourth thickness being defined as forming a first column (227) on the side of the first column (204A) that is open to each other between the first columns; the sixth and seventh layers forming second columns (228) on the side of the second column (204B), the third and fourth thicknesses being defined such that the second columns (228) are connected between the second columns (204B), the connected second columns forming a third column (221) coupling two adjacent second columns. ); and, for example, by etching away the first and second pillars made of the first material; etching the semiconductor substrate (101) through the first, second and third pillars made of the second material from the first surface (101A) to form an etching mask; etching the semiconductor substrate to form a first trench (231) in the semiconductor substrate, defining a first fin (233) between the first trenches in the first region (a), and forming a second trench (232) in the semiconductor substrate, defining a second fin (234) between the second trenches in the fourth region (b2).

[0277] The fourth thickness (e4) is less than the third thickness (e3); and / or the fourth thickness (e4) is less than half of the first distance (D1); and / or the third thickness (e3) is greater than or equal to half of the second distance (D1); and / or the first distance (D1) is substantially equal to the second distance (D1).

[0278] The first thickness (e8) is less than or equal to 15 nm, the second thickness (e9) is greater than or equal to 30 nm; and / or the first length (L1; L3) is less than or equal to 30 nm and the second length (L2; L4) is greater than or equal to 150 nm.

[0279] The various embodiments described above can be combined to provide other embodiments. If desired, aspects of the embodiments can be modified to incorporate concepts from various patents, applications, and publications to provide other embodiments.

[0280] Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of the authorized equivalents of these claims. Therefore, the claims are not limited to this disclosure.

Claims

1. A method for manufacturing an electronic device, comprising: A first fin field-effect transistor is formed in a first region of a first surface of a semiconductor substrate, and at least one second field-effect transistor having a metal-oxide-semiconductor structure is formed in at least one second region of the first surface. The formation of the first fin field-effect transistor and the at least one second field-effect transistor includes: in the first region, forming a plurality of first sacrificial gates of a first length along a first fin of the semiconductor substrate, the first length extending along a first direction, the first fin having a first width at the first surface of the semiconductor substrate and being isolated by a first trench in the semiconductor substrate; in each second region, forming a second sacrificial gate of a second length along the first direction at the first surface of the semiconductor substrate, the second length being greater than the first length, the first sacrificial gate and the second sacrificial gate comprising sacrificial material; the formation of the first sacrificial gate and the second sacrificial gate includes: forming a first spacer of a first thickness on the side surface of the first sacrificial gate; and forming a first spacer of a first thickness on the side surface of the second sacrificial gate. The second spacer has a second thickness greater than the first thickness and includes: a plurality of L-shaped dielectric layers, each having a first portion on a sidewall of the second sacrificial gate and a second portion transverse to the first portion and on the first surface of the semiconductor substrate; and a plurality of circular spacers, each directly located on both the first and second portions of the respective L-shaped dielectric layers; in the semiconductor substrate, a first semiconductor region is formed in the first region on either side of the first sacrificial gate having the first spacer along the first direction, the first semiconductor region forming the drain region and source region of the first transistor; in the semiconductor substrate, a second semiconductor region is formed in each second region on either side of the second sacrificial gate having the second spacer along the first direction, the second semiconductor region forming the drain region and source region of the at least one second transistor; and each first sacrificial gate is replaced with a first gate structure and each second sacrificial gate is replaced with a second gate structure.

2. The method of claim 1, wherein forming the first sacrificial gate and the second sacrificial gate comprises: On the semiconductor substrate, a first portion of a first layer comprising the sacrificial material is formed in the first region, and a second portion of the first layer is formed in each second region, the first portion extending substantially over the entire length of the first region, and the second portion extending over a second length shorter than the length of the second region, thereby forming a portion of the second sacrificial gate; And a stack of layers comprising dielectric material is formed on the side surface of the first portion and the side surface of the second portion of the first layer, wherein the stack of layers comprising the dielectric material on the side surface of the second portion of the first layer forms the second spacer.

3. The method of claim 2, wherein the stack forming the layer comprises: A second layer is formed on the side surface of the first portion of the first layer, the side surface of the second portion of the first layer, and the semiconductor substrate, respectively. The second layer is made of a first dielectric material with a low dielectric constant. A third layer made of a second dielectric material is formed on the second layer. The second and third layers are etched to form: a first L-shaped dielectric layer and a second L-shaped dielectric layer belonging to the plurality of L-shaped dielectric layers, the first L-shaped dielectric layer and the second L-shaped dielectric layer being formed by the second layer; a first D-shaped portion and a second D-shaped portion on the first L-shaped dielectric layer and the second L-shaped dielectric layer, respectively, the first D-shaped portion and the second D-shaped portion being formed by the third layer; and a first portion and a second portion of a fourth layer including a third dielectric material are formed on the first D-shaped portion and the second D-shaped portion, respectively.

4. The method of claim 3, wherein forming the first portion and the second portion of the fourth layer comprises forming the first portion of the fourth layer on the first D-shaped portion by depositing and etching the fourth layer; The third portion of the fourth layer is formed on the first portion of the first layer, the third portions being arranged in rows and each extending over a length substantially equal to the first length; The second portion of the fourth layer is formed on the second D-shaped portion; And the fourth portion of the fourth layer is formed on the second portion of the first layer.

5. The method of claim 4, further comprising forming the third portion of the first layer by etching the first portion of the first layer, the third portions of the first layer being arranged in rows and each extending over a length substantially equal to the first length, thereby forming at least a portion of the first sacrificial gate.

6. The method of claim 5, wherein the etching of the first portion of the first layer is performed by forming the third portion of the fourth layer of the etch mask, the third portion of the first layer extending between the semiconductor substrate and the third portion of the fourth layer.

7. The method of claim 5, wherein forming the first spacer and the second spacer comprises: After forming the third portion of the first layer, a first portion of a fifth layer of a fourth dielectric material is formed on the side of the first sacrificial gate, the first spacer is formed, and a second portion of the fifth layer is formed on the side of each second sacrificial gate covered by the stack of the layers, the second spacer comprising the second portion of the fifth layer.

8. The method of claim 1, wherein the formation of the second semiconductor region is performed simultaneously with the formation of the first semiconductor region.

9. The method of claim 1, wherein the formation of the second semiconductor region is performed at a first time, and the formation of the first semiconductor region is performed at a second time, which is not equal to the first time.

10. The method of claim 9, wherein the fifth layer includes a third portion extending along the second direction on either side of the second sacrificial gate and the second spacer in each second region, the third portion of the fifth layer masking the semiconductor substrate in the second region during the formation of the first semiconductor region.

11. The method according to claim 1, comprising: In the second region of the at least one second region, a second transistor of the at least one second transistor is formed on top of and inside a mesa flush with the first surface of the semiconductor substrate; A third transistor of the at least one second transistor is formed along a second fin in a third region of the at least one second region along the semiconductor substrate. The second fin has a second width at the first surface of the semiconductor substrate and is isolated by a second trench in the semiconductor substrate. The second width is greater than the first width.

12. The method of claim 11, wherein forming the first fin in the first region of the at least one second region and forming the second fin in the third region comprises: A first pillar in the first region of the at least one second region and a second pillar in the third region of the at least one second region are formed on the first surface of the semiconductor substrate. The first pillar and the second pillar are arranged side by side and comprise a first material. The first pillars are separated from each other by a first distance, and the second pillars are separated from each other by a second distance. A sixth layer comprising a second material is formed on the first pillars and the second pillars. The sixth layer is selectively etchable relative to the first material. The sixth layer has a third thickness on the side surfaces of the first pillars and the second pillars. The sixth layer in the second region is removed, and the sixth layer is retained on the side surface of the second pillar in the third region of the at least one second region. A seventh layer comprising the second material is formed on the first column and the second column, the seventh layer having a fourth thickness, the fourth thickness being defined to form first columns separated from each other between the first columns on the side surface of the first column; A second column is formed on the side surface of the second column via the sixth and seventh layers; Remove the first column and the second column; form an etching mask by etching the semiconductor substrate from the first surface through the first column, the second column and the third column; And by etching the semiconductor substrate, forming a first trench in the semiconductor substrate, the first trench defining the first fin between the first trenches in the first region, and forming a second trench in the semiconductor substrate, the second trench defining the second fin between the second trenches in the third region of the at least one second region.

13. The method according to claim 2, further comprising: Prior to the formation of the first portion and the second portion of the first layer, an etch stop layer is formed on the semiconductor substrate. The etch stop layer comprises silicon dioxide and includes: a first portion in the first region, which is suppressed during the formation of the first sacrificial gate and the first gate structure; and a second portion in the at least one second region, which is held below the second spacer during the formation of the second sacrificial gate and the second gate structure.

14. An electronic device comprising: In a first region of a semiconductor substrate, each of the first transistors includes a first gate structure along a first length of a first fin of the semiconductor substrate, the first fin having a first width at a first surface of the semiconductor substrate and being isolated by a first trench in the semiconductor substrate, and each first gate structure having a first spacer on a side surface, the first spacer having a first thickness. And at least one second field-effect transistor of a metal-oxide-semiconductor structure, in at least one second region of the semiconductor substrate, the at least one second transistor including a second gate structure of a second length on the first surface of the semiconductor substrate, the second length being greater than the first length, each second gate structure having a second spacer on its side, the second spacer having a second thickness greater than the first thickness, each second spacer including: a plurality of L-shaped dielectric layers, each having a first portion on the sidewall of the second gate structure and a second portion transverse to the first portion and on the first surface of the semiconductor substrate; And multiple circular spacers, each directly located on both the first and second portions of the corresponding L-shaped dielectric layer.

15. The apparatus of claim 14, wherein in the third region of the at least one second region, the third transistor of the at least one second transistor is formed on top of and inside a mesa coplanar with the first surface of the semiconductor substrate.

16. The apparatus of claim 14, wherein a fourth transistor of the at least one second transistor is formed in a fourth region of the at least one second region along a second fin of the semiconductor substrate, the second fin having a second width at the level of the first surface of the semiconductor substrate and isolated by a second trench in the semiconductor substrate, the second width being greater than the first width.

17. The apparatus according to claim 14, wherein: The first thickness is at most 15 nm, and the second thickness is at least 30 nm.

18. The apparatus of claim 14, wherein each second transistor includes an insulating portion between the semiconductor substrate and the second spacer.

19. A method comprising: A first plurality of gate structures are formed along a first fin in a first region of a semiconductor substrate, the first fin having a first width along a first direction, and each first gate structure having a first length along the first direction; A second gate structure is formed in a second region of the semiconductor substrate, the second gate structure having a second length along the first direction that is greater than the first length; A spacer structure is formed around the second gate structure, the spacer structure comprising: a plurality of insulating portions on the semiconductor substrate, each insulating portion adjacent to the second gate structure; a plurality of L-shaped dielectric layers, each having a first portion on a sidewall of the second gate structure and a second portion transverse to the first portion and on the corresponding insulating portion; and a plurality of circular spacers, each directly located on both the first portion and the second portion of the corresponding L-shaped dielectric layer; a first doped semiconductor region formed on an opposite side of each first gate structure in the first region of the semiconductor substrate along a second direction; and a second doped semiconductor region formed on an opposite side of the second gate structure in the second region of the semiconductor substrate along the second direction.

20. The method of claim 18, wherein the first doped semiconductor region and the first plurality of gate structures together form a first plurality of transistors, and the second doped semiconductor region and the second gate structure together form a second transistor.

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