Semiconductor device and forming method thereof

Abstract

The embodiment of the invention discloses a semiconductor device and a forming method thereof. The embodiment of the invention provides a semiconductor substrate comprising a first device region and a second device region, a semiconductor layer is formed on the surface of the semiconductor substrate, and a deep isolation trench and a gate trench which extend from the upper surface of the semiconductor layer to the interior of the semiconductor layer are formed. And forming a deep isolation structure and a vertical gate structure in the deep isolation trench and the gate trench respectively, forming a first device in the semiconductor layer on the first device region by taking the vertical gate structure as a gate, and forming a second device in the semiconductor layer on the second device region. Wherein the average doping concentration of the semiconductor layer on the first device region is greater than that of the semiconductor layer on the second device region, the gate trench is located on the semiconductor layer on the first device region, and the deep isolation structure isolates the first device region from the second device region. Therefore, the same-chip integration of the high-voltage power device and the control circuit can be realized.

Description

[0001] This application claims priority to Chinese Patent Application No. 202512059625.6, filed on December 31, 2025, entitled "Semiconductor Device and Method of Forming Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for forming the same. Background Technology

[0003] Currently, due to differences in fabrication processes and device requirements, high-voltage power devices and control circuits are typically fabricated as discrete components on separate chips. However, with the further development of device integration technology, integrating high-voltage power devices and control circuits onto a single chip has become the mainstream trend. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a semiconductor device and a method for forming the same, so as to achieve the integration of high-voltage power devices and control circuits on the same chip.

[0005] In a first aspect, embodiments of the present invention aim to provide a method for forming a semiconductor device, the method comprising: A semiconductor substrate is provided, the semiconductor substrate including a first device region and a second device region; A semiconductor layer is formed on the surface of the semiconductor substrate, wherein the average doping concentration of the semiconductor layer on the first device region is greater than the average doping concentration of the semiconductor layer on the second device region; At least one deep isolation trench and at least one gate trench are formed extending from the upper surface of the semiconductor layer into the interior of the semiconductor layer, the gate trench being located on the semiconductor layer in the first device region; A deep isolation structure and a vertical gate structure are formed inside the deep isolation trench and the gate trench, respectively, wherein the deep isolation structure isolates the first device region from the second device region; In the semiconductor layer on the first device region, at least one first device is formed using the vertical gate structure as a gate. At least one second device is formed in the semiconductor layer on the second device region.

[0006] Furthermore, the semiconductor layer includes at least two stacked sub-epitaxial layers, wherein in each pair of adjacent sub-epitaxial layers, the doping concentration of the upper sub-epitaxial layer is less than the doping concentration of the lower sub-epitaxial layer.

[0007] Further, forming a semiconductor layer on the surface of the semiconductor substrate includes: A first epitaxial layer is formed on the surface of the semiconductor substrate; A second epitaxial layer is formed on the surface of the first epitaxial layer; A first high-voltage well region is formed on a second epitaxial layer in the first device region, and the doping type of the first high-voltage well region is the same as that of the semiconductor substrate, the first epitaxial layer and the second epitaxial layer.

[0008] Furthermore, before forming the second epitaxial layer on the surface of the first epitaxial layer, the formation of the semiconductor layer on the surface of the semiconductor substrate further includes: A buried layer is formed inside the first epitaxial layer on the first device region, and the doping type of the buried layer is the same as that of the first epitaxial layer.

[0009] Furthermore, forming a first high-voltage well region within the second epitaxial layer on the first device region includes: Multiple doped ion implantations are performed on the second epitaxial layer in the first device region; Heat treatment is performed to diffuse and activate the implanted dopant ions, forming the first high-voltage trap region.

[0010] Furthermore, after forming the first high-voltage well region, the formation of the semiconductor layer on the surface of the semiconductor substrate further includes: A second high-voltage well region is formed in the second epitaxial layer on the second device region, and the doping type of the second high-voltage well region is opposite to that of the second epitaxial layer.

[0011] Furthermore, the deep isolation structure includes a first shielding dielectric layer and an isolation conductor layer, wherein the first shielding dielectric layer is located at the bottom and sidewalls of the deep isolation trench and isolates the isolation conductor layer from the semiconductor layer.

[0012] Furthermore, the vertical gate structure includes a gate dielectric layer and a control gate, wherein the gate dielectric layer is located at the bottom and sidewalls of the gate trench and isolates the control gate from the semiconductor layer.

[0013] Furthermore, the vertical gate structure includes a second shielding dielectric layer, a shielding gate, a gate dielectric layer, and a control gate. The second shielding dielectric layer is located at the bottom and lower sidewall of the gate trench and isolates the shielding gate from the semiconductor layer. The gate dielectric layer is located at the upper sidewall of the gate trench and isolates the control gate from the semiconductor layer. The gate dielectric layer is also located between the shielding gate and the control gate and isolates the shielding gate from the control gate.

[0014] Furthermore, the shielding grid is stepped, with its width gradually increasing along its height.

[0015] Further, the formation of a deep isolation structure and a vertical gate structure within the deep isolation trench and the gate trench, respectively, includes: Inside the deep isolation trench and inside the gate trench, a shielding dielectric layer is simultaneously formed covering the bottom and sidewalls of the trench; A first polysilicon layer is filled on the shielding dielectric layer to form the isolation conductor layer inside the deep isolation trench; Form a mask covering the deep isolation trench; Inside the gate trench, a portion of the first polysilicon and the shielding dielectric layer are sequentially etched, and a second polysilicon is filled on the retained first polysilicon to form the shielding gate; The gate dielectric layer and the control gate are sequentially formed on the shielding gate; The mask is etched.

[0016] Furthermore, after forming the deep isolation structure and the vertical gate structure, and before forming at least one first device using the vertical gate structure as the gate, the method further includes: Multiple shallow isolation trenches are formed in the semiconductor layer on the second device region; A shallow isolation structure is formed inside the shallow isolation trench.

[0017] Furthermore, forming at least one first device using the vertical gate structure as the gate includes: A body region is formed on one or both sides of the vertical gate structure; Within the body region, a source region and a corresponding body contact region are formed; The substrate serves as the drain of the first device.

[0018] Further, forming at least one second device in the semiconductor layer on the second device region includes: A corresponding second device is formed in each of the second high-pressure trap regions, and a second device is included between two adjacent shallow isolation structures.

[0019] Furthermore, the second device is a BCD device.

[0020] Furthermore, the trench depth of the deep isolation trench is greater than the trench depth of the gate trench.

[0021] Furthermore, the deep isolation structure also isolates different first devices within the first device region, isolates different second devices within the second device region, and / or isolates different device portions within the second devices.

[0022] In a second aspect, embodiments of the present invention aim to provide a semiconductor device, the semiconductor device comprising: A semiconductor substrate, including a first device region and a second device region; A semiconductor layer is formed on the surface of the semiconductor substrate, wherein the average doping concentration of the semiconductor layer on the first device region is greater than the average doping concentration of the semiconductor layer on the second device region, the semiconductor layer includes at least one deep isolation trench and at least one gate trench, the deep isolation trench and the gate trench extending from the upper surface of the semiconductor layer into the interior of the semiconductor layer, and the gate trench is located on the semiconductor layer on the first device region; At least one deep isolation structure is formed inside the deep isolation trench, wherein the deep isolation structure isolates the first device region from the second device region; At least one vertical gate structure is formed inside the gate trench; At least one first device, with the vertical gate structure as the gate; At least one second device, a semiconductor layer formed on the region of the second device.

[0023] Furthermore, the semiconductor layer includes at least two stacked sub-epitaxial layers, wherein in each pair of adjacent sub-epitaxial layers, the doping concentration of the upper sub-epitaxial layer is less than the doping concentration of the lower sub-epitaxial layer.

[0024] Further, the semiconductor layer includes: A first epitaxial layer is formed on the semiconductor substrate; The second epitaxial layer is formed on top of the first epitaxial layer; The first high-voltage well region is formed inside the second epitaxial layer on the first device region.

[0025] Furthermore, the semiconductor layer further includes: The buried layer is formed inside the first epitaxial layer on the first device region.

[0026] Furthermore, the semiconductor substrate, the first epitaxial layer, and the second epitaxial layer have the same doping type, the doping concentration of the first epitaxial layer is less than the doping concentration of the semiconductor substrate, and the doping concentration of the second epitaxial layer is less than the doping concentration of the first epitaxial layer.

[0027] Furthermore, the thickness of the second epitaxial layer is greater than the thickness of the first epitaxial layer.

[0028] Furthermore, the doping type of the buried layer and the first high-voltage trap region is the same as the doping type of the semiconductor substrate, the first epitaxial layer, and the second epitaxial layer.

[0029] Furthermore, the deep isolation structure includes an isolation conductor layer and a first shielding dielectric layer, wherein the first shielding dielectric layer is formed at the bottom and sidewalls of the deep isolation trench and isolates the isolation conductor layer from the semiconductor layer.

[0030] Furthermore, the vertical gate structure includes a gate dielectric layer and a control gate, wherein the gate dielectric layer is located at the bottom and sidewalls of the gate trench and isolates the control gate from the semiconductor layer.

[0031] Furthermore, the vertical gate structure includes a second shielding dielectric layer, a shielding gate, a gate dielectric layer, and a control gate, wherein the second shielding dielectric layer is located at the bottom and lower sidewall of the gate trench and isolates the shielding gate from the semiconductor layer, the gate dielectric layer is located at the upper sidewall of the gate trench and isolates the control gate from the semiconductor layer, and the gate dielectric layer is also located between the shielding gate and the control gate and isolates the shielding gate from the control gate.

[0032] Furthermore, the shielding grid is stepped, with its width gradually increasing along its height.

[0033] Furthermore, the semiconductor device further includes a body region, a source region, and a corresponding body contact region. The body region is formed on one or both sides of the vertical gate structure, and the source region and the corresponding body contact region are formed within the body region. The substrate serves as the drain of the first device.

[0034] Furthermore, the semiconductor device further includes: Multiple shallow isolation structures are formed on the surface of the semiconductor layer on the second device region; A second high-voltage well region is located inside the semiconductor layer on the second device region; and, The doped regions of the second device are correspondingly formed in each of the second high-voltage well regions, wherein a second device is included between two adjacent shallow isolation structures.

[0035] Furthermore, the second device is a BCD device.

[0036] Furthermore, the trench depth of the deep isolation trench is greater than the trench depth of the gate trench.

[0037] Furthermore, the deep isolation structure also isolates different first devices within the first device region, isolates different second devices within the second device region, and / or isolates different device portions within the second devices.

[0038] Furthermore, it also includes a metal contact via corresponding to the source region and the body contact region, wherein the metal contact via extends into the interior of the body contact region.

[0039] This invention provides a semiconductor substrate including a first device region and a second device region. A semiconductor layer is formed on the surface of the semiconductor substrate, and deep isolation trenches and gate trenches are formed extending from the upper surface of the semiconductor layer into the interior of the semiconductor layer. Deep isolation structures and vertical gate structures are formed inside the deep isolation trenches and gate trenches, respectively. A first device is formed in the semiconductor layer on the first device region using the vertical gate structure as the gate, and a second device is formed in the semiconductor layer on the second device region. The average doping concentration of the semiconductor layer on the first device region is greater than the average doping concentration of the semiconductor layer on the second device region. The gate trenches are located in the semiconductor layer on the first device region, and the deep isolation structures isolate the first device region from the second device region. This allows for the integration of high-voltage power devices and control circuitry onto a single chip. Attached Figure Description

[0040] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 2 This is a flowchart of a semiconductor device formation method according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the semiconductor device formation process according to an embodiment of the present invention; Figure 4 This is a flowchart of a semiconductor layer formation method according to an embodiment of the present invention; Figures 5 to 9 This is a schematic diagram of the semiconductor device formation process according to an embodiment of the present invention; Figure 10 This is a flowchart illustrating the method for forming a deep isolation structure and a vertical gate structure according to an embodiment of the present invention; Figures 11 to 16 This is a schematic diagram of the semiconductor device formation process according to an embodiment of the present invention; Figure 17 This is a flowchart of a first device formation method according to an embodiment of the present invention; Figures 18 to 22 This is a schematic diagram of the semiconductor device formation process according to an embodiment of the present invention; Figure 23 This is a structural diagram of a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0041] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0042] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0043] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0044] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0045] Figure 1 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, semiconductor device 1 includes a semiconductor substrate 11, a semiconductor layer 12, a deep isolation structure 13, a vertical gate structure 14, at least one first device 15, and at least one second device 16. It is worth noting that, in embodiments of the present invention, the first device and the second device may specifically refer to a high-voltage power device and a control circuit. Optionally, as an implementation, the high-voltage power device and the control circuit may respectively refer to a VDMOS (Vertical Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor) device and a BCD (Bipolar-CMOS-DMOS) device.

[0046] Specifically, in Figure 1In the illustrated semiconductor device, the semiconductor substrate 11 can be located at the bottom layer of the semiconductor device. The semiconductor substrate 11 serves as the carrier of the entire semiconductor device, providing necessary physical support for the entire semiconductor device during device manufacturing and after device formation. Other regions of the semiconductor device can be sequentially formed on the semiconductor substrate 11. It is worth noting that, to ensure that the high-voltage power device and control circuitry can be jointly formed on the semiconductor substrate 11, the semiconductor substrate 11 can be divided into a first device region and a second device region. The high-voltage power device and control circuitry can be formed on the semiconductor substrate 11 in the first device region and the second device region, respectively.

[0047] Semiconductor layer 12 can be formed on semiconductor substrate 11. Semiconductor layer 12 can serve as the core carrier region of semiconductor devices to support the formed first device and second device. It is worth noting that, in order to meet the device requirements of the high-voltage power device and the control circuit, the average doping concentration of semiconductor layer 12 in the first device region can be greater than the average doping concentration of semiconductor layer 12 in the second device region.

[0048] Optionally, as one configuration, the semiconductor layer 12 can be configured to include at least two stacked sub-epitaxial layers. In each pair of adjacent sub-epitaxial layers, the doping concentration of the upper sub-epitaxial layer can be lower than the doping concentration of the lower sub-epitaxial layer. Further, as a specific configuration, the semiconductor layer 12 can be configured to include a first epitaxial layer 121 and a second epitaxial layer 122. The first epitaxial layer 121 can be formed on the semiconductor substrate 11. The second epitaxial layer 122 can be formed on the first epitaxial layer 121. The semiconductor substrate 11, the first epitaxial layer 121, and the second epitaxial layer 122 can have the same doping type. Furthermore, the doping concentration of the first epitaxial layer 121 can be lower than the doping concentration of the semiconductor substrate 11, and the doping concentration of the second epitaxial layer 122 can be lower than the doping concentration of the first epitaxial layer 121. When the designed device has a high voltage rating, the thickness of the second epitaxial layer 122 can be greater than the thickness of the first epitaxial layer 121. When the designed device has a low voltage rating, the thickness of the second epitaxial layer 122 can be less than or equal to the thickness of the first epitaxial layer 121. Furthermore, in this configuration, the semiconductor substrate 11, the first epitaxial layer 121, and the second epitaxial layer 122 can be N-type doped. The semiconductor substrate 11 can be a low-resistivity red phosphorus substrate. The first epitaxial layer 121 can be an arsenic cap layer. The second epitaxial layer 122 can be a high-resistivity phosphorus epitaxial layer.

[0049] It is worth noting that the semiconductor substrate 11 can serve as the drain of the formed high-voltage power device. Therefore, by using a low-resistivity red phosphorus substrate as the semiconductor substrate 11, this embodiment of the invention can reduce the influence of the semiconductor substrate 11 on the on-resistance (Ron) of the formed device. Compared to phosphorus ions, arsenic ions have a low diffusion coefficient. Therefore, by using an arsenic cap layer with a doping concentration between the semiconductor substrate 11 and the second epitaxial layer 122 as the first epitaxial layer 121, this embodiment of the invention can use the first epitaxial layer 121 as a diffusion barrier layer to prevent doped ions in the semiconductor substrate 11 from diffusing upwards, thereby improving the BVCES (Breakdown Voltage with Shorted Source and Gate) of the control circuit. Furthermore, by using a low-doped, high-resistivity phosphorus epitaxial layer as the second epitaxial layer 122, this embodiment of the invention can improve the BVCEO (Breakdown Voltage from Collector to Emitter with Open Base) of the control circuit, and further improve the BVCES of the control circuit. By setting the doping concentration of the first epitaxial layer 121 to be greater than that of the second epitaxial layer 122, and setting the thickness of the second epitaxial layer 122 to be greater than that of the first epitaxial layer 121, the embodiments of the present invention can effectively reduce the on-resistance of the first epitaxial layer 121 and enable the second epitaxial layer 122 to withstand the withstand voltage of the device.

[0050] Optionally, in addition to the sub-epitaxial layers, the semiconductor layer 12 may also include a first high-voltage well region 123. The first high-voltage well region 123 may be formed within the second epitaxial layer 122 on the first device region. The doping type of the first high-voltage well region 123 may be the same as the doping type of the semiconductor substrate 11, the first epitaxial layer 121, and the second epitaxial layer 122. Furthermore, as a formation method, the first high-voltage well region 123 may be formed by performing heat treatment after implanting multiple dopant ions into the second epitaxial layer 122 to diffuse and activate the implanted ions.

[0051] It is worth noting that by providing a first high-voltage well region 123 inside the second epitaxial layer 122, the embodiments of the present invention can improve the doping concentration of the epitaxial layer, thereby optimizing the Rsp (Specific On-Resistance) and BV (Breakdown Voltage) of the high-voltage power device.

[0052] Optionally, in addition to the sub-epitaxial layers, the semiconductor layer 12 may also include a buried layer 124. The buried layer 124 may be formed within the first epitaxial layer 121 on the first device region. The doping type of the buried layer 124 may be the same as the doping type of the semiconductor substrate 11, the first epitaxial layer 121, and the second epitaxial layer 122. Furthermore, as a formation method, the buried layer 124 may be formed by implanting dopant ions into the first epitaxial layer 121 on the first device region after the formation of the first epitaxial layer 121 and before the formation of the second epitaxial layer 122.

[0053] It is worth noting that by providing a buried layer 124 inside the first epitaxial layer 121 on the first device region, the embodiments of the present invention can improve the influence of the epitaxial resistance of the high-voltage power device on the on-resistance of the formed device.

[0054] Furthermore, the semiconductor layer 12 may include at least one deep isolation trench and at least one gate trench. The deep isolation trench and the gate trench may be recessed structures formed on the upper surface of the epitaxial layer, extending from the upper surface of the semiconductor layer into the interior of the semiconductor layer. The deep isolation trench and the gate trench may be used to form the deep isolation structure 13 and the vertical gate structure 14, respectively. Optionally, to meet the structural requirements of the deep isolation structure 13 and the vertical gate structure 14, the trench depth of the deep isolation trench may be greater than the trench depth of the gate trench.

[0055] The deep isolation structure 13 can be formed inside the deep isolation trench of the semiconductor layer 12. The deep isolation structure 13 can serve as an isolation structure to isolate the first device region from the second device region.

[0056] Optionally, in addition to isolating the first device region and the second device region, the deep isolation structure 13 can also isolate different first devices within the first device region, different second devices within the second device region, and / or different device portions within the second devices. The specific configuration can be determined by relevant personnel according to actual needs. Thus, by setting the position of the deep isolation structure 13, the embodiments of the present invention can achieve the effect of isolating different devices.

[0057] Optionally, as one configuration, the deep isolation structure 13 can be configured to include an isolation conductor layer 131 and a first shielding dielectric layer 132. The first shielding dielectric layer 132 can be formed at the bottom and sidewalls of the deep isolation trench, isolating the isolation conductor layer 131 from the semiconductor layer 12. Further, as one implementation, the isolation conductor layer 131 can be a polysilicon layer, or other suitable materials such as metals. The first shielding dielectric layer 132 can be a shielding oxide layer. The deep isolation structure 13 can be formed by sequentially depositing a shielding oxide layer and a polysilicon layer in the deep isolation trench.

[0058] The vertical gate structure 14 can be formed inside the gate trench of the semiconductor layer 12. The vertical gate structure 14 can serve as the control core of a high-voltage power device.

[0059] Optionally, as an arrangement, the vertical gate structure can be configured to include a second shielding dielectric layer 141, a shielding gate 142, a gate dielectric layer 143, and a control gate 144. The second shielding dielectric layer 141 can be located at the bottom and lower sidewall of the gate trench, isolating the shielding gate 142 from the semiconductor layer 12. The gate dielectric layer 143 can be located at the upper sidewall of the gate trench, isolating the control gate 144 from the semiconductor layer 12. The gate dielectric layer 143 may further include a portion located between the shielding gate 142 and the control gate 144, which isolates the shielding gate 142 from the control gate 144. Further optionally, the shielding gate 142 can be configured in a stepped shape, with its width gradually increasing along its height direction. It is worth noting that by setting the shielding gate to a stepped shape and gradually increasing its width along its height, embodiments of the present invention can optimize the electric field distribution at the edges and drift regions of the polysilicon (POLY) of high-voltage power devices, thereby effectively reducing the device's Rsp and Qgd (Gate-to-Drain Charge). Alternatively, as another configuration, the shielding gate 142 can also be configured to be non-stepped, for example, U-shaped, inverted trapezoidal, etc. Alternatively, as another configuration, the vertical gate structure can also be configured to include a gate dielectric layer and a control gate. The gate dielectric layer can be located at the bottom and sidewalls of the gate trench, isolating the control gate from the semiconductor layer. Further optionally, as a formation method, the deep isolation structure 13 and the vertical gate structure 14 can be formed simultaneously using a process that reuses some steps.

[0060] The first device 15 (i.e., the high-voltage power device) can be formed in the semiconductor layer 12 on the first device region with a vertical gate structure 14 as the gate and a semiconductor substrate 11 as the drain.

[0061] Optionally, as one configuration, the semiconductor device 1 may also include a body region 151, a source region 152, and a corresponding body contact region 153. The body region 151 may be formed on one or both sides of the vertical gate structure 14. The source region 152 and the corresponding body contact region 153 may be formed within the body region 151.

[0062] The second device 16 (i.e., the control circuit) can be formed within the semiconductor layer 12 on the second device region.

[0063] Optionally, as one configuration, the semiconductor device 1 may also include a plurality of shallow isolation structures 161 and a second high-voltage well region 162. The plurality of shallow isolation structures 161 may be formed on the surface of the semiconductor layer 12 on the second device region. Each shallow isolation structure 161 may be located inside the second epitaxial layer 122 on the second device region, specifically, formed in the second high-voltage well region 162. The corresponding second device 16 may be formed in the second high-voltage well region 162 defined by each shallow isolation structure 161. Further optionally, as one implementation, the shallow isolation structure 161 may be formed by forming shallow isolation trenches on the semiconductor layer 12 on the second device region, and then filling the shallow isolation trenches with a corresponding dielectric material (e.g., silicon dioxide). The second high-voltage well region 162 may be formed by covering unrelated areas with a deposition mask before forming deep isolation trenches and gate trenches, then implanting dopant ions into relevant areas of the semiconductor layer 12 on the second device region, and then removing the mask. The second device 16 may be formed within each second high-voltage well region 162 using existing control circuit fabrication processes. The second device 16 may include doped regions (e.g., well regions, source regions, drain regions, etc.), depending on the type of device. If the second device includes a gate control device, the second device 16 may also include a gate structure.

[0064] like Figure 23 The semiconductor device further includes an interlayer dielectric layer 251 and metal contact vias penetrating the interlayer dielectric layer 251. The metal contact vias include a first type of metal contact via 259 contacting the upper surface of the gate of the first device and a first type of metal contact via 260 corresponding to each electrode region of the second device. It also includes a second type of metal contact via 252 contacting the source region and body contact region of the first device, wherein the second type of metal contact via 252 further extends into the interior of the body contact region. This embodiment of the invention can enhance the ability of the body region to absorb holes, thereby reducing the effective current gain β of the parasitic bipolar transistor inside the first device and improving the UIS (Unclamped Inductive Switching) capability of the power device.

[0065] Figure 2 This is a flowchart illustrating a semiconductor device formation method according to an embodiment of the present invention. It is intended to illustrate that by performing the following... Figure 2 The semiconductor device formation method shown in the embodiments of the present invention can realize the integration of high-voltage power devices and control circuits on the same chip to form the semiconductor device as shown in the above embodiments. Optionally, as one implementation, the high-voltage power devices and control circuits can specifically refer to VDMOS devices and BCD devices. Figure 2 As shown, the semiconductor device formation method may specifically include the following steps: Step S100: Provide a semiconductor substrate.

[0066] Specifically, this embodiment can provide a semiconductor substrate. The semiconductor substrate can be located at the bottom layer of the semiconductor device, serving as a carrier for the entire semiconductor device and providing necessary physical support during device manufacturing and after device formation. Other regions of the semiconductor device can be sequentially formed on the semiconductor substrate. It is worth noting that, to ensure that the high-voltage power device and control circuitry can be co-formed on the semiconductor substrate, the semiconductor substrate can be divided into a first device region and a second device region. The high-voltage power device and control circuitry can be formed on the semiconductor substrate in the first and second device regions, respectively.

[0067] Figure 3 This is a schematic diagram of the semiconductor device formation process according to an embodiment of the present invention. Figure 3 As shown, in this embodiment of the invention, a semiconductor substrate 31 may be provided first. The semiconductor substrate 31 may be divided into a first device region and a second device region. Optionally, to reduce the influence of the semiconductor substrate 31 on the on-resistance (Ron) of the shaped device, the semiconductor substrate 31 may be a low-resistance red phosphorus substrate.

[0068] Step S200: A semiconductor layer is formed on the surface of the semiconductor substrate.

[0069] Specifically, after providing a semiconductor substrate, this embodiment can form a semiconductor layer on the surface of the semiconductor substrate. The semiconductor layer can serve as the core carrier region of a semiconductor device, supporting the formed first and second devices. It is worth noting that, to meet the respective device requirements of the high-voltage power device and the control circuit, the average doping concentration of the semiconductor layer in the first device region can be greater than the average doping concentration of the semiconductor layer in the second device region.

[0070] Optionally, as one configuration, the semiconductor layer can be configured to include at least two stacked sub-epitaxial layers. In each pair of adjacent sub-epitaxial layers, the doping concentration of the upper sub-epitaxial layer can be lower than the doping concentration of the lower sub-epitaxial layer. Further, as a specific configuration, the semiconductor layer can be configured to include a first epitaxial layer and a second epitaxial layer. The first epitaxial layer can be formed on a semiconductor substrate. The second epitaxial layer can be formed on the first epitaxial layer. Furthermore, the doping types of the semiconductor substrate, the first epitaxial layer, and the second epitaxial layer can be the same. The doping concentration of the first epitaxial layer can be lower than the doping concentration of the semiconductor substrate, and the doping concentration of the second epitaxial layer can be lower than the doping concentration of the first epitaxial layer. It should be noted that, provided that the doping concentration of the first epitaxial layer is lower than the doping concentration of the semiconductor substrate, and the doping concentration of the second epitaxial layer is lower than the doping concentration of the first epitaxial layer, the specific doping concentrations of the semiconductor substrate, the first epitaxial layer, and the second epitaxial layer can be set by those skilled in the art according to actual needs, and this application does not impose specific limitations in this regard.

[0071] Optionally, to improve the doping concentration of the semiconductor layer and thus optimize the Rsp and BV of the high-voltage power device, in addition to each sub-epitaxial layer, the epitaxial layer may also be configured to include a first high-voltage well region. The first high-voltage well region may be formed inside the second epitaxial layer on the first device region. The doping type of the first high-voltage well region may be the same as the doping type of the semiconductor substrate, the first epitaxial layer, and the second epitaxial layer.

[0072] Figure 4 This is a flowchart of a semiconductor layer formation method according to an embodiment of the present invention. It is intended to illustrate that by performing the following... Figure 4 The semiconductor layer formation method shown in this embodiment of the invention can form a semiconductor layer with multiple sub-epitaxial layers and related structures that meets the requirements of semiconductor devices. For example... Figure 4 As shown, the semiconductor layer formation method may specifically include the following steps: Step S210: A first epitaxial layer is formed on the surface of the semiconductor substrate.

[0073] Specifically, in this embodiment, a first epitaxial layer can be formed on the surface of a semiconductor substrate.

[0074] Figures 5 to 9 This is a schematic diagram of the semiconductor device formation process according to an embodiment of the present invention. Figure 5 As shown, in this embodiment, a first epitaxial layer 321 can be formed on the surface of the semiconductor substrate 31. Optionally, in order to prevent doped ions in the semiconductor substrate 31 from diffusing upwards, thereby improving the BVCES of the control circuit, the first epitaxial layer 321 can be an arsenic cap layer.

[0075] Optionally, to mitigate the impact of the epitaxial resistance of the high-voltage power device on the on-resistance of the formed device, the semiconductor layer, in addition to each sub-epitaxial layer, may also include a buried layer. The buried layer may be formed within the first epitaxial layer on the first device region. The buried layer can be used to improve the concentration of the first epitaxial layer to prevent abrupt concentration changes in the first device region from the substrate to the subsequently formed second epitaxial layer. The doping type of the buried layer may be the same as the doping type of the semiconductor substrate, the first epitaxial layer, and the second epitaxial layer. During the actual formation of the semiconductor layer, the buried layer may be formed before the second epitaxial layer, within the first epitaxial layer on the first device region.

[0076] like Figure 6 As shown, in this embodiment, a buried layer 322 can be formed inside the first epitaxial layer 321 on the first device region. Optionally, as a formation method, the buried layer 322 can be formed by implanting dopant ions into the first epitaxial layer 321 on the first device region. It should be noted that, provided that the doping type is the same as that of the semiconductor substrate 31, the first epitaxial layer 321, and the second epitaxial layer 323, the specific dopant ions implanted here can be set by relevant personnel according to actual needs, and this application does not impose specific limitations on this. Furthermore, during the implantation of dopant ions, the first epitaxial layer 321 on the second device region can be covered by a coated photoresist to avoid contamination by the implanted dopant ions, and the photoresist can be removed after the dopant ion implantation is completed.

[0077] Step S220: Form a second epitaxial layer on the surface of the first epitaxial layer.

[0078] Specifically, in this embodiment, a second epitaxial layer can be formed on the surface of the first epitaxial layer.

[0079] like Figure 7 As shown, in this embodiment, a second epitaxial layer 323 can be formed on the surface of the first epitaxial layer 321, and the thickness of the second epitaxial layer can be greater than the thickness of the first epitaxial layer 321. Optionally, to improve the BVCEO of the control circuit and further improve the BVCES of the control circuit, the second epitaxial layer 323 can be a phosphorus high-resistivity epitaxial layer.

[0080] Step S230: A first high-voltage well region is formed inside the second epitaxial layer on the first device region.

[0081] Specifically, after forming the second epitaxial layer, this embodiment can form a first high-voltage well region inside the second epitaxial layer on the first device region.

[0082] like Figure 8As shown, after forming the second epitaxial layer, this embodiment can form a first high-pressure well region 324 inside the second epitaxial layer 323 on the first device region. Optionally, as a formation method, this embodiment can first perform multiple dopant ion implantations on the second epitaxial layer 323 on the first device region, and then perform heat treatment (specifically, thermal propulsion treatment) to diffuse and activate the implanted dopant ions, thereby forming the first high-pressure well region 324. In an optional embodiment, after heat treatment, the first high-pressure well region can also be diffused to the entire thickness of the second epitaxial layer on the first device region. It is worth noting that, provided that the doping type is the same as that of the first and second epitaxial layers, the specific dopant ions implanted here can be set by relevant personnel according to actual needs, and this application does not specifically limit this. Also, during dopant ion implantation, the second epitaxial layer 323 on the second device region can be covered by a coated photoresist to avoid contamination by the implanted dopant ions, and the photoresist can be removed after the dopant ion implantation is completed.

[0083] Optionally, before performing subsequent steps to form deep isolation trenches and gate trenches in the semiconductor layer, after forming the first high-voltage well region and performing the annealing process, this embodiment may also form a second high-voltage well region within the second epitaxial layer on the second device region. For example... Figure 8 As shown, in this embodiment, a second high-voltage well region 353 can be formed within the second epitaxial layer 323 on the second device region. Optionally, as one implementation, the doping type of the second high-voltage well region 353 can be different from that of the semiconductor substrate 31, the first epitaxial layer 321, and the second epitaxial layer 323. The second high-voltage well region 353 can be formed by implanting dopant ions into the second epitaxial layer 323 on the second device region. It should be noted that, provided that the doping type is different from that of the semiconductor substrate 31, the first epitaxial layer 321, and the second epitaxial layer 323, the specific dopant ions implanted here can be set by those skilled in the art according to actual needs, and this application does not impose specific limitations on this.

[0084] Step S300: Form at least one deep isolation trench and at least one gate trench extending from the upper surface of the semiconductor layer into the interior of the semiconductor layer.

[0085] Specifically, after forming the semiconductor layer, this embodiment can form at least one deep isolation trench and at least one gate trench extending from the upper surface of the semiconductor layer into the interior of the semiconductor layer. The gate trench can be located on the semiconductor layer in the first device region. Optionally, the deep isolation trench and the gate trench can be used to form a deep isolation structure and a vertical gate structure, respectively. To meet the structural requirements of the deep isolation structure and the vertical gate structure, the trench depth of the deep isolation trench can be greater than the trench depth of the gate trench. It is worth noting that setting the trench depth of the deep isolation trench to be greater than the trench depth of the gate trench not only meets the structural requirements of the deep isolation structure and the vertical gate structure, but also effectively ensures that the electric field in the terminal region of the formed control circuit meets the BV requirement of the high-voltage device, and can reduce the effective current gain β between adjacent wells in the second device region to a certain extent.

[0086] like Figure 9 As shown, after forming the semiconductor layer, this embodiment can form at least one deep isolation trench 325 and at least one gate trench 326 extending from the upper surface of the semiconductor layer into the interior of the semiconductor layer. Optionally, as one implementation, the deep isolation trench 325 and the gate trench 326 can be specifically formed inside the second epitaxial layer 323. Furthermore, as one formation method, this embodiment can first use a hard mask to cover unrelated areas and selectively etch the second epitaxial layer 323 to form a trench of the desired depth, and then remove the hard mask to form the deep isolation trench and the gate trench.

[0087] It should be noted that, in the embodiments of the present invention, all material layers involved can be formed using existing semiconductor deposition processes, including but not limited to Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), Molecular Beam Epitaxy (MBE), and Liquid-Phase Deposition (LPD), etc., and this application does not impose any limitations on these processes. The groove structures involved can all be formed using existing semiconductor etching processes, including but not limited to wet etching, dry etching, and ion beam etching (IBE), etc., and this application does not impose any limitations on these processes. Furthermore, although not explicitly stated, in actual process flows, to ensure that the formed material layers meet the requirements, this embodiment may also include other operations, such as planarization operations, and this application does not impose any limitations on these operations.

[0088] Step S400: A deep isolation structure and a vertical gate structure are formed inside the deep isolation trench and the gate trench, respectively.

[0089] Specifically, after forming at least one deep isolation trench and at least one gate trench, this embodiment can form a deep isolation structure and a vertical gate structure inside the deep isolation trench and the gate trench, respectively. The deep isolation structure can isolate the first device region from the second device region.

[0090] Optionally, in addition to isolating the first device region and the second device region, the deep isolation structure can also isolate different first devices within the first device region, different second devices within the second device region, and / or different device portions within the second devices. This application does not impose any limitations on this. It should be noted that, in order to achieve the required isolation function, deep isolation trenches and deep isolation structures located within them can be formed at corresponding locations in the second epitaxial layer. This application does not specifically limit their formation locations.

[0091] Optionally, as an arrangement, the deep isolation structure can be configured to include an isolation conductor layer and a first shielding dielectric layer. The first shielding dielectric layer can be formed at the bottom and sidewalls of the deep isolation trench, isolating the isolation conductor layer from the semiconductor layer. The vertical gate structure can also be configured to include a second shielding dielectric layer, a shielding gate, a gate dielectric layer, and a control gate. The second shielding dielectric layer can be located at the bottom and lower sidewalls of the gate trench, isolating the shielding gate from the semiconductor layer. The gate dielectric layer can be located at the upper sidewall of the gate trench, isolating the control gate from the semiconductor layer. The gate dielectric layer may also include a portion located between the shielding gate and the control gate, which isolates the shielding gate from the control gate. Further optionally, to optimize the electric field distribution at the polysilicon edge and drift region of the high-voltage power device, thereby effectively reducing the device's Rsp and Qgd, the shielding gate can be configured to be stepped, and its width can be configured to gradually increase along its height direction.

[0092] Figure 10 This is a flowchart illustrating a method for forming a deep isolation structure and a vertical gate structure according to an embodiment of the present invention. It is intended to illustrate that by performing the following... Figure 10 The deep isolation structure and vertical gate structure formation method shown in this embodiment of the invention can simultaneously form a deep isolation structure and a vertical gate structure that meet the requirements of semiconductor devices by reusing some process steps. Figure 10 As shown, the method for forming the deep isolation structure and the vertical gate structure may specifically include the following steps: Step S1010: Inside the deep isolation trench and inside the gate trench, a shielding dielectric layer covering the bottom and sidewalls of the trench is formed simultaneously.

[0093] Specifically, in this embodiment, a shielding dielectric layer covering the bottom and sidewalls of the trench can be formed simultaneously inside the deep isolation trench and the gate trench, so as to form a first shielding dielectric layer covering the bottom and sidewalls of the trench inside the deep isolation trench, and a third shielding dielectric layer covering the bottom and sidewalls of the trench inside the gate trench.

[0094] Figures 11 to 16 This is a schematic diagram of the semiconductor device formation process according to an embodiment of the present invention. Figure 11 As shown, in this embodiment, shielding dielectric layers covering the bottom and sidewalls of the trenches can be formed simultaneously inside the deep isolation trench and the gate trench. Specifically, a first shielding dielectric layer 331 covering the bottom and sidewalls of the trench is formed inside the deep isolation trench, and a third shielding dielectric layer 3351 covering the bottom and sidewalls of the trench is formed inside the gate trench. Optionally, the shielding dielectric layer can be a corresponding shielding oxide layer; this application does not specifically limit its application in this regard.

[0095] Step S1020: Fill the shielding dielectric layer with a first polysilicon layer to form the isolation conductor layer inside the deep isolation trench.

[0096] Specifically, after forming a shielding dielectric layer covering the bottom and sidewalls of the trench, this embodiment can fill the shielding dielectric layer with a first polysilicon to form an isolation conductor layer inside the deep isolation trench.

[0097] like Figure 12 As shown, in this embodiment, a first polysilicon layer can be filled on the shielding dielectric layer to form an isolation conductor layer 332 inside the deep isolation trench. It is important to note that the first polysilicon filling inside the deep isolation trench forms the isolation conductor layer 332, which constitutes the deep isolation structure. Furthermore, the operation in step S1020 can be performed synchronously inside the gate trench to form at least a partially shielded gate structure, i.e., the first polysilicon layer 3341.

[0098] Step S1030: Form a mask covering the deep isolation trench.

[0099] Specifically, this embodiment can form a mask covering a deep isolation trench.

[0100] like Figure 13 As shown, this embodiment can form a mask 333 that covers the deep isolation trench and the deep isolation structure formed therein. It is worth noting that, in addition to covering the deep isolation trench and the deep isolation structure formed therein, the mask 333 can also cover unrelated areas of the semiconductor layer.

[0101] Step S1040: Inside the gate trench, a portion of the first polysilicon and the shielding dielectric layer are sequentially etched, and a second polysilicon is filled on the retained first polysilicon to form the shielding gate.

[0102] Specifically, after covering the deep isolation trench and the deep isolation structure formed therein with a mask, this embodiment can sequentially etch a portion of the first polysilicon and the shielding dielectric layer inside the gate trench and fill the remaining first polysilicon with second polysilicon to form a shielding gate 334.

[0103] like Figure 14 As shown, in this embodiment, a portion of the first polysilicon layer 3341 and the third shielding dielectric layer 3351 are sequentially etched inside the gate trench, and then a fourth shielding dielectric layer 3352 is formed. A second polysilicon layer 3342 is then filled onto the retained first polysilicon layer to form a shielding gate 334 and a second shielding dielectric layer 335. The thickness of the fourth shielding dielectric layer 3352 can be less than that of the third shielding dielectric layer 3351, and correspondingly, the thickness of the second polysilicon layer 3342 can be greater than that of the first polysilicon layer 3341. It is important to note that inside the gate trench, the filled first polysilicon layer 3341 (the retained portion) and the second polysilicon layer 3342 form the shielding gate 334 of the vertical gate structure, and the filled third shielding dielectric layer 3351 (the retained portion) and the fourth shielding dielectric layer 3352 form the second shielding dielectric layer 335.

[0104] It should be noted that the above-described formation method is for illustrative purposes only. In actual applications, the stepped second shielding dielectric layer 335 can also be formed by etching the third shielding dielectric layer 3351 separately, and then directly filling the second polysilicon layer 3342.

[0105] As another configuration, the shielding gate 334 can also be configured as a non-stepped shape, such as a U-shape, an inverted trapezoidal shape, etc. Specifically, a portion of the first polysilicon layer 3341 and the third shielding dielectric layer 3351 can be sequentially etched inside the gate trench to form the shielding gate and the second shielding dielectric layer. The retained first polysilicon layer serves as the shielding gate, and the retained third shielding dielectric layer serves as the second shielding dielectric layer.

[0106] Step S1050: The gate dielectric layer and the control gate are sequentially formed on the shielding gate.

[0107] Specifically, after forming the shielding gate, in this embodiment, a gate dielectric layer and a control gate can be sequentially formed on the shielding gate.

[0108] like Figure 15 As shown, in this embodiment, a gate dielectric layer 336 can be formed covering the shielding gate 334 and the upper sidewall of the trench. Furthermore, in this embodiment, a control gate 337 can be formed on the gate dielectric layer 336.

[0109] Step S1060: Etch the mask.

[0110] Specifically, in this embodiment, after forming the gate dielectric layer and the control gate, the mask can be etched.

[0111] like Figure 16 As shown, this embodiment can etch a mask. Therefore, this embodiment can simultaneously form a deep isolation structure and a vertical gate structure that meet the requirements of semiconductor devices by reusing some process steps.

[0112] It should be noted that, after etching the mask, in order to protect the formed deep isolation structure and vertical gate structure, this embodiment can also form a corresponding oxide film on the surface of the entire semiconductor layer. For example... Figure 16 As shown, in this embodiment, an oxide thin film 3331 can be formed on the surface of the entire semiconductor layer.

[0113] It should be noted that the specific structure and fabrication process of the vertical gate structure given above are merely illustrative. In actual applications, the specific structure and fabrication process of the vertical gate structure can be set by relevant personnel according to actual needs. For example, as another configuration, the vertical gate structure can also be configured to include a gate dielectric layer and a control gate. The gate dielectric layer can be located at the bottom and sidewalls of the gate trench, and it isolates the control gate from the semiconductor layer.

[0114] Step S500: In the semiconductor layer on the first device region, at least one first device is formed using the vertical gate structure as a gate.

[0115] Specifically, after forming the deep isolation structure and the vertical gate structure, this embodiment can form at least one first device in the semiconductor layer on the first device region, using the vertical gate structure as the gate.

[0116] Figure 17 This is a flowchart of a first device formation method according to an embodiment of the present invention. It is intended to illustrate that by performing the following... Figure 17 The first device formation method shown in this embodiment of the invention can form a first device that meets the requirements in a semiconductor layer on the first device region, using a vertical gate structure as the gate and a semiconductor substrate 31 as the drain. Figure 17 As shown, the method for forming the first device may specifically include the following steps: Step S510: Form a body region on one or both sides of the vertical gate structure.

[0117] Specifically, in this embodiment, a body region can be formed on one or both sides of the vertical gate structure. The body region can serve as a carrier region for the subsequent formation of the source region and the body contact region.

[0118] Optionally, to avoid the formation process of the shallow isolation structure affecting the formation of the first device structure, this embodiment may first form multiple shallow isolation structures on the semiconductor layer in the second device region before forming the first device. Specifically, this embodiment may first form multiple shallow isolation trenches on the semiconductor layer in the second device region, and then form corresponding shallow isolation structures inside each shallow isolation trench.

[0119] Figures 18 to 22 This is a schematic diagram of the semiconductor device formation process according to an embodiment of the present invention. Figure 18 As shown, in this embodiment, multiple shallow isolation trenches 351 can be formed on the semiconductor layer in the second device region. Optionally, as one implementation, the shallow isolation trenches 351 can be formed inside the second epitaxial layer 323. Furthermore, as one formation method, in this embodiment, an irrelevant area can be first covered with a hard mask, and the second epitaxial layer 323 can be selectively etched to form a trench of the desired depth, and then the hard mask can be removed to form the shallow isolation trench. And, as... Figure 19 As shown, in this embodiment, a shallow isolation structure 352 can be formed inside the shallow isolation trench.

[0120] Furthermore, such as Figure 20 As shown, after forming the shallow isolation structure 352, for each vertical gate structure, this embodiment can form a body region 341 on one or both sides of the vertical gate structure.

[0121] Step S520: Within the body region, a source region and a corresponding body contact region are formed.

[0122] Specifically, after forming the body region, this embodiment can form a source region and a corresponding body contact region within the body region.

[0123] like Figure 21 As shown, for each body region 341, this embodiment can form a source region 342 and a corresponding body contact region 343 within the body region 341, wherein each source region 342 contacts one side of the corresponding vertical gate structure. It is worth noting that in this structure, the substrate can serve as the drain of the first device. The source region can serve as the source of the first device. The control gate in the vertical gate structure can serve as the gate of the first device. It is also worth noting that in this embodiment of the invention, the first device can be a depletion-mode device or an enhancement-mode device; this application does not specifically limit this. The channel layer of the first device can be vertically formed in the body region below the source region, near the control gate. The direction from the semiconductor substrate to the semiconductor layer is defined as a first direction, and the direction from the first device to the second device is defined as a second direction. In a third direction perpendicular to the first and second directions, the source region 342 includes a plurality of body contact regions 343, and the plurality of body contact regions 343 are spaced apart.

[0124] Therefore, by prioritizing the implementation of some pre-processing steps of the first device before forming at least one second device, embodiments of the present invention can ensure that some pre-processing steps of the first device will not affect the formation process of the second device, thereby achieving the integration of high-voltage power devices and control circuits on the same chip.

[0125] Step S600: Form at least one second device in the semiconductor layer on the second device region.

[0126] Specifically, after forming the deep isolation structure and the vertical gate structure, this embodiment can also form at least one second device in the semiconductor layer on the second device region.

[0127] Optionally, in step S600, in this embodiment, a corresponding second device can be formed in each of the second high-pressure well regions. Specifically, a second device is included between two adjacent shallow isolation structures.

[0128] like Figure 22 As shown, in this embodiment, corresponding second devices 354 can be formed in each of the second high-voltage well regions 353. Optionally, depending on the type of BCD device to be formed (which can be a single PMOS, a single NMOS, or CMOS, etc., this application does not limit this), this embodiment can use a corresponding process to form the second device, and this application does not specifically limit this. Furthermore, it should be noted that the second devices in the schematic diagrams provided in this embodiment are merely illustrative.

[0129] Forming the second device includes first forming a doped region corresponding to the second device in each of the second high-voltage well regions, and then forming a corresponding gate structure 255 (e.g., a gate dielectric layer and a polysilicon layer) on the semiconductor layer of the second device region. Further, sidewalls 256 are formed on both sides of the gate structure 255.

[0130] Optionally, after forming the first and second devices, this embodiment further includes forming an interlayer dielectric layer 251 and metal contact vias penetrating the interlayer dielectric layer 251. More optionally, in this embodiment, a first photomask is used to form a metal contact via 260 corresponding to the second device and a metal contact via 259 corresponding to the gate of the first device; a second photomask is used to form a metal contact via 252 corresponding to the source region and body contact region of the first device, wherein the metal contact via 252 corresponding to the source region and body contact region of the first device extends into the interior of the body contact region. It should be noted that the process order of these two steps is not limited.

[0131] Therefore, embodiments of the present invention can enhance the ability of the body region to absorb holes, thereby reducing the effective current gain β of the parasitic bipolar transistor inside the first device and improving the UIS (Unclamped Inductive Switching) capability of the power device. In other embodiments, the same photomask can also be used to simultaneously form metal contact vias corresponding to the first and second devices, wherein the metal contact vias 252 corresponding to the source region and body contact region of the first device extend to the surface of the body contact region.

[0132] Figure 23 This is a structural diagram of a semiconductor device according to an embodiment of the present invention. Figure 23 As shown, this embodiment can form an interlayer dielectric layer 251, first-type metal contact vias 259 and 260, and a second-type metal contact via 252 on the formed first and second devices. The first-type metal contact via 259 contacts the gate of the first device, the first-type metal contact via 260 contacts the gate and source / drain regions of the second device, and the second-type metal contact via 252 contacts the source region and body contact region of the first device. Furthermore, the second-type metal contact via contacting the body contact region can extend further into the interior of the body contact region.

[0133] This invention provides a semiconductor substrate including a first device region and a second device region. A semiconductor layer is formed on the surface of the semiconductor substrate, and deep isolation trenches and gate trenches are formed extending from the upper surface of the semiconductor layer into the interior of the semiconductor layer. Deep isolation structures and vertical gate structures are formed inside the deep isolation trenches and gate trenches, respectively. A first device is formed in the semiconductor layer on the first device region using the vertical gate structure as the gate, and a second device is formed in the semiconductor layer on the second device region. The average doping concentration of the semiconductor layer on the first device region is greater than the average doping concentration of the semiconductor layer on the second device region. The gate trenches are located in the semiconductor layer on the first device region, and the deep isolation structures isolate the first device region from the second device region. This allows for the integration of high-voltage power devices and control circuitry onto a single chip.

[0134] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for forming a semiconductor device, characterized in that, The method includes: A semiconductor substrate is provided, the semiconductor substrate including a first device region and a second device region; A semiconductor layer is formed on the surface of the semiconductor substrate, wherein the average doping concentration of the semiconductor layer on the first device region is greater than the average doping concentration of the semiconductor layer on the second device region; At least one deep isolation trench and at least one gate trench are formed extending from the upper surface of the semiconductor layer into the interior of the semiconductor layer, the gate trench being located on the semiconductor layer in the first device region; A deep isolation structure and a vertical gate structure are formed inside the deep isolation trench and the gate trench, respectively, wherein the deep isolation structure isolates the first device region from the second device region; In the semiconductor layer on the first device region, at least one first device is formed using the vertical gate structure as a gate. At least one second device is formed in the semiconductor layer on the second device region.

2. The method according to claim 1, characterized in that, The semiconductor layer includes at least two stacked sub-epitaxial layers, wherein in each pair of adjacent sub-epitaxial layers, the doping concentration of the upper sub-epitaxial layer is less than the doping concentration of the lower sub-epitaxial layer.

3. The method according to claim 2, characterized in that, Forming a semiconductor layer on the surface of the semiconductor substrate includes: A first epitaxial layer is formed on the surface of the semiconductor substrate; A second epitaxial layer is formed on the surface of the first epitaxial layer; A first high-voltage well region is formed on a second epitaxial layer in the first device region, and the doping type of the first high-voltage well region is the same as that of the semiconductor substrate, the first epitaxial layer and the second epitaxial layer.

4. The method according to claim 3, characterized in that, Before forming the second epitaxial layer on the surface of the first epitaxial layer, forming the semiconductor layer on the surface of the semiconductor substrate further includes: A buried layer is formed inside the first epitaxial layer on the first device region, and the doping type of the buried layer is the same as that of the first epitaxial layer.

5. The method according to claim 3, characterized in that, Forming a first high-pressure well region within the second epitaxial layer on the first device region includes: Multiple doped ion implantations are performed on the second epitaxial layer in the first device region; Heat treatment is performed to diffuse and activate the implanted dopant ions, forming the first high-voltage trap region.

6. The method according to claim 3, characterized in that, After forming the first high-voltage well region, forming the semiconductor layer on the surface of the semiconductor substrate further includes: A second high-voltage well region is formed in the second epitaxial layer on the second device region, and the doping type of the second high-voltage well region is opposite to that of the second epitaxial layer.

7. The method according to claim 1, characterized in that, The deep isolation structure includes a first shielding dielectric layer and an isolation conductor layer. The first shielding dielectric layer is located at the bottom and sidewalls of the deep isolation trench and isolates the isolation conductor layer from the semiconductor layer.

8. The method according to claim 1, characterized in that, The vertical gate structure includes a gate dielectric layer and a control gate. The gate dielectric layer is located at the bottom and sidewalls of the gate trench and isolates the control gate from the semiconductor layer.

9. The method according to claim 7, characterized in that, The vertical gate structure includes a second shielding dielectric layer, a shielding gate, a gate dielectric layer, and a control gate. The second shielding dielectric layer is located at the bottom and lower sidewall of the gate trench and isolates the shielding gate from the semiconductor layer. The gate dielectric layer is located at the upper sidewall of the gate trench and isolates the control gate from the semiconductor layer. The gate dielectric layer is also located between the shielding gate and the control gate and isolates the shielding gate from the control gate.

10. The method according to claim 9, characterized in that, The shielding grid is stepped, with its width increasing progressively along its height.

11. The method according to claim 10, characterized in that, The formation of a deep isolation structure and a vertical gate structure inside the deep isolation trench and the gate trench, respectively, includes: Inside the deep isolation trench and inside the gate trench, a shielding dielectric layer is simultaneously formed covering the bottom and sidewalls of the trench; A first polysilicon layer is filled on the shielding dielectric layer to form the isolation conductor layer inside the deep isolation trench; Form a mask covering the deep isolation trench; Inside the gate trench, a portion of the first polysilicon and the shielding dielectric layer are sequentially etched, and a second polysilicon is filled on the retained first polysilicon to form the shielding gate; The gate dielectric layer and the control gate are sequentially formed on the shielding gate; The mask is etched.

12. The method according to claim 6, characterized in that, After forming the deep isolation structure and the vertical gate structure, and before forming at least one first device using the vertical gate structure as the gate, the method further includes: Multiple shallow isolation trenches are formed in the semiconductor layer on the second device region; A shallow isolation structure is formed inside the shallow isolation trench.

13. The method according to claim 1, characterized in that, Using the vertical gate structure as the gate, forming at least one first device includes: A body region is formed on one or both sides of the vertical gate structure; Within the body region, a source region and a corresponding body contact region are formed; The substrate serves as the drain of the first device.

14. The method according to claim 12, characterized in that, Forming at least one second device in a semiconductor layer on the second device region includes: A corresponding second device is formed in each of the second high-pressure trap regions, and a second device is included between two adjacent shallow isolation structures.

15. The method according to claim 1, characterized in that, The second device is a BCD device.

16. The method according to claim 1, characterized in that, The trench depth of the deep isolation trench is greater than the trench depth of the gate trench.

17. The method according to claim 1, characterized in that, The deep isolation structure also isolates different first devices within the first device region, isolates different second devices within the second device region, and / or isolates different device portions within the second devices.

18. A semiconductor device, characterized in that, The semiconductor device includes: A semiconductor substrate, including a first device region and a second device region; A semiconductor layer is formed on the surface of the semiconductor substrate, wherein the average doping concentration of the semiconductor layer on the first device region is greater than the average doping concentration of the semiconductor layer on the second device region, the semiconductor layer includes at least one deep isolation trench and at least one gate trench, the deep isolation trench and the gate trench extending from the upper surface of the semiconductor layer into the interior of the semiconductor layer, and the gate trench is located on the semiconductor layer on the first device region; At least one deep isolation structure is formed inside the deep isolation trench, wherein the deep isolation structure isolates the first device region from the second device region; At least one vertical gate structure is formed inside the gate trench; At least one first device, with the vertical gate structure as the gate; At least one second device, a semiconductor layer formed on the region of the second device.

19. The semiconductor device according to claim 18, characterized in that, The semiconductor layer includes at least two stacked sub-epitaxial layers, wherein in each pair of adjacent sub-epitaxial layers, the doping concentration of the upper sub-epitaxial layer is less than the doping concentration of the lower sub-epitaxial layer.

20. The semiconductor device according to claim 19, characterized in that, The semiconductor layer includes: A first epitaxial layer is formed on the semiconductor substrate; The second epitaxial layer is formed on top of the first epitaxial layer; The first high-voltage well region is formed inside the second epitaxial layer on the first device region.

21. The semiconductor device according to claim 20, characterized in that, The semiconductor layer further includes: The buried layer is formed inside the first epitaxial layer on the first device region.

22. The semiconductor device according to claim 20, characterized in that, The semiconductor substrate, the first epitaxial layer, and the second epitaxial layer have the same doping type. The doping concentration of the first epitaxial layer is less than the doping concentration of the semiconductor substrate, and the doping concentration of the second epitaxial layer is less than the doping concentration of the first epitaxial layer.

23. The semiconductor device according to claim 20, characterized in that, The thickness of the second epitaxial layer is greater than the thickness of the first epitaxial layer.

24. The semiconductor device according to claim 21, characterized in that, The doping type of the buried layer and the first high-voltage trap region is the same as the doping type of the semiconductor substrate, the first epitaxial layer and the second epitaxial layer.

25. The semiconductor device according to claim 18, characterized in that, The deep isolation structure includes an isolation conductor layer and a first shielding dielectric layer, wherein the first shielding dielectric layer is formed at the bottom and sidewalls of the deep isolation trench and isolates the isolation conductor layer from the semiconductor layer.

26. The semiconductor device according to claim 18, characterized in that, The vertical gate structure includes a gate dielectric layer and a control gate, wherein the gate dielectric layer is located at the bottom and sidewalls of the gate trench and isolates the control gate from the semiconductor layer.

27. The semiconductor device according to claim 18, characterized in that, The vertical gate structure includes a second shielding dielectric layer, a shielding gate, a gate dielectric layer, and a control gate. The second shielding dielectric layer is located at the bottom and lower sidewall of the gate trench and isolates the shielding gate from the semiconductor layer. The gate dielectric layer is located at the upper sidewall of the gate trench and isolates the control gate from the semiconductor layer. The gate dielectric layer is also located between the shielding gate and the control gate and isolates the shielding gate from the control gate.

28. The semiconductor device according to claim 27, characterized in that, The shielding grid is stepped, with its width increasing progressively along its height.

29. The semiconductor device according to claim 18, characterized in that, The semiconductor device further includes a body region, a source region, and a corresponding body contact region. The body region is formed on one or both sides of the vertical gate structure, and the source region and the corresponding body contact region are formed within the body region. The substrate serves as the drain of the first device.

30. The semiconductor device according to claim 18, characterized in that, The semiconductor device further includes: Multiple shallow isolation structures are formed on the surface of the semiconductor layer on the second device region; A second high-voltage well region is located inside the semiconductor layer on the second device region; and, The doped regions of the second device are correspondingly formed in each of the second high-voltage well regions, wherein a second device is included between two adjacent shallow isolation structures.

31. The semiconductor device according to claim 18, characterized in that, The second device is a BCD device.

32. The semiconductor device according to claim 18, characterized in that, The trench depth of the deep isolation trench is greater than the trench depth of the gate trench.

33. The semiconductor device according to claim 18, characterized in that, The deep isolation structure also isolates different first devices within the first device region, isolates different second devices within the second device region, and / or isolates different device portions within the second devices.

34. The semiconductor device according to claim 29, characterized in that, It also includes metal contact vias corresponding to the source region and the body contact region, wherein the metal contact vias extend into the interior of the body contact region.

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