Semiconductor structure, preparation method thereof and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor structure, a preparation method thereof and electronic equipment. The electronic device includes a semiconductor structure. The semiconductor structure comprises a device layer, a contact layer and an interconnection layer. The device layer includes one or more devices. The contact layer is located above the device layer and comprises a first dielectric layer, one or more first conductive parts and second conductive parts; each first conductive part is in contact with one source electrode or one drain electrode; the first dielectric layer covers one or more grid electrodes; the second conductive part is arranged on the first dielectric layer to be separated from the source electrode, the drain electrode and the grid electrode; the interconnection layer is located above the contact layer and comprises a first interconnection line; the second conductive part is electrically connected between the first interconnection line and the other conductive structure, so that the second conductive part can be used as any type of interconnection line, and the wiring flexibility is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor structure and its fabrication method, and an electronic device. Background Technology

[0002] With the rapid development of mobile terminals, higher requirements have been placed on the parameters of semiconductor chips in these terminals. These parameters include the number of devices in the semiconductor chip, the chip's area utilization rate, and various electrical parameters. For example, efforts are being made to increase the overall gate width, improve the chip's area utilization rate, and reduce on-resistance.

[0003] In a semiconductor chip, various devices require multiple interconnects to be electrically connected to the outside world. These interconnects between different devices exhibit electrical isolation and connection relationships. Understandably, when designing semiconductor chips, interconnects are often interwoven to accommodate the overall device layout. However, existing semiconductor chip wiring methods are not flexible enough, making it easy for some types of interconnects to be interrupted by others.

[0004] In some scenarios, certain interconnects require both ends to serve as input terminals to ensure current uniformity on the interconnect. If one end of the interconnect is interrupted by another type of interconnect and cannot be electrically connected to the input potential, poor current uniformity will occur. Furthermore, if certain areas of a semiconductor chip are blocked by other types of interconnects and cannot be used to place interconnects, devices cannot be placed below those blocked areas. This results in a reduction in the effective device area of ​​the semiconductor chip, a decrease in the overall gate width, and low area utilization. Summary of the Invention

[0005] This application provides a semiconductor structure and its fabrication method, as well as an electronic device, which can solve the problem of limited wiring and inflexible wiring in existing semiconductor chips.

[0006] In a first aspect, a semiconductor structure is provided, comprising: a device layer including one or more devices; each device including a source, a drain, and a gate; a contact layer located above the device layer, including a first dielectric layer, one or more first conductive portions, and a second conductive portion; each first conductive portion contacting a source or a drain; the first dielectric layer covering one or more gates; the second conductive portion disposed on the first dielectric layer to be separate from the source, drain, and gate; an interconnect layer located above the contact layer, including first interconnect lines; the second conductive portion electrically connected between the first interconnect lines and one or more first conductive portions, and the second conductive portion being directly electrically connected to the one or more first conductive portions; or the interconnect layer including second interconnect lines, the second conductive portion being electrically connected between the first interconnect lines and the second interconnect lines; or the second conductive portion being electrically connected between the first interconnect lines and one or more gates. In this implementation, the second conductive portion is located in the contact layer, and its position in the semiconductor structure is lower than that of the interconnect lines in the interconnect layer; therefore, the second conductive portion differs from the interconnect lines in the prior art. The separation of the second conductive portion from the source, drain, and gate of the device means that the second conductive portion does not directly contact the source, drain, and gate of the device. In subsequent applications, the second conductive portion can be electrically connected to the source, drain, or gate of the device through other structures (such as interconnects or the first conductive portion) when necessary. This semiconductor structure has the second conductive portion disposed in the contact layer below the interconnect layer; the separation of the second conductive portion from the source, drain, and gate of the device allows it to be used as any type of interconnect. When the second conductive portion is electrically connected to the first interconnect, it can be used as an interconnect of the same type as the first interconnect. The second conductive portion can then be electrically connected to other structures to be connected. It should be noted that the first interconnect and the second conductive portion can be electrically connected solely through a via; alternatively, the first interconnect and the second conductive portion can be electrically connected together through a via and other conductive structures. For example, the first interconnect can be electrically connected to the second conductive portion sequentially through a via and the first conductive portion. The electrical connection method between the second interconnect and the second conductive portion can be the same as that between the first interconnect and the second conductive portion, and will not be repeated here. The second conductive portion can be electrically connected to the gate through a conductive via penetrating the first dielectric layer. In this implementation, the second conductive portion in the contact layer can provide additional wiring options when the wiring structure of the interconnect layer is limited, thus improving wiring flexibility.

[0007] In conjunction with the first aspect, in a first possible implementation of the first aspect, the one or more first conductive portions and the second conductive portion are fabricated using a simultaneous process. The first and second conductive portions fabricated using the simultaneous process have several identifiable characteristics, such as being made of the same material and having substantially the same thickness. This implementation allows the second conductive portion to be fabricated simultaneously with the first conductive portion, eliminating the need for additional process steps and saving on semiconductor fabrication costs.

[0008] In conjunction with the first aspect and the first possible implementation of the first aspect, in the second possible implementation of the first aspect, the projections of the first conductive part and the second conductive part along the length direction at least partially overlap.

[0009] In conjunction with the first aspect and the first or second possible implementation of the first aspect, in a third possible implementation of the first aspect, the first dielectric layer includes a first dielectric portion that continuously covers at least two gates; the second conductive portion is disposed on the first dielectric portion and spans the at least two gates. In this implementation, the second conductive portion can span multiple devices, connecting interconnects or first conductive portions that are far apart, thereby improving the applicability of the second conductive portion.

[0010] In conjunction with the first aspect, or any of the first to third possible implementations of the first aspect, in a fourth possible implementation of the first aspect, the first dielectric layer has a undulating surface at the location covering each of the gates; the first interconnect and the second conductive portion are electrically connected through one or more conductive vias; the one or more conductive vias avoid all the undulating surfaces. Since the undulating surfaces are not smooth enough, the placement of conductive vias on the undulating surfaces would result in poor conductivity. Therefore, this implementation allows the conductive vias to avoid the undulating surfaces, thereby improving the quality of the conductive vias.

[0011] In conjunction with the second possible implementation of the first aspect, in the fifth possible implementation of the first aspect, the second conductive portion is separated from the one or more first conductive portions; the first interconnect and the second conductive portion are electrically connected through one or more conductive vias; the second interconnect and the second conductive portion are electrically connected through one or more conductive vias. In this implementation, the separation of the second conductive portion from the first conductive portion means that the second conductive portion does not directly contact the first conductive portion. In subsequent applications, the second conductive portion can be electrically connected to some first conductive portions through other structures (such as interconnects) when necessary. In this implementation, the second conductive portion serves as a connecting line between two interconnect segments, providing a flexible and reliable wiring method from outside the interconnect layer.

[0012] In a sixth possible implementation of the first aspect, combining any of the second to fifth possible implementations, the interconnect layer further includes a third interconnect; the interconnects in the interconnect layer are arranged in layers; the first interconnect, the second interconnect, and the third interconnect are located on the same layer; the first interconnect and the second interconnect are located on opposite sides of the third interconnect and are electrically isolated from the third interconnect; the second conductive portion is located directly below the third interconnect. In this implementation, the type of the third interconnect is different from the types of the first and second interconnects. It is understood that when an interconnect is interrupted in a certain layer of the interconnect layer, for example, when the first interconnect is interrupted by the third interconnect, the second conductive portion can act as a bridging structure, allowing the second interconnect to be routed around the third interconnect, and a corresponding device can be placed below the second interconnect. This implementation provides a flexible wiring method.

[0013] In a seventh possible implementation of the first aspect, combining any of the second to fifth possible implementations, the interconnects in the interconnect layer are arranged in layers; the first interconnect is located in the bottommost first layer of the interconnect layer; the interconnect layer also includes a plurality of fourth interconnects; each of the fourth interconnects is electrically isolated from the first interconnect and the second interconnect; the plurality of fourth interconnects are located around and above the first interconnect to surround the first interconnect. In the prior art, when a certain area in the first layer of the interconnect layer is surrounded by one or more types of interconnects, other different types of interconnects cannot be arranged in that area, and consequently, corresponding devices cannot be arranged in the device layer below that area. The flexible wiring method provided by this implementation reduces the areas in the semiconductor structure that cannot be wired, which can increase the number of devices, increase the effective area of ​​the devices and the overall gate width, and improve the area utilization rate.

[0014] In conjunction with the first aspect, or any of the first to seventh possible implementations of the first aspect, in the eighth possible implementation of the first aspect, the plurality of devices includes GaN devices. Specifically, the GaN devices may be GaNHEMTs.

[0015] In a second aspect, a method for fabricating a semiconductor structure is provided. The method includes: obtaining a device layer comprising one or more devices; each device comprising a source, a drain, and a gate; forming a contact layer over the device layer, the contact layer comprising a first dielectric layer, one or more first conductive portions, and a second conductive portion; each first conductive portion contacting a source or a drain; the first dielectric layer covering the one or more gates; the second conductive portion disposed on the first dielectric layer to be separate from the source, drain, and gate; forming an interconnect layer over the contact layer, the interconnect layer comprising first interconnect lines; the second conductive portion electrically connected between the first interconnect lines and one or more first conductive portions, and the second conductive portion being directly electrically connected to the one or more first conductive portions; or the interconnect layer comprising second interconnect lines, the second conductive portion electrically connected between the first interconnect lines and the second interconnect lines; or the second conductive portion electrically connected between the first interconnect lines and one or more gates. In this implementation, the second conductive portion is located in the contact layer, and its position in the semiconductor structure is lower than that of the interconnect lines in the interconnect layer. Therefore, the second conductive portion differs from the interconnect lines in the prior art. The separation of the second conductive portion from the source, drain, and gate of the device means that the second conductive portion does not directly contact the source, drain, and gate of the device. In subsequent applications, the second conductive portion can be electrically connected to the source, drain, or gate of the device through other structures (such as interconnects or the first conductive portion) when necessary. This semiconductor structure has a second conductive portion disposed below the interconnect layer; the separation of the second conductive portion from the source, drain, and gate of the device allows it to be used as any type of interconnect. When the second conductive portion is electrically connected to the first interconnect, it can be used as an interconnect of the same type as the first interconnect. The second conductive portion can then be electrically connected to other structures to be connected. It should be noted that the first interconnect and the second conductive portion can be electrically connected solely through a via; alternatively, the first interconnect and the second conductive portion can be electrically connected together through a via and other conductive structures. For example, the first interconnect can be electrically connected to the second conductive portion sequentially through a via and the first conductive portion. The electrical connection method between the second interconnect and the second conductive portion can be the same as that between the first interconnect and the second conductive portion, and will not be repeated here. The second conductive portion can be electrically connected to the gate through a via penetrating the first dielectric layer. The second conductive portion in the contact layer of this implementation can provide additional wiring options when the wiring structure of the interconnect layer is limited, thereby improving the flexibility of wiring.

[0016] In conjunction with the second aspect, in a first possible implementation of the second aspect, forming a contact layer above the device layer includes: forming a first dielectric layer above the one or more gates; and fabricating the one or more first conductive portions and the second conductive portions using a simultaneous process. The first and second conductive portions fabricated using the simultaneous process have several identifiable characteristics, such as being made of the same material and having substantially the same thickness. This implementation allows the second conductive portion to be fabricated simultaneously with the first conductive portion, eliminating the need for additional process steps and saving on semiconductor fabrication costs.

[0017] In conjunction with the second aspect and the first possible implementation of the second aspect, in the second possible implementation of the second aspect, the projections of the first conductive part and the second conductive part along the length direction at least partially overlap.

[0018] In conjunction with the second aspect, or any of the first to second possible implementations of the second aspect, in a third possible implementation of the second aspect, the first dielectric layer includes a first dielectric portion that continuously covers at least two of the gates; the second conductive portion is disposed on the first dielectric portion and spans the at least two gates. In this implementation, the second conductive portion can span multiple devices and connect interconnects that are far apart, thus improving the applicability of the second conductive portion.

[0019] In conjunction with the second aspect, or any of the first to third possible implementations of the second aspect, in a fourth possible implementation of the second aspect, the contact layer further includes a second dielectric layer and one or more conductive vias; the first dielectric layer has undulating surfaces at locations covering each of the gates; forming the contact layer over the device layer includes: forming a second dielectric layer over the one or more first conductive portions, the second conductive portions, and the first dielectric layer; forming one or more conductive vias in the second dielectric layer; the one or more conductive vias in the second dielectric layer are electrically connected to the second conductive portions and avoid all the undulating surfaces; the first interconnect is electrically connected to the one or more conductive vias. Since the undulating surfaces are not smooth enough, the conductive vias located on the undulating surfaces will result in poor conductivity. Therefore, this implementation allows the conductive vias to avoid the undulating surfaces, which can improve the quality of the conductive vias.

[0020] In conjunction with the second possible implementation of the second aspect, in the fifth possible implementation of the second aspect, the second conductive portion is separated from the one or more first conductive portions; the first interconnect and the second conductive portion are electrically connected through one or more conductive vias; the second interconnect and the second conductive portion are electrically connected through one or more conductive vias. In this implementation, the separation of the second conductive portion from the first conductive portion means that the second conductive portion does not directly contact the first conductive portion. In subsequent applications, the second conductive portion can be electrically connected to the first conductive portion through other structures (such as interconnects) when necessary. In this implementation, the second conductive portion serves as a connecting line between two interconnect segments to provide a flexible and reliable wiring method from outside the interconnect layer.

[0021] In a sixth possible implementation of the second aspect, combining any of the second to fifth possible implementations, the interconnects in the interconnect layer are arranged in layers; the interconnect layer is formed above the contact layer, including: forming the first interconnect, the second interconnect, and the third interconnect above the contact layer; the first interconnect, the second interconnect, and the third interconnect are located on the same layer; the first interconnect and the second interconnect are located on opposite sides of the third interconnect and are electrically isolated from the third interconnect; the second conductive portion is located directly below the third interconnect. In this implementation, the type of the third interconnect is different from the types of the first and second interconnects. It can be understood that when an interconnect is interrupted in a certain layer of the interconnect layer, for example, when the first interconnect is interrupted by the third interconnect, the second conductive portion can act as a bridging structure, thereby allowing the second interconnect to be arranged around the third interconnect, and a corresponding device can be arranged below the second interconnect. This implementation provides a flexible wiring method.

[0022] In a seventh possible implementation of the second aspect, combining any of the second to fifth possible implementations, the interconnects in the interconnect layer are arranged in layers; the interconnect layer formed above the contact layer includes: forming the first interconnect, the second interconnect, and a plurality of fourth interconnects above the contact layer; the first interconnect is located in the lowest first layer of the interconnect layer; each of the fourth interconnects is electrically isolated from the first interconnect and the second interconnect; the plurality of fourth interconnects are located around and above the first interconnect to surround the first interconnect. In the prior art, when a certain area in the first layer of the interconnect layer is surrounded and above by one or more types of interconnects, other different types of interconnects cannot be arranged in that area, and consequently, corresponding devices cannot be arranged in the device layer below that area. This implementation allows the first interconnect to be arranged in that area, and the first interconnect is led out through the second conductive portion in the contact layer. After the first interconnect is led out, it can be electrically connected to the second interconnect, thereby enabling the arrangement of corresponding devices below the area where the first interconnect is located. The flexible wiring method provided by this implementation reduces the areas in the semiconductor structure that cannot be wired, which can increase the number of devices, increase the effective area of ​​devices and the overall gate width, and improve area utilization.

[0023] In conjunction with the second aspect, or any of the first to seventh possible implementations of the second aspect, in the eighth possible implementation of the second aspect, the plurality of devices includes GaN devices. Specifically, the GaN devices can be GaNHEMTs.

[0024] Thirdly, an electronic device is provided, comprising the semiconductor structure described in the first aspect, or any of the first to eighth possible implementations of the first aspect, or a semiconductor structure obtained by the fabrication method of the semiconductor structure described in the second aspect, or any of the first to eighth possible implementations of the second aspect. The electronic device may include mobile phones, tablets, televisions, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), drones, radar, aerospace equipment, power conversion equipment, 5G communication equipment, servers, routers, base stations, etc. Attached Figure Description

[0025] Figure 1 A cross-sectional schematic diagram of a semiconductor structure provided for some embodiments of this application;

[0026] Figure 2 A cross-sectional schematic diagram of a semiconductor structure provided for some embodiments of this application;

[0027] Figure 3 A cross-sectional schematic diagram of a semiconductor structure provided for some embodiments of this application;

[0028] Figure 4 A cross-sectional schematic diagram of a semiconductor structure provided for some embodiments of this application;

[0029] Figure 5 Flowcharts illustrating methods for fabricating semiconductor structures provided in some embodiments of this application;

[0030] Figure 6 A schematic cross-sectional view of the structure obtained in step S410 of the method for fabricating a semiconductor structure provided in some embodiments of this application;

[0031] Figure 7 A schematic cross-sectional view of the semiconductor structure obtained in step S421 of the method for fabricating a semiconductor structure provided in some embodiments of this application;

[0032] Figure 8 A schematic cross-sectional view of the structure obtained in step S422 of the method for fabricating a semiconductor structure provided in some embodiments of this application;

[0033] Figure 9 A cross-sectional schematic diagram of the intermediate structure in step S425 of the method for fabricating a semiconductor structure provided in some embodiments of this application;

[0034] Figure 10 This is a cross-sectional schematic diagram of the semiconductor structure obtained in step S425 of the method for fabricating a semiconductor structure according to some embodiments of this application.

[0035] Explanation of reference numerals in the attached figures:

[0036] 1- Semiconductor structure;

[0037] 11-Device layer; 12-Contact layer; 13-Interconnect layer;

[0038] 111 - Device; 112 - Nitride-based semiconductor layer; 113 - Nitride-based semiconductor layer; 120 - Conductive via; 121 - First conductive portion;

[0039] 122 - Second conductive part; 124 - First dielectric layer; 125 - Second dielectric layer; 130 - Conductive via; 131 - First interconnect layer; 132 - Second interconnect layer; 135 - Third dielectric layer;

[0040] 1111 - Source; 1112 - Drain; 1113 - Gate; 1241 - First dielectric section; 1241' - First dielectric section; 1311 - First interconnect; 1312 - Second interconnect; 1313 - Third interconnect; 1314 - Fourth interconnect; 1324 - Fourth interconnect;

[0041] 11131 - Third conductive part; 11132 - Doped nitride-based semiconductor layer. Detailed Implementation

[0042] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0043] In the description of this application, "multiple" means two or more, unless otherwise explicitly specified. It should be noted that the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone.

[0044] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between the components; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0045] In the description of this application, it should be understood that the terms "upper", "lower", "side", "front", "rear", "inner", "outer", etc., indicate the orientation or positional relationship based on the installation orientation or positional relationship, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0046] It should also be noted that in the embodiments of this application, the same reference numerals are used to represent the same component or part. For the same part in the embodiments of this application, the reference numerals may only be used to mark one part or component as an example. It should be understood that the reference numerals are also applicable to other identical parts or components.

[0047] This application provides an electronic device. This electronic device may include a mobile phone, tablet computer, television, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), drones, radar, aerospace equipment, power conversion equipment, 5G communication equipment, servers, routers, base stations, etc. This application does not impose any special limitations on the specific form of the above-mentioned electronic device.

[0048] Electronic devices include circuit boards. For example, circuit boards can include printed circuit boards (PCBs), which may have semiconductor structures, capacitors, inductors, and other devices disposed on them to achieve corresponding functions. The semiconductor structures may include memory, microprocessors, central processing units (CPUs), digital signal processors (DSPs), etc.

[0049] like Figure 1 As shown, some embodiments of this application relate to a semiconductor structure 1. The semiconductor structure 1 includes a device layer 11, a contact layer 12, and an interconnect layer 13. The device layer is a region on a substrate having one or more semiconductor device structures. The semiconductor device can be a metal-oxide-semiconductor field-effect transistor (MOSFET) or a gallium nitride high electron mobility transistor (GaN HEMT). The interconnect layer is a multilayer interconnect and dielectric layer grown on the semiconductor substrate in the back-end-of-line (BEOL) process of the semiconductor device, facilitating the electrical outward connection of the semiconductor device to the outside of the semiconductor structure according to wiring requirements. The contact layer is located between the device layer and the interconnect layer, having a structure that forms an ohmic contact with the source and drain of the semiconductor device. A dielectric layer covers the ohmic contact structure, and vias in the dielectric layer are used to electrically lead the source, drain, and gate of the semiconductor device upward to the interconnect layer. Therefore, the contact layer of this embodiment includes the following structural regions: a dielectric layer directly covering the ohmic contact structure, vias located in the dielectric layer, and structures covered below the dielectric layer (which may include other structures besides the ohmic contact structure). For ease of description, a three-dimensional coordinate system will be used as the direction reference, where, Figure 1 The diagram shows semiconductor structure 1 in the XZ plane. The Y-axis direction is perpendicular to the paper and points inwards. Figure 1 The X-axis direction from the center to the right is the first direction, the Y-axis direction perpendicular to the paper and inward is the second direction, and the Z-axis direction upward is the third direction.

[0050] Device layer 11 includes one or more devices 111 arranged along a first direction (X-axis direction). Optionally, device layer 11 can be fabricated on an epitaxial layer of semiconductor structure 1. To highlight the focus of this embodiment, Figure 1 Only the device layer 11 of semiconductor structure 1 and a portion of the structure above device layer 11 are shown. Specifically, device layer 11 has a plurality of source electrodes 1111 and a plurality of drain electrodes 1112 arranged alternately along a first direction (X-axis direction), with a gate electrode 1113 between adjacent source electrodes 1111 and drain electrodes 1112. The source electrodes 1111, gate electrodes 1113, and drain electrodes 1112 all extend along a second direction (Y-axis direction). A device 111 includes a gate electrode 1113 and source electrodes 1111 and drain electrodes 1112 located on both sides of the gate electrode 1113 along the first direction (X-axis direction). Figure 1 As shown, in one implementation, two adjacent devices 111 share a source 1111 or a drain 1112. Subsequently, different potentials can be applied to the gate 1113 of device 111 to make the source 1111 and drain 1112 of device 111 conduct or disconnect. It is worth mentioning that in certain specific applications, the source 1111 and drain 1112 of the same device 111 may not be fixed. For example, when device 111 is a symmetrical or bidirectional device, the source 1111 and drain 1112 of the same device 111 can be interchanged at any time. That is, at one moment, the electrode to the left of the gate 1113 of the same device 111 is the source 1111, and the electrode to the right of the gate 1113 is the drain 1112; at another moment, the electrode to the left of the gate 1113 of the same device 111 is the drain 1112, and the electrode to the right of the gate 1113 is the source 1111.

[0051] The contact layer 12 is located above the device layer 11. The contact layer 12 includes a first conductive portion 121, a second conductive portion 122, and a first dielectric layer 124.

[0052] The number of first conductive portions 121 is one or more, and each first conductive portion 121 is located above a source 1111 or a drain 1112 to directly contact a source 1111 or a drain 1112. The source 1111 or drain 1112 of the device 111 is a semiconductor material, while the electrical connection structure above the device layer 11 (such as the conductive via 120) is usually metal. Optionally, in order to avoid a large contact resistance when the source 1111 or drain 1112 contacts the electrical connection structure above the device layer 11, which would affect the electrical transmission performance, in this embodiment, the first conductive portion 121 is a specific metal material. By controlling the material of the first conductive portion 121 so that the first conductive portion 121 forms an ohmic contact with the source 1111 or drain 1112, the contact resistance can be reduced.

[0053] The first dielectric layer 124 covers one or more gates 1113 to avoid leakage caused by direct electrical connection between the gates 1113 and the source 1111 and drain 1112 on both sides. Specifically, the first dielectric layer 124 may include multiple first dielectric portions 1241 (1241'), each first dielectric portion 1241 (1241') covering one or more gates 1113 of the device 111. The number of gates 1113 covered by different first dielectric portions 1241 (1241') may be the same or different. It can be understood that the first dielectric layer 124 covering one or more gates 1113 means that the first dielectric layer 124 covers, for example, Figure 1 The cross-section shown covers the gate 1113 along the first direction (X-axis direction), but does not completely cover the gate 1113 in the second direction (Y-axis direction) (e.g., there is a conductive via through the first dielectric layer 124 above the gate 1113), so that the uncovered gate 1113 can form an electrical connection with the corresponding interconnect above, which facilitates the subsequent application of potential to the gate 1113 through the interconnect.

[0054] It is understood that whether two adjacent devices 111 share at least one of the gate, source, or drain will not affect the implementation of the first dielectric layer 124 and the first conductive portion 121. Two adjacent devices 111 may share more or fewer gates, sources, or drains. For example, in some possible implementations, two adjacent devices 111 may share the gate and drain; in some possible implementations, two adjacent devices 111 may share the gate and source; in some possible implementations, two adjacent devices 111 may not share the gate, source, and drain.

[0055] The number of second conductive portions 122 is one or more. Each second conductive portion 122 is disposed on the first dielectric layer 124, thereby separating the second conductive portion 122 from the source 1111, drain 1112, and gate 1113. It should be noted that the separation of the second conductive portion 122 from the source 1111, drain 1112, and gate 1113 of the device 111 means that the second conductive portion 122 does not directly contact the source 1111, drain 1112, and gate 1113 of the device 111. In subsequent applications, the second conductive portion 122 can form an electrical connection with the source 1111, drain 1112, or gate 1113 of the device 111 through other structures (such as interconnects, first conductive portions, or conductive vias, etc.) when necessary.

[0056] The contact layer 12 also includes a second dielectric layer 125 and one or more conductive vias 120. The second dielectric layer 125 covers one or more first conductive portions 121, second conductive portions 122, and the first dielectric layer 124. Each conductive via 120 penetrates the second dielectric layer 125, with one end contacting the first conductive portion 121 or the second conductive portion 122, and the other end exposed from the surface of the second dielectric layer 125, thereby electrically connecting the first conductive portion 121 or the second conductive portion 122 to the interconnect layer 13.

[0057] Interconnect layer 13 is located above contact layer 12 and includes interconnects, dielectric layers, and conductive vias. There are multiple interconnects. These interconnects are layered, from bottom to top as the first interconnect layer 131, the second interconnect layer, the third interconnect layer, ..., the Nth interconnect layer, where N is an integer greater than or equal to 1. Each interconnect layer includes one or more interconnects. It can be understood that the multiple interconnects in each interconnect layer are manufactured using a synchronous process, meaning that the multiple interconnects in each interconnect layer have the same material and substantially the same thickness. Dielectric layers are present between adjacent interconnect layers to achieve electrical isolation between different interconnect layers. Each dielectric layer has one or more conductive vias, which are used to electrically connect two specific interconnects in adjacent interconnect layers. Since different interconnect layers have similar interconnect structures, and different dielectric layers have similar conductive via structures, the main differences lie in the location and size of the interconnects and the location and size of the conductive vias. Therefore, for simplicity and ease of understanding, ... Figure 1 Only the first interconnect layer 131, the lowest of interconnect layers 13, is shown as an example. The first interconnect layer 131 is located above the second dielectric layer 125.

[0058] The second conductive portion 122 is electrically connected to at least one of the plurality of interconnects, enabling the second conductive portion 122 to participate in the wiring. Since the second conductive portion 122 is separated from the source 1111, drain 1112, and gate 1113 of the device 111, the second conductive portion 122 can be used as any type of interconnect. For example, the designer can electrically connect the second conductive portion 122 to a specific type of interconnect in the upper interconnect layer 13 according to the wiring requirements, and then connect the second conductive portion 122 to other structures to be connected. At this time, the second conductive portion 122 acts as that specific type of interconnect. Specifically, the structure to be connected to the second conductive portion 122 can be the source 1111, gate 1113, or drain 1112 of the device 111. For example, the second conductive portion 122 can be directly electrically connected to the first conductive portion 121 on the source 1111 or drain 1112, in which case the second conductive portion 122 can be regarded as a source interconnect or a drain interconnect; or the second conductive portion 122 can be electrically connected to the gate 1113 through a conductive via penetrating the first dielectric layer 124, in which case the second conductive portion 122 can be regarded as a gate interconnect; the structure to be connected to the second conductive portion 122 can also be a segment of interconnect in the interconnect layer 13. It should be noted that the electrical connection between the second conductive portion 122 and the interconnect can be directly achieved through the conductive via 120, or it can be achieved through the first conductive portion 121 and the conductive via 120. This embodiment can provide an additional wiring scheme by using the second conductive portion 122 located in the contact layer 12 when the wiring structure of the interconnect layer 13 is limited, thereby improving the flexibility of wiring.

[0059] It is understood that although the second conductive portion 122 can function similarly to an interconnect wire, it differs from an interconnect wire. For example, the second conductive portion 122 is located within the contact layer 12, below the interconnect layer 13 where the interconnect wire is located. Optionally, the first conductive portion 121 and the second conductive portion 122 are fabricated using a simultaneous process, such that the second conductive portion 122 and the first conductive portion 121 are located at approximately the same height in the semiconductor structure 1, while the interconnect wires in the interconnect layer 13 are all higher than the first conductive portion 121. Optionally, the projections of the first conductive portion 121 and the second conductive portion 122 along the length direction (X-axis direction) at least partially overlap, so that they are located at approximately the same height in the semiconductor structure 1. For example, the material of the second conductive portion 122 may be different from the material of the interconnect. Optionally, the material of the second conductive portion 122 may be the same as the material of the first conductive portion 121. The material of the first conductive portion 121 satisfies the condition that it can form an ohmic contact with the source 1111 and / or drain 1112 of the device 111, while the material of the interconnect does not need to consider this condition. Therefore, the material of the second conductive portion 122 may be different from the material of the interconnect. Furthermore, the thickness of the second conductive portion 122 may be different from the thickness of the interconnect. Optionally, the thickness of the second conductive portion 122 may be less than the thickness of the interconnect.

[0060] As an optional implementation method, such as Figure 1 As shown, the first conductive portion 121 is located on both sides of the first dielectric layer 124 in the first direction (X-axis direction), that is, the edge of the first conductive portion 121 climbs onto the first dielectric layer 124. This ensures that the fabricated first conductive portion 121 completely covers the source 1111 or drain 1112, avoiding the problem of poor contact between the first conductive portion 121 and the source 1111 or drain 1112. Optionally, the first dielectric layer 124 can be fabricated first. The first dielectric layer 124 has a multi-segment structure with gaps between adjacent segments to expose a source 1111 or a drain 1112. Then, the first conductive portion 121 is fabricated in the gaps so that the first conductive portion 121 fills the gaps and the edge of the first conductive portion 121 climbs onto the first dielectric layer 124.

[0061] Further, as an optional implementation, the first dielectric portion 1241' is continuous along a first direction (X-axis direction) and covers at least two gates 1113; the second conductive portion 122 is disposed on the first dielectric portion 1241' and spans at least two gates 1113 along the first direction (X-axis direction). Optionally, the number of first dielectric portions 1241' can be one or more, and each first dielectric portion 1241' can be provided with one or more second conductive portions 122. It should be noted that when the first dielectric portion 1241' is continuous and covers at least two gates 1113, the first dielectric portion 1241' will necessarily cover the source 1111 and / or drain 1112 between the gates 1113 of at least two devices 111. It can be understood that the first dielectric portion 1241' covering the aforementioned source 1111 and / or drain 1112 means that the first dielectric portion 1241' covers the source 1111 and / or drain 1112 as described above. Figure 1 The cross-section shown covers the aforementioned source 1111 and / or drain 1112 along the first direction (X-axis direction), but does not completely cover the aforementioned source 1111 and / or drain 1112 in the second direction (Y-axis direction). This allows the aforementioned source 1111 and / or drain 1112 to form an electrical connection with the corresponding interconnect in the area not covered by the first dielectric portion 1241' in the second direction (Y-axis direction). In this embodiment, the second conductive portion 122 can cross the gates 1113 of at least two devices 111 through the first dielectric portion 1241' and remain separated from the source 1111, drain 1112, and gate 1113. Therefore, during wiring, two interconnects or the first conductive portion 121 that are far apart can be electrically connected as needed. In this embodiment, the second conductive portion 122 has higher applicability.

[0062] Optionally, the first conductive portion 121 and the second conductive portion 122 are manufactured using a simultaneous process, meaning that the first conductive portion 121 and the second conductive portion 122 are manufactured using the same set of processes, thus allowing the first conductive portion 121 and the second conductive portion 122 to be fabricated simultaneously. For example, the first conductive portion 121 and the second conductive portion 122 can be fabricated simultaneously through steps such as deposition, resist coating, exposure, development, etching, and resist removal. It should be noted that the mask used during exposure must simultaneously contain the regions corresponding to the first conductive portion 121 and the second conductive portion 122. It can be understood that the first conductive portion 121 and the second conductive portion 122 manufactured using a simultaneous process have several identifiable characteristics, such as the first conductive portion 121 and the second conductive portion 122 being made of the same material, and the first conductive portion 121 and the second conductive portion 122 having the same thickness (i.e., the same material). Figure 1 The thickness in the third direction (Z-axis direction) is basically the same. The second conductive part 122 is manufactured using the same process as the first conductive part 121, so there is no need to add additional process steps such as photomask for the fabrication of the second conductive part 122, which can save the wafer fabrication cost of semiconductor structure 1.

[0063] Please refer to Figure 1 , Figure 1 A specific embodiment of the second conductive portion 122 participating in wiring is shown, wherein the first interconnect layer 131 includes a first interconnect line 1311 and a second interconnect line 1312. The first interconnect line 1311 and the second interconnect line 1312 are electrically connected to the sources 1111 of different devices 111, therefore, the first interconnect line 1311 and the second interconnect line 1312 are source interconnect lines. The second conductive portion 122 is electrically connected between the first interconnect line 1311 and a first conductive portion 121, and the second conductive portion 122 is directly electrically connected to the first conductive portion 121. It should be noted that... Figure 1 A separator line distinguishes the second conductive portion 122 from the first conductive portion 121. However, when the second conductive portion 122 and the first conductive portion 121 are fabricated using the same process, there may be no obvious separator between them in the actual semiconductor structure 1. Typically, the source interconnect can be directly electrically connected to the source 1111 of the device 111 located directly below the source interconnect via the conductive via 120 and the first conductive portion 121. Figure 1The first interconnect 1311 directly passes through the conductive via 120 and the first conductive portion 121, electrically connecting to the source of a device located directly below the first interconnect 1311; the second interconnect 1312 directly passes through the conductive via 120 and the first conductive portion 121, electrically connecting to the source 1111 of a device 111 located directly below the second interconnect 1312. In this embodiment, the second conductive portion 122 is incorporated into the wiring, allowing the source interconnect to be electrically connected to the source 1111 of a device 111 located in other positions with the help of the second conductive portion 122: such as... Figure 1 The first interconnect 1311 is also electrically connected to the source 1111 of another device 111 located directly below the second interconnect 1312 via a conductive via 120, a first conductive portion 121, a second conductive portion 122, and another first conductive portion 121. It can be understood that when the second conductive portion 122 is connected to the interconnect, the second conductive portion 122 can first be electrically connected to the first conductive portion 121, and then electrically connected to the interconnect via the conductive via 120 above the first conductive portion 121. In this case, it is equivalent to the second conductive portion 122 and the first conductive portion 121 sharing a conductive via 120, thereby eliminating the need for a conductive via 120 that directly connects the second conductive portion 122 to the interconnect.

[0064] Please refer to Figure 2 , Figure 2Another specific embodiment of the second conductive portion 122 participating in wiring is shown, wherein the first interconnect layer 131 includes a first interconnect 1311, a second interconnect 1312, and a third interconnect 1313. The first interconnect 1311, the second interconnect 1312, and the third interconnect 1313 are located on the same layer, with the first interconnect 1311 and the second interconnect 1312 located on opposite sides of the third interconnect 1313. Specifically, the first interconnect 1311, the second interconnect 1312, and the third interconnect 1313 can be fabricated using a synchronous process. The first interconnect 1311 and the second interconnect 1312 are electrically connected to the sources 1111 of different devices 111, therefore, the first interconnect 1311 and the second interconnect 1312 are source interconnects. The third interconnect 1313 is used to electrically connect to the gate 1113 of at least one device 111, therefore, the third interconnect 1313 is a gate interconnect. Since the first interconnect 1311 and the second interconnect 1312 are different types of interconnects from the third interconnect 1313, the first interconnect 1311 and the second interconnect 1312 need to be electrically isolated from the third interconnect 1313 to maintain different potentials. The second conductive portion 122 is electrically connected between the first interconnect 1311 and the second interconnect 1312. Specifically, the second conductive portion 122 is located directly below the third interconnect 1313. One end of the second conductive portion 122 extends across the third interconnect 1313 along the X-axis and is electrically connected to the first interconnect 1311 through the conductive via 120. The other end of the second conductive portion 122 extends across the third interconnect 1313 along the X-axis and is electrically connected to the second interconnect 1312 through the conductive via 120. Therefore, if the first interconnect 1311 and the second interconnect 1312 are interrupted by the third interconnect 1313, the second conductive portion 122 can be used to reconnect the first interconnect 1311 and the second interconnect 1312. It is understandable that when one end of the first interconnect 1311 and the second interconnect 1312 are connected to the upper-layer interconnect and there is no second conductive part 122 between the first interconnect 1311 and the second interconnect 1312, the first interconnect 1311 and the second interconnect 1312 each have only one input terminal that can input current, resulting in poor current uniformity. In this embodiment, the second conductive part 122 can provide a conductive path between the first interconnect 1311 and the second interconnect 1312. This conductive path can connect the first interconnect 1311 and the second interconnect 1312 into a whole, which has two input terminals, thereby improving current uniformity.

[0065] It is understood that when the second conductive portion 122 is only used to connect two interconnect segments, the second conductive portion 122 can be separated from the first conductive portion 121, and the second conductive portion 122 is directly electrically connected to the interconnect segment through the conductive via 120. Since the gate 1113 typically protrudes relative to the planes of the source 1111 and drain 1112, the first dielectric layer 124 has an undulating surface at the location covering the gate 1113. If the undulating surface is not smooth enough, placing the conductive via 120 on the undulating surface will result in poor conductivity. Therefore, in this embodiment, the conductive via 120 avoids the undulating surface, which can enhance the quality of the conductive via 120.

[0066] It should be noted that in some other feasible embodiments, the two interconnecting lines electrically connected to the second conductive portion 122 may also be located in different interconnecting layers. For example, the first interconnecting line 1311 may be located in the first interconnecting layer 131, and the first interconnecting line 1311 is connected to the second conductive portion 122 through a conductive via 120 in the second dielectric layer 125; the second interconnecting line 1312 may be located in the second interconnecting layer above the first interconnecting layer, and the second interconnecting line 1312 is electrically connected to the second conductive portion 122 through at least two conductive vias 120, wherein at least one conductive via 120 is located in the dielectric layer between the second interconnecting layer and the first interconnecting layer 131, and at least one conductive via 120 is located in the second dielectric layer 125 between the first interconnecting layer 131 and the contact layer 12.

[0067] Please refer to Figure 3 , Figure 3Another specific embodiment of the second conductive portion 122 participating in wiring is shown, wherein the first interconnect layer 131 includes a first interconnect 1311, a second interconnect 1312, and a third interconnect 1313. The first interconnect 1311, the second interconnect 1312, and the third interconnect 1313 are located on the same layer, with the first interconnect 1311 and the second interconnect 1312 located on opposite sides of the third interconnect 1313. Specifically, the first interconnect 1311, the second interconnect 1312, and the third interconnect 1313 can be fabricated using a synchronous process. The first interconnect 1311 and the second interconnect 1312 are electrically connected to the sources 1111 of different devices 111, therefore, the first interconnect 1311 and the second interconnect 1312 are source interconnects. The third interconnect 1313 is used to electrically connect to the gate 1113 of at least one device 111, therefore, the third interconnect 1313 is a gate interconnect. Since the first interconnect 1311 and the second interconnect 1312 are different types of interconnects from the third interconnect 1313, the first interconnect 1311 and the second interconnect 1312 need to be electrically isolated from the third interconnect 1313 to maintain different potentials. The second conductive portion 122 is located directly below the third interconnect 1313. One end of the second conductive portion 122 extends across the third interconnect 1313 along the X-axis and establishes an electrical connection with the first interconnect 1311 through the first conductive portion 121 located below the first interconnect 1311 and the conductive via 120. The other end of the second conductive portion 122 extends across the third interconnect 1313 along the X-axis and establishes an electrical connection with the second interconnect 1312 through the first conductive portion 121 located below the second interconnect 1312 and the conductive via 120. Therefore, when the first interconnect 1311 and the second interconnect 1312 are interrupted by the third interconnect 1313, the electrical connection between the first interconnect 1311, the second interconnect 1312, the device 111 below the first interconnect 1311, and the device 111 below the second interconnect 1312 can be restored using the second conductive part 122.

[0068] It is important to note that Figures 1-3 Several specific embodiments of the second conductive part 122 participating in wiring are shown, but the way the second conductive part 122 participates in wiring is not limited to these embodiments. Figures 1-3 Specific implementation methods. Figures 1-3 The first interconnect 1311 is located in the first interconnect layer 131. In some other feasible embodiments, the first interconnect 1311, which is electrically connected to the second conductive part 122, may be located in other interconnect layers. Similarly, the second interconnect 1312 and the third interconnect 1313 may also be located in other interconnect layers outside the first interconnect layer 131. Figures 1-3In this configuration, the first interconnect 1311 and the second interconnect 1312 are source interconnects, and the third interconnect 1313 is a gate interconnect. It is understood that in other feasible embodiments, the first interconnect 1311 and the second interconnect 1312 can be electrically connected to the drain 1112 or the gate 1113 of different devices 111, respectively. That is, the first interconnect 1311 and the second interconnect 1312 can also serve as drain interconnects or gate interconnects, and the third interconnect 1313 can be connected to the source 1111 or the drain 1112 of device 111. In other words, the third interconnect 1313 can also serve as a source interconnect or a drain interconnect, as long as the types of the first interconnect 1311 and the second interconnect 1312 are different from the type of the third interconnect 1313. For example, when the first interconnect 1311 serves as a gate interconnect, the second conductive portion 122 can also be electrically connected between the first interconnect 1311 and one or more gates 1113.

[0069] Please refer to Figure 4 , Figure 4 Another specific embodiment in which the second conductive portion 122 participates in wiring is shown. The interconnect layer 13 includes a first interconnect layer 131, a second interconnect layer 132, a third dielectric layer 135 located between the first interconnect layer 131 and the second interconnect layer 132, and a conductive via 130 located in the third dielectric layer 135.

[0070] The first interconnect layer 131 includes a first interconnect 1311, a second interconnect 1312, and a plurality of fourth interconnects 1314. Each fourth interconnect 1314 is electrically isolated from the first interconnect 1311 and the second interconnect 1312; specifically, the plurality of fourth interconnects 1314 are located around the first interconnect 1311. The second interconnect layer 132 includes one or more fourth interconnects 1324 located above the first interconnect 1311. Each fourth interconnect 1324 is electrically isolated from the first interconnect 1311 and the second interconnect 1312. The plurality of fourth interconnects 1314 and 1324 collectively surround the first interconnect 1311, and the type of the plurality of fourth interconnects 1314 and 1324 is different from the type of the first interconnect 1311. It is understood that the plurality of fourth interconnects 1314 and 1324 may be of the same type or different types from each other. Figure 4 As shown, portions of the fourth interconnect 1314 and 1324 can be connected via a conductive via 130 to serve as interconnects of the same type. It is worth noting that the fourth interconnects 1314 and 1324 can also be other types of interconnects besides gate, source, and drain interconnects. For example, a fourth interconnect 1324 located directly above the first interconnect 1311 can be electrically connected to the substrate of the semiconductor structure to control the substrate potential, thus preventing the fourth interconnect 1324 from being electrically connected to the gate, source, or drain.

[0071] It is understood that in the prior art, when a certain area in the first interconnect layer of the interconnect layer is surrounded by one or more types of interconnects on all sides and above, other different types of interconnects cannot be arranged in that area (because the paths leading upwards or outwards from that area are blocked, and since that area is at the bottom layer, there are no paths leading out below it). Consequently, the corresponding devices cannot be arranged in the device layer below that area. In this embodiment, a first interconnect 1311 can be arranged in that area, and the first interconnect 1311 can be led out through the second conductive part 122 in the contact layer 12. After the first interconnect 1311 is led out, it can be electrically connected to the second interconnect 1312, thereby enabling the arrangement of the corresponding devices below the area where the first interconnect 1311 is located. The flexible wiring method provided by this embodiment reduces the areas in the semiconductor structure that cannot be wired, can increase the number of devices, increase the effective area of ​​the devices and the overall gate width, and improve the area utilization rate.

[0072] As an optional implementation, the plurality of devices 111 of device layer 11 include gallium nitride (GaN) devices. Specifically, the GaN devices can be gallium nitride high electron mobility transistors (GaN HEMTs). GaN HEMTs have high operating frequencies and can be used in high-frequency products such as: power amplifiers for wireless communication devices such as 5G, Wi-Fi, and Bluetooth; high-efficiency switching power supplies; DC-DC converters; inverters; charging equipment and on-board chargers for electric vehicles; server power supplies and cooling equipment for data centers; high-brightness LED drivers; motor drives and frequency converters; high-power amplifiers for radar and communication systems; high-voltage inverters; and power quality improvement equipment. They can improve power conversion efficiency, reduce energy consumption, miniaturize devices, and extend lifespan. It should be noted that when device 111 includes a GaN device, the device layer may have a nitride-based semiconductor layer 112, a nitride-based semiconductor layer 113, a doped nitride-based semiconductor layer 11132, and a third conductive portion 11131 arranged from bottom to top, wherein the band gap of the nitride-based semiconductor layer 112 is different from the band gap of the nitride-based semiconductor layer 113. Optionally, the nitride-based semiconductor layer 112 may include GaN, the nitride-based semiconductor layer 113 may include AlGaN, the doped nitride-based semiconductor layer 11132 may include P-GaN, the band gap of the nitride-based semiconductor layer 112 is larger than the band gap of the nitride-based semiconductor layer 113, and a two-dimensional electron gas (2DEG) is formed between the nitride-based semiconductor layer 112 and the nitride-based semiconductor layer 113. The gate 1113 includes a doped nitride-based semiconductor layer 11132 and a third conductive portion 11131. Optionally, the contact between the doped nitride-based semiconductor layer 11132 and the third conductive portion 11131 is a Schottky contact. The source 1111 and drain 1112 are the regions of the nitride-based semiconductor layer 112 and the nitride-based semiconductor layer 113 on both sides of the gate 1113. Figure 2 Taking the GaN device as an example, the first conductive portion 121 is located on the nitride-based semiconductor layer 113 and on one side of the gate 1113. The regions of the nitride-based semiconductor layer 112 and the nitride-based semiconductor layer 113 below the first conductive portion 121 are the source 1111 or the drain 1112. When the first dielectric portion 1241' is continuous along the first direction (X-axis direction) and covers at least two gates 1113, the regions of the nitride-based semiconductor layer 112 and the nitride-based semiconductor layer 113 below the first dielectric portion 1241' between the two gates 1113 are the source 1111 or the drain 1112. Accordingly, in the semiconductor structure 1 containing the GaN device, the material of the first conductive portion 121 used to form the ohmic contact can be at least one of Ti, Al, or TiN. It is worth mentioning that, in addition to the doped nitride-based semiconductor layer 11132 and the third conductive part 11131, the gate 1113 can also be a MIS structure (Metal Insulator Semiconductor), which is a structure that bonds metal, insulating layer and semiconductor together.

[0073] Some embodiments of this application relate to a method for fabricating a semiconductor structure 1. For example... Figure 5 As shown, the preparation method includes the following multiple steps. It is understood that this preparation method can be used to prepare the semiconductor structure 1 in any of the foregoing embodiments; therefore, structural features identical to those in the semiconductor structure 1 of the foregoing embodiments will not be repeated here. For ease of explanation, the processing... Figure 2 Taking the semiconductor structure 1 shown as an example, please refer to the structural diagrams corresponding to each step. Figures 6 to 10 , Figure 2 .

[0074] Step S410, a device layer 11 including one or more devices 111 is obtained.

[0075] Specifically, an epitaxial layer can be formed on a substrate, and one or more devices 111 can be fabricated on the epitaxial layer. For example... Figure 6 As shown, device 111 includes a source 1111, a drain 1112, and a gate 1113. For ease of description, a three-dimensional coordinate system is used as the direction reference, wherein... Figure 6 The diagram shows semiconductor structure 1 in the XZ plane. The Y-axis direction is perpendicular to the paper and points inwards. Figure 6The X-axis direction from the center to the right is the first direction, the Y-axis direction perpendicular to the paper and inward is the second direction, and the upward Z-axis direction is the third direction. Specifically, the device layer 11 has multiple sources 1111 and multiple drains 1112 arranged alternately along the first direction (X-axis direction), with a gate 1113 between adjacent sources 1111 and drains 1112. The sources 1111, gates 1113, and drains 1112 all extend along the second direction (Y-axis direction). A device 111 includes a gate 1113 and source 1111 and drain 1112 located on both sides of the gate 1113 along the first direction (X-axis direction). Subsequently, different potentials can be applied to the gate 1113 of the device 111 to make the source 1111 and drain 1112 of the device 111 conduct or disconnect. It is worth mentioning that in certain specific application scenarios, the source 1111 and drain 1112 of device 111 may not be fixed. For example, when device 111 is a symmetrical device or a bidirectional device, the source 1111 and drain 1112 of device 111 can be interchanged at any time. That is, at a certain moment, the electrode on the left side of gate 1113 is the source 1111 and the electrode on the right side of gate 1113 is the drain 1112. At another moment, the electrode on the left side of gate 1113 is the drain 1112 and the electrode on the right side of gate 1113 is the source 1111.

[0076] In step S420, a contact layer 12 is formed above the device layer 11; the contact layer 12 includes one or more first conductive portions 121, second conductive portions 122, and a first dielectric layer 124; each first conductive portion 121 is in contact with a source 1111 or a drain 1112; the first dielectric layer 124 covers one or more gates 1113; the second conductive portion 122 is disposed on the first dielectric layer 124 to be separated from the source 1111, drain 1112, and gate 1113.

[0077] Optionally, step S420 includes steps S421-S422.

[0078] Step S421: A first dielectric layer 124 is formed over one or more gates 1113.

[0079] like Figure 7 As shown, the first dielectric layer 124 covers one or more gates 1113 to avoid leakage caused by direct electrical connection between the gates 1113 and the source 1111 and drain 1112 on both sides. Specifically, the first dielectric layer 124 may include multiple first dielectric portions 1241 (1241'), each first dielectric portion 1241 (1241') covering one or more gates 1113 of the device 111. The number of gates 1113 covered by different first dielectric portions 1241 (1241') may be the same or different. It can be understood that the first dielectric layer 124 covering one or more gates 1113 means that the first dielectric layer 124 covers, for example, Figure 1 The gate 1113 is covered along the first direction (X-axis direction) in the cross section shown, but not completely covered in the second direction (Y-axis direction) (e.g., having a conductive via through the first dielectric layer 124), so that the uncovered gate 1113 can form an electrical connection with the corresponding interconnect above, which facilitates the subsequent application of potential to the gate 1113 below through the interconnect.

[0080] Step S422: One or more first conductive parts and second conductive parts are fabricated using a synchronous process.

[0081] like Figure 8 As shown, each first conductive portion 121 is located above a source 1111 or a drain 1112 to directly contact a source 1111 or a drain 1112. The source 1111 or drain 1112 of device 111 is made of semiconductor material, while the electrical connection structure above device layer 11 (such as conductive via 120) is typically made of metal. Optionally, to avoid a large contact resistance when the source 1111 or drain 1112 contacts the electrical connection structure above device layer 11, which would affect electrical transmission performance, in this embodiment, the first conductive portion 121 is made of a specific metal material. By controlling the material of the first conductive portion 121 to form an ohmic contact with the source 1111 or drain 1112, the contact resistance can be reduced.

[0082] The number of second conductive portions 122 is one or more. Each second conductive portion 122 is disposed on the first dielectric layer 124, thereby separating the second conductive portion 122 from the source 1111, drain 1112, and gate 1113. It should be noted that the separation of the second conductive portion 122 from the source 1111, drain 1112, and gate 1113 of the device 111 means that the second conductive portion 122 does not directly contact the source 1111, drain 1112, and gate 1113 of the device 111. In subsequent applications, the second conductive portion 122 can form an electrical connection with the source 1111, drain 1112, or gate 1113 of the device 111 through other structures (such as interconnects, first conductive portions 121, or conductive vias, etc.) when necessary.

[0083] The first conductive portion 121 and the second conductive portion 122 are manufactured using a synchronous process, meaning that the first conductive portion 121 and the second conductive portion 122 are manufactured using the same set of processes, thus allowing for the simultaneous fabrication of both. For example, the first conductive portion 121 and the second conductive portion 122 can be fabricated simultaneously through steps such as deposition, resist coating, exposure, development, etching, and resist removal. It is important to note that the photomask used during exposure must simultaneously contain the areas corresponding to both the first conductive portion 121 and the second conductive portion 122. It can be understood that the first conductive portion 121 and the second conductive portion 122 manufactured using a synchronous process have several identifiable characteristics, such as the same material for both, and the same thickness (i.e., the same material for both). Figure 1 The thickness in the third direction (Z-axis direction) is basically the same. The second conductive part 122 is manufactured using the same process as the first conductive part 121, so there is no need to add additional process steps such as photomask for the fabrication of the second conductive part 122, which can save the wafer fabrication cost of semiconductor structure 1.

[0084] The contact layer 12 further includes a second dielectric layer 125 and one or more conductive vias 120. The first dielectric layer 124 has an undulating surface at the location covering each gate 1113. Step S420 further includes steps S424 and S425.

[0085] Step S424: A second dielectric layer 125 is formed over one or more first conductive portions 121, second conductive portions 122, and first dielectric layer 124.

[0086] In step S425, one or more conductive vias 120 are processed in the second dielectric layer 125; the one or more conductive vias 120 in the second dielectric layer 125 are electrically connected to the second conductive portion 122 and avoid all undulating surfaces.

[0087] In this embodiment, the second dielectric layer 125 covers one or more first conductive portions 121, second conductive portions 122, and the first dielectric layer 124. For example... Figure 9 As shown, multiple through-hole regions can be fabricated in the second dielectric layer 125 first. For example... Figure 10 As shown, conductive material, such as metal, can be deposited in the via region to obtain conductive via 120. It can be understood that there can be multiple conductive vias 120 processed in the second dielectric layer 125, and some of the conductive vias 120 directly contact the second conductive part 122 to form an electrical connection. Figure 10 The diagram shows that the second conductive part 122 is electrically connected to the conductive through hole 120 through direct contact. It should be noted that in some other feasible embodiments, the second conductive part 122 can also be electrically connected to the conductive through hole 120 through the first conductive part 121, depending on the wiring requirements.

[0088] Each conductive via 120 penetrates the second dielectric layer 125, with one end in contact with the first conductive part 121 or the second conductive part 122, and the other end exposed from the surface of the second dielectric layer 125, thereby electrically leading out the first conductive part 121 or the second conductive part 122.

[0089] Since the gate 1113 typically protrudes relative to the planes of the source 1111 and drain 1112, the first dielectric layer 124 has an undulating surface at the location covering the gate 1113. If the undulating surface is not smooth enough, placing the conductive via 120 on the undulating surface will result in poor conductivity. Therefore, in this embodiment, the conductive via 120 avoids the undulating surface, which can improve the quality of the conductive via 120.

[0090] In step S430, an interconnect layer 13 is formed above the contact layer 12. The interconnect layer 13 includes a first interconnect line 1311. The first interconnect line 1311 and the second conductive portion 122 are electrically connected.

[0091] like Figure 2 As shown, in the semiconductor structure finally obtained in step S430, the first interconnect line 1311 is electrically connected to the second conductive part 122 through the conductive via 120.

[0092] It is important to note that there are multiple interconnects in interconnect layer 13. These interconnects are layered, from bottom to top as the first interconnect layer 131, the second interconnect layer, the third interconnect layer, ..., the Nth interconnect layer, where N is an integer greater than or equal to 1. Each interconnect layer includes one or more interconnects, and the first interconnect 1311 can be located in any interconnect layer. It can be understood that the multiple interconnects in each interconnect layer are manufactured using a synchronous process, meaning that the multiple interconnects in each interconnect layer have the same material and approximately the same thickness. Dielectric layers exist between adjacent interconnect layers to achieve electrical isolation between them. Each dielectric layer has one or more conductive vias, which are used to electrically connect two specific interconnects in adjacent interconnect layers. Since different interconnect layers have similar interconnect structures, and different dielectric layers have similar conductive via structures, the main differences lie in the location and size of the interconnects and the location and size of the conductive vias. Therefore, for simplicity and ease of understanding, Figure 2 The example shown is the first interconnect 1311 located in the bottommost first interconnect layer 131 of interconnect layer 13.

[0093] The second conductive portion 122 is electrically connected to at least one of the plurality of interconnects, enabling the second conductive portion 122 to participate in the wiring. Since the second conductive portion 122 is separate from the source 1111, drain 1112, and gate 1113 of the device 111, the second conductive portion 122 can be used as any type of interconnect. For example, the designer can electrically connect one end of the second conductive portion 122 to a specific type of interconnect in the upper interconnect layer 13 according to the wiring requirements, and then connect the other end of the second conductive portion 122 to the structure to be connected. At this time, the second conductive portion 122 acts as that type of interconnect. Specifically, the structure to be connected to the second conductive portion 122 can be the source 1111, gate 1113, or drain 1112 of the device 111. For example, the second conductive portion 122 can be directly electrically connected to the first conductive portion 121 on the source 1111 or drain 1112, in which case the second conductive portion 122 can be regarded as a source interconnect or a drain interconnect; or the second conductive portion 122 can be electrically connected to the gate 1113 through a conductive via penetrating the first dielectric layer 124, in which case the second conductive portion 122 can be regarded as a gate interconnect; the structure to be connected to the second conductive portion 122 can also be a segment of interconnect in the interconnect layer 13. It should be noted that the electrical connection between the second conductive portion 122 and the interconnect can be directly achieved through the conductive via 120, or it can be achieved through the first conductive portion 121 and the conductive via 120. This embodiment can provide an additional wiring scheme by using the second conductive portion 122 located in the contact layer 12 when the wiring structure of the interconnect layer 13 is limited, thereby improving the flexibility of wiring.

[0094] It is understood that whether two adjacent devices 111 share at least one of the gate, source, or drain will not affect the implementation of the first dielectric layer 124 and the first conductive portion 121. Two adjacent devices 111 may share more or fewer gates, sources, or drains. In some possible implementations, two adjacent devices 111 may share both the gate and drain; in some possible implementations, two adjacent devices 111 may share both the gate and source; in some possible implementations, two adjacent devices 111 may not share the gate, source, and drain.

[0095] It is understood that although the second conductive portion 122 can function similarly to an interconnect wire, it differs from an interconnect wire. For example, the second conductive portion 122 is located within the contact layer 12, below the interconnect layer 13 where the interconnect wire is located. Optionally, the first conductive portion 121 and the second conductive portion 122 are fabricated using a synchronous process, such that the second conductive portion 122 and the first conductive portion 121 are located at approximately the same height in the semiconductor structure 1, while the interconnect wires in the interconnect layer 13 are all higher than the first conductive portion 121. Optionally, the projections of the first conductive portion 121 and the second conductive portion 122 along a first direction (X-axis direction) at least partially overlap, so that they are located at approximately the same height in the semiconductor structure 1. For example, the material of the second conductive portion 122 may be different from the material of the interconnect. Optionally, the material of the second conductive portion 122 may be the same as the material of the first conductive portion 121. The material of the first conductive portion 121 satisfies the condition that it can form an ohmic contact with the source 1111 and / or drain 1112 of the device 111, while the material of the interconnect does not need to consider this condition. Therefore, the material of the second conductive portion 122 may be different from the material of the interconnect. Furthermore, the thickness of the second conductive portion 122 may be different from the thickness of the interconnect. Optionally, the thickness of the second conductive portion 122 may be less than the thickness of the interconnect.

[0096] As an optional implementation method, such as Figure 2 As shown, the first conductive portion 121 is located on both sides of the first dielectric layer 124 in the first direction (X-axis direction), that is, the edge of the first conductive portion 121 climbs onto the first dielectric layer 124. This ensures that the fabricated first conductive portion 121 completely covers the source 1111 or drain 1112, avoiding the problem of poor contact between the first conductive portion 121 and the source 1111 or drain 1112. Optionally, the first dielectric layer 124 obtained in step S421 has a multi-segment structure with a gap between adjacent segments to expose a source 1111 or a drain 1112. Subsequently, the first conductive portion 121 is fabricated in the gap in step S422 so that the first conductive portion 121 fills the gap and the edge of the first conductive portion 121 climbs onto the first dielectric layer 124.

[0097] Furthermore, as an optional implementation method, such as Figure 7As shown, the first dielectric layer 124 processed in step S422 includes a first dielectric portion 1241', which continuously covers the gates 1113 of at least two devices 111 along a first direction (X-axis direction); a second conductive portion 122 is disposed on the first dielectric portion 1241' and spans the gates 1113 of at least two devices 111 along the first direction (X-axis direction). Optionally, the number of first dielectric portions 1241' can be one or more, and each first dielectric portion 1241' can have one or more second conductive portions 122. It should be noted that when the first dielectric portion 1241' continuously covers the gates 1113 of at least two devices 111, the first dielectric portion 1241' will necessarily cover the source 1111 and / or drain 1112 between the gates 1113 of at least two devices 111. It can be understood that the first dielectric portion 1241' covering the aforementioned source 1111 and / or drain 1112 means that the first dielectric portion 1241' covers the source 1111 and / or drain 1112 as described above. Figure 7 The cross-section shown covers the aforementioned source 1111 and / or drain 1112 along the first direction (X-axis direction), but does not completely cover the aforementioned source 1111 and / or drain 1112 in the second direction (Y-axis direction). This allows the aforementioned source 1111 and / or drain 1112 to form an electrical connection with the corresponding interconnect in the area not covered by the first dielectric portion 1241' in the second direction (Y-axis direction). In this embodiment, the second conductive portion 122 can cross the gates 1113 of at least two devices 111 through the first dielectric portion 1241' and remain separated from the source 1111, drain 1112, and gate 1113. Therefore, during wiring, two interconnects or the first conductive portion 121 that are far apart can be electrically connected as needed, making the second conductive portion 122 more versatile.

[0098] In some embodiments, step S430 includes forming the first interconnect 1311, the second interconnect 1312, and the third interconnect 1313 over the second dielectric layer 125. For example... Figure 2As shown, the first interconnect layer 131 includes a first interconnect 1311, a second interconnect 1312, and a third interconnect 1313. The first interconnect 1311, second interconnect 1312, and third interconnect 1313 are located on the same layer, with the first interconnect 1311 and second interconnect 1312 located on opposite sides of the third interconnect 1313. Specifically, the first interconnect 1311, second interconnect 1312, and third interconnect 1313 can be fabricated using a synchronous process. In this embodiment, the first interconnect 1311 and second interconnect 1312 are electrically connected to the sources 1111 of different devices 111, therefore, the first interconnect 1311 and second interconnect 1312 are source interconnects. The third interconnect 1313 is used to electrically connect to the gate 1113 of at least one device 111, therefore, the third interconnect 1313 is a gate interconnect. It is understood that in some other feasible embodiments, the first interconnect 1311 and the second interconnect 1312 can be electrically connected to the drain 1112 or the gate 1113 of different devices 111, respectively. That is, the first interconnect 1311 and the second interconnect 1312 can also serve as drain interconnects or gate interconnects. The third interconnect 1313 can be connected to the source 1111 or the drain 1112 of device 111. That is, the third interconnect 1313 can also serve as a source interconnect or a drain interconnect, as long as the types of the first interconnect 1311 and the second interconnect 1312 are different from the type of the third interconnect 1313. Since the first interconnect 1311 and the second interconnect 1312 are different types of interconnects from the third interconnect 1313, the first interconnect 1311 and the second interconnect 1312 need to be electrically isolated from the third interconnect 1313 to maintain different potentials. The second conductive part 122 is located directly below the third interconnect line 1313. One end of the second conductive part 122 extends beyond the third interconnect line 1313 and is electrically connected to the first interconnect line 1311 through the conductive via 120. The other end of the second conductive part 122 extends beyond the third interconnect line 1313 and is electrically connected to the second interconnect line 1312 through the conductive via 120. Therefore, when the first interconnect line 1311 and the second interconnect line 1312 are interrupted by the third interconnect line 1313, the second conductive part 122 can be used to re-establish the electrical connection between the first interconnect line 1311 and the second interconnect line 1312. It can be understood that when one end of each of the first interconnect line 1311 and the second interconnect line 1312 is connected to the upper-layer interconnect line and there is no second conductive part 122 between the first interconnect line 1311 and the second interconnect line 1312, each of the first interconnect line 1311 and the second interconnect line 1312 has only one input terminal that can input current, resulting in poor current uniformity. In this embodiment, the second conductive part 122 can provide a conductive path between the first interconnect 1311 and the second interconnect 1312. This conductive path can connect the first interconnect 1311 and the second interconnect 1312 into a whole, which has two input terminals, thereby improving current uniformity.

[0099] It is understood that when the second conductive part 122 is only used to connect two interconnecting lines, the second conductive part 122 can be separated from the first conductive part 121, and the second conductive part 122 can be directly electrically connected to the interconnecting line through the conductive through hole 120.

[0100] It should be noted that, although Figure 2 In the illustrated embodiment, the two interconnect lines (first interconnect line 1311 and second interconnect line 1312) connected by the second conductive portion 122 are located in the same interconnect layer. However, in other feasible embodiments, the two interconnect lines electrically connected by the second conductive portion 122 may also be located in different interconnect layers. For example, the first interconnect line 1311 is located in the first interconnect layer 131, and the first interconnect line 1311 is connected to the second conductive portion 122 through a conductive via 120; the second interconnect line 1312 is located in the second interconnect layer, and the second interconnect line 1312 is electrically connected to the second conductive portion 122 through two conductive vias 120, one of which is located in the dielectric layer between the second interconnect layer and the first interconnect layer 131, and the other conductive via 120 is located in the second dielectric layer 125 between the first interconnect layer 131 and the contact layer 12.

[0101] In some embodiments, when the preparation method is used to process such as Figure 4 When the semiconductor structure shown is used, step S430 includes: forming a first interconnect 1311, a second interconnect 1312, and a plurality of fourth interconnects 1314 and 1324 above the contact layer 12. The first interconnect 1311 is located at the bottommost first interconnect layer 131 of the interconnect layer 13; each fourth interconnect 1314 and 1324 is electrically isolated from the first interconnect 1311 and the second interconnect 1312; the plurality of fourth interconnects 1314 and 1324 are located around and above the first interconnect 1311 to surround the first interconnect 1311.

[0102] Specifically, a first interconnect layer 131 can be formed above the contact layer 12. The first interconnect layer 131 includes a first interconnect line 1311, a second interconnect line 1312, and a plurality of fourth interconnect lines 1314. The plurality of fourth interconnect lines 1314 are located around the first interconnect line 1311. Then, a third dielectric layer 135 and one or more conductive vias 130 penetrating the third dielectric layer 135 are formed above the first interconnect layer 131. Then, a second interconnect layer 132 is formed above the third dielectric layer 135. The second interconnect layer 132 includes a plurality of fourth interconnect lines 1324 located above the first interconnect line 1311. The plurality of fourth interconnect lines 1314 and 1324 together surround the first interconnect line 1311, and the type of the plurality of fourth interconnect lines 1314 and 1324 is different from the type of the first interconnect line 1311. It can be understood that the types of the plurality of fourth interconnect lines 1314 and 1324 can be the same or different from each other. Figure 4 As shown, portions of the fourth interconnect 1314 and 1324 can be connected via a conductive via 130 to serve as interconnects of the same type. It is worth noting that the fourth interconnects 1314 and 1324 can also be other types of interconnects besides gate, source, and drain interconnects. For example, a fourth interconnect 1324 located directly above the first interconnect 1311 can be electrically connected to the substrate of the semiconductor structure to control the substrate potential, thus preventing the fourth interconnect 1324 from being electrically connected to the gate, source, or drain.

[0103] It is understood that in the prior art, when a certain area in the first interconnect layer of the interconnect layer is surrounded by one or more types of interconnects on its periphery and above, other different types of interconnects cannot be arranged in that area (because the paths leading upwards or outwards from that area are blocked, and since that area is at the bottom layer, there are no paths leading out below it). Consequently, the corresponding devices cannot be arranged in the device layer below that area. In this embodiment, a first interconnect 1311 can be arranged in that area, and the first interconnect 1311 can be led out through the second conductive part 122. After the first interconnect 1311 is led out, it can be electrically connected to the second interconnect 1312, thereby enabling the arrangement of the corresponding devices below the area where the first interconnect 1311 is located. The flexible wiring method provided by this embodiment reduces the areas in the semiconductor structure that cannot be wired, can increase the number of devices, increase the effective area of ​​the devices and the overall gate width, and improve the area utilization rate.

[0104] As an optional implementation, the plurality of devices 111 in device layer 11 include gallium nitride (GaN) devices 111. Specifically, the GaN devices 111 can be gallium nitride high electron mobility transistors (GaN HEMTs). GaN HEMTs have high operating frequencies and can be used in high-frequency electronic devices, such as power amplifiers for wireless communication devices like 5G, Wi-Fi, and Bluetooth; high-efficiency switching power supplies; DC-DC converters; inverters; charging equipment and on-board chargers for electric vehicles; server power supplies and cooling equipment for data centers; high-brightness LED drivers; motor drives and frequency converters; high-power amplifiers for radar and communication systems; high-voltage inverters; and power quality improvement equipment. These technologies can improve power conversion efficiency, reduce energy consumption, miniaturize devices, and extend their lifespan. Accordingly, the material used to form the first conductive portion 121 of the ohmic contact can be at least one of Ti, Al, or TiN.

[0105] The semiconductor structure and its preparation method provided by the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and embodiments of this application. The above description of the embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in specific embodiments and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: a device layer comprising one or more devices; each device includes a source, a drain, and a gate; A contact layer, located above the device layer, includes a first dielectric layer, one or more first conductive portions and a second conductive portion; each first conductive portion contacts one of the source electrodes or one of the drain electrodes; the first dielectric layer covers one or more of the gate electrodes; the second conductive portion is disposed on the first dielectric layer to be separate from the source electrodes, drain electrodes and gate electrodes. An interconnect layer, located above the contact layer, includes a first interconnect line; The second conductive portion is electrically connected between the first interconnect and one or more of the first conductive portions, and the second conductive portion is directly electrically connected to the one or more of the first conductive portions; or The interconnect layer includes a second interconnect line, and the second conductive portion is electrically connected between the first interconnect line and the second interconnect line; or The second conductive portion is electrically connected between the first interconnect and one or more of the gates.

2. The semiconductor structure as described in claim 1, characterized in that, The one or more first conductive parts and the second conductive parts are manufactured using a synchronous process.

3. The semiconductor structure according to any one of claims 1-2, characterized in that, The projections of the first conductive portion and the second conductive portion along the length direction at least partially overlap.

4. The semiconductor structure according to any one of claims 1-3, characterized in that, The first dielectric layer includes a first dielectric portion, which continuously covers at least two of the gates; The second conductive portion is disposed on the first dielectric portion and spans the at least two gates.

5. The semiconductor structure according to any one of claims 1-4, characterized in that, The first dielectric layer has an undulating surface at the location where it covers each of the gates; The first interconnect and the second conductive portion are electrically connected through one or more conductive vias; The one or more conductive vias avoid all the undulating surfaces.

6. The semiconductor structure as described in claim 3, characterized in that, The second conductive portion is separated from the one or more first conductive portions; The first interconnect and the second conductive portion are electrically connected through one or more conductive vias; The second interconnect and the second conductive portion are electrically connected through one or more conductive vias.

7. The semiconductor structure according to any one of claims 3-6, characterized in that, The interconnect layer also includes a third interconnect line; The interconnect lines in the interconnect layer are arranged in layers; the first interconnect line, the second interconnect line, and the third interconnect line are located in the same layer; The first interconnect and the second interconnect are located on both sides of the third interconnect and are electrically isolated from the third interconnect; The second conductive portion is located directly below the third interconnect line.

8. The semiconductor structure according to any one of claims 3-6, characterized in that, The interconnect lines in the interconnect layer are arranged in layers; The first interconnect is located in the first layer, which is the lowest layer of the interconnect layer; The interconnect layer further includes a plurality of fourth interconnects; each of the fourth interconnects is electrically isolated from the first interconnect and the second interconnect; The plurality of fourth interconnects are located around and above the first interconnect to surround the first interconnect.

9. The semiconductor structure according to any one of claims 1-8, characterized in that, The plurality of devices include GaN devices.

10. A method for fabricating a semiconductor structure, characterized in that, The method includes: A device layer comprising one or more devices is obtained; each device includes a source, a drain, and a gate; A contact layer is formed above the device layer. The contact layer includes a first dielectric layer, one or more first conductive portions, and a second conductive portion. Each first conductive portion contacts one of the source electrodes or one of the drain electrodes. The first dielectric layer covers the one or more gate electrodes. The second conductive portion is disposed on the first dielectric layer to be separate from the source electrode, drain electrode, and gate electrode. An interconnect layer is formed above the contact layer, the interconnect layer including a first interconnect line; The second conductive portion is electrically connected between the first interconnect and one or more of the first conductive portions, and the second conductive portion is directly electrically connected to the one or more of the first conductive portions; or The interconnect layer includes a second interconnect line, and the second conductive portion is electrically connected between the first interconnect line and the second interconnect line; or The second conductive portion is electrically connected between the first interconnect and one or more of the gates.

11. The method for preparing a semiconductor structure as described in claim 10, characterized in that, The formation of a contact layer above the device layer includes: A first dielectric layer is formed over one or more of the gates; The one or more first conductive parts and the second conductive parts are manufactured using a synchronous process.

12. The method for fabricating a semiconductor structure as described in claim 10 or 11, characterized in that, The projections of the first conductive portion and the second conductive portion along the length direction at least partially overlap.

13. The method for preparing a semiconductor structure according to any one of claims 10-12, characterized in that, The first dielectric layer includes a first dielectric portion, which continuously covers at least two of the gates; The second conductive portion is disposed on the first dielectric portion and spans the at least two gates.

14. The method for preparing a semiconductor structure according to any one of claims 10-13, characterized in that, The contact layer further includes a second dielectric layer and one or more conductive vias; The first dielectric layer has an undulating surface at the location where it covers each of the gates; The formation of a contact layer above the device layer includes: A second dielectric layer is formed over the one or more first conductive portions, the second conductive portions, and the first dielectric layer; One or more conductive vias are fabricated in the second dielectric layer; the one or more conductive vias in the second dielectric layer are electrically connected to the second conductive portion and avoid all the undulating surfaces; The first interconnect is electrically connected to one or more of the conductive vias.

15. The method for preparing a semiconductor structure as described in claim 12, characterized in that, The second conductive portion is separated from the one or more first conductive portions; The first interconnect and the second conductive portion are electrically connected through one or more conductive vias; The second interconnect and the second conductive portion are electrically connected through one or more conductive vias.

16. The method for preparing a semiconductor structure according to any one of claims 12-15, characterized in that, The interconnect lines in the interconnect layer are arranged in layers; The formation of an interconnect layer above the contact layer includes: The first interconnect, the second interconnect, and the third interconnect are formed above the contact layer; The first interconnect, the second interconnect, and the third interconnect are located on the same layer; the first interconnect and the second interconnect are located on both sides of the third interconnect and are electrically isolated from the third interconnect; the second conductive part is located directly below the third interconnect.

17. The method for preparing a semiconductor structure according to any one of claims 12-15, characterized in that, The interconnect lines in the interconnect layer are arranged in layers; The formation of an interconnect layer above the contact layer includes: A first interconnect, a second interconnect, and a plurality of fourth interconnects are formed above the contact layer; the first interconnect is located in the first layer at the bottom of the interconnect layer; each of the fourth interconnects is electrically isolated from the first interconnect and the second interconnect; the plurality of fourth interconnects are located around and above the first interconnect to surround the first interconnect.

18. The method for preparing a semiconductor structure according to any one of claims 10-17, characterized in that, The plurality of devices include GaN devices.

19. An electronic device, characterized in that, The electronic device includes: The semiconductor structure as described in any one of claims 1-9, or the semiconductor structure obtained by the method for preparing the semiconductor structure as described in any one of claims 10-18.

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