Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. Disclosed is a semiconductor device including: a bit line extending in a first direction; a first gate extending in a second direction perpendicular to the first direction; a second gate extending parallel to the first gate; an active region including a vertical portion between the first gate and the second gate and a horizontal portion in contact with the bit line and the vertical portion; and a first gate insulating layer disposed between the first gate and the vertical portion. The first gate insulating layer includes a lower gate insulating layer in contact with the first gate and an upper gate insulating layer in contact with the vertical portion. The upper gate insulating layer has a higher dielectric constant than the lower gate insulating layer.

Description

Semiconductor devices and their manufacturing methods

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0152857, filed on October 31, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor device, and more specifically, to a semiconductor device including a memory cell. Background Technology

[0004] As the compactness and integration of semiconductor devices become major issues, memory cells in semiconductor devices can be formed with three-dimensional patterns. Compact memory cells with three-dimensional patterns can include components for improving the operating characteristics of the memory cells. Summary of the Invention

[0005] This disclosure aims to address the aforementioned problems in the prior art while maintaining the advantages achieved by the prior art.

[0006] One aspect of this disclosure provides a semiconductor device with improved integration.

[0007] Another aspect of this disclosure provides a semiconductor device with improved leakage current characteristics.

[0008] The technical problems to be solved by this disclosure are not limited to those described above, and any other technical problems not mentioned herein will be clearly understood by those skilled in the art from the following description.

[0009] According to one aspect of this disclosure, a semiconductor device includes: a bit line extending along a first direction; a first gate extending along a second direction perpendicular to the first direction; a second gate extending parallel to the first gate; an active region including a vertical portion located between the first gate and the second gate and a horizontal portion contacting the bit line and the vertical portion; and a first gate insulating layer disposed between the first gate and the vertical portion. The first gate insulating layer includes a lower gate insulating layer contacting the first gate and an upper gate insulating layer contacting the vertical portion. The dielectric constant of the upper gate insulating layer is higher than that of the lower gate insulating layer.

[0010] According to one embodiment, the semiconductor device may further include a second gate insulating layer disposed between the second gate and the active region.

[0011] According to one embodiment, the active region may include an indium gallium zinc oxide semiconductor and may have a channel region formed therein.

[0012] According to one embodiment, the semiconductor device may further include a first contact region located on opposite sides of the vertical portion and a second contact region overlapping the first contact region.

[0013] According to one embodiment, the first contact region may contain the same material as the active region, and the second contact region may contain at least one of a metal, a metal silicide, or a metal nitride.

[0014] According to one embodiment, the semiconductor device may further include a capacitor that overlaps with the second contact area.

[0015] According to one embodiment, the first gate may be configured to receive a control signal different from the control signal provided to the second gate.

[0016] According to one embodiment, the lower gate insulating layer may comprise silicon oxide, and the upper gate insulating layer may comprise at least one of hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanium oxide.

[0017] According to another aspect of this disclosure, a semiconductor device includes: a bit line extending along a first direction; a first gate extending along a second direction perpendicular to the first direction; a pair of second gates located on both sides of the first gate and extending parallel to the first gate; an active region including a vertical portion located between one of the paired second gates and the first gate; a horizontal portion contacting one side of the vertical portion and extending along the first direction; and a first gate insulating layer disposed between the first gate and the active region. The first gate insulating layer includes a lower gate insulating layer in contact with the first gate and an upper gate insulating layer in contact with the vertical portion. The dielectric constant of the upper gate insulating layer is higher than that of the lower gate insulating layer.

[0018] According to another embodiment, the bit line may contact the horizontal portion.

[0019] According to another embodiment, the semiconductor device may further include a second gate insulating layer disposed between the second gate and the active region.

[0020] According to another embodiment, the active region may include an amorphous indium gallium zinc oxide semiconductor.

[0021] According to another embodiment, the semiconductor device may further include a first contact region located on opposite sides of the vertical portion and a second contact region overlapping the first contact region.

[0022] According to another embodiment, the first contact region may contain the same material as the active region, and the second contact region may contain at least one of a metal, a metal silicide, or a metal nitride.

[0023] According to another embodiment, the semiconductor device may further include a capacitor that overlaps with the second contact area.

[0024] According to another embodiment, the lower gate insulating layer may comprise silicon oxide, and the upper gate insulating layer may comprise at least one of hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanium oxide.

[0025] According to another aspect of this disclosure, a method of manufacturing a semiconductor device includes: forming a bit line extending along a first direction in a substrate; forming a first gate extending along a second direction perpendicular to the first direction on the bit line; forming a first gate insulating layer in contact with the first gate; forming an active region including a vertical portion and a horizontal portion, the vertical portion extending along a sidewall of the first gate insulating layer and the horizontal portion in contact with the bit line; forming a second gate insulating layer in contact with the active region; and forming a second gate in contact with the second gate insulating layer. Forming the first gate insulating layer includes: forming a lower gate insulating layer in contact with the first gate; and forming an upper gate insulating layer located on the lower gate insulating layer. The dielectric constant of the upper gate insulating layer is higher than that of the lower gate insulating layer.

[0026] According to another embodiment, the active region may include an amorphous indium gallium zinc oxide semiconductor.

[0027] According to another embodiment, the lower gate insulating layer may comprise silicon oxide, and the upper gate insulating layer may comprise at least one of hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanium oxide. Attached Figure Description

[0028] The above and other objects, features and advantages of this disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings:

[0029] Figure 1 is a schematic perspective view of a semiconductor device according to an embodiment of the present disclosure;

[0030] Figure 2A is a cross-sectional view obtained by cutting the center of the first gate along a cutting line parallel to the second direction according to an embodiment of the present disclosure.

[0031] Figure 2B is a cross-sectional view obtained by cutting the center of the second gate along a cutting line parallel to the second direction according to an embodiment of the present disclosure.

[0032] Figure 2C is a cross-sectional view obtained by cutting the center of the bit line along a cutting line parallel to a first direction according to an embodiment of the present disclosure.

[0033] Figures 3A to 3C are diagrams illustrating a method for forming bit lines included in a semiconductor device according to an embodiment of the present disclosure;

[0034] Figures 4A to 4C are diagrams illustrating a method for forming a first gate included in a semiconductor device according to an embodiment of the present disclosure.

[0035] Figures 5A to 5C and 6A to 6C are diagrams for explaining a method of forming a lower gate insulating layer included in a semiconductor device according to an embodiment of the present disclosure;

[0036] Figures 7A to 7C and Figures 8A to 8C are diagrams for explaining a method of forming an upper gate insulating layer included in a semiconductor device according to an embodiment of the present disclosure;

[0037] Figures 9A to 9C are diagrams illustrating a method for forming an active region included in a semiconductor device according to an embodiment of the present disclosure;

[0038] Figures 10A to 10C are diagrams illustrating a method for forming a second gate insulating layer included in a semiconductor device according to an embodiment of the present disclosure.

[0039] Figures 11A to 11C are diagrams illustrating a method for forming a second gate included in a semiconductor device according to an embodiment of the present disclosure; and

[0040] Figures 12A to 12C and 13A to 13C are diagrams illustrating a method of forming a capacitor included in a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0041] Various embodiments of the present disclosure will now be described with reference to the accompanying drawings. The above and other aspects, features, and advantages of the present disclosure will become clearer from the following description of embodiments given in conjunction with the accompanying drawings. However, this is not intended to limit the present disclosure to the specific embodiments.

[0042] This disclosure is not limited to the embodiments disclosed herein and can be implemented in various different forms. Those skilled in the art to which this disclosure pertains will understand that various modifications, equivalents, and / or substitutions can be made to the various embodiments disclosed herein without departing from the scope and spirit of this disclosure.

[0043] When adding reference numerals to components in each figure, it should be noted that the same reference numerals should be used to represent the same components even if they are shown in other figures.

[0044] In describing embodiments of this disclosure, detailed descriptions of well-known features or functions will be excluded so as not to unnecessarily obscure the essential points of this disclosure.

[0045] As used herein, the singular form includes the plural form unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including” as used in this specification specify the presence of the said components, steps, operations, and / or elements, but do not exclude the presence or addition of one or more other components, steps, operations, and / or elements.

[0046] The semiconductor device and its manufacturing method according to embodiments of the present disclosure will now be described with reference to the accompanying drawings.

[0047] Figure 1 is a schematic perspective view of a semiconductor device according to an embodiment of the present disclosure.

[0048] Referring to Figure 1, the semiconductor device may include a substrate LS and a memory cell array MCA formed on the substrate LS. The memory cell array MCA may include a plurality of memory cells MC arranged repeatedly on the substrate LS.

[0049] According to one embodiment, each storage cell (MC) may have a three-dimensional structure.

[0050] More specifically, each memory cell MC included in the memory cell array MCA may include a bit line BL, a transistor TR, and a capacitor CAP.

[0051] Bit lines BL can be located inside the substrate LS and extend along a first direction D1 parallel to one surface of the substrate LS. Adjacent bit lines BL can be separated from each other by a bit line separation layer (not shown).

[0052] Bit line separation layers may include, for example, silicon oxide, silicon nitride, or combinations thereof.

[0053] Capacitors CAP can be spaced apart from bit line BL on third-direction D3. Capacitors CAP can be arranged in a matrix or tilted relative to the regions of gates G1 and G2 that overlap with bit line BL.

[0054] The capacitor CAP can be configured to overlap with the central portion of the first contact area CT1 and the second contact area CT2, which are in contact with one side of the active area ACT.

[0055] The first contact area CT1 and the second contact area CT2 can constitute a contact area CT.

[0056] The transistor TR can be located between the capacitor CAP and the bit line BL.

[0057] The transistor TR may include at least a portion of an active region ACT connected to the bit line BL, and may include a first gate G1 and a second gate G2. Furthermore, the transistor TR may include a first gate insulating layer GD1 located between the first gate G1 and a vertical portion of its adjacent active region ACT, and a second gate insulating layer GD2 located between the second gate G2 and a vertical portion of its adjacent active region ACT. According to one embodiment, the first gate insulating layer GD1 may include a plurality of insulating layers with different dielectric constants. For example, the first gate insulating layer GD1 may include a lower gate insulating layer GDL in contact with the first gate G1 and an upper gate insulating layer GDH in contact with the active region ACT.

[0058] According to one embodiment, the lower gate insulating layer (GDL) may comprise silicon oxide. The dielectric constant of the silicon oxide may be about 3.9.

[0059] The upper gate insulating layer (GDH) may contain a high-k material with a dielectric constant of 4 or higher. For example, the dielectric constant of the high-k material may be about 20 or higher.

[0060] High-k materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). In another embodiment, the upper gate insulating layer GDH may be formed of a composite layer comprising two or more layers of the above-mentioned high-k materials.

[0061] According to the embodiment of FIG1, a word line drive voltage can be provided to a second gate G2 extending along the second direction D2. In other words, the second gate G2 can operate as a word line of transistor TR.

[0062] In this configuration, a voltage different from the voltage supplied to the second gate G2 can be supplied to the first gate G1, which extends to face the second gate G2 to block interference between the gates G2 of adjacent transistors TR. For example, ground voltage can be supplied to the first gate G1, which can then operate as a back gate.

[0063] The first direction D1 can be a direction perpendicular to the second direction D2, and the third direction D3 can be a direction perpendicular to the first direction D1 and the second direction D2.

[0064] Each memory cell MC may include an active region ACT located between a capacitor CAP and a bit line BL. The active region ACT may include a first contact region CT1 located on one side of the vertical portion, and a second contact region CT2 disposed on the first contact region CT1.

[0065] The capacitor CAP can contact the active region ACT through the second contact area CT2 and the first contact area CT1.

[0066] The active region ACT can include the channel region and source / drain regions of the transistor TR. In other words, the active region ACT can be the region that forms the channel when the transistor TR is operating, and it can be a region that includes both source and drain regions.

[0067] Based on the voltage applied to the second gate G2 of the transistor TR, a channel region can be formed in the active region ACT, and electrons can move between the source and drain regions through the formed channel region.

[0068] The active region ACT may include a horizontal portion extending along a first direction D1 and a vertical portion extending along a third direction D3.

[0069] Each memory cell (MC) may include a transistor (TR).

[0070] Two adjacent vertical portions of the active region ACT can be connected by a horizontal portion. The horizontal portion of the active region ACT can be connected to the bit line BL.

[0071] The active region ACT can be electrically isolated from the gates G1 and G2 through insulating layers GD1 and GD2.

[0072] The memory cell array (MCA) may include a dynamic random access memory (DRAM) array. In another embodiment, the memory cell array (MCA) may include a phase-change RAM (PCRAM), paraelectric random access memory (PERAM), or magnetoresistive random access memory (MRAM) array.

[0073] Depending on the type of memory cell array (MCA), the capacitor (CAP) can be replaced by different memory elements.

[0074] The substrate LS can be a material suitable for semiconductor processing.

[0075] The substrate LS may include a semiconductor substrate. The substrate LS may be formed of a silicon-containing semiconductor material. The substrate LS may include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, or multiples thereof.

[0076] The substrate LS can contain different semiconductor materials, such as germanium. The substrate LS can contain group III / V semiconductor substrates, such as compound semiconductor substrates like GaAs.

[0077] The substrate LS may include a silicon-on-insulator (SOI) substrate. In another embodiment, the substrate LS may include a peripheral circuitry region (not shown) in its lower portion. The peripheral circuitry region may include multiple control circuits for controlling the memory cell array (MCA). At least one control circuit in the peripheral circuitry region may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit in the peripheral circuitry region may include address decoding circuitry, read circuitry, and write circuitry.

[0078] Bit line BL can be referred to as lateral orientation bit line or lateral extension bit line.

[0079] Bit lines BL may contain conductive materials. Bit lines BL may contain silicon-based materials, metal-based materials, or combinations thereof. Bit lines BL may contain polysilicon, metals, metal nitrides, metal silicides, or combinations thereof.

[0080] Bit line BL may comprise polycrystalline silicon, titanium nitride, tungsten (W), or combinations thereof. For example, bit line BL may comprise polycrystalline silicon or titanium nitride (TiN) doped with N-type impurities.

[0081] Bit lines BL may contain a stack of titanium nitride (TiN) and tungsten (W) (TiN / W). Bit lines BL may also contain ohmic contacts, such as metal silicides.

[0082] Memory cells MC arranged horizontally along the first direction D1 can share a single bit line BL. Bit line separation layers extending along the first direction D1 can be provided between adjacent bit lines BL. The bit line separation layers can be composed of multiple layers and can be used as spacers to separate adjacent bit lines BL from each other.

[0083] Gates G1 and G2 may comprise metal, metal mixture, metal alloy, titanium nitride, tungsten, polysilicon, or combinations thereof.

[0084] For example, gates G1 and G2 may contain a TiN / W stack in which titanium nitride and tungsten are stacked sequentially.

[0085] Gates G1, G2, and bit lines BL may extend in directions that intersect each other. The active region ACT may contain semiconductor material or oxide semiconductor material.

[0086] Bit line BL can be electrically isolated from gates G1 and G2 through a bit line separation layer. In other words, the bit line separation layer can be located between bit line BL and gates G1 and G2.

[0087] The active region ACT can include multiple impurity regions. Impurity regions can include the source / drain regions of the transistor TR.

[0088] The active region ACT may include doped polycrystalline silicon, undoped polycrystalline silicon, amorphous silicon, amorphous indium gallium zinc oxide (IGZO) semiconductor, indium zinc oxide (IZO), indium tin oxide (ITO), and indium oxide (InO3).

[0089] The horizontal portion of the active region ACT can be electrically connected to the bit line BL. Furthermore, the first contact area CT1 can contact the vertical portion of the active region ACT, and the capacitor CAP can be electrically connected to the active region ACT through the first contact area CT1 and the second contact area CT2.

[0090] The active region ACT can be electrically isolated from the gates G1 and G2 through gate insulating layers GD1 and GD2. In other words, gate insulating layers GD1 and GD2 can be disposed between the active region ACT and the gates G1 and G2 to prevent the active region ACT from being electrically connected to the gates G1 and G2.

[0091] In addition, an additional insulating layer (not shown) may be disposed between the second gates G2, and the second gates G2 may be electrically isolated from each other through the additional insulating layer (not shown).

[0092] The insulating layer may have different compositions depending on its location. For example, the insulating layer located between the second gates G2 may contain silicon oxide or silicon nitride, while the first gate insulating layer GD1 located between the gates G1 and G2 and the active region ACT may contain a high-k material.

[0093] The second gate insulating layer GD2 located between the second gate G2 and the active region ACT may contain silicon oxide or silicon nitride.

[0094] The capacitor CAP may have a shape extending vertically from one surface of the substrate LS and may be configured to contact the vertical portion included in the active region ACT. The capacitor CAP may, for example, include a capacitor having a metal-insulator-metal (MIM) structure.

[0095] The capacitor CAP can have a three-dimensional structure. A capacitor CAP with a three-dimensional structure can be repeatedly arranged in a matrix relative to a surface of the substrate LS. This three-dimensional structure can be, for example, cylindrical, columnar, or cylindrical-column shaped. Here, cylindrical-column shaped can refer to a structure combining columnar and cylindrical shapes.

[0096] According to another embodiment, the capacitor CAP may have a structure in which a second contact region CT2 is arranged at an angle relative to the region where the bit line BL overlaps with the gates G1 and G2, such that the maximum number of capacitors can be provided in the same area.

[0097] Each memory cell MC may share a first gate G1 and a second gate G2. The first gate G1 and the second gate G2 may contain the same conductive material.

[0098] Figure 2A is a cross-sectional view obtained by cutting the center of the first gate along a cutting line (line A-A' in Figure 1) parallel to the second direction according to an embodiment of the present disclosure.

[0099] Figure 2B is a cross-sectional view obtained by cutting the center of the second gate along a cutting line (line B-B' in Figure 1) parallel to the second direction according to an embodiment of the present disclosure.

[0100] Figure 2C is a cross-sectional view obtained by cutting the center of the cutting line along a cutting line (line C-C' in Figure 1) parallel to a first direction according to an embodiment of the present disclosure.

[0101] Referring to Figures 2A, 2B and 2C, a substrate layer 110, a silicide layer 120 formed on the substrate layer 110 and a first nitride layer 130 located on the silicide layer 120 are shown.

[0102] The substrate 110 may contain a silicon semiconductor material, such as silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, or carbon-doped silicon.

[0103] The substrate 110 may include multiple control circuits for controlling the operation of semiconductor devices, and the area where the control circuits are provided may be referred to as the peripheral circuit area.

[0104] The silicide layer 120 located on the substrate 110 may contain a metal silicide material, such as cobalt silicide (CoSi). The silicide layer 120 reduces the operating resistance of the semiconductor device. Furthermore, the silicide layer 120 also serves as a protective layer for the substrate 110, preventing damage to the substrate 110 during semiconductor manufacturing processes.

[0105] The first nitride layer 130 located on the silicide layer 120 may be a layer containing silicon nitride. Since the first nitride layer 130 contains silicon nitride, it can prevent damage to the substrate layer 110 during high-temperature semiconductor manufacturing processes.

[0106] The first oxide layer 140 may be disposed on the first nitride layer 130. The first oxide layer 140 may be a layer containing silicon oxide.

[0107] Because a first nitride layer 130 and a first oxide layer 140 are provided, the control circuitry included in the substrate layer 110 can be electrically isolated from the bit line 150.

[0108] Bit lines 150 disposed on the first oxide layer 140 may include a plurality of layers extending along a first direction D1. For example, bit lines 150 may include: a first bit line layer 152 comprising titanium nitride (TiN); a second bit line layer 154 comprising tungsten (W); and a third bit line layer 156 comprising titanium nitride (TiN).

[0109] The resistance of bit line 150 can be adjusted by adjusting the material of the multiple layers included in bit line 150.

[0110] When the second bit line layer 154 is exposed to oxygen, tungsten (W) may be oxidized, leading to disconnections and defects. The first bit line layer 152 and the third bit line layer 156 included in bit line 150 prevent the second bit line layer 154 from being oxidized by oxygen exposure.

[0111] Furthermore, since the titanium nitride (TiN) included in the first bit line layer 152 has higher adhesion to silicon oxide than tungsten (W), the first bit line layer 152 provided between the first oxide layer 140 and the second bit line layer 154 can improve the interface stability of the bit line 150.

[0112] Bit line 150 can be formed by depositing multiple layers and then performing an etching process using a mask.

[0113] Referring to Figures 2A and 2B, a second bit line separation layer 170 and a third bit line separation layer 180 may be provided between adjacent bit lines 150. According to one embodiment, the second bit line separation layer 170 may comprise silicon nitride, and the third bit line separation layer 180 may comprise silicon oxide.

[0114] Bit line 150 and first gate 190 can be separated from each other by first bit line separation layer 160.

[0115] The second bit line separation layer 170 and the third bit line separation layer 180 can be used as spacers to electrically isolate adjacent bit lines 150.

[0116] A first bit isolation layer 160 may be disposed on each bit line 150 to electrically isolate the bit line 150 from the first gate 190. The first bit isolation layer 160 may comprise carbon-containing silicon oxide (SiCO).

[0117] According to Figures 2B and 2C, the active region 240 may be disposed on the bit line 150 to be electrically connected to at least a portion of the bit line 150. The active region 240 may be electrically isolated from the second gate 260 through the second gate insulating layer 250.

[0118] The first gate 190 and the second gate 260 may each comprise a metal, a metal mixture, a metal alloy, polysilicon, or a combination thereof. For example, the first gate 190 and the second gate 260 may comprise titanium nitride.

[0119] Referring to Figure 2C, a first gate insulating layer 220 may be provided along the sidewall of the first gate 190.

[0120] According to one embodiment, the first gate insulating layer 220 may include a plurality of insulating layers with different dielectric constants.

[0121] For example, the first gate insulating layer 220 may include a lower gate insulating layer 222 that contacts the sidewall of the first gate 190 and the first line separation layer 160, and an upper gate insulating layer 224 that is located on the lower gate insulating layer 222 and contacts the lower gate insulating layer 222 and the active region 240.

[0122] The lower gate insulating layer 222 may include silicon oxide (SiO2) having, for example, a dielectric constant of about 3.9.

[0123] The upper gate insulating layer 224 may comprise, for example, a high-k material with a dielectric constant of 4 or higher. According to one embodiment, the dielectric constant of the upper gate insulating layer 224 may be about 20 or higher, and may comprise hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). In another embodiment, the upper gate insulating layer 224 may be formed of a composite layer comprising two or more layers of the aforementioned high-k materials.

[0124] Since the first gate insulating layer 220 includes the upper gate insulating layer 224, the leakage current characteristics of the first gate insulating layer 220 can be improved.

[0125] Furthermore, in the semiconductor device according to embodiments of this disclosure, the upper gate insulating layer 224 is formed before the active region 240 is formed. Therefore, the active region 240 is not damaged during the high-temperature process of forming the upper gate insulating layer 224.

[0126] According to one embodiment, a second nitride layer 200 may be disposed on the first gate 190.

[0127] A third nitride layer 270 may be disposed between adjacent second gates 260, and a second oxide layer 280 may be formed on the third nitride layer 270.

[0128] The first contact region 310 disposed on the active region 240 may contain the same oxide semiconductor material as the active region 240.

[0129] The first contact area 310 may be formed in a groove formed in the contact insulation layer 300.

[0130] The second contact region 330, which overlaps with the upper part of the first contact region 310, may contain metal, metal silicide, or metal nitride. The second contact region 330 may be a region formed to reduce the contact resistance between the first contact region 310 and the storage element 340.

[0131] The second contact area 330 may be a region formed in the insulating layer 320 of the storage element. The second contact area 330 and the storage element 340 may be formed by etching at least a portion of the insulating layer 320 of the storage element.

[0132] The active region 240 may include a horizontal portion that contacts the bit line 150 and a vertical portion that extends in a vertical direction (direction D3) between the first gate 190 and the second gate 260.

[0133] The active region 240 may contain, for example, an oxide semiconductor material, which may include indium gallium zinc oxide (IGZO).

[0134] According to another embodiment, the active region ACT may include doped polysilicon, undoped polysilicon, amorphous silicon, indium zinc oxide (IZO), indium tin oxide (ITO), and indium oxide (InO3).

[0135] Because IGZO has low leakage current characteristics, semiconductor devices with low standby power can be realized by forming the active region 240 with IGZO.

[0136] Furthermore, since the active region 240 contains IGZO, the process difficulty of forming a three-dimensional semiconductor can be reduced, and an active region with a three-dimensional structure including horizontal and vertical portions can be easily formed.

[0137] The first contact area 310 may overlap with the upper part of the upper gate insulating layer 224. The upper gate insulating layer 224 can prevent leakage current generated in the first contact area 310.

[0138] The width of the first contact area 310 may be greater than the width of the vertical portion of the active area 240 in the first direction (direction D1). The width of the first contact area 310 may be the same as the width of the second contact area 330.

[0139] Since the width of the first contact area 310 is greater than the width of the vertical portion of the active area 240, the contact area between the second contact area 330 and the first contact area 310 can be guaranteed, and the contact stability between the second contact area 330 and the first contact area 310 can be guaranteed.

[0140] The second contact area 330 may contain metal, metal silicide, or metal nitride. The storage element 340 located on the second contact area 330 may be configured to at least partially overlap with the second contact area 330.

[0141] The contact insulation layer 300 may be provided in the form of surrounding the first contact area 310. In other words, the contact insulation layer 300 may be disposed between adjacent first contact areas 310.

[0142] The layer in which the storage element 340 is set can be called the storage element layer.

[0143] The storage element layer may include at least a portion of the second contact area 330. Furthermore, the storage element layer may include storage elements 340 that overlap the upper portion of the second contact area 330, and may include storage element insulating layers 320 located between storage elements 340 and between the second contact areas 330.

[0144] Each storage element 340 can be used as a data storage device for writing or reading data according to control signals applied to the semiconductor device.

[0145] Each storage element 340 may include a capacitor dielectric film and storage electrodes. Based on control signals provided to the first gate 190 and the second gate 260, it can be determined whether a voltage is supplied to the storage element 340 and the magnitude of the voltage supplied to the storage element 340. The semiconductor device can read stored data based on signals corresponding to the voltage of the storage element 340.

[0146] The memory element 340 may have a shape extending in a vertical direction (third direction D3) relative to the substrate layer 110 within the memory element layer. More specifically, the memory element 340 may have a cylindrical or cylindrical shape. Because the memory element 340 has a cylindrical or cylindrical shape, the number of memory elements 340 disposed within the same area can be increased. When the number of memory elements 340 disposed within the same area increases, the data storage capacity of the semiconductor device can be increased.

[0147] Each storage element 340 may correspond to a second contact area 330, and a second contact area 330 may contact a storage element 340.

[0148] In a semiconductor device according to an embodiment of the present disclosure, during data read / write timing, a ground voltage and a word line drive voltage can be provided to a first gate 190 and a second gate 260, respectively. When a ground voltage is provided to the first gate 190, the first gate 190 can be provided with a reverse bias within the semiconductor device.

[0149] The first gate 190 may be located between two adjacent second gates 260. Since a ground voltage is provided to the first gate 190, the adjacent second gates 260 may be electrically isolated from each other.

[0150] When adjacent second gates 260 are electrically isolated from each other, this means that electrical interference between adjacent second gates 260 is blocked.

[0151] As semiconductor devices become more compact, the distance between the second gates 260 can be reduced. When the distance between the second gates 260 decreases, the word line drive voltage supplied to each second gate 260 may cause coupling between adjacent second gates 260. This coupling can lead to errors in data read / write operations of the semiconductor device.

[0152] According to embodiments of this disclosure, by providing a first gate 190 between the second gates 260 and providing a ground voltage to the first gate 190, coupling between the second gates 260 can be prevented, thereby improving the operating characteristics of the semiconductor device. Furthermore, by providing a ground voltage to the first gate 290, coupling between adjacent active regions 240 during operation of the semiconductor device can be prevented.

[0153] Furthermore, by providing a reverse bias to the semiconductor device through the first gate 190, which provides a ground voltage, leakage current (e.g., gate-induced drain current (GIDL)) can be effectively suppressed, and the electrical characteristics of the semiconductor device can be improved. Additionally, by providing a reverse bias to the semiconductor device through the first gate 190, the threshold voltage characteristics of the semiconductor device can be adjusted.

[0154] Figures 3A to 3C are diagrams illustrating a method for forming bit lines included in a semiconductor device according to an embodiment of the present disclosure.

[0155] More specifically, Figures 3A to 3C are cross-sectional views illustrating the manufacturing steps of a semiconductor device, wherein bit lines 150 are formed on a substrate layer 110, a silicide layer 120, a first nitride layer 130 and a first oxide layer 140, and a first bit line separation layer 160 is formed on the bit lines 150.

[0156] Figure 3A is a cross-sectional view obtained during the manufacturing process by cutting the center of the region in which the first gate G1 of the semiconductor device is formed along a cutting line (line A-A' in Figure 1) parallel to the second direction D2.

[0157] Figure 3B is a cross-sectional view obtained during the manufacturing process by cutting the center of the region where the second gate G2 of the semiconductor device is formed along a cutting line (line B-B' in Figure 1) parallel to the second direction D2.

[0158] Figure 3C is a cross-sectional view obtained by cutting the center of the bit line BL of the semiconductor device along a cutting line (line C-C' in Figure 1) parallel to the first direction D1 during the manufacturing process.

[0159] Referring to Figures 3A to 3C, substrate 110 may include a semiconductor substrate.

[0160] The silicide layer 120 may be located on the substrate layer 110 and may contain a metal silicide material, such as cobalt silicide (CoSi).

[0161] The first nitride layer 130 may be formed on the silicide layer 120 and may contain silicon nitride.

[0162] The first oxide layer 140 may be formed on the first nitride layer 130 and may contain silicon oxide.

[0163] The structure of the substrate layer 110, the silicide layer 120, the first nitride layer 130 and the first oxide layer 140 is substantially the same as the structure described with reference to Figures 2A, 2B and 2C.

[0164] Bit line 150 may include: a first bit line layer 152 containing titanium nitride (TiN); a second bit line layer 154 containing tungsten (W); and a third bit line layer 156 containing titanium nitride (TiN).

[0165] Because bit line 150 includes multiple layers, the operating resistance of the semiconductor device can be adjusted.

[0166] The first bit line layer 152 and the third bit line layer 156 included in bit line 150 prevent the second bit line layer 154 from being exposed to oxygen and oxidized. When the second bit line layer 154 is exposed to oxygen, tungsten (W) may be oxidized, resulting in broken connections and defects.

[0167] Furthermore, since the titanium nitride (TiN) contained in the first bit line layer 152 has a higher adhesion to silicon oxide than tungsten (W), the first bit line layer 152 provided between the first oxide layer 140 and the second bit line layer 154 can improve the mechanical stability of the bit line 150.

[0168] Bit line 150 can be formed by depositing multiple layers and then performing an etching process using a mask.

[0169] Figures 4A to 4C are diagrams illustrating a method for forming a first gate included in a semiconductor device according to an embodiment of the present disclosure.

[0170] More specifically, Figures 4A to 4C are cross-sectional views illustrating the manufacturing steps of a semiconductor device, wherein a second bit line separation layer 170 and a third bit line separation layer 180 are formed between bit lines 150, and a first gate 190 is formed on the first bit line separation layer 160.

[0171] Figure 4A is a cross-sectional view obtained during the manufacturing process by cutting the center of the region in which the first gate G1 of the semiconductor device is formed along a cutting line (line A-A' in Figure 1) parallel to the second direction D2.

[0172] Figure 4B is a cross-sectional view obtained during the manufacturing process by cutting the center of the region in which the second gate G2 of the semiconductor device is formed along a cutting line (line B-B' in Figure 1) parallel to the second direction D2.

[0173] Figure 4C is a cross-sectional view obtained by cutting the center of the bit line BL of the semiconductor device along a cutting line (line C-C' in Figure 1) parallel to the first direction D1 during the manufacturing process.

[0174] Referring to Figures 4A to 4C, the second bit line separation layer 170 and the third bit line separation layer 180 can be disposed between adjacent bit lines 150.

[0175] According to one embodiment, the second bit line separation layer 170 may comprise silicon nitride, and the third bit line separation layer 180 may comprise silicon oxide.

[0176] The first gate 190 may be selectively formed on the first line separation layer 160. The first gate 190 may have a shape extending along the second direction D2. The first gate 190 may comprise a metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first gate 190 may comprise titanium nitride.

[0177] The first gate 190 can be selectively formed on a portion of the first line separation layer 160 by forming a conductive material layer comprising metal, metal nitride and polysilicon on the first line separation layer 160 and selectively etching the formed conductive material layer.

[0178] A second nitride layer 200 and a protective oxide layer 210 may be formed on the first gate 190. The second nitride layer 200 and the protective oxide layer 210 serve to prevent damage to the first gate 190 during semiconductor processing and to electrically isolate the first gate 190 from other components (e.g., active regions) in the semiconductor device. The protective oxide layer 210 may comprise silicon oxide, and the second nitride layer 200 may comprise silicon nitride.

[0179] More specifically, as shown in Figures 4B and 4C, the first gate 190 may be selectively formed in a region other than the region where the second gate is formed.

[0180] Figures 5A to 5C are diagrams illustrating a method for forming a lower gate insulating layer included in a semiconductor device according to an embodiment of the present disclosure.

[0181] More specifically, Figures 5A to 5C are cross-sectional views illustrating the manufacturing steps of a semiconductor device, wherein a lower gate insulating layer 222 and a protective silicon layer 230 are formed on a first gate 190.

[0182] Figure 5A is a cross-sectional view obtained during the manufacturing process by cutting the center of the region in which the first gate G1 of the semiconductor device is formed along a cutting line (line A-A' in Figure 1) parallel to the second direction D2.

[0183] Figure 5B is a cross-sectional view obtained during the manufacturing process by cutting the center of the region in which the second gate G2 of the semiconductor device is formed along a cutting line (line B-B' in Figure 1) parallel to the second direction D2.

[0184] Figure 5C is a cross-sectional view obtained by cutting the center of the bit line BL of the semiconductor device along a cutting line (line C-C' in Figure 1) parallel to the first direction D1 during the manufacturing process.

[0185] Referring to Figures 5A to 5C, the lower gate insulating layer 222 and the protective silicon layer 230 may be formed to contact the upper and side portions of the first gate 190.

[0186] The lower gate insulating layer 222 may comprise silicon oxide. The protective silicon layer 230 may comprise polysilicon and may overlap the upper portion of the lower gate insulating layer 222 to protect the lower gate insulating layer 222 during the etching process.

[0187] When the protective silicon layer 230 is not provided, the gate insulating layer 222 may be directly exposed to plasma during the etching process, and side effects may occur such as a reduction in the thickness of the gate insulating layer 222 or surface defects caused by the plasma.

[0188] Figures 6A to 6C are diagrams illustrating a method for forming a lower gate insulating layer included in a semiconductor device according to an embodiment of the present disclosure.

[0189] More specifically, Figures 6A to 6C are cross-sectional views illustrating the manufacturing steps of a semiconductor device, wherein at least a portion of the gate insulating layer 222 and the protective silicon layer 230 are etched.

[0190] Figure 6A is a cross-sectional view obtained during the manufacturing process by cutting the center of the region in which the first gate G1 of the semiconductor device is formed along a cutting line (line A-A' in Figure 1) parallel to the second direction D2.

[0191] Figure 6B is a cross-sectional view obtained during the manufacturing process by cutting the center of the region in which the second gate G2 of the semiconductor device is formed along a cutting line (line B-B' in Figure 1) parallel to the second direction D2.

[0192] Figure 6C is a cross-sectional view obtained by cutting the center of the bit line BL of the semiconductor device along a cutting line (line C-C' in Figure 1) parallel to the first direction D1 during the manufacturing process.

[0193] Referring to Figures 6A to 6C, the lower gate insulating layer 222 and the protective silicon layer 230 that are in contact with the upper part of the bit line 150 can be removed by an etching process.

[0194] By selectively removing a portion of the lower gate insulating layer 222 and the protective silicon layer 230, only the lower gate insulating layer 222 that contacts the sidewall of the first gate 190 and the first line separation layer 160 can be selectively left.

[0195] In addition, a protective silicon layer 230 may be selectively left overlapping with the lower gate insulating layer 222, which contacts the sidewall of the first gate 190 and the first line separation layer 160.

[0196] The retained protective silicon layer 230 can then be selectively removed by a separate silicon etching process. This silicon etching process may include, for example, a wet etching process.

[0197] The lower gate insulating layer 222 may comprise silicon oxide, and the silicon oxide may have a dielectric constant of about 3.9.

[0198] Figures 7A to 7C are diagrams illustrating a method for forming an upper gate insulating layer included in a semiconductor device according to an embodiment of the present disclosure.

[0199] More specifically, Figures 7A to 7C are cross-sectional views illustrating the manufacturing steps of a semiconductor device, wherein an upper gate insulating layer 224 is formed on a lower gate insulating layer 222.

[0200] Figure 7A is a cross-sectional view obtained during the manufacturing process by cutting the center of the region in which the first gate G1 of the semiconductor device is formed along a cutting line (line A-A' in Figure 1) parallel to the second direction D2.

[0201] Figure 7B is a cross-sectional view obtained during the manufacturing process by cutting the center of the region in which the second gate G2 of the semiconductor device is formed along a cutting line (line B-B' in Figure 1) parallel to the second direction D2.

[0202] Figure 7C is a cross-sectional view obtained by cutting the center of the bit line BL of the semiconductor device along a cutting line (line C-C' in Figure 1) parallel to the first direction D1 during the manufacturing process.

[0203] Referring to Figures 7A to 7C, the upper gate insulating layer 224 may comprise a high-k material with a dielectric constant higher than that of silicon oxide. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3).

[0204] The upper gate insulating layer 224 may be formed to overlap with the upper part of the lower gate insulating layer 222 and the upper part of the bit line 150, and may be formed on the second bit line separation layer 170 and the third bit line separation layer 180.

[0205] Figures 8A to 8C are diagrams illustrating a method for forming an upper gate insulating layer included in a semiconductor device according to an embodiment of the present disclosure.

[0206] More specifically, Figures 8A to 8C are cross-sectional views illustrating the manufacturing steps of a semiconductor device, wherein at least a portion of the gate insulating layer 224 is etched.

[0207] Figure 8A is a cross-sectional view obtained during the manufacturing process by cutting the center of the region in which the first gate G1 of the semiconductor device is formed along a cutting line (line A-A' in Figure 1) parallel to the second direction D2.

[0208] Figure 8B is a cross-sectional view obtained during the manufacturing process by cutting the center of the region in which the second gate G2 of the semiconductor device is formed along a cutting line (line B-B' in Figure 1) parallel to the second direction D2.

[0209] Figure 8C is a cross-sectional view obtained by cutting the center of the bit line BL of the semiconductor device along a cutting line (line C-C' in Figure 1) parallel to the first direction D1 during the manufacturing process.

[0210] Referring to Figures 8A to 8C, by etching a portion of the upper gate insulating layer 224 formed on the first gate 190 and a portion of the upper gate insulating layer 224 formed on the bit line 150, the upper gate insulating layer 224 overlapping the upper portion of the lower gate insulating layer 222 can be selectively retained. The upper gate insulating layer 224 can be selectively removed by an etching process.

[0211] The lower gate insulating layer 222 and the upper gate insulating layer 224 may be referred to as the first gate insulating layer 220. In other words, the first gate insulating layer 220 may include multiple dielectric layers.

[0212] Since the first gate insulating layer 220 includes multiple dielectric layers, the leakage current characteristics of the first gate insulating layer 220 can be improved.

[0213] Figures 9A to 9C are diagrams illustrating a method for forming an active region included in a semiconductor device according to an embodiment of the present disclosure.

[0214] More specifically, Figures 9A to 9C are cross-sectional views illustrating the manufacturing steps of a semiconductor device, wherein an active region 240 is formed on a first gate insulating layer 220 and a bit line 150.

[0215] Figure 9A is a cross-sectional view obtained during the manufacturing process by cutting the center of the region in which the first gate G1 of the semiconductor device is formed along a cutting line (line A-A' in Figure 1) parallel to the second direction D2.

[0216] Figure 9B is a cross-sectional view obtained during the manufacturing process by cutting the center of the region in which the second gate G2 of the semiconductor device is formed along a cutting line (line B-B' in Figure 1) parallel to the second direction D2.

[0217] Figure 9C is a cross-sectional view obtained by cutting the center of the bit line BL of the semiconductor device along a cutting line (line C-C' in Figure 1) parallel to the first direction D1 during the manufacturing process.

[0218] Referring to Figures 9A to 9C, the active region 240 may contain semiconductor material or oxide semiconductor material.

[0219] The active region 240 may include doped polycrystalline silicon, undoped polycrystalline silicon, amorphous silicon, amorphous indium gallium zinc oxide (IGZO) semiconductor, indium zinc oxide (IZO), indium tin oxide (ITO), and indium oxide (InO3).

[0220] At least a portion of the active region 240 may be electrically connected to bit line 150.

[0221] Figures 10A to 10C are diagrams illustrating a method for forming a second gate insulating layer included in a semiconductor device according to an embodiment of the present disclosure.

[0222] More specifically, Figures 10A to 10C are cross-sectional views illustrating the manufacturing steps of a semiconductor device, wherein adjacent active regions 240 are separated from each other, and a second gate insulating layer 250 is formed that overlaps with the upper portion of the active regions 240.

[0223] Figure 10A is a cross-sectional view obtained during the manufacturing process by cutting the center of the region in which the first gate G1 of the semiconductor device is formed along a cutting line (line A-A' in Figure 1) parallel to the second direction D2.

[0224] Figure 10B is a cross-sectional view obtained during the manufacturing process by cutting the center of the region in which the second gate G2 of the semiconductor device is formed along a cutting line (line B-B' in Figure 1) parallel to the second direction D2.

[0225] Figure 10C is a cross-sectional view obtained by cutting the center of the bit line BL of the semiconductor device along a cutting line (line C-C' in Figure 1) parallel to the first direction D1 during the manufacturing process.

[0226] Referring to Figures 10A to 10C, adjacent active regions 240 can be separated from each other by forming a mask that overlaps with the active region 240 and selectively etching at least a portion of the active region 240. The mask used for etching may include a spin-coated carbon (SOC) layer and a silicon oxynitride (SiON) layer.

[0227] The second gate insulating layer 250 may comprise silicon oxide and may electrically isolate adjacent active regions 240 or electrically isolate active regions 240 from a second gate 260 formed later.

[0228] Figures 11A to 11C are diagrams illustrating a method for forming a second gate included in a semiconductor device according to an embodiment of the present disclosure.

[0229] More specifically, Figures 11A to 11C are cross-sectional views illustrating the manufacturing steps of a semiconductor device, wherein a second gate 260 is formed and a third nitride layer 270 and a second oxide layer 280 are formed overlapping the upper portion of the second gate 260.

[0230] Figure 11A is a cross-sectional view obtained during the manufacturing process by cutting the center of the region in which the first gate G1 of the semiconductor device is formed along a cutting line (line A-A' in Figure 1) parallel to the second direction D2.

[0231] Figure 11B is a cross-sectional view obtained during the manufacturing process by cutting the center of the region in which the second gate G2 of the semiconductor device is formed along a cutting line (line B-B' in Figure 1) parallel to the second direction D2.

[0232] Figure 11C is a cross-sectional view obtained by cutting the center of the bit line BL of the semiconductor device along a cutting line (line C-C' in Figure 1) parallel to the first direction D1 during the manufacturing process.

[0233] Referring to Figures 11A to 11C, the second gate 260 may face the first gate 190 and may have a shape extending along the second direction D2. The second gate 260 may comprise a metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the second gate 260 may comprise titanium nitride.

[0234] The second gate 260 can be formed by forming a conductive material layer comprising metal, metal nitride and polysilicon and selectively etching the formed conductive material layer.

[0235] A third nitride layer 270 may be formed on the second gate 260 and may contain silicon nitride. The third nitride layer 270 may be disposed on the second gate 260 and may electrically isolate the second gate 260 from another adjacent second gate 260.

[0236] The second oxide layer 280 may be formed on the third nitride layer 270 and may contain silicon oxide.

[0237] A mask can be formed on the second oxide layer 280 to form a contact portion at one end of the first gate 190 along the second direction D2 and a contact portion at one end of the second gate 260 along the second direction D2. After the mask is formed, the contact portions can be formed by an etching process, and the second oxide layer 280 can protect the first gate 190 and the second gate 260 during the etching process.

[0238] Figures 12A to 12C are diagrams illustrating a method of forming a capacitor included in a semiconductor device according to an embodiment of the present disclosure.

[0239] More specifically, Figures 12A to 12C are cross-sectional views illustrating the manufacturing steps of a semiconductor device, wherein portions of the third nitride layer 270 and the second oxide layer 280 are removed.

[0240] Figure 12A is a cross-sectional view obtained during the manufacturing process by cutting the center of the region in which the first gate G1 of the semiconductor device is formed along a cutting line (line A-A' in Figure 1) parallel to the second direction D2.

[0241] Figure 12B is a cross-sectional view obtained during the manufacturing process by cutting the center of the region in which the second gate G2 of the semiconductor device is formed along a cutting line (line B-B' in Figure 1) parallel to the second direction D2.

[0242] Figure 12C is a cross-sectional view obtained by cutting the center of the bit line BL of the semiconductor device along a cutting line (line C-C' in Figure 1) parallel to the first direction D1 during the manufacturing process.

[0243] Referring to Figures 12A to 12C, the third nitride layer 270 and the second oxide layer 280 can be removed by chemical mechanical polishing (CMP).

[0244] By removing a portion of the third nitride layer 270, a portion of the second oxide layer 280, a portion of the second gate layer 250, a portion of the first gate insulating layer 220, the protective oxide layer 210, and a portion of the active region 240, the vertical portion included in the active region 240 can be exposed.

[0245] Figures 13A to 13C are diagrams illustrating a method of forming a capacitor included in a semiconductor device according to an embodiment of the present disclosure.

[0246] More specifically, Figures 13A to 13C are cross-sectional views illustrating the manufacturing steps of a semiconductor device, wherein a first contact region 310 and a second contact region 330 are formed on an active region 240, and a storage element 340 is disposed on the second contact region 330.

[0247] Figure 13A is a cross-sectional view obtained during the manufacturing process by cutting the center of the region in which the first gate G1 of the semiconductor device is formed along a cutting line (line A-A' in Figure 1) parallel to the second direction D2.

[0248] Figure 13B is a cross-sectional view obtained during the manufacturing process by cutting the center of the region in which the second gate G2 of the semiconductor device is formed along a cutting line (line B-B' in Figure 1) parallel to the second direction D2.

[0249] Figure 13C is a cross-sectional view obtained by cutting the center of the bit line BL of the semiconductor device along a cutting line (line C-C' in Figure 1) parallel to the first direction D1 during the manufacturing process.

[0250] Referring to Figures 13A to 13C, the first contact region 310 and the second contact region 330 can be formed by sequentially stacking an oxide semiconductor layer and a conductive material layer and selectively etching the areas where the first contact region 310 and the second contact region 330 are not formed.

[0251] A contact insulating layer 300 may be formed between the first contact areas 310. The contact insulating layer 300 may contain an insulating material such as silicon oxide and may electrically isolate adjacent first contact areas 310.

[0252] The second contact areas 330 can be separated from each other by the memory element insulating layer 320 included in the memory element layer.

[0253] The storage element 340 may have a shape that overlaps with at least a portion of the second contact area 330.

[0254] Storage element 340 may be a data memory for writing or reading data, and may include, for example, a MIM capacitor.

[0255] As described above, the semiconductor device disclosed herein may include a three-dimensional channel. Therefore, a semiconductor device with improved integration can be provided.

[0256] Furthermore, the semiconductor device disclosed herein may include an upper gate insulating layer and a lower gate insulating layer between the first gate and the active region. Therefore, a semiconductor device with improved leakage current characteristics can be provided.

[0257] In addition, this disclosure may provide various effects, directly or indirectly recognized.

[0258] While this disclosure has been described above with reference to exemplary embodiments and accompanying drawings, it is not limited thereto. Various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of this disclosure, which is defined by the appended claims.

Claims

1. A semiconductor device, comprising: bit lines, It extends along the first direction; A first gate extends along a second direction perpendicular to the first direction; A second gate extends parallel to the first gate; an active region includes a vertical portion between the first gate and the second gate, and a horizontal portion that contacts the bit line and the vertical portion. and a first gate insulating layer disposed between the first gate and the vertical portion, wherein the first gate insulating layer includes a lower gate insulating layer in contact with the first gate and an upper gate insulating layer in contact with the vertical portion, and wherein the upper gate insulating layer has a higher dielectric constant than the lower gate insulating layer.

2. The semiconductor device according to claim 1, further comprising: A second gate insulating layer is disposed between the second gate and the active region.

3. The semiconductor device according to claim 1, wherein, The active region includes an indium gallium zinc oxide semiconductor, and wherein the active region includes a channel region formed therein.

4. The semiconductor device according to claim 1, further comprising: The first contact area is located on the opposite side of the vertical portion; The second contact area overlaps with the first contact area.

5. The semiconductor device according to claim 4, wherein, The first contact region comprises the same material as the active region, and the second contact region comprises at least one of a metal, a metal silicide, or a metal nitride.

6. The semiconductor device according to claim 4, further comprising: A capacitor that overlaps with the second contact area.

7. The semiconductor device according to claim 1, wherein, The first gate receives a control signal that is different from the control signal provided to the second gate.

8. The semiconductor device according to claim 1, wherein, The lower gate insulating layer comprises silicon oxide, and the upper gate insulating layer comprises at least one of hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or titanium strontium oxide.

9. A semiconductor device, comprising: bit lines, It extends along a first direction; a first gate extends along a second direction perpendicular to the first direction; A pair of second gates located on opposite sides of the first gate and extending parallel to the first gate; an active region comprising: a vertical portion located between one of the paired second gates and the first gate; and a horizontal portion contacting one side of the vertical portion and extending in the first direction; and a first gate insulating layer disposed between the first gate and the active region, wherein the first gate insulating layer comprises a lower gate insulating layer in contact with the first gate and an upper gate insulating layer in contact with the vertical portion, and wherein the upper gate insulating layer has a higher dielectric constant than the lower gate insulating layer.

10. The semiconductor device according to claim 9, wherein, The bit line contacts the horizontal portion.

11. The semiconductor device according to claim 9, further comprising: A second gate insulating layer is disposed between one of the paired second gates and the active region.

12. The semiconductor device according to claim 9, wherein, The active region comprises an amorphous indium gallium zinc oxide semiconductor.

13. The semiconductor device according to claim 9, further comprising: The first contact area is located on the opposite side of the vertical portion; The second contact area overlaps with the first contact area.

14. The semiconductor device according to claim 13, wherein, The first contact region comprises the same material as the active region, and the second contact region comprises at least one of a metal, a metal silicide, or a metal nitride.

15. The semiconductor device of claim 14, further comprising: A capacitor that overlaps with the second contact area.

16. The semiconductor device according to claim 9, wherein, The lower gate insulating layer comprises silicon oxide, and the upper gate insulating layer comprises at least one of hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or titanium strontium oxide.

17. A method for manufacturing a semiconductor device, the method comprising: A bit line extending along a first direction is formed in the substrate; A first gate is formed on the bit line, extending in a second direction perpendicular to the first direction; A first gate insulating layer is formed in contact with the first gate; an active region is formed including a vertical portion and a horizontal portion, the vertical portion extending along the sidewall of the first gate insulating layer, and the horizontal portion in contact with the bit line; A second gate insulating layer is formed in contact with the active region; The first gate insulating layer is formed in contact with the second gate insulating layer, wherein forming the first gate insulating layer includes: forming a lower gate insulating layer in contact with the first gate; and forming an upper gate insulating layer on the lower gate insulating layer, wherein the upper gate insulating layer has a higher dielectric constant than the lower gate insulating layer.

18. The method according to claim 17, wherein, The active region comprises an amorphous indium gallium zinc oxide semiconductor.

19. The method of claim 17, wherein, The lower gate insulating layer comprises silicon oxide, and the upper gate insulating layer comprises at least one of hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or titanium strontium oxide.

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