Display panel, preparation method thereof and display device

Abstract

The invention provides a display panel, a preparation method thereof and a display device. The preparation method comprises the following steps: providing a substrate; forming an active layer, an ohmic contact layer and a first source and drain electrode layer on the substrate; etching a first opening on the first source and drain electrode layer by wet etching to expose a first region of the ohmic contact layer; forming a second source-drain electrode layer on one side, deviating from the substrate, of the first source-drain electrode layer and on the first region of the ohmic contact layer; the thickness of the second source-drain electrode layer is smaller than that of the first source-drain electrode layer; etching a second opening in the second source and drain electrode layer by using wet etching to expose a second region of the ohmic contact layer; wherein the first opening is communicated with the second opening, and the width of the second opening is smaller than that of the first opening; and etching the ohmic contact layer in the second region and the active layer with a preset thickness by using a dry etching method. According to the invention, the length of the distance between the source and drain metal electrodes on the amorphous silicon TFT can be reduced, and the conduction current characteristic of the amorphous silicon TFT is improved.

Description

Display panel and its manufacturing method, display device Technical Field

[0001] This invention relates to the field of display technology, specifically to a display panel, its manufacturing method, and a display device. Background Technology

[0002] Liquid crystal display (LCD) panels have advantages such as balanced image quality, controllable power consumption, affordable cost, and high reliability, and occupy a dominant position in mainstream consumer electronics and commercial display fields.

[0003] TFT (Thin Film Transistor) panels are the main driving components for liquid crystal display (LCD) panels. Their core is the integration of a thin film transistor switch beneath each pixel, forming an "active driving unit" in conjunction with a capacitor. The Ion (on-state current) of the TFT directly determines the charging efficiency, refresh rate, resolution, and image stability of the display panel; therefore, the TFTs in a TFT panel must have good Ion. The Ion of a TFT is related to the distance between the source and drain metal electrodes; the shorter the distance, the better the Ion characteristics. Among these, amorphous silicon (a-Si) thin film transistors are field-effect transistors that use hydrogenated amorphous silicon as the channel material. Due to their low cost, large-area compatibility, and mature technology, they are widely used in TFT panels.

[0004] To improve the Ion characteristics of TFTs in amorphous silicon TFT panels, the distance between the source and drain metal electrodes on the amorphous silicon TFT needs to be further reduced. However, the distance between the source and drain metal electrodes on the existing amorphous silicon TFT structure is difficult to reduce to the ideal size in the current process. Summary of the Invention

[0005] To address the problems in the prior art, the present invention aims to provide a display panel and its manufacturing method, as well as a display device, which reduces the length of the source and drain metal electrode spacing on amorphous silicon TFT and improves the conduction current characteristics of amorphous silicon TFT.

[0006] In a first aspect, embodiments of the present invention provide a method for fabricating a display panel, comprising: providing a substrate; forming an active layer, an ohmic contact layer, and a first source / drain electrode layer on the substrate; etching a first opening in the first source / drain electrode layer using wet etching to expose a first region of the ohmic contact layer; forming a second source / drain electrode layer on a side of the first source / drain electrode layer away from the substrate and on the first region of the active layer; the thickness of the second source / drain electrode layer being less than the thickness of the first source / drain electrode layer; etching a second opening in the second source / drain electrode layer using wet etching to expose a second region of the ohmic contact layer; wherein the first opening and the second opening are interconnected, and the width of the second opening is less than the width of the first opening; and etching the ohmic contact layer and the active layer of a predetermined thickness in the second region using dry etching to form a channel region on the active layer.

[0007] Secondly, an embodiment of the present invention also provides a display panel, comprising: a substrate; an active layer disposed on the substrate; the active layer including a source contact region, a drain contact region, and a channel region located between the source contact region and the drain contact region; the source contact region and the drain contact region being provided with an ohmic contact layer; a source-drain electrode layer disposed on the side of the active layer away from the substrate; the source-drain electrode layer including a first source-drain electrode layer and a second source-drain electrode layer, the second source-drain electrode layer being disposed on the side of the first source-drain electrode layer away from the substrate; the source-drain electrode layer including a source electrode and a drain electrode spaced apart, the source electrode being connected to the source contact region, and the drain electrode being connected to the drain contact region; the first source-drain electrode layer being provided with a first opening, the second source-drain electrode layer being provided with a second opening, the first opening communicating with the second opening, and the width of the second opening being smaller than the width of the first opening; the second opening corresponding to the channel region.

[0008] Thirdly, embodiments of the present invention also provide a display device, including a display panel as described in any of the preceding claims.

[0009] The display panel, its fabrication method, and display device provided by this invention have the following advantages: by setting the source and drain electrode layers as a thicker first source and drain electrode layer and a thinner second source and drain electrode layer, the thicker first source and drain electrode layer can reduce the drain resistance and improve the current transmission efficiency; the thinner second source and drain electrode layer can achieve the formation of a smaller second opening by wet etching, thereby reducing the length of the source and drain metal electrode spacing on the TFT to the ideal length and improving the conduction current characteristics of the amorphous silicon TFT. Attached Figure Description

[0010] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0011] Figure 1 is a cross-sectional schematic diagram of an amorphous silicon TFT forming source and drain metal electrodes in the prior art; Figure 2 is a cross-sectional schematic diagram of an amorphous silicon TFT forming a channel region in the prior art; Figure 3 is a flowchart of a method for fabricating a display panel according to an embodiment of the present invention; Figure 4 is a schematic diagram of an intermediate structure obtained after step S300 using the fabrication method of Figure 3; Figure 5 is a schematic diagram of an intermediate structure obtained after step S400 using the fabrication method of Figure 3; Figure 6 is a schematic diagram of an intermediate structure obtained after step S500 using the fabrication method of Figure 3; Figure 7 is a schematic diagram of an intermediate structure obtained after step S600 using the fabrication method of Figure 3; Figure 8 is a schematic diagram of an amorphous silicon TFT in the prior art where the source and drain electrode layers include Cu layers during the formation of source and drain metal electrodes; Figure 9 is a schematic diagram of an amorphous silicon TFT in the prior art where the source and drain electrode layers include Cu layers during the formation of a channel region; Figure 10 Figure 11 is a schematic diagram of the second source / drain electrode layer of an amorphous silicon TFT (with source and drain metal electrodes already formed) covering the sidewalls of the first source / drain electrode layer according to an embodiment of the present invention; Figure 12 is a schematic diagram of the formation of a first via and a second via (not fully etched) in an amorphous silicon TFT according to an embodiment of the present invention; Figure 13 is a schematic diagram of the formation of a first via and a second via (fully etched) in an amorphous silicon TFT according to an embodiment of the present invention; Figure 14 is a schematic diagram of a broken line in the source / drain electrode layer of an amorphous silicon TFT in the prior art; Figure 15 is a schematic diagram of the second source / drain electrode layer of an amorphous silicon TFT filling the broken line in the first source / drain electrode layer according to an embodiment of the present invention; Figure 16 is a cross-sectional schematic diagram of a display panel according to an embodiment of the present invention; Figure 17 is a schematic diagram of a display device according to an embodiment of the present invention.

[0012] Figure label: Detailed Implementation

[0013] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that the invention will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted.

[0014] In this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics represented in connection with that embodiment or example, which are included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate different embodiments or examples represented in this application, as well as features of different embodiments or examples.

[0015] Furthermore, the terms "first" and "second" are used for illustrative purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the representation of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0016] It should be further understood that the terms "comprising" or "including" indicate the presence of a feature, step, operation, element, component, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" as used herein are interpreted as inclusive, or mean any one or any combination thereof. Therefore, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C." Exceptions to this definition only arise when a combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0017] The limitation on the distance between the source and drain metal electrodes in amorphous silicon TFTs is mainly caused by the large etching CD (Critical Dimension) loss of the source and drain electrode layers.

[0018] Figure 1 shows a cross-sectional view of an amorphous silicon TFT after the formation of source and drain metal electrodes in the prior art; Figure 2 shows a cross-sectional view of an amorphous silicon TFT after the formation of a channel region in the prior art. As shown in Figures 1 and 2, the amorphous silicon TFT of the prior art includes a substrate 10', an active layer 20', an ohmic contact layer 21', a source / drain electrode layer 30', and a gate electrode layer 40'; wherein, the active layer 20' includes a source contact region S', a drain contact region D', and a channel region L' disposed between the source contact region S' and the drain contact region D'. The source / drain electrode layer 30' disposed on the source contact region S' is a source metal electrode, and the source / drain electrode layer 30' disposed on the drain contact region D' is a drain metal electrode. Ohmic contact layers 21' are formed on both the source contact region S' and the drain contact region D' to form ohmic contacts between the source / drain electrode layer 30' and the active layer 20', thereby reducing the contact resistance between them. In an amorphous silicon TFT, the ohmic contact layer 21' is formed by implanting impurity atoms into the active layer 20'.

[0019] As shown in Figure 1, the source and drain metal electrodes of the amorphous silicon TFT are formed by forming a mask layer 50' on the side of the source / drain electrode layer 30' facing away from the substrate 10'. Then, the mask layer 50' is exposed and developed using a mask to form a pattern consistent with the pattern on the mask. The portion of the source / drain electrode layer 30' not covered by the mask layer 50' is the part that needs to be etched. When this portion of the source / drain electrode layer 30' not covered by the mask layer 50' is etched away, the portion of the source / drain electrode layer 30' in contact with the source contact region S' becomes the source metal electrode, and the portion of the source / drain electrode layer 30' in contact with the drain contact region D' becomes the drain metal electrode. As shown in Figure 2, the channel region L' of the amorphous silicon TFT is formed by dry etching of the ohmic contact layer 21' not covered by the mask layer 50' and the active layer 20' of a certain thickness on the structure obtained in Figure 1.

[0020] Please refer to Figure 1. The etching of the source and drain electrode layers 30' to form the source and drain metal electrodes is performed using a wet etching process. Wet etching is isotropic etching (i.e., the etching rate is similar in all directions), which has the advantages of high etching rate and simple process, but also has the characteristics of lower etching precision. Please refer to Figure 2. The formation of the channel region of the amorphous silicon TFT is performed using a dry etching process. Dry etching is anisotropic etching (i.e., the etching rate in the vertical direction is much greater than the etching rate in the horizontal direction), which has the characteristics of high etching selectivity and high etching precision, but also has the characteristics of low etching rate, complex process, and high cost.

[0021] In existing technologies, to reduce the drain resistance in amorphous silicon TFTs, the thickness of the source / drain electrode layer 30' is typically set to be relatively thick. As shown in Figure 1, since wet etching is an isotropic etching process, the wet etching process of a thick source / drain electrode layer 30' will cause a problem of a large CD loss in the source / drain electrode layer 30' (as shown in Figure 1, wet etching causes lateral side etching of the source / drain electrode layer 30'). A large CD loss in the source / drain electrode layer 30' results in a larger distance between the source and drain metal electrodes, i.e., the source / drain metal electrode spacing L. SD 'Too large. The source / drain metal electrode spacing L is relatively long.' SD 'Impact on the performance improvement of Ion in amorphous silicon TFTs.'

[0022] It should be noted that when preparing the source and drain metal electrodes of amorphous silicon TFTs, wet etching is usually used instead of dry etching because the source and drain electrode layers 30' usually contain Cu or Mo metal layers, and it is difficult to etch Cu or Mo metal layers using existing mass-produced dry etching processes.

[0023] To solve the above-mentioned technical problems, embodiments of the present invention provide a method for fabricating a display panel. Figure 3 shows a flowchart of a method for fabricating a display panel according to an embodiment of the present invention; Figures 4 to 7 show schematic diagrams of intermediate structures obtained using the method for fabricating a display panel according to an embodiment of the present invention. Referring to Figures 3 to 7, the method for fabricating a display panel includes: Step S100: providing a substrate 10; Step S200: forming an active layer 20, an ohmic contact layer 21, and a first source / drain electrode layer 31 on the substrate 10; Step S300: etching a first opening 311 on the first source / drain electrode layer 31 using wet etching to expose a first region of the ohmic contact layer 21, obtaining the structure shown in Figure 4; Step S400: forming a second source / drain electrode layer 32 on the side of the first source / drain electrode layer 31 facing away from the substrate 10 and on the first region of the ohmic contact layer 21; the second source / drain electrode layer 32... The thickness of the electrode layer 32 is less than the thickness of the first source / drain electrode layer 31, resulting in the structure shown in Figure 5; Step S500: A second opening 321 is etched on the second source / drain electrode layer 32 using wet etching to expose the second region of the ohmic contact layer 21; wherein, the first opening 311 and the second opening 321 are connected, and the width of the second opening 321 is less than the width of the first opening 311, resulting in the structure shown in Figure 6; S600: The ohmic contact layer 21 of the second region and the active layer 20 of a preset thickness are etched to form a channel region L on the active layer 20, resulting in the structure shown in Figure 7.

[0024] In this technical solution, by setting the source / drain electrode layers as a thicker first source / drain electrode layer 31 and a thinner second source / drain electrode layer 32, the thicker first source / drain electrode layer 31 can reduce the drain resistance and improve the current transmission efficiency; the thinner second source / drain electrode layer 32 can achieve the formation of a smaller second opening using wet etching. The width of the first opening 311 is the same as the source / drain metal electrode spacing L in the prior art. SD The length of the second opening 321 and the width of the second opening 321 are the source-drain metal electrode spacing L. SD The length of the source-drain metal electrode spacing L of the TFT can be achieved using the fabrication method provided in this embodiment of the invention. SD By reducing the length to the ideal length, the on-current characteristics of amorphous silicon TFTs are improved.

[0025] Specifically, the substrate 10 can be a rigid substrate or a flexible substrate. The rigid substrate can be made of metal or glass; the flexible substrate can be made of at least one of polyimide resin, polyamide resin, epoxy resin, and vinyl resin.

[0026] Furthermore, the active layer 20 is made of amorphous silicon. The ohmic contact layer 2 is formed by implanting doped impurity atoms into the active layer 20.

[0027] Furthermore, the materials of the first source / drain electrode layer 31 and the second source / drain electrode layer 32 may be at least one metal selected from, but not limited to, molybdenum, aluminum, gold, copper, magnesium, palladium, platinum, titanium, and tungsten.

[0028] Further, referring to Figure 4, before step S300, which uses wet etching to etch a first opening 311 into the first source / drain electrode layer 31 to expose the first region of the ohmic contact layer 21, the method further includes: forming a first mask layer 51 on the side of the first source / drain electrode layer 31 facing away from the substrate 10; and forming a first pattern on the first mask layer 51 using a first mask plate to expose a portion of the first source / drain electrode layer 31. In this embodiment, the first pattern is an opening pattern on the first mask layer 51.

[0029] Further, referring to Figure 6, before step S500, which involves etching a second opening 321 on the second source / drain electrode layer 32 using wet etching to expose the second region of the ohmic contact layer 21, the method further includes: forming a second mask layer 52 on the side of the second source / drain electrode layer 32 facing away from the substrate 10; forming a second pattern on the second mask layer 52 using the second mask to expose a portion of the ohmic contact layer 21; the first mask and the second mask are the same mask. In this embodiment, the second pattern is the opening pattern on the second mask layer 52.

[0030] It should be noted that the first mask layer 51 and the second mask layer 52 can be photoresist.

[0031] Using the same mask to form the first and second patterns can save on the number of masks required, reducing the cost of manufacturing the display panel. Since the same mask is used, the first and second patterns are identical; that is, the opening patterns formed on the first mask layer 51 and the second mask layer 52 are exactly the same size, and the exposed first source / drain electrode layers 31 and 32 are exactly the same size. Film thickness affects etching time. When the exposed first source / drain electrode layers 31 and 32 are exactly the same size, etching the thicker first source / drain electrode layer 31 requires a longer etching time, while etching the thinner second source / drain electrode layer 32 requires a relatively shorter etching time. A longer etching time results in a larger lateral etching amount on the first source / drain electrode layer 31, ultimately leading to a larger CD loss1 (CD loss1 is the distance between the bottom edge of the first mask layer 51 and the bottom edge of the first source / drain electrode layer 31) on the first source / drain electrode layer 31. Conversely, a shorter etching time results in a smaller lateral etching amount on the second source / drain electrode layer 32, ultimately leading to a smaller CD loss2 (CD loss2 is the distance between the bottom edge of the second mask layer 52 and the bottom edge of the second source / drain electrode layer 32) on the second source / drain electrode layer 32. When etching the first source / drain electrode layer 31 using a wet etching process, a first opening 311 is formed on the first source / drain electrode layer 31. When etching the second source / drain electrode layer 32 using a wet etching process, a second opening 321 is formed on the second source / drain electrode layer 32. Since the lateral etching amount on the first source / drain electrode layer 31 is larger and the lateral etching amount on the second source / drain electrode layer 32 is smaller, the width of the corresponding second opening 321 is smaller than the width of the first opening 311. As shown in Figures 6 and 7, this means that after the second source / drain electrode layer 32 etches the second opening 321, it can still completely cover the sidewall of the first source / drain electrode layer 31.

[0032] Figures 8 and 9 show schematic diagrams of amorphous silicon TFTs in the prior art where the source and drain electrode layers include a Cu metal layer during the formation of the source metal electrode, drain metal electrode, and channel region. Figures 10 and 11 show schematic diagrams of an amorphous silicon TFT (with a formed source metal electrode, drain metal electrode, and channel region) according to an embodiment of the present invention, where the second source and drain electrode layer covers the sidewalls of the first source and drain electrode layer. As shown in Figures 8 and 9, in the prior art, when the source and drain electrode layer 30' includes a Cu metal layer, after forming an opening structure on the source and drain electrode layer 30' using a wet etching process, part of the Cu will be exposed on the sidewalls of the source and drain electrode layer 30'. The exposed Cu can easily diffuse to other areas, affecting the performance of the TFT device. As shown in Figures 10 and 11, in this embodiment, the second source and drain electrode layer 32 completely covers the exposed sidewalls of the first source and drain electrode layer 31. When the first source and drain electrode layer 31 includes Cu, Cu is less likely to diffuse to other areas, thereby reducing the risk of copper contaminating other film layers of the TFT device and affecting its performance.

[0033] To further reduce the contact resistance between the first source / drain electrode layer 31 and the ohmic contact layer 21, the first source / drain electrode layer 31 typically includes a low-resistance material, such as aluminum, copper, molybdenum, titanium, or alloys of these metals. Preferably, molybdenum, molybdenum alloys, titanium, or titanium alloys are disposed at the position closest to the ohmic contact layer 21, which can achieve a lower contact resistance between the first source / drain electrode layer 31 and the ohmic contact layer 21. When the first source / drain electrode layer 31 includes aluminum or copper, aluminum or copper tends to diffuse into the ohmic contact layer 21 and the active layer 20. To improve this problem, a 20-80 nm layer of other metal material is typically disposed at the position of the first source / drain electrode layer 31 closest to the ohmic contact layer 21.

[0034] Further, referring to Figure 4, the difference between the width d2 of the first pattern and the width d1 of the first opening 311 is loss1, and the range of loss1 is greater than 2μm.

[0035] Further, referring to Figure 6, the difference between the width d4 of the second pattern and the width d3 of the second opening 321 is loss2, and the range of loss2 is less than 1 μm.

[0036] Furthermore, using the display panel fabrication method provided by this invention, the source / drain metal electrode spacing L SD The length of the channel region is less than 3 μm. For example, the length of the channel region is 2.5 μm, 2 μm, or 1.5 μm.

[0037] Furthermore, the thickness of the first source / drain electrode layer 31 is greater than 300 nm. For example, the thickness of the first source / drain electrode layer 31 can be 350 nm, 400 nm, 450 nm, etc.

[0038] Furthermore, the thickness of the second source / drain electrode layer 32 is less than 150 nm. For example, the thickness of the second source / drain electrode layer 32 is 120 nm, 90 nm, etc.

[0039] Figure 12 is a schematic diagram of the formation of the first and second vias (not fully etched) in an amorphous silicon TFT according to an embodiment of the present invention; Figure 13 is a schematic diagram of the formation of the first and second vias (fully etched) in an amorphous silicon TFT according to an embodiment of the present invention. As shown in Figures 12 and 13, after forming the second source / drain electrode layer 32, a passivation layer 70 is formed on the side of the second source / drain electrode layer 32 facing away from the substrate 10. Then, a first via 71 and a second via 72 are formed on the passivation layer 70 using a dry etching process. The first via 71 exposes part of the structure of the second source / drain electrode layer 32, and the second via 72 exposes the conductive structure 42 in the same layer as the gate metal electrode 41. By filling the first via 71 and the second via 72 with conductive material, corresponding signals are provided to the second source / drain electrode layer 32 and the conductive structure 42. Referring to Figure 13, the etching depth of the fully etched first via 71 is less than the etching depth of the fully etched second via 72. The formation of the first via 71 and the second via 72 is performed simultaneously. As shown in Figure 12, when the first via 71 is etched to completion, the second via 72 is not yet fully etched, thus requiring an increase in the etching time. However, once the second via 72 is fully etched, the first via 71 will experience over-etching. In the prior art, since the source / drain electrode layer 30' does not include the second source / drain electrode layer 32 in this embodiment, the issue of over-etching of the top metal of the source / drain electrode layer 30 exposed during the etching of the first via 71 must be considered. The prior art requires consideration of the step morphology after wet etching of the source / drain electrode layer 30', making it difficult to change the top metal material of the source / drain electrode layer 30' to improve the over-etching problem of the first via 71. However, the amorphous silicon TFT provided in this embodiment of the invention has a second source / drain electrode layer 32, and the thinner second source / drain electrode layer 32 has a more easily controlled step morphology after wet etching. Therefore, it is relatively easy to improve the over-etching problem of the first via 71 by changing the material of the second source / drain electrode layer 32.

[0040] Figure 14 is a schematic diagram of a broken line in the source / drain electrode layer of an amorphous silicon TFT in the prior art; Figure 15 is a schematic diagram of the second source / drain electrode layer of the amorphous silicon TFT in an embodiment of the present invention filling the broken line at the first source / drain electrode layer. As shown in Figure 14, in the prior art, because the film thickness of the source / drain electrode layer 30' is relatively thick, a broken line defect (the position shown by the circle in Figure 13) caused by foreign matter is easily encountered during the fabrication of the source / drain electrode layer 30'. As shown by the circle in Figure 15, in this embodiment, because the thinner second source / drain electrode layer 32 is fabricated after the thicker first source / drain electrode layer 31, the first source / drain electrode layer 31 can repair the broken line problem of the thick first source / drain electrode layer 31, reducing the defect rate of the first source / drain electrode layer 31. Furthermore, the film thickness of the second source / drain electrode layer 32 is relatively thin, so the number of foreign matter appearing during film formation is small, and the broken line defect rate is low. Furthermore, during the fabrication of the second opening on the second source / drain electrode layer 32, a mask layer is first formed and then exposed, developed, and cleaned. These steps also remove some foreign matter generated during the fabrication of the second source / drain electrode layer 32, improving the yield of the fabrication. Therefore, the provision of the second source / drain electrode layer 32 can reduce the breakage rate of the source / drain electrode layer and improve its reliability.

[0041] Further, referring to FIG4, before step S200 forms the active layer 20, the ohmic contact layer 21 and the first source / drain electrode layer 31 on the substrate 10, it further includes: forming a gate electrode layer 40 on the substrate 10, patterning the gate electrode layer 40 to form a gate metal electrode 41, at least a portion of the structure of the gate metal electrode 41 corresponding to the channel region L; forming a gate insulating layer 60 on the side of the gate metal electrode 41 away from the substrate 10, the gate insulating layer 60 completely covering the gate metal electrode 41.

[0042] The material of the gate electrode layer 40 includes, but is not limited to, at least one metal selected from molybdenum, aluminum, gold, magnesium, palladium, platinum, titanium, and tungsten.

[0043] The material of the gate insulating layer 60 includes, but is not limited to, insulating layers such as silicon nitride and silicon dioxide.

[0044] Furthermore, this embodiment of the invention also provides a display panel. Figure 16 shows a schematic diagram of a display panel provided in an embodiment of the present invention. As shown in Figure 16, the display panel includes: a substrate 10; an active layer 20 disposed on the substrate 10; the active layer 20 includes a source contact region S, a drain contact region D, and a channel region L located between the source contact region S and the drain contact region D; an ohmic contact layer 21 is disposed on the source contact region S and the drain contact region D; a source / drain electrode layer is disposed on the side of the active layer 20 away from the substrate 10; the source / drain electrode layer includes a first source / drain electrode layer 31 and a second source / drain electrode layer 32, the second source / drain electrode layer 32, and the second source / drain electrode layer 33, the second source / drain electrode layer 32 ... The electrode layer 32 is disposed on the side of the first source / drain electrode layer 31 away from the substrate 10; the source / drain electrode layer includes a source metal electrode and a drain metal electrode disposed at intervals, the source metal electrode is connected to the source contact region S, and the drain metal electrode is connected to the drain contact region D; the first source / drain electrode layer 31 is provided with a first opening 311, and the second source / drain electrode layer 32 is provided with a second opening 321, the first opening 311 and the second opening 321 are connected, and the width of the second opening 321 is smaller than the width of the first opening 311; the second opening 321 corresponds to the channel region L.

[0045] The display panel obtained by the display panel preparation method provided in the embodiments of the present invention can achieve all the technical effects of the above preparation method, which will not be repeated here.

[0046] Furthermore, in the display panel provided in this embodiment, the distance L between the source and drain metal electrodes is... SD The length is less than 3μm.

[0047] Furthermore, the first source / drain electrode layer 31 includes multiple layers of metal stacked together, with the thickness of the metal layer closest to the active layer 20 being 20~80nm.

[0048] Furthermore, referring to FIG16, at the first opening 311, the second source / drain electrode layer 32 covers the sidewall of the first source / drain electrode layer 31. The second source / drain electrode layer 32 completely covers the exposed sidewall of the first source / drain electrode layer 31. When the first source / drain electrode layer 31 includes Cu, it makes it difficult for Cu to diffuse to other areas, thereby reducing the risk of copper contaminating other film layers of the TFT device and affecting its performance.

[0049] Further, referring to FIG16, in this embodiment, the second opening 321 exposes a portion of the ohmic contact layer 21. That is, the source metal electrode and the drain metal electrode do not completely cover the ohmic contact layer 21, which can reduce the diffusion of metal atoms into the ohmic contact layer 21 during subsequent processes (such as annealing) and improve the long-term electrical stability of the TFT device. This embodiment of the invention also provides a display device, including the display panel described above. The display device includes the display panel described above, and therefore can achieve all the technical effects of the above-mentioned display panel, which will not be repeated here. FIG17 shows a schematic diagram of a display device provided in an embodiment of the present invention. As shown in FIG17, the display device 1000 includes the display panel described above. Specifically, the display device 1000 can be a mobile phone, wireless device, personal data assistant (PDA), handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, watch, clock, calculator, television monitor, flat panel display, computer monitor, car display, electronic photograph, electronic billboard or sign, projector, building structure, packaging and aesthetic structure, etc.

[0050] In summary, the display panel and its fabrication method provided by the present invention have the following advantages: by setting the source and drain electrode layers as a thicker first source and drain electrode layer and a thinner second source and drain electrode layer, the thicker first source and drain electrode layer can reduce the drain resistance and improve the current transmission efficiency; the thinner second source and drain electrode layer can achieve the formation of a smaller second opening by wet etching, thereby reducing the length of the source and drain metal electrode spacing on the TFT to the ideal length and improving the conduction current characteristics of the amorphous silicon TFT.

[0051] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for manufacturing a display panel, characterized in that, include: Provide a base; An active layer, an ohmic contact layer, and a first source / drain electrode layer are formed on the substrate; A first opening is etched on the first source / drain electrode layer using wet etching to expose a first region of the ohmic contact layer; A second source / drain electrode layer is formed on the side of the first source / drain electrode layer away from the substrate and on the first region of the ohmic contact layer; The thickness of the second source / drain electrode layer is less than the thickness of the first source / drain electrode layer; a second opening is etched on the second source / drain electrode layer using wet etching to expose a second region of the ohmic contact layer; wherein the first opening and the second opening are interconnected, and the width of the second opening is less than the width of the first opening; the ohmic contact layer and the active layer of a predetermined thickness in the second region are etched using dry etching to form a channel region on the active layer.

2. The method for manufacturing a display panel according to claim 1, characterized in that, Before the step of etching a first opening in the first source / drain electrode layer using wet etching to expose a first region of the ohmic contact layer, the method further includes: forming a first mask layer on the side of the first source / drain electrode layer away from the substrate; and forming a first pattern on the first mask layer using a first mask plate to expose a portion of the first source / drain electrode layer.

3. The method for manufacturing a display panel according to claim 2, characterized in that, Before the step of etching a second opening on the second source / drain electrode layer using wet etching to expose a second region of the ohmic contact layer, the method further includes: forming a second mask layer on the side of the second source / drain electrode layer away from the substrate; forming a second pattern on the second mask layer using a second mask to expose a portion of the second source / drain electrode layer; the first mask and the second mask are the same mask.

4. The method for manufacturing a display panel according to claim 2, characterized in that, The difference between the width of the first pattern and the width of the first opening is loss1, and the range of loss1 is greater than 2μm.

5. The method for manufacturing a display panel according to claim 3, characterized in that, The difference between the width of the second pattern and the width of the second opening is loss2, and the range of loss2 is less than 1μm.

6. The method for manufacturing a display panel according to claim 1, characterized in that, The length of the channel region is less than 3 μm.

7. The method for manufacturing a display panel according to claim 1, characterized in that, The thickness of the first source / drain electrode layer is greater than 300 nm.

8. The method for manufacturing a display panel according to claim 1, characterized in that, The thickness of the second source / drain electrode layer is less than 150 nm.

9. A display panel, characterized in that, include: Base; An active layer is disposed on the substrate; The active layer includes a source contact region, a drain contact region, and a channel region located between the source contact region and the drain contact region; the source contact region and the drain contact region are provided with ohmic contact layers; a source / drain electrode layer is disposed on the side of the active layer away from the substrate; the source / drain electrode layer includes a first source / drain electrode layer and a second source / drain electrode layer, the second source / drain electrode layer being disposed on the side of the first source / drain electrode layer away from the substrate; the source / drain electrode layer includes a source and a drain electrode spaced apart, the source electrode being connected to the source contact region, and the drain electrode being connected to the drain contact region; the first source / drain electrode layer has a first opening, the second source / drain electrode layer has a second opening, the first opening and the second opening are interconnected, and the width of the second opening is smaller than the width of the first opening; the second opening corresponds to the channel region.

10. The display panel according to claim 9, characterized in that, The length of the distance between the source and drain metal electrodes is less than 3 μm.

11. The display panel according to claim 9, characterized in that, The first source / drain electrode layer comprises multiple layers of metal stacked together, with the thickness of the metal layer closest to the active layer being 20-80 nm.

12. The display panel according to claim 9, characterized in that, At the first opening, the second source / drain electrode layer covers the sidewall of the first source / drain electrode layer.

13. The display panel according to claim 9, characterized in that, The second opening exposes a portion of the ohmic contact layer.

14. A display device, characterized in that, Includes the display panel as described in any one of claims 9 to 13.

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