CIS device and manufacturing method thereof

Abstract

The invention relates to a CIS device and a manufacturing method thereof. The CIS device comprises a stacked substrate structure, the stacked substrate structure comprises a first pixel substrate and a second pixel substrate which are bonded with each other in the vertical direction, and at least one visible light pixel unit and at least one infrared light pixel unit are distributed on the stacked substrate structure in a non-overlapping mode in the transverse direction. The visible light pixel unit comprises a visible light sensing element formed in the first pixel substrate, and the infrared light pixel unit comprises an infrared light sensing element formed in the second pixel substrate. The visible light sensing element and the infrared light sensing element are respectively used for sensing visible light and infrared light which are incident from one side, far away from the second pixel substrate, of the first pixel substrate, and compared with a visible light pixel unit, an incident light signal of the infrared light pixel unit passes through a longer optical path before being detected, so that the infrared response capability is enhanced, and the detection efficiency is improved. And meanwhile, the incident light signal of the visible light pixel unit is short in optical path and low in depletion layer depth before being detected, so that the crosstalk risk between adjacent pixel units is low.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a CIS device and its fabrication method. Background Technology

[0002] After years of development, CIS (CMOS Image Sensor) technology has become increasingly mature. Near-infrared response is one of the important parameters of CIS devices. For example, automotive-grade CIS chips operate in complex lighting environments, and in addition to requiring high dynamic range, the detection of near-infrared light is particularly important because it directly affects the life and property safety of drivers and passengers.

[0003] Currently, CIS devices based on silicon materials have different absorption depths for different wavelengths of light. For visible light, the absorption depth is greatest for red light (approximately 3 μm). For longer wavelengths of light, the absorption depth is even greater, which can cause the incident light signal to pass through the depletion layer of the photodiode without generating a response. This is also the main reason why the quantum efficiency (QE) of CIS devices decreases as the wavelength increases in the near-infrared band.

[0004] To enhance the infrared response of CIS devices, one approach is to increase the depth of the photodiodes in each pixel, thereby increasing the depletion layer depth so that each pixel can collect light signals that would otherwise escape to the outer layer of the depletion layer. However, this makes it easier for free charges generated within the pixel to be collected by neighboring pixels, increasing the risk of crosstalk between pixels. Another approach is to make the incident light signal, after entering the pixel, not propagate along a straight path as in traditional pixel structures, but undergo multiple reflections to be collected in the depletion layer. This greatly increases the actual optical path length, and because infrared light has weak reflectivity at interfaces, it often cannot be effectively collected. Summary of the Invention

[0005] To enhance the infrared response capability of CIS devices and avoid increasing the risk of crosstalk between adjacent pixels, this invention provides a CIS device and a method for manufacturing a CIS device.

[0006] On one hand, the present invention provides a CIS device, the CIS device comprising a stacked substrate structure, the stacked substrate structure including a first pixel substrate and a second pixel substrate bonded to each other in the vertical direction, and at least one visible light pixel unit and at least one infrared light pixel unit distributed non-overlappingly in the lateral direction, the visible light pixel unit including a visible light sensing element formed in the first pixel substrate, the infrared light pixel unit including an infrared light sensing element formed in the second pixel substrate, the visible light sensing element and the infrared light sensing element being used to sense visible light and infrared light incident from the side of the first pixel substrate away from the second pixel substrate, respectively.

[0007] Optionally, the first pixel substrate includes a first substrate and a first dielectric layer formed on the side of the first substrate facing the second pixel substrate, and the second pixel substrate includes a second substrate and a second dielectric layer formed on the side of the second substrate facing the first pixel substrate, wherein the first dielectric layer and the second dielectric layer are adjacent and bonded.

[0008] Optionally, a trench isolation structure is formed in the first substrate, and the at least one visible light pixel unit and the at least one infrared light pixel unit are isolated in the first substrate by the trench isolation structure.

[0009] Optionally, a first metal ring is formed in the first dielectric layer, and the infrared pixel unit is isolated in the first dielectric layer by the first metal ring; and / or, a second metal ring is formed in the second dielectric layer, and the infrared pixel unit is isolated in the second dielectric layer by the second metal ring.

[0010] Optionally, when the same infrared pixel unit is isolated by the first metal ring in the first dielectric layer and by the second metal ring in the second dielectric layer, the first metal ring and the second metal ring are bonded to each other at the bonding interface of the first dielectric layer and the second dielectric layer.

[0011] Optionally, the first pixel substrate is a back-illuminated substrate, the first dielectric layer is located on the front side of the first substrate, and the first pixel substrate further includes a first metal interconnect structure formed in the first dielectric layer; the second pixel substrate is a front-illuminated substrate, the second dielectric layer is located on the front side of the second substrate, and the second pixel substrate further includes a second metal interconnect structure formed in the second dielectric layer; the first metal interconnect structure and the second metal interconnect structure are bonded at the bonding interface of the first dielectric layer and the second dielectric layer.

[0012] Optionally, the CIS device further includes a filter layer formed on the side of the first pixel substrate away from the second pixel substrate and a lens layer formed on the side of the filter layer away from the first pixel substrate; the filter layer includes a black matrix grid covering the region between the at least one visible light pixel unit and the at least one infrared light pixel unit and having openings corresponding to the visible light pixel unit and the infrared light pixel unit, and color filter units filling the openings; the lens layer includes microlenses formed respectively corresponding to the at least one visible light pixel unit and the at least one infrared light pixel unit.

[0013] On the other hand, the present invention provides a method for fabricating a CIS device, the method comprising:

[0014] A first pixel substrate and a second pixel substrate are respectively formed. The first pixel substrate includes at least one visible light pixel region and at least one first infrared light pixel region that are not overlapped in the lateral direction. A visible light sensing element is formed in the visible light pixel region. The second pixel substrate includes at least one second infrared light pixel region that is not overlapped in the lateral direction. An infrared light sensing element is formed in the second infrared light pixel region.

[0015] The first pixel substrate and the second pixel substrate are vertically stacked and bonded to form a stacked substrate structure, wherein at least one first infrared light pixel region in the first pixel substrate and at least one second infrared light pixel region in the second pixel substrate are vertically aligned one by one. The stacked substrate structure includes visible light pixel units formed corresponding to the visible light pixel regions and infrared light pixel units formed corresponding to the first infrared light pixel regions. The visible light sensing element and the infrared light sensing element are respectively used to sense visible light and infrared light incident from the side of the first pixel substrate away from the second pixel substrate.

[0016] Optionally, forming the first pixel substrate includes:

[0017] Shallow trench isolation is formed on the front side of the first substrate to define the at least one visible light pixel area and the at least one first infrared light pixel area;

[0018] A visible light sensing element is formed in the at least one visible light pixel region; and

[0019] A first pixel circuit element coupled to the visible light sensing element, a first dielectric layer covering the first pixel circuit element, and a first metal interconnect structure formed on the first dielectric layer and connected to the first pixel circuit element are formed on the front side of the first substrate.

[0020] Optionally, when forming the first dielectric layer and the first metal interconnect structure, a first metal ring is also formed in the first dielectric layer, and the orthographic projection of the first metal ring on the front side of the first substrate is located around the first infrared pixel region.

[0021] Optionally, forming the second pixel substrate includes:

[0022] Shallow trench isolation is formed on the front side of the second substrate to define the at least one second infrared pixel region;

[0023] An infrared light sensing element is formed in the at least one second infrared light pixel region; and

[0024] A second pixel circuit element coupled to the infrared light sensing element, a second dielectric layer covering the second pixel circuit element, and a second metal interconnect structure formed on the front side of the second substrate are formed thereon;

[0025] Specifically, when bonding the first pixel substrate and the second pixel substrate, the first dielectric layer and the second dielectric layer are bonded together, and the first metal interconnect structure and the second metal interconnect structure are bonded at the bonding interface between the first dielectric layer and the second dielectric layer.

[0026] Optionally, when forming the second dielectric layer and the second metal interconnect structure, a second metal ring is also formed in the second dielectric layer, and the orthographic projection of the second metal ring on the front side of the second substrate is located around the second infrared pixel region.

[0027] Optionally, after bonding the first pixel substrate and the second pixel substrate, the fabrication method further includes:

[0028] Thinning the first substrate from its back side to form a deep trench isolation corresponding to the region between the at least one visible light pixel unit and the at least one infrared light pixel unit; and

[0029] A filter layer and a lens layer are sequentially formed on the back side of the first substrate.

[0030] In the CIS device and the method for fabricating the CIS device provided by the present invention, at least one visible light pixel unit and at least one infrared light pixel unit are distributed in a non-overlapping manner in the lateral direction. The visible light pixel unit includes a visible light sensing element formed in a first pixel substrate, and the infrared light pixel unit includes an infrared light sensing element formed in a second pixel substrate. The visible light sensing element and the infrared light sensing element are respectively used to sense visible light and infrared light incident from the side of the first pixel substrate away from the second pixel substrate. Compared with the visible light pixel unit, the incident light signal of the infrared light pixel unit has to pass through a longer optical path before being detected, which enhances the infrared response capability. At the same time, the incident light signal of the visible light pixel unit has a shorter optical path before being detected and a smaller depletion layer depth, which reduces the risk of crosstalk between adjacent pixel units. Attached Figure Description

[0031] Figure 1 This is a schematic flowchart illustrating the fabrication method of a CIS device according to an embodiment of the present invention.

[0032] Figure 2A and Figure 2B These are cross-sectional schematic diagrams showing the fabrication method of a CIS device according to an embodiment of the present invention, after shallow trench isolation is formed on the front sides of the first and second substrates.

[0033] Figure 3A and Figure 3B These are cross-sectional schematic diagrams showing the fabrication method of a CIS device according to an embodiment of the present invention, after forming a visible light sensing element in a first substrate and an infrared light sensing element in a second substrate.

[0034] Figure 4A and Figure 4B These are cross-sectional schematic diagrams showing the fabrication method of a CIS device according to an embodiment of the present invention, after pixel circuit elements are formed on the surfaces of a first substrate and a second substrate.

[0035] Figure 5A and Figure 5B These are cross-sectional schematic diagrams showing the fabrication method of a CIS device according to an embodiment of the present invention, after forming a first dielectric layer on a first substrate and a second dielectric layer on a second substrate.

[0036] Figure 6 This is a cross-sectional schematic diagram of a CIS device fabrication method according to an embodiment of the present invention, after bonding a first pixel substrate and a second pixel substrate.

[0037] Figure 7 This is a cross-sectional view of a method for fabricating a CIS device according to an embodiment of the present invention, after forming a deep trench isolation layer, a filter layer and a lens layer on the side of the first pixel substrate away from the second pixel substrate. Detailed Implementation

[0038] The CIS device and its fabrication method of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be understood that the accompanying drawings are in a very simplified form and use non-precise scales, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. It should be noted that the order of the steps in the method presented herein is not necessarily the only order in which these steps are performed; some steps may be omitted and / or some other steps not described herein may be added to the method. It should be understood that spatial relative terms are intended to include different orientations in use or operation besides the orientation of the device as depicted in the figures. For example, if the structure in the figures is inverted or positioned in other different ways (e.g., rotated), the exemplary term "on" may also include "below" and other orientational relationships.

[0039] Reference Figure 1 The method for fabricating a CIS device according to an embodiment of the present invention includes:

[0040] Step S1: A first pixel substrate and a second pixel substrate are formed respectively. The first pixel substrate includes at least one visible light pixel area and at least one first infrared light pixel area that are not overlapped in the horizontal direction. A visible light sensing element is formed in the visible light pixel area. The second pixel substrate includes at least one second infrared light pixel area that is not overlapped in the horizontal direction. An infrared light sensing element is formed in the second infrared light pixel area.

[0041] Step S2: The first pixel substrate and the second pixel substrate are vertically stacked and bonded to form a stacked substrate structure, wherein at least one first infrared light pixel region in the first pixel substrate and at least one second infrared light pixel region in the second pixel substrate are vertically aligned one by one. The stacked substrate structure includes visible light pixel units formed corresponding to the visible light pixel regions and infrared light pixel units formed corresponding to the first infrared light pixel regions. The visible light sensing element and the infrared light sensing element are respectively used to sense visible light and infrared light incident from the side of the first pixel substrate away from the second pixel substrate.

[0042] In the stacked substrate structure formed by the above fabrication method, for the visible light pixel unit, incident light enters the visible light sensing element in the first pixel substrate from the side of the first pixel substrate away from the second pixel substrate (i.e., the light incident side) and is sensed. For the infrared light pixel unit, after the incident light enters from the side of the first pixel substrate away from the second pixel substrate, it needs to pass through the first pixel substrate, then through the medium between the first and second pixel substrates, and then enter the second pixel substrate to be sensed by the infrared light sensing element. It can be seen that the detection of infrared light adopts a longer optical path structure than the detection of visible light. While the optical path corresponding to the visible light pixel unit is shorter and visible light detection is achieved, the longer optical path corresponding to the infrared light pixel unit can avoid the infrared light signal passing through the depletion layer of the infrared light sensing element, making it easier for the infrared light signal to be detected in the depletion layer of the infrared light sensing element, thus enhancing the infrared response capability. Moreover, the depletion layer depth of the visible light pixel unit is small, which can reduce the risk of crosstalk. The above fabrication method bonds the first pixel substrate and the second pixel substrate and integrates both the visible light pixel unit and the infrared light pixel unit simultaneously, resulting in high integration and contributing to the miniaturization of CIS devices and chips. Furthermore, in the stacked substrate structure, the visible light pixel units and infrared light pixel units are offset from each other laterally and do not overlap, enabling the visible light pixel units and infrared light pixel units to image separately without sharing an optical path, thus avoiding mutual interference between optical paths. Moreover, using independent infrared pixel units for imaging allows for targeted signal collection and processing, improving the imaging capability and quality of infrared light. The above manufacturing method is described below with reference to specific embodiments.

[0043] Figure 2A and Figure 2BA cross-section is shown after shallow trench isolation (STI) is formed on the front sides of the first substrate 100 and the second substrate 200. (Refer to...) Figure 1 , Figure 2A and Figure 2B In step S1, a first substrate 100 and a second substrate 200 are used to form a first pixel substrate and a second pixel substrate, respectively. The first substrate 100 and the second substrate 200 can be various substrates used in the art for fabricating CIS devices. For example, either the first substrate 100 or the second substrate 200 can include one or a combination of silicon, germanium, silicon-germanium, silicon carbide, gallium oxide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP. The first substrate 100 and the second substrate 200 can have a certain concentration of doped ions as required. Both the first substrate 100 and the second substrate 200 include a front side and a back side facing away from each other, wherein the front side is the surface on which ion implantation is performed to form a photoelectric element internally.

[0044] Reference Figure 2A and Figure 2B In one embodiment, to define and isolate different pixel units and other areas requiring isolation, shallow trench isolation (STI) is formed on the front surfaces of the first substrate 100 and the second substrate 200. The depth of the shallow trench isolation STI is, for example, in... The range. For the first substrate 100, at least one visible light pixel region (e.g., by forming a shallow trench isolation STI) can be defined. Figure 2A The first substrate 100 includes visible light pixel regions A1-A3 and at least one first infrared pixel region A41. The first infrared pixel region and the visible light pixel region are arranged laterally within the first substrate 100 without overlapping. As an example, by forming a shallow trench isolation (STI), multiple large pixel regions can be defined in the first substrate 100. Each large pixel region includes three of the visible light pixel regions and one first infrared pixel region. The three visible light pixel regions are subsequently used to sense visible light signals in the red, green, and blue bands, respectively. The first infrared pixel region A41 is used to propagate infrared light (including near-infrared light).

[0045] like Figure 2B As shown, for the second substrate 200, at least one second infrared pixel region A42 can be defined by forming a shallow trench isolation (STI) on the front side. In another embodiment, to effectively isolate the second infrared pixel region A42 from interference by signals surrounding it, the second substrate 200 may not have a shallow trench isolation (STI) formed on the front side, but instead may have a deep trench isolation (DTI) with a greater depth. Both the deep trench isolation (DTI) and the shallow trench isolation (STI) can be fabricated using existing processes.

[0046] Figure 3A A cross-section is shown after the visible light sensing element PD1 is formed in the first substrate 100. (Refer to...) Figure 3A After forming a shallow trench isolation (STI) on the front side of the first substrate 100, one or more ion implantations can be performed on the first substrate 100 from the front side to form a visible light sensing element PD1 for sensing visible light in at least one visible light pixel region (such as visible light pixel regions A1 to A3) in the first substrate 100. If necessary, a doped region can also be formed in the area other than the visible light sensing element PD1 in the first substrate 100. For example, in order to transmit the signal sensed by the visible light sensing element PD1, a first pixel circuit element coupled to the visible light sensing element PD1 can be formed on the front side of the first substrate 100. The first pixel circuit element includes a MOS device. If necessary, a well region can be formed in the first substrate 100 by ion implantation corresponding to the formation region of the MOS device.

[0047] Figure 3B A cross-section is shown after the infrared light sensing element PD2 is formed in the second substrate 200. (Refer to...) Figure 3B After shallow trench isolation (STI) is formed on the front side of the second substrate 200, one or more ion implantations can be performed on the second substrate 200 from the front side. An infrared light sensing element PD2 for sensing infrared light is formed in the at least one second infrared light pixel region A42 in the second substrate 100. If necessary, other doped regions can also be formed in the second substrate 200. For example, in order to transmit the signal sensed by the infrared light sensing element PD2, a second pixel circuit element coupled to the infrared light sensing element PD2 can be formed on the front side of the second substrate 200. The second pixel circuit element includes a MOS device. If necessary, a well region can be formed in the second substrate 100 by ion implantation corresponding to the formation region of the MOS device.

[0048] The visible light sensing element PD1 and the infrared light sensing element PD2 are formed, for example, by doping ion dopant into the respective substrates. Either the visible light sensing element PD1 or the infrared light sensing element PD2 can be a PN type photodiode, a PNP type photodiode, an NPN type photodiode, or other types of optoelectronic devices. In this embodiment, the visible light sensing element PD1 and the infrared light sensing element PD2 are, for example, PN type photodiodes.

[0049] Figure 4A A cross-section is shown after the first pixel circuit element is formed on the front side of the first substrate 100. (Refer to...) Figure 4AAfter forming a visible light sensing element PD1 in the visible light pixel region of the first substrate 100, a first pixel circuit element can be further formed on the surface region of the first substrate 100. The structure of the first pixel circuit element can be configured according to a specific pixel circuit design. The first pixel circuit element can be formed using processes known in the art. For example, a floating diffusion region for transmitting the signal sensed by the visible light sensing element PD1 and multiple MOS transistors (such as...) can be formed on the surface of the first substrate 100 in each visible light pixel region. Figure 4A The MOS transistor (represented as "MOS") may include a gate dielectric layer 101 formed on the surface of a first substrate 100, a gate stacked on the gate dielectric layer 101, a sidewall covering the side of the gate, an LDD region formed in the first substrate 100 on the side of the gate, and source / drain regions. Optionally, before, after, or during the formation of the MOS transistor on the surface of the first substrate 100, the first substrate 100 on top of the visible light sensing element PD1 may be heavily doped to form a pinned (PIN) layer (not shown) on top of the visible light sensing element PD1.

[0050] Figure 4B A cross-section is shown after the second pixel circuit element is formed on the front side of the second substrate 200. (Refer to...) Figure 4B After the infrared light sensing element PD2 is formed in the second infrared light pixel region A42 in the second substrate 200, a second pixel circuit element can be further formed on the surface of the second substrate 200. The structure of the second pixel circuit element can be set according to the specific pixel circuit design. For example, a floating diffusion region for transmitting the signal sensed by the infrared light sensing element PD2 and multiple MOS transistors (such as...) can be formed on the surface of the second substrate 200. Figure 4B The MOS transistor (represented as "MOS") may include a gate dielectric layer 201 formed on the surface of the second substrate 200, a gate stacked on the gate dielectric layer 201, a sidewall covering the side of the gate, an LDD region formed in the second substrate 200 on the side of the gate, and source / drain regions. Optionally, before, after, or during the formation of the MOS transistor on the surface of the second substrate 200, the second substrate 200 on top of the infrared light sensing element PD2 may be heavily doped to form a pinned (PIN) layer (not shown) on top of the infrared light sensing element PD2.

[0051] Figure 5A A cross-section is shown after the first dielectric layer 110 and the first metal interconnect structure 120 are formed on the front side of the first substrate 100. (Refer to...) Figure 5AAfter forming a first pixel circuit element on the surface of the first substrate 100, a first dielectric layer 110 covering the first pixel circuit element and a first metal interconnect structure 120 formed on the first dielectric layer 110 and connected to the first pixel circuit element are further formed. The first metal interconnect structure 120 may include a metal bonding pad flush with the top surface of the first dielectric layer 110.

[0052] In one embodiment, such as Figure 5A As shown, when forming the first dielectric layer 110 and the first metal interconnect structure 120, a first metal ring MR1 can also be formed in the first dielectric layer 110. The orthographic projection of the first metal ring MR1 on the front side of the first substrate 100 is located around the first infrared pixel region A41. As an example, when forming vias and metal layers for constituting the first metal interconnect structure 120 in the first dielectric layer 110, vias and metal layers can be formed simultaneously corresponding to the area around the first infrared pixel region A41. When the first dielectric layer 110 and the first metal interconnect structure 120 are completed, a first metal ring MR1 is also formed corresponding to the area around the first infrared pixel region A41. Figure 5A As shown, a first metal ring MR1 extends in its height direction and penetrates part or all of the thickness of the first dielectric layer 110. The first metal ring MR1 can connect to the shallow trench isolation STI surrounding the first infrared pixel region A41. When the incident light signal is transmitted from the first infrared pixel region A41 to the first dielectric layer 110, it will be blocked by the first metal ring MR1, reducing the risk of deviation. After the above process, a structure is formed on the first substrate 100 as shown. Figure 5A The first pixel substrate 10 shown.

[0053] Figure 5B A cross-section is shown after the second dielectric layer 210 and the second metal interconnect structure 220 are formed on the front side of the second substrate 200. (Refer to...) Figure 5B After forming the second pixel circuit element on the surface of the second substrate, a second dielectric layer 210 covering the second pixel circuit element and a second metal interconnect structure 220 formed on the second dielectric layer 210 and connected to the second pixel circuit element are further formed. The second metal interconnect structure 220 may include a metal bonding pad flush with the top surface of the second dielectric layer 210.

[0054] In one embodiment, such as Figure 5BAs shown, when forming the second dielectric layer 210 and the second metal interconnect structure 220, a second metal ring MR2 can also be formed in the second dielectric layer 210. The orthogonal projection of the second metal ring MR2 on the front side of the second substrate 200 is located around the second infrared light pixel region A42. As an example, when forming vias and metal layers for constituting the second metal interconnect structure 220 in the second dielectric layer 210, vias and metal layers can be formed simultaneously around the second infrared light pixel region A42. When the second dielectric layer 210 and the second metal interconnect structure 220 are completed, a second metal ring MR2 is also formed around the second infrared light pixel region A42. Figure 5B As shown, the second metal ring MR2 extends in its height direction and penetrates part or all of the thickness of the second dielectric layer 210. The second metal ring MR2 can connect to the shallow trench isolation STI surrounding the second infrared light pixel region A42. When the incident light signal is transmitted to the second dielectric layer 210, it will be blocked by the second metal ring MR2 to prevent deviation. After the above process, a structure is formed on the second substrate 100 as shown. Figure 5B The second pixel substrate 20 is shown.

[0055] Figure 6 A cross-section is shown after bonding the first pixel substrate 10 and the second pixel substrate 20. (Refer to...) Figure 1 and Figure 6 After forming the first pixel substrate 10 and the second pixel substrate 20, step S2 is performed to vertically stack and bond the first pixel substrate 10 and the second pixel substrate 20 to form a stacked substrate structure.

[0056] A hybrid bonding process or a fusion bonding process can be used to bond the first dielectric layer 120 and the second dielectric layer 220 together, thereby bonding the first pixel substrate 10 and the second pixel substrate 20. By properly setting the positions of the first infrared pixel region A41 in the first substrate 100 and the second infrared pixel region A42 in the second substrate 200, after the first pixel substrate 10 and the second pixel substrate 20 are bonded, the at least one first infrared pixel region A41 in the first pixel substrate 10 and the at least one second infrared pixel region A42 in the second pixel substrate 20 are vertically aligned (that is, each pair of corresponding first infrared pixel regions A41 and second infrared pixel regions A42 are located on the same straight line perpendicular to the first pixel substrate 10 and the second pixel substrate 20).

[0057] In this embodiment, after bonding the first pixel substrate 10 and the second pixel substrate 20 to form a stacked substrate structure, the first infrared light pixel area A41 and the second infrared light pixel area A42, which are arranged vertically, are laterally distributed and do not overlap with the visible light pixel area in the stacked substrate structure. Therefore, the infrared light sensing element PD2 formed by the second infrared light pixel area A42 and the visible light sensing element PD1 formed by the visible light pixel area are laterally distributed and do not overlap, thus forming different sensing areas, i.e., different pixel units, laterally distributed within the stacked substrate structure. Specifically, the stacked substrate structure includes visible light pixel units (such as...) corresponding to the visible light pixel areas formed (e.g.,...) Figure 6 The diagram shows visible light pixel units PX1, PX2, and PX3, and an infrared light pixel unit PX4 formed corresponding to the first infrared light pixel region A41. Each of the visible light pixel units and infrared light pixel units PX4 extends in the thickness direction of the stacked substrate structure. The visible light sensing element PD1 and the infrared light sensing element PD2 are used to sense visible light and infrared light incident from the side of the first pixel substrate 10 away from the second pixel substrate 20, respectively. That is, the side of the first pixel substrate 10 away from the second pixel substrate 20 is the light incident side. The light radiation incident from the light incident side corresponding to the visible light pixel unit can be sensed by the visible light sensing element PD1 in the first pixel substrate 10 to obtain a visible light signal. At the same time, the light radiation incident corresponding to the infrared light pixel unit PX4 passes through the first pixel substrate 10, the first dielectric layer 110, and the second dielectric layer 210 before entering the second pixel substrate 20 and being sensed by the infrared light sensing element PD2. Since the optical path of the light radiation incident corresponding to the infrared light pixel unit PX4 is relatively long, the infrared light signal is not easy to pass through the depletion layer of the infrared light sensing element PD2 and is easily sensed. The stack thickness of the first dielectric layer 110 and the second dielectric layer 210 is, for example, about 4 μm to 7 μm.

[0058] In this embodiment, when bonding the first pixel substrate 10 and the second pixel substrate 20, the first dielectric layer 110 and the second dielectric layer 210 are bonded to each other. Simultaneously, the first metal interconnect structure 120 and the first metal ring MR1 exposed on the top surface of the first dielectric layer 110 can be bonded to the second metal interconnect structure 220 and the second metal ring MR2 exposed on the top surface of the second dielectric layer 210, respectively, thereby interconnecting the first pixel substrate 10 and the second pixel substrate 20. By bonding the first metal ring MR1 and the second metal ring MR2, a metal ring MR is formed between the first substrate 100 and the second substrate 200, oriented in the direction surrounding the infrared light pixel unit. The metal ring MR forms physical isolation around the infrared light pixel unit PX4, effectively preventing the light signal incident on the infrared light pixel unit PX4 from deviating to areas outside the infrared light pixel unit PX4 when propagating to the infrared light sensing element PD2.

[0059] like Figure 6As shown, after bonding is completed, the first substrate 100 can be thinned from the back side to isolate each of the visible light pixel units and infrared light pixel units PX4 on the back side of the first substrate 100 and form a light incident structure. The thickness of the first substrate 100 after thinning is, for example, 2 μm to 4 μm.

[0060] Figure 7 A cross-section is shown after the deep trench isolation (DTI), filter layer 130, and lens layer 140 are formed on the side of the first pixel substrate 10 away from the second pixel substrate 20. (Refer to...) Figure 7 After bonding the first pixel substrate 10 and the second pixel substrate 20, the manufacturing method may further include the following processes.

[0061] First, the first substrate 100 is thinned from the back side to form a deep trench isolation DTI corresponding to the region between the at least one visible light pixel unit and the at least one infrared light pixel unit PX4. The depth of the deep trench isolation DTI can be set as needed. For example, in one embodiment, the deep trench isolation DTI can completely penetrate the first substrate 100.

[0062] Next, a filter layer 130 is formed on the back side of the first substrate 100. The filter layer 130 includes a black matrix grid (BMG) covering the region between the at least one visible light pixel unit and the at least one infrared light pixel unit PX4, and having openings corresponding to the visible light pixel unit and the infrared light pixel unit PX4, as well as color filter units filling the openings. Figure 7As shown, as an example, a silicon oxide buffer layer and a black matrix material layer can be formed on the back side of the first substrate 100. The black matrix material layer can be made of a material with low transparency, such as black or close to black. Then, the black matrix material layer is etched to form openings corresponding to each visible light pixel unit and infrared light pixel unit PX4. Then, red filter material is filled into the openings corresponding to a portion of the visible light pixel units (such as visible light pixel unit PX3) to form red filter units RF. Green filter material is filled into the openings corresponding to another portion of the visible light pixel units (such as visible light pixel unit PX2) to form green filter units GF. Blue filter material is filled into the openings corresponding to yet another portion of the visible light pixel units (such as visible light pixel unit PX1) to form blue filter units BF. Infrared filter material is filled into the openings corresponding to the infrared light pixel unit PX4 to form infrared filter units IRF. The red filter unit RF filters the incident light, allowing red-band light to enter the visible light sensing element PD1 in the corresponding visible light pixel unit. The green filter unit GF filters the incident light, allowing green-band light to enter the visible light sensing element PD1 in the corresponding visible light pixel unit. The blue filter unit BF filters the incident light, allowing blue-band light to enter the visible light sensing element PD1 in the corresponding visible light pixel unit. The infrared filter unit IRF filters the incident light, allowing infrared-band light to enter the infrared light sensing element PD2 in the corresponding infrared light pixel unit PX4. In another embodiment, the openings corresponding to the infrared light pixel unit PX4 can also be filled with transparent material without infrared light filtering.

[0063] Next, a lens layer 140 is formed on the side of the filter layer 130 away from the first substrate 100. The lens layer 140 includes microlenses formed respectively corresponding to the at least one visible light pixel unit and the at least one infrared light pixel unit PX4.

[0064] Using the CIS device fabrication method described in the above embodiments, after forming the first pixel substrate 10 and the second pixel substrate 20, they are bonded together. The resulting stacked substrate structure includes visible light pixel units corresponding to the visible light pixel region and infrared light pixel units PX4 corresponding to the first infrared light pixel region A41 (or the second infrared light pixel region A42). The different pixel units are laterally offset and non-overlapping, imaging separately without sharing an optical path, thus avoiding mutual interference between optical paths. Compared to the visible light pixel units, the infrared light pixel unit PX4 undergoes a longer optical path before the incident light signal is detected, resulting in enhanced infrared response. Simultaneously, the visible light pixel units have a shorter optical path before the incident light signal is detected, resulting in a smaller depletion layer depth and lower risk of crosstalk between adjacent pixel units. In addition, since infrared light has a longer wavelength, shallow trench isolation (STI) and deep trench isolation (DTI) have weaker crosstalk isolation capabilities for infrared light compared to visible light. By forming a metal ring MR around the infrared pixel unit PX4 located between the first substrate 100 and the second substrate 200, crosstalk isolation for infrared light can be enhanced.

[0065] In some embodiments, after bonding the first pixel substrate 10 and the second pixel substrate 20, the second substrate 200 can be further thinned from the back side (the thickness of the thinned second substrate 100 is, for example, 2 μm to 4 μm), and one or more substrates can be bonded on the side of the second pixel substrate 20 opposite to the first pixel substrate 10. The substrates bonded on the side of the second pixel substrate 20 opposite to the first pixel substrate 10 can be used for, for example, to store or process data.

[0066] In the CIS device fabrication method described in the above embodiments, the first pixel substrate 10 is formed as a back-illuminated substrate and the second pixel substrate 20 is formed as a front-illuminated substrate. The two are electrically interconnected by bonding. However, the present invention is not limited to this. In some other embodiments, the first pixel substrate 10 and the second pixel substrate 20 can both be formed as back-illuminated substrates or front-illuminated substrates, or the first pixel substrate 10 is a front-illuminated substrate and the second pixel substrate 20 is a back-illuminated substrate. By laterally integrating visible light pixel units with shorter incident light optical paths and infrared light pixel units PX4 with longer incident light optical paths, the infrared response capability of the CIS device can be enhanced, and the risk of increased crosstalk between adjacent pixel units can be avoided.

[0067] This invention also relates to a CIS device, which can be formed using the CIS device fabrication method described in the above embodiments or other suitable methods. (See also...) Figures 1 to 7The CIS device includes a stacked substrate structure, which vertically includes a first pixel substrate 10 and a second pixel substrate 20 bonded to each other, and horizontally has at least one visible light pixel unit (e.g., ...) distributed non-overlappingly. Figure 7 The diagram shows visible light pixel units PX1 to PX3 and at least one infrared light pixel unit PX4. The visible light pixel unit includes a visible light sensing element PD1 formed in the first pixel substrate 10, and the infrared light pixel unit PX4 includes an infrared light sensing element PD2 formed in the second pixel substrate 20. The visible light sensing element PD1 and the infrared light sensing element PD2 are used to sense visible light and infrared light incident from the side of the first pixel substrate 10 away from the second pixel substrate 20, respectively.

[0068] like Figure 7 As shown, the first pixel substrate 10 includes a first substrate 100 and a first dielectric layer 110 formed on the side of the first substrate 100 facing the second pixel substrate 20. A visible light sensing element PD1, corresponding to the visible light pixel unit, is located within the first substrate 100. The second pixel substrate 20 includes a second substrate 200 and a second dielectric layer 210 formed on the side of the second substrate 200 facing the first pixel substrate 10, wherein the first dielectric layer 110 and the second dielectric layer 210 are adjacent and bonded. An infrared light sensing element PD2, corresponding to the infrared light pixel unit PX4, is located within the second substrate 200. Optionally, a trench isolation structure (shallow trench isolation STI and / or deep trench isolation DTI) is formed in the first substrate 100, and the at least one visible light pixel unit and the at least one infrared light pixel unit PX4 are isolated in the first substrate 100 by the trench isolation structure.

[0069] As an example, the first pixel substrate 10 is a back-illuminated substrate, and the side of the first pixel substrate 10 away from the second pixel substrate 20 (i.e., the light incident side) is the back side of the first substrate 100. The first dielectric layer 110 is located on the front side of the first substrate 100. The first pixel substrate 10 may also include a first metal interconnect structure 120 formed in the first dielectric layer 110. However, it is not limited to this. In another embodiment, the first pixel substrate 100 is a front-illuminated substrate, and the light incident side is the front side of the first substrate 100. The first dielectric layer 110 is formed on the back side of the first substrate 100.

[0070] like Figure 7As shown, as an example, the second pixel substrate 20 is a front-illuminated substrate, with the light incident side being the front side of the second substrate 200. The second dielectric layer 210 is formed on the front side of the second substrate 100. The second pixel substrate 20 may also include a second metal interconnect structure 220 formed within the second dielectric layer 210. However, it is not limited to this. In another embodiment, the second pixel substrate 20 is a back-illuminated substrate, with the light incident side being the back side of the second substrate 200. The second dielectric layer 210 is formed on the back side of the second substrate 100.

[0071] Reference Figure 7 The first metal interconnect structure 120 may include metal bonding pads located on the top surface of the first dielectric layer 110, and the second metal interconnect structure 220 may include metal bonding pads located on the top surface of the second dielectric layer 210. The first pixel substrate 10 and the second pixel substrate 20 are, for example, hybrid-bonded. At the bonding interface of the first dielectric layer 110 and the second dielectric layer 120, the metal bonding pads on the top surface of the first dielectric layer 110 and the top surface of the second dielectric layer 120 may also be correspondingly bonded, thereby interconnecting the first metal interconnect structure 120 and the second metal interconnect structure 220. In another embodiment, the first metal interconnect structure 120 and the second metal interconnect structure 220 may also be interconnected without bonding.

[0072] like Figure 7 As shown, optionally, the first pixel substrate 10 includes a first metal ring MR1 formed in the first dielectric layer 110. The orthographic projection of the first metal ring MR1 onto the front side of the first substrate 100 is located around the infrared light pixel unit PX4, that is, the infrared light pixel unit PX4 is isolated by the first metal ring MR1 in the first dielectric layer 110. Exemplarily, a shallow trench isolation STI is formed on the front side of the first substrate 100 to isolate each pixel unit. The first metal ring MR1, for example, is connected to the shallow trench isolation STI that isolates the infrared light pixel unit PX4 and extends in the thickness direction of the first dielectric layer 110. The first metal ring MR1 may penetrate part or all of the thickness of the first dielectric layer 110. The first metal ring MR1 helps to enhance the isolation of crosstalk to infrared light.

[0073] like Figure 7 As shown, optionally, the second pixel substrate 20 includes a second metal ring MR2 formed in the second dielectric layer 210. The orthographic projection of the second metal ring MR2 on the front side of the first substrate 100 is also located around the infrared pixel unit PX4, that is, the infrared pixel unit PX4 is isolated by the second metal ring MR2 in the second dielectric layer 210. Exemplarily, a shallow trench isolation STI is formed on the front side of the second substrate 200 to isolate the infrared pixel unit PX4. The second metal ring MR2 is connected to the shallow trench isolation STI to isolate the infrared pixel unit PX4 and extends in the thickness direction of the second dielectric layer 210. The second metal ring MR2 may penetrate part or all of the thickness of the second dielectric layer 210.

[0074] In some embodiments, when the same infrared pixel unit PX4 is isolated by a first metal ring MR1 in the first dielectric layer 110 and by a second metal ring MR2 in the second dielectric layer 210, the first metal ring MR1 and the second metal ring MR2 around the same infrared pixel unit PX4 can be bonded to each other at the bonding interface of the first dielectric layer 110 and the second dielectric layer 210 to form a metal ring MR. The metal ring MR can enhance the isolation of crosstalk to infrared light.

[0075] like Figure 7 As shown, the first pixel substrate 10 may include a deep trench isolation (DTI), a filter layer 130, and a lens layer 140 formed on the back side of the first substrate 100. The deep trench isolation (DTI) is formed corresponding to the region between the at least one visible light pixel unit and the at least one infrared light pixel unit PX4. The filter layer 130 includes a black matrix grid (BMG) covering the region between the at least one visible light pixel unit and the at least one infrared light pixel unit PX4 and having openings corresponding to the visible light pixel unit and the infrared light pixel unit PX4, and color filter units filling the openings. The lens layer 140 is formed on the side of the filter layer 130 away from the first pixel substrate 10, and the lens layer 140 includes microlenses formed corresponding to the at least one visible light pixel unit and the at least one infrared light pixel unit PX4, respectively.

[0076] In the CIS device described in the above embodiments, at least one visible light pixel unit and at least one infrared light pixel unit PX4 are distributed non-overlappingly in the lateral direction. The visible light pixel unit includes a visible light sensing element PD1 formed in the first pixel substrate 10, and the infrared light pixel unit PX4 includes an infrared light sensing element PD2 formed in the second pixel substrate 20. The visible light sensing element PD1 and the infrared light sensing element PD2 are used to sense visible light and infrared light incident from the side of the first pixel substrate 10 away from the second pixel substrate 20, respectively. Compared with the visible light pixel unit, the incident light signal of the infrared light pixel unit PX4 has to travel a longer optical path before being detected, which enhances the infrared response capability. At the same time, the incident light signal of the visible light pixel unit has a shorter optical path before being detected, and the depletion layer depth is smaller, which reduces the risk of crosstalk between adjacent pixel units. By forming a metal ring MR around the infrared light pixel unit PX4 in the region between the first substrate 100 and the second substrate 200, the crosstalk isolation of infrared light can be enhanced.

[0077] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Relevant details can be understood by referring to these examples.

[0078] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A CIS device, characterized in that, The invention includes a stacked substrate structure, which vertically comprises a first pixel substrate and a second pixel substrate bonded to each other, and horizontally comprises at least one visible light pixel unit and at least one infrared light pixel unit that are not overlapping. The visible light pixel unit includes a visible light sensing element formed in the first pixel substrate, and the infrared light pixel unit includes an infrared light sensing element formed in the second pixel substrate. The visible light sensing element and the infrared light sensing element are respectively used to sense visible light and infrared light incident from the side of the first pixel substrate away from the second pixel substrate.

2. The CIS device as described in claim 1, characterized in that, The first pixel substrate includes a first substrate and a first dielectric layer formed on the side of the first substrate facing the second pixel substrate. The second pixel substrate includes a second substrate and a second dielectric layer formed on the side of the second substrate facing the first pixel substrate. The first dielectric layer and the second dielectric layer are adjacent and bonded.

3. The CIS device as described in claim 2, characterized in that, A trench isolation structure is formed in the first substrate, and the at least one visible light pixel unit and the at least one infrared light pixel unit are isolated in the first substrate by the trench isolation structure.

4. The CIS device as described in claim 2, characterized in that, A first metal ring is formed in the first dielectric layer, and the infrared light pixel unit is isolated in the first dielectric layer by the first metal ring; and / or, a second metal ring is formed in the second dielectric layer, and the infrared light pixel unit is isolated in the second dielectric layer by the second metal ring.

5. The CIS device as described in claim 4, characterized in that, When the same infrared pixel unit is isolated by the first metal ring in the first dielectric layer and by the second metal ring in the second dielectric layer, the first metal ring and the second metal ring are bonded to each other at the bonding interface of the first dielectric layer and the second dielectric layer.

6. The CIS device as described in claim 2, characterized in that, The first pixel substrate is a back-illuminated substrate, the first dielectric layer is located on the front side of the first substrate, and the first pixel substrate further includes a first metal interconnect structure formed in the first dielectric layer; the second pixel substrate is a front-illuminated substrate, the second dielectric layer is located on the front side of the second substrate, and the second pixel substrate further includes a second metal interconnect structure formed in the second dielectric layer; the first metal interconnect structure and the second metal interconnect structure are bonded at the bonding interface of the first dielectric layer and the second dielectric layer.

7. The CIS device as described in claim 1, characterized in that, Also includes: A filter layer is formed on the side of the first pixel substrate away from the second pixel substrate. The filter layer includes a black matrix grid covering the area between the at least one visible light pixel unit and the at least one infrared light pixel unit and having openings corresponding to the visible light pixel unit and the infrared light pixel unit, and color filter units filling the openings. as well as A lens layer is formed on the side of the filter layer away from the first pixel substrate, and the lens layer includes microlenses formed respectively corresponding to the at least one visible light pixel unit and the at least one infrared light pixel unit.

8. A method for fabricating a CIS device, characterized in that, include: A first pixel substrate and a second pixel substrate are formed respectively. The first pixel substrate includes at least one visible light pixel region and at least one first infrared light pixel region that are not overlapped in the lateral direction. A visible light sensing element is formed in the visible light pixel region. The second pixel substrate includes at least one second infrared light pixel region that is not overlapped in the lateral direction. An infrared light sensing element is formed in the second infrared light pixel region. as well as The first pixel substrate and the second pixel substrate are vertically stacked and bonded to form a stacked substrate structure, wherein at least one first infrared light pixel region in the first pixel substrate and at least one second infrared light pixel region in the second pixel substrate are vertically aligned one by one. The stacked substrate structure includes visible light pixel units formed corresponding to the visible light pixel regions and infrared light pixel units formed corresponding to the first infrared light pixel regions. The visible light sensing element and the infrared light sensing element are respectively used to sense visible light and infrared light incident from the side of the first pixel substrate away from the second pixel substrate.

9. The manufacturing method as described in claim 8, characterized in that, The first pixel substrate includes: Shallow trench isolation is formed on the front side of the first substrate to define the at least one visible light pixel area and the at least one first infrared light pixel area; A visible light sensing element is formed in the at least one visible light pixel region; and A first pixel circuit element coupled to the visible light sensing element, a first dielectric layer covering the first pixel circuit element, and a first metal interconnect structure formed on the first dielectric layer and connected to the first pixel circuit element are formed on the front side of the first substrate.

10. The manufacturing method as described in claim 9, characterized in that, When forming the first dielectric layer and the first metal interconnect structure, a first metal ring is also formed in the first dielectric layer, and the orthographic projection of the first metal ring on the front side of the first substrate is located around the first infrared pixel region.

11. The manufacturing method as described in claim 9, characterized in that, Forming the second pixel substrate includes: Shallow trench isolation is formed on the front side of the second substrate to define the at least one second infrared pixel region; An infrared light sensing element is formed in the at least one second infrared light pixel region; and A second pixel circuit element coupled to the infrared light sensing element, a second dielectric layer covering the second pixel circuit element, and a second metal interconnect structure formed on the front side of the second substrate are formed thereon; Specifically, when bonding the first pixel substrate and the second pixel substrate, the first dielectric layer and the second dielectric layer are bonded together, and the first metal interconnect structure and the second metal interconnect structure are bonded at the bonding interface between the first dielectric layer and the second dielectric layer.

12. The manufacturing method as described in claim 11, characterized in that, During the formation of the second dielectric layer and the second metal interconnect structure, a second metal ring is also formed in the second dielectric layer, and the orthogonal projection of the second metal ring on the front side of the second substrate is located around the second infrared pixel region.

13. The manufacturing method as described in claim 9, characterized in that, After bonding the first pixel substrate and the second pixel substrate, the fabrication method further includes: Thinning the first substrate from its back side to form a deep trench isolation corresponding to the region between the at least one visible light pixel unit and the at least one infrared light pixel unit; and A filter layer and a lens layer are sequentially formed on the back side of the first substrate.

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