Vertically stacked micro display panel and manufacturing method thereof

Abstract

The present invention relates to a vertically stacked micro display panel, comprising: a back wafer having a plurality of CMOS electrode pads arranged on the upper surface thereof; a plurality of LED stacks each including a light emitting portion stacked in a vertical direction by a bonding layer, the plurality of LED stacks being arranged on the plurality of CMOS electrode pads; and a common electrode formed on the plurality of LED stacks, each of the plurality of LED stacks forming a short channel in a partial region, the short channel including a first short channel formed so as to correspond to the width of the light-emitting section, the first short channel including a second short channel formed so as to correspond to the width of the light-emitting section, the second short channel including a second short channel formed so as to correspond to the width of the light-emitting section, and the first short channel including a second short channel formed so as to correspond to the width of the light-emitting section, and the second short channel including a third short channel formed so as to correspond to the width of the light-emitting section. And a second short channel formed so as to pass through the light-emitting unit. According to the present invention, there is an effect of facilitating the formation of a short channel in a vertically stacked serial connection (tandem) structure.

Description

Vertically stacked micro display panels and their manufacturing methods Technical Field

[0001] This invention relates to a vertically stacked microdisplay panel and its manufacturing method, and more specifically, to a vertically stacked LEDoS microdisplay panel and its manufacturing method that utilizes an engineering monolithic epitaxy wafer and enables each LED stack to emit only a specific color, thereby eliminating the need for a color filter. Background Technology

[0002] The types used to represent the recently much-discussed Metaverse are categorized into four forms: VR (virtual reality), AR (augmented reality), MR (mixed reality), and XR (extended reality). Among these, the future development of the Metaverse ecosystem is expected to center on XR, which serves as the link between VR, AR, and MR. To effectively represent these, a next-generation computing platform software capable of providing innovative user experiences is needed, requiring devices (smart glasses, head-mounted displays, etc.) with microdisplay panels as core components, including those with a diagonal length of less than one inch. In particular, to provide XR users with maximum immersion, visibility, and convenience, while minimizing motion sickness, the development of high-performance microdisplay panel technology is absolutely essential.

[0003] As shown in Figure 1, the existing microdisplay panel 10 combines Si CMOS semiconductor wafer processing with high-resolution, high-brightness ultra-small display processing. The existing microdisplay panel 10 can have a structure that bonds a Si CMOS wafer 11 with a 4” or larger (100) crystal plane having multiple CMOS electrode pads 12, a microLED electrode pad 14, and a 4” or larger transparent wafer 13 having multiple microLED chips 15 via conductive bonding 16. On the one hand, the types of microdisplay panels suitable for XR devices are expected to include LCoS (LC on Si) based on liquid crystal (LC), OLEDoS (OLED on Si) based on OLED (organic light-emitting diode), and LEDoS (LED on Si) based on ultra-small microLEDs with pixel sizes less than 5μm. In the case of VR displays suitable for low pixel density displays, development and mass production are centered around LCoS and OLEDoS.

[0004] However, with the development of metaverse realization technology, the demand for lightweight AR, MR, and XR devices with high pixel density micro-display panels is gradually increasing. Based on this demand, there is an urgent need to develop LEDoS technology, which is theoretically a more ideal solution and has attracted much attention, based on the advantages of inorganic materials. However, a micro-display panel platform for this purpose has not yet been established.

[0005] In XR devices, LEDoS based on ultra-small microLEDs with pixel sizes less than 5μm offers advantages such as excellent performance-to-power ratio (electrical efficiency ratio), short response time, long lifespan due to its inorganic composition, efficient power utilization to reduce heat generation, and extended battery life. In particular, in XR devices, the distance between the display and the eyes is very short, making even slight delays in image transitions susceptible to dizziness and other inconveniences. Therefore, compared to LCoS and OLEDoS with microsecond response times, LEDoS with nanosecond response times is considered the most suitable for XR devices.

[0006] Furthermore, unlike VR, the biggest reason why LEDoS is attracting attention in AR, MR, and XR devices is its brightness and luminous efficiency. Due to the characteristics of smart glasses that can be worn anywhere, high brightness is required even in outdoor environments such as sunlight to achieve normal operation. Theoretically, microLEDs can support brightness of tens to millions of nits. Moreover, although OLEDs are organic materials, microLEDs are inorganic materials, thus having the advantage of high luminous efficiency.

[0007] However, despite the aforementioned advantages, the biggest reason why LEDoS, based on ultra-small microLEDs with pixel sizes less than 5μm, cannot become a major component of XR devices is its inability to achieve mass production. Specifically, LEDoS requires mounting millions of ultra-small microLEDs onto a Si CMOS wafer, resulting in high process complexity, very low yield, increased manufacturing costs, and high component prices. This ultimately translates into higher consumer prices, supplying expensive XR devices, making it difficult to match market demand.

[0008] On the one hand, as shown in Figure 2, the development of LEDoS applicable to microLED light sources of group 3-5 compounds (GaN, GaP, etc.) is carried out through traditional methods such as ① monolithic integration of wafers (or unit chips) composed of microLED arrays on Si CMOS wafers, or ② hybridization between wafers (or unit chips) on blue, green, and red light source wafers (or unit chips) on which Si CMOS wafers or microLED arrays are fabricated.

[0009] To date, one of the biggest obstacles in the development of LEDoS using blue, green, and red microLED light sources composed of group 3-5 compounds has been the difficulty in ensuring solutions for pixels smaller than 5μm. Recently, 5μm-level pixels have been successfully demonstrated using monolithic integration technology. Furthermore, some demonstration products developed based on hybrid technology are fabricated using sapphire flip chips to achieve 10μm-level pixels. Additionally, microtube wiring is used in hybrid technology to similarly reduce the number of pixels to the 5μm level. However, both monolithic integration and hybrid technologies remain impractical solutions with significant difficulties in terms of quality and yield, hindering mass production.

[0010] Regarding the aforementioned monolithic integration and hybrid technologies, they share the common characteristic of assembling a front-plane wafer composed of a group 3-5 compound microLED array and a back-plane SiCMOS wafer composed of numerous IC electrode pad arrays, which are designed and fabricated separately. However, regardless of the method, it is necessary to ultra-finely align the microLED array fabricated at the unit die-level or wafer-level on the SiCMOS wafer. In this case, the alignment is limited by the precision of the process-related equipment, which ultimately has a significant impact on the pixel and the pitch between pixels, making mass production difficult. Therefore, in order to fabricate LEDoS with high resolution, high brightness, and high-speed driving of blue, green, and red microLED light sources with pixels smaller than 5μm and pitch smaller than 3μm, a new alternative solution that can circumvent the aforementioned ultra-fine alignment limitations is needed.

[0011] Consequently, while several impressive demonstration products with 6μm pixels have recently been launched using engineering monolithic epitaxy wafers fabricated through a low-temperature metal bonding process between Si CMOS wafers and microLED array wafers, these products have been deemed unsuitable for mass production due to low quality and yield issues stemming from the low-temperature metal bonding process and the use of small-diameter wafers (below 6 inches). Most importantly, when using existing engineering monolithic epitaxy wafers with metal bonding to fabricate ultra-micro pixels smaller than 3μm for microdisplay panels, even greater difficulties arise during patterning etching.

[0012] As another example, a new engineering monolithic epitaxial wafer method has recently been proposed, which, while making great progress in addressing the limitations on the brightness and resolution of LEDoS for MicroLEDs applicable to group 3-5 compound light sources, can provide a solution for mass production and low-cost fabrication by using 12-inch large-aperture Si CMOS wafers.

[0013] As shown in Figure 3, specifically, in the corresponding technology, the process of utilizing an engineering monolithic epitaxial wafer is implemented through the following four steps: ① First, LED epitaxial wafers are cut to a specified size (e.g., 4mm × 6mm) on a 12-inch large-aperture Si blanket wafer in a unit chip-level arrangement and bonded. Then, after removing the growth wafer and buffer layer of the LED epitaxial wafer, planarization is performed, thereby retaining an LED active layer of a specified thickness (e.g., approximately 1.5μm) on the large-aperture Si blanket wafer, and the LED wafer fab process ends in the form of pixel chips. ② Then, the Si blanket wafer with completed pixel chips is bonded to the 12-inch CMOS IC Si wafer at the wafer level using multilayer metal bonding. ③ Then, the Si blanket wafer is removed. ④ Finally, for the microLED array used as pixels, a final residual process is performed on the CMOS IC Si wafer.

[0014] However, when bonding LED epitaxial unit chips to the Si blanket wafer in step ①, there is a limitation that bonding must be performed on CMOS IC Si wafers of the same size. Furthermore, when bonding with multilayer metals containing low-melting-point metals (Sn, In) in step ②, the overflow of low-melting-point metal components is more likely to occur, leading to short-circuit defects in electrical connections between the microLED sub-pixel array within the panel or with adjacent CMOS IC electrode pad arrays. Further, in step ②, due to the optically opaque nature of the Si blanket wafer and the multilayer metal bonding layer, it is difficult to achieve ultra-micro alignment wafer bonding (bonding) between the Si blanket wafer (i.e., the front plane wafer) and the CMOS IC Si wafer, resulting in defects. Ultra-micro alignment refers to arranging multiple (hundreds to tens of millions) ultra-small pixel chips (microLED arrays) on the Si blanket wafer and the CMOS IC electrode pad arrays on the CMOS IC Si wafer in a 1:1 ratio.

[0015] That is, the engineering monolithic epitaxial wafer access method proposed by the above technology is evaluated as providing a solution for LEDoS based on ultra-small microLEDs with pixel size less than 5μm. However, there are quality and yield problems caused by the use of metals (low temperature, multilayer) in wafer bonding, making it difficult to manufacture high-resolution micro-display panels with ultra-small pixels less than 3μm. In addition, there are also problems caused by some alignment processes. Therefore, new countermeasures are needed.

[0016] Furthermore, the vertically stacked tandem structure in existing micro-display panels still uses color filters to achieve full color, which has disadvantages in terms of color quality, process complexity, and productivity.

[0017] On the one hand, in a vertically stacked series structure, there is a problem that unnecessary sub-pixel emission can occur due to photoexcitation. As shown in Figure 4, to solve this problem, a structure can be formed by etching the portion of each LED stack L except for the light-emitting part 120 used to emit a specific color to form a short channel 180. However, in this case, the etching process is more difficult because it requires deep etching down to the light-emitting part 120 located in the middle layer. Furthermore, the short channel 180 is difficult to form stably due to insufficient filling of conductive material. Therefore, improvements are needed.

[0018] Existing technical documents

[0019] Patent documents

[0020] Patent Document 0001: Korean Patent Publication No. 10-2018-0009116 Summary of the Invention

[0021] The problem to be solved

[0022] The purpose of this invention is to provide a vertically stacked LEDoS micro-display panel and its manufacturing method that utilizes an engineering monolithic epitaxial wafer to enable each LED stack to emit only a specific color, thereby eliminating the need for a color filter, and easily forming short channels in a vertically stacked tandem structure, in order to solve the aforementioned existing problems.

[0023] Solution to the problem

[0024] The objective is achieved by a vertically stacked microdisplay panel. According to the present invention, the vertically stacked microdisplay panel includes: a back wafer with a plurality of CMOS electrode pads arranged on its upper surface; a plurality of LED stacks, each including light-emitting portions stacked vertically by bonding layers and arranged on the plurality of CMOS electrode pads; and a common electrode formed on the plurality of LED stacks. The plurality of LED stacks each form a short channel in a portion of a region, allowing current to flow through the light-emitting portions without the short channel to emit only a specific color. The short channel includes a first short channel formed in a manner corresponding to the width of the light-emitting portion, and a second short channel formed in a manner that penetrates the light-emitting portion.

[0025] Furthermore, the plurality of LED stacks may include: a first LED stack including a first light-emitting portion for emitting a first color; a second LED stack including a second light-emitting portion for emitting a second color; and a third LED stack including a third light-emitting portion for emitting a third color.

[0026] Furthermore, the first LED stack may include a first short channel formed in the third light-emitting portion region, a second short channel formed in a manner that penetrates the second light-emitting portion, and the first light-emitting portion; the second LED stack may include a first short channel formed in the third light-emitting portion region, the second light-emitting portion, and the first short channel formed in the first light-emitting portion region; and the third LED stack may include the third light-emitting portion, the second short channel formed in a manner that penetrates the second light-emitting portion, and the first short channel formed in the first light-emitting portion region.

[0027] Furthermore, the common electrode can be an anode or a cathode.

[0028] The objective is achieved by a method for fabricating a vertically stacked microdisplay panel. According to the present invention, the method for fabricating a vertically stacked microdisplay panel includes: a preparation step, preparing multiple front wafers including a support wafer and light-emitting portions, and a back wafer with multiple CMOS electrode pads arranged on its upper surface; a stacking step, repeatedly performing the process of bonding one front wafer to another through a bonding layer and then removing the support wafer from the other front wafer, thereby forming a stack of multiple light-emitting portions vertically stacked on the support wafer; a first processing step, after bonding a temporary wafer to one side of the stack, removing the support wafer, and then forming a short channel on the other side of the stack; a bonding step, in... After the back wafer is bonded to the stack, the temporary wafer is removed to stack multiple light-emitting portions on the back wafer; in the second processing step, the short channel is formed on one side of the stack; in the etching step, the stack is etched to separate them in preset units, so that multiple LED stacks are respectively arranged on multiple CMOS electrode pads; and in the forming step, a common electrode is formed on the multiple LED stacks, and the multiple LED stacks respectively pass current to the light-emitting portions without the short channel to emit only a specific color, the short channel including a first short channel formed in a manner corresponding to the width of the light-emitting portion, and a second short channel formed in a manner that penetrates the light-emitting portion.

[0029] Furthermore, the plurality of LED stacks may include: a first LED stack including a first light-emitting portion for emitting a first color; a second LED stack including a second light-emitting portion for emitting a second color; and a third LED stack including a third light-emitting portion for emitting a third color.

[0030] Furthermore, the first LED stack may include a first short channel formed in the third light-emitting portion region, a second short channel formed in a manner that penetrates the second light-emitting portion, and the first light-emitting portion; the second LED stack may include a first short channel formed in the third light-emitting portion region, the second light-emitting portion, and the first short channel formed in the first light-emitting portion region; and the third LED stack may include the third light-emitting portion, the second short channel formed in a manner that penetrates the second light-emitting portion, and the first short channel formed in the first light-emitting portion region.

[0031] Furthermore, the common electrode can be an anode or a cathode.

[0032] The objective is achieved by a method for fabricating a vertically stacked microdisplay panel. According to the present invention, the method includes: a preparation step, preparing multiple front wafers including a support wafer and light-emitting portions, and a back wafer with multiple CMOS electrode pads arranged on its upper surface; a stacking step, repeatedly performing the process of bonding one front wafer to another through a bonding layer and then removing the support wafer from the other front wafer, thereby forming a stack of multiple light-emitting portions vertically stacked on the support wafer; a first processing step, forming a short channel on one side of the stack; a second processing step, bonding a temporary wafer to one side of the stack and then removing the support wafer, after which… The short channel is formed on the other side of the stack; in the bonding step, after bonding the stack to the back wafer, the temporary wafer is removed to stack multiple light-emitting portions on the back wafer; in the etching step, the stack is etched to separate them in preset units, such that multiple LED stacks are respectively arranged on multiple CMOS electrode pads; and in the forming step, a common electrode is formed on the multiple LED stacks, and the multiple LED stacks respectively pass current to the light-emitting portions without the short channel to emit only a specific color, wherein the short channel includes a first short channel formed in a manner corresponding to the width of the light-emitting portion, and a second short channel formed in a manner that penetrates the light-emitting portion.

[0033] Furthermore, the plurality of LED stacks may include: a first LED stack including a first light-emitting portion for emitting a first color; a second LED stack including a second light-emitting portion for emitting a second color; and a third LED stack including a third light-emitting portion for emitting a third color.

[0034] Furthermore, the first LED stack may include a first short channel formed in the third light-emitting portion region, a second short channel formed in a manner that penetrates the second light-emitting portion, and the first light-emitting portion; the second LED stack may include a first short channel formed in the third light-emitting portion region, the second light-emitting portion, and the first short channel formed in the first light-emitting portion region; and the third LED stack may include the third light-emitting portion, the second short channel formed in a manner that penetrates the second light-emitting portion, and the first short channel formed in the first light-emitting portion region.

[0035] Furthermore, the common electrode can be an anode or a cathode.

[0036] The effects of the invention

[0037] According to the present invention, even when using a vertically stacked tandem structure, color filters are not required. Therefore, the color quality of microdisplays can be significantly improved, and the complexity of the process and productivity can be greatly reduced.

[0038] Furthermore, according to the present invention, unlike the conventional monolithic integration or hybrid methods that have arrangement problems, an engineering monolithic epitaxial wafer with multiple LED light-emitting parts is first fabricated by bonding red, green, and blue LED epitaxial wafers. Then, the stack of engineering monolithic epitaxial wafers can be etched and separated in a predetermined unit, so that multiple LED stacks are arranged on multiple CMOS electrode pads. This not only allows the use of small-diameter wafers of 6 inches or less, but also large-diameter wafers of 8 inches or more, thereby significantly increasing the product yield.

[0039] Furthermore, according to the present invention, since both the bonding layer and the ohmic contact electrode are made of transparent ceramic material, etching is not only convenient in the plasma dry process for arranging LED stacks, but also avoids the problem of re-deposition of etching byproducts. Moreover, since the above-mentioned etching is convenient, it provides the advantage of being more conducive to the fabrication of high-resolution microdisplays with ultra-micro pixels smaller than 3 μm.

[0040] Furthermore, according to the present invention, after stacking red, green and blue LED light-emitting parts on a temporary wafer to form a stack, this is transferred to a back wafer, and then etched in pixel units to form an LED stack. Therefore, it has the effect of preventing misalignment between the red, green and blue LED light-emitting parts.

[0041] Furthermore, according to the present invention, it has the effect of facilitating the formation of short channels in a vertically stacked tandem structure.

[0042] Furthermore, according to the present invention, since red light is not absorbed by other light-emitting parts, the luminous efficiency of red light can be significantly improved in a vertically stacked tandem structure.

[0043] Furthermore, in each LED stack of the present invention, in addition to the light-emitting part emitting the corresponding color, other light-emitting parts are partially removed. Therefore, the problem of unwanted sub-pixel light emission caused by photoexcitation due to short-wavelength blue light can be reduced.

[0044] On the one hand, the effects of the present invention are not limited to those mentioned above, but may include a variety of effects that are self-evident to those skilled in the art to which this invention pertains, as will be described below. Attached Figure Description

[0045] Figure 1 shows the structure of a prior art microdisplay panel.

[0046] Figure 2 illustrates the existing LEDoS development method.

[0047] Figure 3 illustrates a method for engineering monolithic epitaxial wafers using existing technologies.

[0048] Figure 4 shows an example of a micro-display panel structure with short channels.

[0049] Figure 5 is a sequence diagram of the manufacturing method of the vertically stacked micro display panel according to the first embodiment of the present invention.

[0050] Figures 6 to 9 illustrate the process of preparing the front wafer in the method for fabricating a vertically stacked microdisplay panel according to the first embodiment of the present invention.

[0051] Figure 10 illustrates the process of preparing the back wafer in the method for fabricating a vertically stacked microdisplay panel according to the first embodiment of the present invention.

[0052] Figures 11 to 13 illustrate the process of manufacturing a vertically stacked microdisplay panel according to a method of manufacturing a vertically stacked microdisplay panel according to a first embodiment of the present invention.

[0053] Figure 14 shows a vertically stacked micro-display panel according to a first embodiment of the present invention.

[0054] Figure 15 is a sequence diagram of the manufacturing method of the vertically stacked micro display panel according to the second embodiment of the present invention.

[0055] Figures 16 to 18 illustrate the process of manufacturing a vertically stacked microdisplay panel according to a second embodiment of the present invention.

[0056] Figure 19 shows a vertically stacked micro-display panel according to a second embodiment of the present invention.

[0057] Explanation of reference numerals in the attached figures

[0058] 10: Existing microdisplay panels

[0059] 11: Si CMOS wafer

[0060] 12: CMOS electrode pads

[0061] 13: Transparent wafer

[0062] 14: microLED electrode pads

[0063] 15: microLED chip

[0064] 16: Conductive bonding

[0065] S100: Method for manufacturing a vertically stacked micro-display panel according to the first embodiment of the present invention

[0066] S110: Preparation Steps

[0067] S120: Stacking Steps

[0068] S130: First processing step

[0069] S140: Joining Step

[0070] S150: Second processing step

[0071] S160: Etching Step

[0072] S170: Formation Steps

[0073] 100: Vertically stacked micro display panel of the first embodiment of the present invention

[0074] 110, 210: Front wafer

[0075] S: Support wafer

[0076] 120: Light-emitting part

[0077] 111, 211: First pre-wafer

[0078] 121: First Light-Emitting Part

[0079] 112, 212: Second pre-wafer

[0080] 122: Second light-emitting part

[0081] 113, 213: Third pre-wafer

[0082] 123: Third Light-Generating Part

[0083] L: LED stack

[0084] L1: First LED stack

[0085] L2: Second LED stack

[0086] L3: Third LED stack

[0087] 1201: First semiconductor region

[0088] 1202: Second semiconductor region

[0089] 1203: Active region

[0090] 124: Ohmic contact electrode

[0091] G: Wafer growth

[0092] T: Temporary wafer

[0093] B: Bonding layer

[0094] 130a: First bonding layer

[0095] 130b: Second bonding layer

[0096] 140: Backside wafer

[0097] 141: CMOS electrode pads

[0098] 150: Mold Department

[0099] 160: Common Electrode

[0100] 171: Transmission layer

[0101] 172: Residual Layer

[0102] 180: Short Channel

[0103] 181: First Short Channel

[0104] 182: Second Short Channel

[0105] S200: Method for manufacturing a vertically stacked micro-display panel according to the second embodiment of the present invention

[0106] S210: Preparation Steps

[0107] S220: Stacking Steps

[0108] S230: First processing step

[0109] S240: Second processing step

[0110] S250: Joining Step

[0111] S260: Etching Step

[0112] S270: Formation Steps

[0113] 200: A vertically stacked micro-display panel according to a second embodiment of the present invention. Detailed Implementation

[0114] Hereinafter, some embodiments of the present invention will be described in detail with reference to the illustrative accompanying drawings. It should be noted that, in assigning reference numerals to the structural elements in the various drawings, even when shown in different drawings, the same reference numerals should be assigned to the same structural elements as much as possible.

[0115] Furthermore, in the process of describing the embodiments of the present invention, detailed descriptions of related well-known structures or functions will be omitted if it is determined that such detailed descriptions may hinder the description of the embodiments of the present invention.

[0116] Furthermore, in describing the structural elements of the embodiments of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish its structural elements from other structural elements, and the nature, order, or sequence of the corresponding structural elements are not limited by these terms.

[0117] Hereinafter, the manufacturing method S100 of the vertically stacked micro display panel of the first embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[0118] Figure 5 is a sequence diagram of the fabrication method of the vertically stacked microdisplay panel according to the first embodiment of the present invention. Figures 6 to 9 show the process of preparing the front wafer in the fabrication method of the vertically stacked microdisplay panel according to the first embodiment of the present invention. Figure 10 shows the process of preparing the back wafer in the fabrication method of the vertically stacked microdisplay panel according to the first embodiment of the present invention. Figures 11 to 13 show the process of fabricating the vertically stacked microdisplay panel according to the fabrication method of the vertically stacked microdisplay panel according to the first embodiment of the present invention.

[0119] As shown in Figures 5 to 13, the manufacturing method S100 of the vertically stacked micro display panel of the first embodiment of the present invention includes a preparation step S110, a stacking step S120, a first processing step S130, a bonding step S140, a second processing step S150, an etching step S160, and a forming step S170.

[0120] Preparation step S110 is the step of preparing multiple front wafers 110, 210 and back wafers 140.

[0121] Multiple front wafers 110 and 210 are used to emit different colors. These front wafers 110 and 210 may include a first front wafer 111 or 211 for emitting a first color, a second front wafer 112 or 212 for emitting a second color different from the first color, and a third front wafer 113 or 213 for emitting a third color different from both the first and second colors. On one hand, the first, second, and third colors may be, for example, red, green, and blue, but are not limited to these and may include a variety of other colors.

[0122] The first front wafers 111 and 211 include a supporting wafer S and a first light-emitting portion 121 disposed on the upper part of the supporting wafer S; the second front wafers 112 and 212 include a supporting wafer S and a second light-emitting portion 122 disposed on the upper part of the supporting wafer S; and the third front wafers 113 and 213 include a supporting wafer S and a third light-emitting portion 123 disposed on the upper part of the supporting wafer S.

[0123] The light-emitting part 120 is used to emit light, which can emit blue light, green light or red light. In the present invention, when the light-emitting part 120 emits blue light or green light, in the group 3-5 compound semiconductor, binary, ternary or quaternary compounds such as InN, InGaN, GaN, AlGaN, AlN, AlGaInN, etc., which are group 3 (Al, Ga, In) nitride semiconductors, can be arranged in appropriate positions and sequences on the initial growth wafer G, and epitaxial growth can be realized.

[0124] In particular, in order to emit blue or green light, a high-quality InGaN group 3 nitride semiconductor with In composition needs to be formed on top of a group 3 nitride semiconductor composed of GaN, AlGaN, AlN, and AlGaInN, but it is not limited to this.

[0125] Furthermore, in this invention, when the light-emitting part 120 emits red light, binary, ternary, and quaternary compound semiconductors such as InP, InGaP, GaP, AlInP, AlGaP, AlP, and AlGaInP, which are group 3 (Al, Ga, In) phosphide semiconductors, can be arranged in appropriate positions and sequences on the initial growth wafer G to achieve epitaxial growth. Moreover, recently, in order to further improve the development of equipment and process technologies and the value of display panel products, when emitting red light, a high-quality group 3 nitride semiconductor with a high In content of 30% or more, other than group 3 phosphide semiconductors, can be formed first on top of the group 3 nitride semiconductor composed of GaN, AlGaN, AlN, and AlGaInN.

[0126] In particular, in order to emit red light, a high-quality InGaP phosphide semiconductor with a high In composition is required. This is first formed on top of a phosphide semiconductor composed of GaP, AlInP, AlGaP, AlP, and AlGaInP, but it is not limited to this. The following explanation will focus on a phosphide semiconductor.

[0127] More specifically, each light-emitting portion 120 includes a first semiconductor region 1201 (e.g., a p-type semiconductor region), an active region 1203 (e.g., multi quantum wells, MQWs), and a second semiconductor region 1202 (e.g., an n-type semiconductor region). It may have a structure in which the second semiconductor region 1202, the active region 1203, and the first semiconductor region 1201 are epitaxially grown sequentially on the growth wafer G, and ultimately contains multiple layers of group III nitrides. It typically has an overall thickness of about 5.0 to 8.0 μm, but is not limited to this.

[0128] The first semiconductor region 1201, active region 1203, and second semiconductor region 1202 can each be formed as a single layer or multiple layers. Although not shown, before the epitaxial growth of the light-emitting portion 120 on the upper part of the growth wafer G, necessary layers such as a buffer layer can be additionally provided to achieve high quality of the epitaxially grown light-emitting portion 120. For example, to achieve stress relief and improve film quality, the buffer layer may include a compliant layer (CL) composed of a nucleation layer (NL) and an un-doped semiconductor region, typically set to a thickness of about 4.0 μm. Furthermore, when the growth wafer G is removed using laser lift-off (LLO) technology, a sacrificial layer (SL) can be provided between the nucleation layer and the undoped semiconductor region, and the seed layer can function as a sacrificial layer.

[0129] The second semiconductor region 1202 has a second conductivity and is formed on the growth wafer G. This second semiconductor region 1202 may have a thickness of 2.0 to 3.5 μm.

[0130] The active region 1203 generates light by recombination of electrons and holes and is formed in the second semiconductor region 1202. This active region 1203 can have multiple layers with a thickness of tens of nm.

[0131] The first semiconductor region 1201 has a first conductivity (p-type) and is formed in the active region 1203. This first semiconductor region 1201 may have multiple layers with a thickness of tens of nm to several μm, and the surface may have gallium polarity (Ga-polarity).

[0132] That is, the active region 1203 is located between the first semiconductor region 1201 and the second semiconductor region 1202. If the holes of the first semiconductor region 1201, which is a p-type semiconductor region, and the electrons of the second semiconductor region 1202, which is an n-type semiconductor region, are recombinated in the active region 1203, light can be generated.

[0133] Furthermore, during the preparation of the pre-wafer 110, at least one of the upper or lower surfaces of the light-emitting portion 120 may be formed with an optically transparent and conductive ohmic contact electrode 124 that makes an ohmic contact with and is electrically connected to the light-emitting portion 120, as will be described later.

[0134] The support wafer S is used to support the light-emitting part 120 (first light-emitting part 121, second light-emitting part 122 or third light-emitting part 123) disposed on the upper part. If the initial growth wafer G is not removed, the growth wafer G can be the support wafer S, and can be an additional wafer bonded in order to remove the initial growth wafer G.

[0135] The following describes the fabrication process of the front wafer 110 used to form the cathode common electrode 160 in the vertical stacked micro display panel 100 of the present invention, in which the light-emitting portion 120 is stacked into an n-side up structure.

[0136] As shown in Figure 6, the process of fabricating the first front wafer 111 is as follows.

[0137] In the case of the first front wafer 111 used to emit red light, the second semiconductor region 1202, the active region 1203, and the first semiconductor region 1201 can be epitaxially grown sequentially on the GaAs growth wafer G. A transparently conductive p-type ohmic contact electrode 124 is then formed on the upper surface of the first semiconductor region 1201. Subsequently, a transparently conductive second bonding layer 130b is deposited on the ohmic contact electrode 124, thereby preparing the front wafer 110 in a p-side-up configuration. At this time, the growth wafer G can function as a support wafer S and can have a structure in which the support wafer S, the light-emitting portion 120, the ohmic contact electrode 124, and the second bonding layer 130b are sequentially stacked.

[0138] Furthermore, as shown in Figure 6, the process of fabricating the second front wafer 112 in this embodiment is as follows.

[0139] In the case of the second front wafer 112 used to emit green light, the second semiconductor region 1202, the active region 1203, and the first semiconductor region 1201 are epitaxially grown sequentially on the sapphire (α-phase Al2O3) growth wafer G. A transparently conductive p-type ohmic contact electrode 124 is then formed on the upper surface of the first semiconductor region 1201. Subsequently, a transparently conductive second bonding layer 130b is deposited on the ohmic contact electrode 124, thereby preparing the front wafer 110 in a p-side-up configuration. At this time, the growth wafer G serves as a support for the wafer S and can have a structure in which the support wafer S, the light-emitting portion 120, the ohmic contact electrode 124, and the second bonding layer 130b are sequentially stacked.

[0140] Furthermore, as shown in Figure 7, the process of fabricating the third front wafer 113 in this embodiment is as follows.

[0141] In the case of the third front wafer 113 used to emit blue light, the second semiconductor region 1202, the active region 1203, and the first semiconductor region 1201 are sequentially epitaxially grown on the sapphire (α-phase Al2O3) growth wafer G. A p-type ohmic contact electrode 124 with transparent conductivity is formed on the upper surface of the first semiconductor region 1201. Then, the support wafer S and the ohmic contact electrode 124 are bonded together through the bonding layer B. Next, the growth wafer G is separated from the light-emitting portion 120 using laser liftoff (LLO) technology, and the second semiconductor region 1202 is etched to reduce its thickness. Then, an n-type ohmic contact electrode 124 with transparent conductivity is formed on the surface of the second semiconductor region 1202 with reduced thickness, and a second bonding layer 130b is deposited on the n-type ohmic contact electrode 124, thereby preparing the front wafer 110 in an n-side-up configuration. At this time, in addition to optically transparent materials such as sapphire or glass, the supporting wafer S can also be formed of Si material with (111), (110) or (100) crystal planes, but is not limited to this, and can have a structure in which the supporting wafer S, bonding layer B, ohmic contact electrode 124, light-emitting part 120, ohmic contact electrode 124 and second bonding layer 130b are stacked in sequence.

[0142] On one hand, the following describes the fabrication process of the front wafer 210 used to form the anode common electrode 160 in the vertical stacked micro display panel 100 of the present invention, in which the light-emitting portion 120 is stacked into a p-side up structure.

[0143] As shown in Figure 8, the process of fabricating the first front wafer 211 in this embodiment is as follows.

[0144] In the case of the first front wafer 211 used to emit red light, the second semiconductor region 1202, the active region 1203, and the first semiconductor region 1201 are epitaxially grown sequentially on the GaAs growth wafer G. A p-type ohmic contact electrode 124 with transparent conductivity is formed on the upper surface of the first semiconductor region 1201. Then, the support wafer S and the ohmic contact electrode 124 are bonded together through the bonding layer B. Next, the growth wafer G is separated from the light-emitting part 120 using chemical lift-off (CLO) technology, and the second semiconductor region 1202 is etched to reduce its thickness. Then, an n-type ohmic contact electrode 124 with transparent conductivity is formed on the surface of the second semiconductor region 1202 with reduced thickness, and a second bonding layer 130b is deposited on the n-type ohmic contact electrode 124 to prepare the front wafer 210 in an n-side-up configuration. At this time, in addition to optically transparent materials such as sapphire or glass, the supporting wafer S can also be formed of Si material with (111), (110) or (100) crystal planes, but is not limited to this, and can have a structure in which the supporting wafer S, bonding layer B, ohmic contact electrode 124, light-emitting part 120, ohmic contact electrode 124 and second bonding layer 130b are stacked in sequence.

[0145] Furthermore, as shown in Figure 8, the process of fabricating the second front wafer 212 in this embodiment is as follows.

[0146] In the case of the second front wafer 212 used to emit green light, the second semiconductor region 1202, the active region 1203, and the first semiconductor region 1201 are sequentially epitaxially grown on the sapphire (α-phase Al2O3) growth wafer G. A p-type ohmic contact electrode 124 with transparent conductivity is formed on the upper surface of the first semiconductor region 1201. Then, the support wafer S and the ohmic contact electrode 124 are bonded together through the bonding layer B. Next, the growth wafer G is separated from the light-emitting part 120 using laser liftoff (LLO) technology, and the second semiconductor region 1202 is etched to reduce its thickness. Then, an n-type ohmic contact electrode 124 with transparent conductivity is formed on the surface of the second semiconductor region 1202 with reduced thickness, and a second bonding layer 130b is deposited on the n-type ohmic contact electrode 124 to prepare the front wafer 210 in an n-side up configuration. At this time, in addition to optically transparent materials such as sapphire or glass, the supporting wafer S can also be formed of Si material with (111), (110) or (100) crystal planes, but is not limited to this, and can have a structure in which the supporting wafer S, bonding layer B, ohmic contact electrode 124, light-emitting part 120, ohmic contact electrode 124 and second bonding layer 130b are stacked in sequence.

[0147] Furthermore, as shown in Figure 9, the process of fabricating the third front wafer 213 in this embodiment is as follows.

[0148] In the case of the third front wafer 213 used to emit blue light, after the second semiconductor region 1202, the active region 1203, and the first semiconductor region 1201 are sequentially epitaxially grown in a sapphire (α-phase Al2O3) growth wafer G, which is an optically transparent wafer that transmits 100% (theoretically) a laser beam (single wavelength light) without absorption and has high-temperature heat resistance, a p-type ohmic contact electrode 124 with transparent conductivity is formed on the upper surface of the first semiconductor region 1201. Then, a second bonding layer 130b with transparent conductivity is deposited on the ohmic contact electrode 124, thereby preparing the front wafer 210 in a p-side up configuration. At this time, the growth wafer G serves to support the wafer S, and in addition to optically transparent materials such as sapphire or glass, it can also have a structure in which the supporting wafer S, the light-emitting part 120, the ohmic contact electrode 124, and the second bonding layer 130b are sequentially stacked.

[0149] On the one hand, in the case of green light and blue light, instead of sapphire (α-phase Al2O3) grown wafer G, a light-emitting part 120 with blue light or green light can also be formed on Si with (111) crystal plane. At this time, the Si grown wafer G can be separated and removed by mechanical polishing or chemical lift-off (CLO) technology.

[0150] Furthermore, in this invention, the materials used for the growth wafer G, the support wafer S, and / or the temporary wafer T can all be silicon (Si) or sapphire, but the choice of materials can be determined according to the wafer bonding method.

[0151] For example, when surface activated bonding is performed at room temperature, it is fine to choose different materials such as silicon (Si) or sapphire regardless of their coefficient of thermal expansion. However, when wafer bonding is performed between the growth wafer G, the support wafer S, the temporary wafer T, and the back wafer 140, and bonding is performed at a temperature above 50°C, or when annealing is performed at a temperature above 50°C without removing one side of the wafer after bonding is achieved between the wafers, it is necessary to choose wafers of the same material.

[0152] On the one hand, during the fabrication process of the aforementioned front wafers 110 and 210, before forming the ohmic contact electrode 124 on the surface of the first semiconductor region 1201 or the surface of the second semiconductor region 1202, the corresponding surfaces can be polished by mechanical polishing (MP) or chemical-mechanical polishing (CMP) respectively, and planarization can be smoothly obtained so that a smooth surface can be obtained when the surface of the first semiconductor region 1201 is exposed (p-sideup form) or the surface of the second semiconductor region 1202 is exposed (n-sideup form).

[0153] Furthermore, the ohmic contact electrodes 124 of the front wafers 110 and 210 are formed of a transparent conductive material. When the ohmic contact electrode 124 is formed in contact with the first semiconductor region 1201, which is a p-type semiconductor, the material of the ohmic contact electrode 124 may include NiO, PtO, PdO, AgO2, Au, Rh2O3, RuO2, In2O3, SnO2, ZnO, IZO, ITO, and IGZO. When the ohmic contact electrode 124 is formed in contact with the second semiconductor region 1202, which is an n-type semiconductor, the material of the ohmic contact electrode 124 may include TiN, CrN, VN, In2O3, SnO2, ZnO, IZO, ITO, and IGZO. Furthermore, compared to the surface of the first semiconductor region 1201 with gallium polarity, the surface roughness of the second semiconductor region 1202 with nitrogen polarity is very large. Therefore, preferably, before forming the transparent conductive ohmic contact electrode 124, a chemical-mechanical polishing (CMP) process is introduced to polish the surface of the second semiconductor region 1202 to achieve planarization.

[0154] Furthermore, the surfaces of the ohmic contact electrodes 124 formed on the front wafers 110 and 210 can be polished by mechanical polishing (MP) or chemical-mechanical polishing (CMP), respectively, and planarization can be achieved smoothly.

[0155] Hereinafter, the process of stacking the light-emitting portion 120 of the vertically stacked micro-display panel 100 of the present invention into an n-side up structure and forming a cathode common electrode 160 will be described as an example.

[0156] As shown in Figure 10, the back wafer 140 is an active-matrix (AM) driven IC, meaning it is a CMOS wafer with multiple CMOS electrode pads 141 arranged in an array on its upper surface. A passivation layer can be formed on the upper surface of this back wafer 140 to prevent partial exposure of the multiple CMOS electrode pads 141. When the front wafer 110 is bonded, a portion of the passivation layer can be etched to expose the multiple CMOS electrode pads 141.

[0157] After exposing the upper surfaces of the plurality of CMOS electrode pads 141, a first bonding layer 130a is formed on the upper surface of the back wafer 140 using a conductive material. Preferably, the first bonding layer is formed of an optically transparent conductive material.

[0158] The back wafer 140 can be formed from a Si wafer with a (100) crystal plane. According to the standard CMOS IC process, it can be formed from an 8-inch or 12-inch Si wafer. However, considering that the usual LED wafer (front wafer 110) used for bonding is 4 inches or 6 inches, the size of the back wafer is not particularly limited.

[0159] The stacking step S120 is a step of repeatedly removing the support wafer S of the other front wafer 110 after bonding one front wafer 110 to another front wafer 110 through the second bonding layer 130b, thereby forming a stack body on the support wafer S composed of multiple light-emitting parts 120 stacked vertically.

[0160] The second bonding layer 130b can be made of an optically transparent and electrically insulating transparent insulating material (e.g., SiO2, SiN). x The bonding agent can be formed from an optically transparent and conductive transparent conductive material (e.g., ITO, IZO, ZnO), and preferably, to ensure bonding strength, it is formed from a transparent insulating material.

[0161] Optical transparency means that the light (including visible light) used in the photolithography process has a transmittance of more than 80% or translucent (transparent with a transmittance of more than 50%) within the wavelength band. Conductivity means having a conductivity of less than 10... -3 Resistance in Ω / cm.

[0162] When the second bonding layer 130b is formed from a transparent insulating material, the transparent insulating material may be formed from oxides such as SiO2, Al2O3, HfO2, ZrO2 or Ta2O5 or nitrides such as Si3N4 or AlN, but is not limited to these.

[0163] Furthermore, when the second bonding layer 130b is formed of a transparent conductive material, the transparent conductive material can be formed of a ceramic material, such as a transparent conductive oxide (TCO), a transparent conductive nitride (TCN), or a transparent conductive oxide nitride (TCON). In this case, if the ceramic material is a transparent conductive oxide, it can contain In₂O₃, SnO₂, ZnO, IZO, ITO, and IGZO; if the ceramic material is a transparent conductive nitride, it can contain TiN, CrN, and VN; and if the ceramic material is a transparent conductive oxide nitride, it can contain InON, SnON, ZnON, IZON, ITON, and IGZON, but is not limited to these.

[0164] On the one hand, the second bonding layer 130b can also be formed of an opaque conductive metallic material (e.g., Au, Ag, Cu, Sn, In, Zn).

[0165] As shown in Figure 11, specifically, for example, in the stacking step S120, after bonding the second front wafer 112 (emitting green light in a p-side-up shape) to the third front wafer 113 (emitting blue light in an n-side-up shape) via the second bonding layer 130b, the support wafer S of the second front wafer 112 is removed using laser lift-off or the like. Then, the second semiconductor region 1202 of the second light-emitting portion 122, exposed by removing the support wafer S, is etched to reduce its thickness. An n-type ohmic contact electrode 124 is then formed on the surface of the second semiconductor region 1202, and the second bonding layer 130b is deposited on the n-type ohmic contact electrode 124.

[0166] Then, after bonding the first front wafer 111, which emits red light in a p-side-up configuration, through the second bonding layer 130b, the support wafer S of the first front wafer 111 is removed using chemical stripping or the like. Afterwards, the second semiconductor region 1202 of the first light-emitting portion 121, exposed by removing the support wafer S, is etched to reduce its thickness, and an n-type ohmic contact electrode 124 is formed on the surface of the second semiconductor region 1202. At this time, while etching the second semiconductor region 1202 of the first light-emitting portion 121, a surface texturing process can be performed on the surface of the second semiconductor region 1202.

[0167] Then, in this invention, a heat treatment at a high temperature of 200–900°C is performed to improve the bonding strength of the second bonding layer 130b. That is, in this invention, after all the RGB light sources are stacked to form a stack, a high-temperature heat treatment is performed to ensure the bonding strength between the RGB epitaxial layers, and then the RGB stack structure can be bonded to the CMOS Si back wafer 140 in one step.

[0168] In this way, a support wafer S, a bonding layer B, a third light-emitting portion 123 with ohmic contact electrodes 124 formed on the upper and lower surfaces, a second bonding layer 130b, a second light-emitting portion 122 with ohmic contact electrodes 124 formed on the upper and lower surfaces, a second bonding layer 130b, and a first light-emitting portion 121 with ohmic contact electrodes 124 formed on the upper and lower surfaces are stacked vertically to form a stack on the support wafer S. The stack is then heat-treated at high temperature to ensure strong bonding between the RGB epitaxial layers.

[0169] On the one hand, the stacking step S120 can be performed without using high voltage or an external electric field, but by utilizing the property of smooth surfaces to adhere to each other using van der Waals forces. Therefore, preferably, before bonding the front wafers 110 together, a chemical-mechanical polishing (CMP) process is introduced to make the roughness of each bonding surface very low (Rq, <0.5nm@2μm×2μm), and free of impurities or particles between the surfaces. Therefore, in the stacking step S120, before bonding the front wafers 110 together, the surface of the second bonding layer 130b of the front wafers 110 can be polished by mechanical polishing (MP) or chemical-mechanical polishing (CMP), respectively, and planarization can be smoothly achieved.

[0170] The first processing step S130 is to bond a temporary wafer T on one side of the stack, remove the support wafer S, and then form a short channel 180 on the other side of the stack.

[0171] Specifically, in the first processing step S130, after the temporary wafer T is bonded to one side of the stack body, i.e., the upper n-type ohmic contact electrode 124, by the bonding layer B, the lower supporting wafer S is separated by laser lift-off or chemical lift-off, and the bonding layer B is removed.

[0172] Subsequently, in the first processing step S130, the third light-emitting portion 123, on which the ohmic contact electrode 124 is formed, is first etched in the upper and lower portions of the portion where the first LED stack L1 will be formed and the portion where the second LED stack L2 will be formed, until the second bonding layer 130b is exposed and removed. Then, after forming a through-hole in the portion where the first LED stack L1 will be formed, penetrating the second light-emitting portion 122, a conductive material is filled into the through-hole to form a second short channel 182.

[0173] At this time, the through hole can be formed in such a way that it penetrates the active region 1203 of the second light-emitting part 122. In particular, preferably, when the second bonding layer 130b is formed of a transparent insulating material, it also penetrates the second bonding layer 130b between the third light-emitting part 123 and the second light-emitting part 122 and the second bonding layer 130b between the second light-emitting part 122 and the first light-emitting part 121, and is formed until the surface of the ohmic contact electrode 124 of the first light-emitting part 121 is exposed.

[0174] Subsequently, in the first processing step S130, the etched portion is filled with a conductive material to form a first short channel 181.

[0175] At this time, after the first short channel 181 is formed, the corresponding material can either remain on the ohmic contact electrode 124 of the unetched third light-emitting part 123 or be removed. If the corresponding material remains on the ohmic contact electrode 124 of the third light-emitting part 123, a residual layer 172 is formed. After the etched part is filled with conductive material, a different material can also be used to form the residual layer 172.

[0176] Furthermore, the short channel 180 and the residual layer 172 formed on the other side of the stack can be formed by a transparent conductive material or a reflective opaque conductive material, respectively.

[0177] When the short channel 180 and the residual layer 172 are formed by a transparent conductive material, it is preferably formed by a material with low resistance and high transmission characteristics. Such material may include, but is not limited to, In2O3, SnO2, ZnO, IZO, ITO, and IGZO.

[0178] Conversely, when the short channel 180 and the residual layer 172 are formed from a transparent reflective material, it is preferable to form them from a material with low resistance and high reflectivity. This material can be formed from highly reflective materials such as Ag, Al, and Rh in various wavelength regions, or from highly reflective materials such as Cu and Au in specific wavelength regions. Furthermore, to improve the adhesion of the highly reflective material, a thin layer of materials such as Ti, Ni, Cr, and Pt can be formed at a thickness of several nm or less to improve the stacking structure of the adhesion-improving material. It can also be formed from alloys of AgCu, AgNi, etc., but is not limited to these.

[0179] On the one hand, the short channel 180 in the etched and removed part or in the process of forming the through hole can be filled with conductive material by direct self-alignment or by liquid phase coating method such as sol-gel to form the short channel 180, but it is not limited to this. As long as it is used to form the short channel 180, it is fine to form it in any way.

[0180] The bonding step S140 is a step after the first processing step S130, in which multiple light-emitting parts 120 bond a temporary wafer T stacked in the vertical direction to the back wafer 140 through the first bonding layer 130a, and then remove the temporary wafer T.

[0181] At this time, the material of the first bonding layer 130a used for bonding with the back wafer 140 is not limited to a transparent conductive material or an opaque conductive material with reflectivity, as long as it can be conductive and ensure bonding force.

[0182] After the temporary wafer T is bonded to the back wafer 140, the first bonding layer 130a must be heat-treated at a temperature below 400°C to prevent damage to the CMOS circuitry of the back wafer 140. Furthermore, the temporary wafer T can be removed using mechanical polishing (MP) and chemical lift-off (CLO) techniques. Alternatively, when using a sapphire temporary wafer T, laser lift-off (LLO) techniques can also be used to remove it.

[0183] On the one hand, in this invention, a part of the alignment process between the short channel 180 and the CMOS electrode pad 141 needs to be performed in the bonding step S140. However, since a number of alignment process keys are designed in the place adjacent to the multiple micro display panels formed on the back wafer 140, high-precision bonding can be achieved.

[0184] Thus, in this invention, the third light-emitting part 123 emitting blue light, the second light-emitting part 122 emitting green light, and the first light-emitting part 121 emitting red light have an n-side up shape on the back wafer 140 and are stacked in sequence, while the upper surface of the first light-emitting part 121 having nitrogen polarity can be textured.

[0185] The second processing step S150 is to form a short channel 180 on one side of the stack of the temporary wafer T after it has been removed and exposed.

[0186] In the second processing step S150, the first light-emitting portion 121, on which the ohmic contact electrode 124 is formed, is first etched in the upper and lower portions of the portion where the third LED stack L3 will be formed and the portion where the second LED stack L2 will be formed, until the second bonding layer 130b is exposed and removed. Then, a through-hole is formed in the portion where the third LED stack L3 will be formed, penetrating through the second light-emitting portion 122, and a conductive transmissive material is filled into the through-hole to form a second short channel 182.

[0187] At this time, the through hole can be formed in such a way that it penetrates the active region 1203 of the second light-emitting part 122. In particular, preferably, when the second bonding layer 130b is formed of a transparent insulating material, the second bonding layer 130b between the first light-emitting part 121 and the second light-emitting part 122 and the second bonding layer 130b between the second light-emitting part 122 and the third light-emitting part 123 are also formed until the surface of the ohmic contact electrode 124 of the third light-emitting part 123 is exposed.

[0188] Subsequently, in the second processing step S150, conductive material is filled into the etched portion to form the first short channel 181.

[0189] At this time, after the first short channel 181 is formed, the corresponding material can either remain on the ohmic contact electrode 124 of the first light-emitting part 121 that has not been etched, or it can be removed. If the corresponding material remains on the ohmic contact electrode 124 of the first light-emitting part 121, a transmission layer 171 is formed. After the etched part is filled with conductive material, a different material can also be used to form the transmission layer 171.

[0190] Furthermore, the short channel 180 and the transmission layer 171 formed on one side of the stack are formed of transparent conductive material so that light can be transmitted to the outside.

[0191] When the short channel 180 and the transmission layer 171 are formed of a transparent conductive material, they are preferably formed of a material with low resistance and high transmission characteristics. Such a material may include, but is not limited to, In2O3, SnO2, ZnO, IZO, ITO, and IGZO.

[0192] The etching step S160 etches the stacked multiple light-emitting parts 120, ohmic contact electrodes 124 and second bonding layer 130b, and separates them in preset units, so that the multiple LED stacks L are respectively arranged on multiple CMOS electrode pads 141 to achieve the arrangement.

[0193] That is, in etching step S160, the transmissive layer 171, the light-emitting portion 120, the ohmic contact electrode 124, the second bonding layer 130b, and the residual layer 172 are etched in a vertical direction to arrange them in an array until the surface of the back wafer 140 or the adjacent area is exposed. In other words, multiple LED stacks L are arranged on the top of the arranged CMOS electrode pads 141, and through etching step S160, the width of the first short channel 181 is formed corresponding to the width of the light-emitting portion 120. Here, the set unit can mean a pixel or sub-pixel unit, and can mean the width (diameter) of the multiple LED stacks L.

[0194] At this time, the transmissive layer 171, the light-emitting portion 120, the ohmic contact electrode 124, and the second bonding layer 130b of the present invention are all transparent, allowing visible light to pass through. Therefore, it has the advantage of not having alignment errors during the exposure process. Furthermore, the second bonding layer 130b and the ohmic contact electrode 124 of the present invention are both made of non-metallic ceramic materials. Therefore, etching is easy to perform in the plasma dry process, and it has the advantage of not having the problem of re-deposition of etching byproducts.

[0195] On one hand, the multiple LED stacks L include a first LED stack L1 used only to emit the first color, a second LED stack L2 used only to emit the second color, and a third LED stack L3 used only to emit the third color.

[0196] After the above-described etching step S160, the first LED stack L1 includes a first short channel 181 formed in the region of the third light-emitting part 123 after the removal of the region of the third light-emitting part 123, a second short channel 182 formed in a manner that penetrates the second light-emitting part 122, and a first light-emitting part 121. Furthermore, through the short channel 180, current can be directed only to the first light-emitting part 121 to emit a first color. When a transmission layer 171 is formed in the first light-emitting part 121, the first color generated in the first light-emitting part 121 can be transmitted through the corresponding transmission layer 171.

[0197] Furthermore, the second LED stack L2 includes a first short channel 181 formed in the region of the third light-emitting part 123 after the removal of the region of the third light-emitting part 123, a second light-emitting part 122, and a first short channel 181 formed in the region of the first light-emitting part 121 after the removal of the region of the first light-emitting part 121. Moreover, current can be directed only to the second light-emitting part 122 through the short channel 180, so that only the second color is emitted.

[0198] Furthermore, the third LED stack L3 includes a second short channel 182 formed in a manner that penetrates the third light-emitting part 123 and the second light-emitting part 122, and a first short channel 181 formed in the region of the first light-emitting part 121 after the region of the first light-emitting part 121 is removed. The current can be directed only to the third light-emitting part 123 through the short channel 180, emitting only the third color. In addition, a residual layer 172 can be formed at the lower part of the third light-emitting part 123.

[0199] Furthermore, the first light-emitting part 121 of the first LED stack L1 has an n-side up shape and is located on the upper side of the second light-emitting part 122 of the second LED stack L2. The second light-emitting part 122 of the second LED stack L2 has an n-side up shape and is located on the upper side of the third light-emitting part 123 of the third LED stack L3. The upper surface of the first light-emitting part 121 with nitrogen polarity can be textured.

[0200] According to the present invention, it has the effect of facilitating the formation of short channels 180 in a vertically stacked tandem structure.

[0201] Furthermore, according to the present invention, since red light is not absorbed by other light-emitting parts 120, the luminous efficiency of red light can be greatly improved in a vertically stacked tandem structure.

[0202] Furthermore, in addition to the light-emitting part 120 that emits the corresponding color, each LED stack L of the present invention removes a portion of the other light-emitting parts 120. Therefore, the problem of unwanted sub-pixel light emission caused by photoexcitation due to short-wavelength blue light can be reduced.

[0203] On the one hand, in this invention, the light-emitting areas of the multiple LED stacks L can all be the same, and the operating voltages of the multiple LED stacks L can all be set to the same. Normally, the individual light-emitting parts 120 emitting red, green, or blue light do not have the same operating voltage. However, assuming that the operating voltage of each light-emitting part 120 is 3V, this invention is a stacked structure, but energization is achieved through a short channel 180, thus de-series connection is broken, making it similar to a parallel structure. Therefore, the operating voltages can all be set to the same 3V.

[0204] Forming step S170 involves forming a common electrode 160 on the multiple LED stacks L after forming a mold portion 150 to fill the spaces between the stacked LEDs L. In this case, if the light-emitting portion 120 is in an n-side-up configuration, the common electrode 160 can be formed as a cathode; if the light-emitting portion 120 is in a p-side-up configuration, the common electrode 160 can be formed as an anode.

[0205] At this point, preferably, before forming the mold portion 150 that fills the spaces between the arranged plurality of LED stacks L, it is possible to use an optically transparent and electrically insulating material (e.g., SiO2, SiN) to perform the process. x The process of surrounding all the sides of the light-emitting part 120 with Al2O3 is called passivation.

[0206] More specifically, in the formation step S170, a mold portion 150 is formed between and above the arranged plurality of LED stacks L, and the mold portion 150 is etched to expose the upper part of the plurality of LED stacks L. Then, a common electrode 160 is formed in contact with the upper part of the plurality of LED stacks L, thereby completing the vertically stacked LEDoS structure. The common electrode 160 can be formed from a transparent conductive material similar to the ohmic contact electrode 124. When the common electrode 160 is a cathode, the material of the common electrode 160 can include TiN, CrN, VN, In2O3, SnO2, ZnO, IZO, ITO and IGZO. When the common electrode 160 is an anode, the material of the common electrode 160 can include NiO, PtO, PdO, AgO2, Au, Rh2O3, RuO2, In2O3, SnO2, ZnO, IZO, ITO and IGZO.

[0207] Furthermore, the surface of the common electrode 160 can also be polished by mechanical polishing (MP) or chemical-mechanical polishing (CMP) to achieve smooth planarization.

[0208] Furthermore, although not illustrated, a protective layer can also be formed using transparent organic materials to protect the common electrode 160 from the atmospheric environment.

[0209] Hereinafter, the vertically stacked micro display panel 100 of the first embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[0210] Figure 14 shows a vertically stacked micro-display panel according to a first embodiment of the present invention.

[0211] As shown in FIG14, the vertically stacked micro display panel 100 of the first embodiment of the present invention includes a back wafer 140, a plurality of LED stacks L, a mold section 150 and a common electrode 160.

[0212] Hereinafter, some descriptions will be omitted regarding content that overlaps with the manufacturing method S100 of the vertically stacked micro-display panel of the first embodiment of the present invention.

[0213] Hereinafter, we will describe an example of a vertically stacked micro-display panel 100 of the present invention, in which the light-emitting portion 120 is stacked into an n-side up structure and forms a cathode common electrode 160.

[0214] As an active matrix (AM) driven IC, the back wafer 140 means that it is a CMOS wafer with multiple CMOS electrode pads 141 arranged in an array on its upper surface. A passivation layer can be formed on the upper surface of this back wafer 140, and when the current wafer 110 is bonded, a portion of the passivation layer can be etched to expose the multiple CMOS electrode pads 141.

[0215] The multiple LED stacks L include light-emitting portions 120 that are stacked vertically through a first bonding layer 130a and have ohmic contact electrodes 124 on their upper and lower surfaces, respectively arranged on multiple CMOS electrode pads 141.

[0216] Specifically, the multiple LED stacks L include a first LED stack L1 used only to emit a first color, a second LED stack L2 used only to emit a second color, and a third LED stack L3 used only to emit a third color.

[0217] The first LED stack L1 includes a first short channel 181 formed in the region of the third light-emitting part 123 after the region of the third light-emitting part 123 is removed, a second short channel 182 formed in a manner that penetrates the second light-emitting part 122, and a first light-emitting part 121. Furthermore, through the short channel 180, current can be passed only to the first light-emitting part 121, and only the first color is emitted. When a transmission layer 171 is formed in the first light-emitting part 121, the first color generated in the first light-emitting part 121 can be transmitted through the corresponding transmission layer 171.

[0218] Furthermore, the second LED stack L2 includes a first short channel 181 formed in the region of the third light-emitting part 123 after the region of the third light-emitting part 123 is removed, and a first short channel 181 formed in the region of the first light-emitting part 121 after the regions of the second light-emitting part 122 and the first light-emitting part 121 are removed. Moreover, current can be directed only to the second light-emitting part 122 through the short channel 180, so that only the second color is emitted.

[0219] Furthermore, the third LED stack L3 includes a second short channel 182 formed in a manner that penetrates the third light-emitting part 123 and the second light-emitting part 122, and a first short channel 181 formed in the region of the first light-emitting part 121 after the region of the first light-emitting part 121 is removed. The current can be directed only to the third light-emitting part 123 through the short channel 180, emitting only the third color. In addition, a residual layer 172 can be formed at the lower part of the third light-emitting part 123.

[0220] Furthermore, the first light-emitting part 121 of the first LED stack L1 has an n-side up shape and is located on the upper side of the second light-emitting part 122 of the second LED stack L2. The second light-emitting part 122 of the second LED stack L2 has an n-side up shape and is located on the upper side of the third light-emitting part 123 of the third LED stack L3. The upper surface of the first light-emitting part 121 with nitrogen polarity can be textured.

[0221] Furthermore, the first short channel 181 is formed corresponding to the width of the light-emitting portion 120, and the second short channel 182 is formed in a manner that penetrates the light-emitting portion 120. In the case where the second bonding layer 130b is formed by a transparent insulating material, it can penetrate all the second bonding layers 130b between the light-emitting portions 120 to contact the ohmic contact electrode 124 of the first light-emitting portion 121 (in the case of the first LED stack L1) or the ohmic contact electrode 124 of the third light-emitting portion 123 (in the case of the third LED stack L3).

[0222] According to the present invention, it has the effect of facilitating the formation of short channels 180 in a vertically stacked tandem structure.

[0223] Furthermore, according to the present invention, since red light is not absorbed by other light-emitting parts 120, the luminous efficiency of red light can be greatly improved in a vertically stacked tandem structure.

[0224] Furthermore, in addition to the light-emitting part 120 that emits the corresponding color, each LED stack L of the present invention removes a portion of the other light-emitting parts 120. Therefore, the problem of unwanted sub-pixel light emission caused by photoexcitation due to short-wavelength blue light can be reduced.

[0225] The mold section 150 is used to support the vertically stacked LEDoS structure, which is formed in a way that fills the spaces between the multiple LED stacks L.

[0226] The common electrode 160 can be configured as a cathode or anode and formed on a plurality of LED stacks L on which the mold portion 150 has been formed. It can be in contact with the upper part of the plurality of LED stacks L and can be formed of a transparent conductive material similar to the ohmic contact electrode 124. When the common electrode 160 is a cathode, the material of the common electrode 160 can include TiN, CrN, VN, In2O3, SnO2, ZnO, IZO, ITO and IGZO. When the common electrode 160 is an anode, the material of the common electrode 160 can include NiO, PtO, PdO, AgO2, Au, Rh2O3, RuO2, In2O3, SnO2, ZnO, IZO, ITO and IGZO.

[0227] Hereinafter, the manufacturing method S200 of the vertically stacked micro-display panel of the second embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[0228] Figure 15 is a sequence diagram of the manufacturing method S200 of the vertically stacked micro-display panel according to the second embodiment of the present invention. Figures 16 and 17 show the process of preparing the front wafer 210 in the manufacturing method S200 of the vertically stacked micro-display panel according to the second embodiment of the present invention. Figures 16 to 18 show the process of manufacturing the vertically stacked micro-display panel according to the manufacturing method S200 of the second embodiment of the present invention.

[0229] As shown in Figures 15 to 18, the manufacturing method S200 of the vertically stacked micro display panel of the second embodiment of the present invention includes a preparation step S210, a stacking step S220, a first processing step S230, a second processing step S240, a bonding step S250, an etching step S260, and a forming step S270.

[0230] Hereinafter, some descriptions will be omitted regarding content that overlaps with the manufacturing method S100 of the vertically stacked micro-display panel of the first embodiment of the present invention.

[0231] Preparation step S210 is the step of preparing multiple front wafers 210 and back wafers 140.

[0232] Multiple front wafers 210 are used to emit different colors. The multiple front wafers 210 may include a first front wafer 211 for emitting a first color, a second front wafer 212 for emitting a second color different from the first color, and a third front wafer 213 for emitting a third color different from the first and second colors. On the one hand, the first color, the second color, and the third color may be, for example, red, green, and blue, but are not limited to these, and may include a variety of other colors.

[0233] The first front wafer 211 includes a supporting wafer S and a first light-emitting portion 121 disposed on the upper part of the supporting wafer S; the second front wafer 212 includes a supporting wafer S and a second light-emitting portion 122 disposed on the upper part of the supporting wafer S; and the third front wafer 213 includes a supporting wafer S and a third light-emitting portion 123 disposed on the upper part of the supporting wafer S.

[0234] The following description will take the process of stacking the light-emitting portion 120 of the vertically stacked micro-display panel 200 of the present invention into a p-side up structure and forming an anode common electrode 160 as an example.

[0235] As shown in Figure 10, the back wafer 140 is an active-matrix (AM) driven IC, meaning it is a CMOS wafer with multiple CMOS electrode pads 141 arranged in an array on its upper surface. A passivation layer can be formed on the upper surface of this back wafer 140 to prevent partial exposure of the multiple CMOS electrode pads 141. When bonding the front wafer 210 is performed, a portion of the passivation layer can be etched to expose the multiple CMOS electrode pads 141.

[0236] After exposing the upper surfaces of the plurality of CMOS electrode pads 141, a first bonding layer 130a is formed on the upper surface of the back wafer 140 using a conductive material. Preferably, the first bonding layer is formed of an optically transparent conductive material.

[0237] The stacking step S220 is a step of bonding one front wafer 210 onto another front wafer 210 through the second bonding layer 130b, and then repeatedly removing the support wafer S of the other front wafer 210, thereby forming a stacked body composed of multiple light-emitting parts 120 stacked vertically on the support wafer S.

[0238] As shown in Figure 16, specifically, in the stacking step S220, firstly, the second front wafer 212 emitting green light in an n-side up shape is bonded to the third front wafer 213 emitting blue light in a p-side up shape using the second bonding layer 130b, then the supporting wafer S of the second front wafer 212 is removed by means of laser lift-off, and the second bonding layer 130b is deposited on the p-type ohmic contact electrode 124.

[0239] After bonding the first front wafer 211, which emits red light in a p-side up shape, through the second bonding layer 130b, the supporting wafer S of the first front wafer 211 is removed by chemical stripping or the like, so as to expose the p-type ohmic contact electrode 124 to the outside.

[0240] Then, in this invention, a heat treatment at a high temperature of 200–900°C is performed to improve the bonding strength of the second bonding layer 130b. That is, in this invention, after all the RGB light sources are stacked to form a stack, a high-temperature heat treatment is performed to ensure the bonding strength between the RGB epitaxial layers, and then the RGB stack structure can be bonded to the CMOS Si back wafer 140 in one step.

[0241] In this way, a support wafer S, a bonding layer B, a third light-emitting portion 123 with ohmic contact electrodes 124 formed on the upper and lower surfaces, a second bonding layer 130b, a second light-emitting portion 122 with ohmic contact electrodes 124 formed on the upper and lower surfaces, a second bonding layer 130b, and a first light-emitting portion 121 with ohmic contact electrodes 124 formed on the upper and lower surfaces are stacked vertically to form a stack on the support wafer S. The stack is then heat-treated at high temperature to ensure strong bonding between the RGB epitaxial layers.

[0242] The first processing step S230 is to form a short channel 180 on one side of the stack.

[0243] Specifically, in the first processing step S230, the first light-emitting portion 121, on which the ohmic contact electrode 124 is formed, is first etched in the upper and lower portions of the portion where the third LED stack L3 will be formed and the portion where the second LED stack L2 will be formed, until the second bonding layer 130b is exposed and removed. Then, a through-hole is formed in the portion where the third LED stack L3 will be formed, penetrating through the second light-emitting portion 122, and a conductive transmissive material is filled into the through-hole to form a second short channel 182.

[0244] At this time, the through hole can be formed in such a way that it penetrates the active region 1203 of the second light-emitting part 122. In particular, preferably, when the second bonding layer 130b is formed of a transparent insulating material, the second bonding layer 130b between the first light-emitting part 121 and the second light-emitting part 122 and the second bonding layer 130b between the second light-emitting part 122 and the third light-emitting part 123 are also formed until the surface of the ohmic contact electrode 124 of the third light-emitting part 123 is exposed.

[0245] Subsequently, in the first processing step S230, conductive material is filled into the etched portion to form a first short channel 181.

[0246] At this time, after the first short channel 181 is formed, the corresponding material can either remain on the ohmic contact electrode 124 of the first light-emitting part 121 that has not been etched, or it can be removed. If the corresponding material remains on the ohmic contact electrode 124 of the first light-emitting part 121, a transmission layer 171 is formed. After the etched part is filled with conductive material, a different material can also be used to form the transmission layer 171.

[0247] Furthermore, the short channel 180 and the transmission layer 171 formed on one side of the stack are made of a transparent conductive material so that light can be transmitted to the outside.

[0248] The second processing step S240 is to bond a temporary wafer T to one side of the stack, remove the support wafer S, and then form a short channel 180 on the other side of the stack.

[0249] Specifically, in the second processing step S240, after the temporary wafer T is bonded to one side of the stack body, i.e., after the transmission layer 171, by means of the bonding layer B, the lower supporting wafer S is separated by means of laser lift or chemical lift, and the bonding layer B is removed.

[0250] Subsequently, in the second processing step S240, the third light-emitting portion 123, on which the ohmic contact electrode 124 is formed, is first etched in the upper and lower portions of the portion where the first LED stack L1 will be formed and the portion where the second LED stack L2 will be formed, until the second bonding layer 130b is exposed and removed. Then, after forming a through-hole in the portion where the first LED stack L1 will be formed, penetrating the second light-emitting portion 122, a conductive material is filled into the through-hole to form a second short channel 182.

[0251] At this time, the through hole can be formed in such a way that it penetrates the active region 1203 of the second light-emitting part 122. In particular, preferably, when the second bonding layer 130b is formed of a transparent insulating material, it also penetrates the second bonding layer 130b between the third light-emitting part 123 and the second light-emitting part 122 and the second bonding layer 130b between the second light-emitting part 122 and the first light-emitting part 121, and is formed until the surface of the ohmic contact electrode 124 of the first light-emitting part 121 is exposed.

[0252] Subsequently, in the second processing step S240, the etched portion is filled with a conductive material to form a first short channel 181.

[0253] At this time, after the first short channel 181 is formed, the corresponding material can either remain on the ohmic contact electrode 124 of the unetched third light-emitting part 123 or be removed. If the corresponding material remains on the ohmic contact electrode 124 of the third light-emitting part 123, a residual layer 172 is formed. After the etched part is filled with conductive material, a different material can also be used to form the residual layer 172.

[0254] Furthermore, the short channel 180 and the residual layer 172 formed on the other side of the stack can be formed by a transparent conductive material or a reflective opaque conductive material, respectively.

[0255] The bonding step S250 is the step after the second processing step S240, in which multiple light-emitting parts 120 bond the temporary wafer T stacked in the vertical direction to the back wafer 140 through the first bonding layer 130a, and then remove the temporary wafer T.

[0256] After the temporary wafer T is bonded to the back wafer 140, the first bonding layer 130a must be heat-treated at a temperature below 400°C to prevent damage to the CMOS circuitry of the back wafer 140. Furthermore, the temporary wafer T can be removed using mechanical polishing (MP) and chemical lift-off (CLO) techniques. Alternatively, when using a sapphire temporary wafer T, laser lift-off (LLO) techniques can also be used to remove it.

[0257] Thus, in this invention, the third light-emitting part 123 emitting blue light, the second light-emitting part 122 emitting green light, and the first light-emitting part 121 emitting red light are stacked sequentially on the back wafer 140 in a p-side-up configuration.

[0258] Etching step S260 involves etching the stacked multiple light-emitting portions 120, ohmic contact electrodes 124, and second bonding layer 130b, and separating them in a preset unit so that multiple LED stacks L are respectively arranged on multiple CMOS electrode pads 141. The first short channel 181 is formed by etching step S260 to correspond to the width of the light-emitting portion 120.

[0259] On one hand, the multiple LED stacks L include a first LED stack L1 used only to emit the first color, a second LED stack L2 used only to emit the second color, and a third LED stack L3 used only to emit the third color.

[0260] After the above-described etching step S260, the first LED stack L1 includes a first short channel 181 formed in the region of the third light-emitting part 123 after the removal of the region of the third light-emitting part 123, a second short channel 182 formed in a manner that penetrates the second light-emitting part 122, and a first light-emitting part 121. Furthermore, through the short channel 180, current can be directed only to the first light-emitting part 121, emitting only the first color. When a transmission layer 171 is formed in the first light-emitting part 121, the first color generated in the first light-emitting part 121 can be transmitted through the corresponding transmission layer 171.

[0261] Furthermore, the second LED stack L2 includes a first short channel 181 formed in the region of the third light-emitting part 123 after the region of the third light-emitting part 123 is removed, and a first short channel 181 formed in the region of the first light-emitting part 121 after the regions of the second light-emitting part 122 and the first light-emitting part 121 are removed. Moreover, current can be directed only to the second light-emitting part 122 through the short channel 180, so that only the second color is emitted.

[0262] Furthermore, the third LED stack L3 includes a second short channel 182 formed in a manner that penetrates the third light-emitting part 123 and the second light-emitting part 122, and a first short channel 181 formed in the region of the first light-emitting part 121 after the region of the first light-emitting part 121 is removed. The current can be directed only to the third light-emitting part 123 through the short channel 180, emitting only the third color. In addition, a residual layer 172 can be formed at the lower part of the third light-emitting part 123.

[0263] Furthermore, the first light-emitting part 121 of the first LED stack L1 may have a p-side up shape and be located on the upper side of the second light-emitting part 122 of the second LED stack L2. The second light-emitting part 122 of the second LED stack L2 may have a p-side up shape and be located on the upper side of the third light-emitting part 123 of the third LED stack L3.

[0264] According to the present invention, it has the effect of facilitating the formation of short channels 180 in a vertically stacked tandem structure.

[0265] Furthermore, according to the present invention, since red light is not absorbed by other light-emitting parts 120, the luminous efficiency of red light can be greatly improved in a vertically stacked tandem structure.

[0266] Furthermore, in addition to the light-emitting part 120 that emits the corresponding color, each LED stack L of the present invention removes a portion of the other light-emitting parts 120. Therefore, the problem of unwanted sub-pixel light emission caused by photoexcitation due to short-wavelength blue light can be reduced.

[0267] Forming step S270 involves forming a common electrode 160 on the multiple LED stacks L after forming a mold portion 150 to fill the spaces between the stacked LEDs L. In this case, if the light-emitting portion 120 is in an n-side-up configuration, the common electrode 160 can be formed as a cathode; if the light-emitting portion 120 is in a p-side-up configuration, the common electrode 160 can be formed as an anode.

[0268] The common electrode 160 can be formed from a transparent conductive material, similar to the ohmic contact electrode 124. When the common electrode 160 is a cathode, the material of the common electrode 160 can include TiN, CrN, VN, In2O3, SnO2, ZnO, IZO, ITO, and IGZO. When the common electrode 160 is an anode, the material of the common electrode 160 can include NiO, PtO, PdO, AgO2, Au, Rh2O3, RuO2, In2O3, SnO2, ZnO, IZO, ITO, and IGZO.

[0269] Hereinafter, the vertically stacked micro display panel 200 of the second embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[0270] Figure 19 shows a vertically stacked micro-display panel according to a second embodiment of the present invention.

[0271] As shown in FIG19, the vertically stacked micro display panel 200 of the second embodiment of the present invention includes a back wafer 140, a plurality of LED stacks L, a mold section 150 and a common electrode 160.

[0272] Hereinafter, some descriptions will be omitted regarding content that overlaps with the manufacturing method S200 of the vertically stacked micro-display panel of the second embodiment of the present invention.

[0273] Hereinafter, we will describe an example of the vertically stacked micro-display panel 100 of the present invention, in which the light-emitting portion 120 is stacked into a p-side up structure and forms an anode common electrode 160.

[0274] As an active matrix (AM) driven IC, the back wafer 140 means that a CMOS wafer with multiple CMOS electrode pads 141 arranged in an array on its upper surface. A passivation layer can be formed on the upper surface of this back wafer 140. When bonding the front wafer 210 is performed, a portion of the passivation layer can be etched, exposing the multiple CMOS electrode pads 141.

[0275] The multiple LED stacks L include light-emitting portions 120 that are stacked vertically through a first bonding layer 130a and have ohmic contact electrodes 124 on their upper and lower surfaces, respectively arranged on multiple CMOS electrode pads 141.

[0276] Specifically, the multiple LED stacks L include a first LED stack L1 used only to emit a first color, a second LED stack L2 used only to emit a second color, and a third LED stack L3 used only to emit a third color.

[0277] The first LED stack L1 includes a first short channel 181 formed in the region of the third light-emitting part 123 after the region of the third light-emitting part 123 is removed, a second short channel 182 formed in a manner that penetrates the second light-emitting part 122, and a first light-emitting part 121. Furthermore, through the short channel 180, current can be passed only to the first light-emitting part 121, and only the first color is emitted. When a transmission layer 171 is formed in the first light-emitting part 121, the first color generated in the first light-emitting part 121 can be transmitted through the corresponding transmission layer 171.

[0278] Furthermore, the second LED stack L2 includes a first short channel 181 formed in the region of the third light-emitting part 123 after the region of the third light-emitting part 123 is removed, and a first short channel 181 formed in the region of the first light-emitting part 121 after the regions of the second light-emitting part 122 and the first light-emitting part 121 are removed. Moreover, current can be directed only to the second light-emitting part 122 through the short channel 180, so that only the second color is emitted.

[0279] Furthermore, the third LED stack L3 includes a second short channel 182 formed in a manner that penetrates the third light-emitting part 123 and the second light-emitting part 122, and a first short channel 181 formed in the region of the first light-emitting part 121 after the region of the first light-emitting part 121 is removed. The current can be directed only to the third light-emitting part 123 through the short channel 180, emitting only the third color. In addition, a residual layer 172 can be formed at the lower part of the third light-emitting part 123.

[0280] Furthermore, the first light-emitting part 121 of the first LED stack L1 may have a p-side up shape and be located on the upper side of the second light-emitting part 122 of the second LED stack L2. The second light-emitting part 122 of the second LED stack L2 may have a p-side up shape and be located on the upper side of the third light-emitting part 123 of the third LED stack L3.

[0281] Furthermore, the first short channel 181 is formed corresponding to the width of the light-emitting portion 120, and the second short channel 182 is formed in a manner that penetrates the light-emitting portion 120. In the case where the second bonding layer 130b is formed by a transparent insulating material, it can penetrate all the second bonding layers 130b between the light-emitting portions 120 to contact the ohmic contact electrode 124 of the first light-emitting portion 121 (in the case of the first LED stack L1) or the ohmic contact electrode 124 of the third light-emitting portion 123 (in the case of the third LED stack L3).

[0282] The mold section 150 is used to support the vertically stacked LEDoS structure, which is formed in a way that fills the spaces between the multiple LED stacks L.

[0283] The common electrode 160 can be configured as a cathode or anode and formed on a plurality of LED stacks L on which the mold portion 150 has been formed. It can be in contact with the upper part of the plurality of LED stacks L and can be formed of a transparent conductive material similar to the ohmic contact electrode 124. When the common electrode 160 is a cathode, the material of the common electrode 160 can include TiN, CrN, VN, In2O3, SnO2, ZnO, IZO, ITO and IGZO. When the common electrode 160 is an anode, the material of the common electrode 160 can include NiO, PtO, PdO, AgO2, Au, Rh2O3, RuO2, In2O3, SnO2, ZnO, IZO, ITO and IGZO.

[0284] While the above description illustrates an embodiment of the invention where all structural elements are combined or operated in combination, the invention is not limited to such embodiments. That is, all structural elements can be selectively combined into one operation as long as they fall within the scope of the invention's objectives.

[0285] Furthermore, unless otherwise stated, the terms "comprising," "constituting," or "having" used above imply the inclusion of the corresponding structural elements, and should therefore be interpreted as including, rather than excluding, other structural elements. Unless defined differently, all terms containing technical or scientific terms have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms commonly used and identical to their dictionary definitions should be interpreted as having meanings consistent with the literal meaning of the relevant art, and should not be interpreted as having overly ideal or formal meanings unless explicitly defined in this invention.

[0286] Moreover, the above description is merely illustrative of the technical concept of the present invention. Anyone skilled in the art to which this invention pertains can implement various modifications and variations without departing from the essential characteristics of this embodiment.

[0287] Therefore, the embodiments disclosed in this invention are not intended to limit the technical concept of the invention, but rather to illustrate it. The scope of the technical concept of the invention is not limited by these embodiments. The scope of protection of this invention should be interpreted through the scope of the claims, and all technical concepts within the same scope should be interpreted as being included within the scope of protection of this invention.

Claims

1. A vertically stacked micro display panel, characterized in that, include: The back wafer has multiple CMOS electrode pads arranged on its top surface; multiple LED stacks, each including light-emitting portions stacked vertically via bonding layers and arranged on the multiple CMOS electrode pads; and a common electrode formed on the multiple LED stacks. The multiple LED stacks each form a short channel in a portion of their respective regions, allowing current to flow through the light-emitting portions without the short channel to emit only a specific color. The short channel includes a first short channel formed in a manner corresponding to the width of the light-emitting portion, and a second short channel formed in a manner that penetrates the light-emitting portion.

2. The vertically stacked micro-display panel according to claim 1, characterized in that, The plurality of LED stacks include: a first LED stack including a first light-emitting portion for emitting a first color; a second LED stack including a second light-emitting portion for emitting a second color; and a third LED stack including a third light-emitting portion for emitting a third color.

3. The vertically stacked micro-display panel according to claim 2, characterized in that, The first LED stack includes a first short channel formed in the third light-emitting portion region, a second short channel formed in a manner that penetrates the second light-emitting portion, and a first light-emitting portion. The second LED stack includes a first short channel formed in the third light-emitting portion region, a second light-emitting portion, and a first short channel formed in the first light-emitting portion region. The third LED stack includes the third light-emitting portion, a second short channel formed in a manner that penetrates the second light-emitting portion, and a first short channel formed in the first light-emitting portion region.

4. The vertically stacked micro-display panel according to claim 1, characterized in that, The common electrode is either an anode or a cathode.

5. A method for manufacturing a vertically stacked micro-display panel, characterized in that, include: Preparation steps include preparing multiple front wafers, including support wafers and light-emitting parts, and a back wafer with multiple CMOS electrode pads arranged on its upper surface. The stacking step involves repeatedly bonding one front wafer to another through a bonding layer and then removing the support wafer from the other front wafer, thereby forming a stack of multiple light-emitting parts vertically stacked on the support wafer. In the first processing step, after bonding a temporary wafer to one side of the stack, the support wafer is removed, and then a short channel is formed on the other side of the stack. In the bonding step, after bonding the back wafer to the stack, the temporary wafer is removed to stack a plurality of the light-emitting parts on the back wafer. The second processing step involves forming the short channel on one side of the stacked body; The etching step involves etching the stacked structures to separate them in preset units, such that multiple LED stacks are arranged on multiple CMOS electrode pads; and the forming step involves forming a common electrode on the multiple LED stacks, wherein each of the multiple LED stacks allows current to be passed to the light-emitting portion without the short channel to emit only a specific color, wherein the short channel includes a first short channel formed in a manner corresponding to the width of the light-emitting portion, and a second short channel formed in a manner that penetrates the light-emitting portion.

6. The method for manufacturing a vertically stacked microdisplay panel according to claim 5, characterized in that, The plurality of LED stacks include: a first LED stack including a first light-emitting portion for emitting a first color; a second LED stack including a second light-emitting portion for emitting a second color; and a third LED stack including a third light-emitting portion for emitting a third color.

7. The method for manufacturing a vertically stacked microdisplay panel according to claim 6, characterized in that, The first LED stack includes a first short channel formed in the third light-emitting portion region, a second short channel formed in a manner that penetrates the second light-emitting portion, and a first light-emitting portion. The second LED stack includes a first short channel formed in the third light-emitting portion region, a second light-emitting portion, and a first short channel formed in the first light-emitting portion region. The third LED stack includes the third light-emitting portion, a second short channel formed in a manner that penetrates the second light-emitting portion, and a first short channel formed in the first light-emitting portion region.

8. The method for manufacturing a vertically stacked microdisplay panel according to claim 5, characterized in that, The common electrode is either an anode or a cathode.

9. A method for manufacturing a vertically stacked micro-display panel, characterized in that, include: Preparation steps include preparing multiple front wafers, including support wafers and light-emitting parts, and a back wafer with multiple CMOS electrode pads arranged on its upper surface. The stacking step involves repeatedly bonding one front wafer to another through a bonding layer and then removing the support wafer from the other front wafer, thereby forming a stack of multiple light-emitting parts vertically stacked on the support wafer. The first processing step involves forming a short channel on one side of the stacked body; The second processing step involves bonding a temporary wafer to one side of the stack, removing the support wafer, and then forming the short channel on the other side of the stack. The bonding step involves bonding the stack to the back wafer, removing the temporary wafer to stack multiple light-emitting portions on the back wafer. The etching step involves etching the stack to separate it in predetermined units, such that multiple LED stacks are respectively arranged on multiple CMOS electrode pads. The forming step involves forming a common electrode on the multiple LED stacks, and each of the multiple LED stacks allows current to flow to the light-emitting portion without the short channel to emit only a specific color. The short channel includes a first short channel formed in a manner corresponding to the width of the light-emitting portion, and a second short channel formed in a manner that penetrates the light-emitting portion.

10. The method for manufacturing a vertically stacked microdisplay panel according to claim 9, characterized in that, The plurality of LED stacks include: a first LED stack including a first light-emitting portion for emitting a first color; a second LED stack including a second light-emitting portion for emitting a second color; and a third LED stack including a third light-emitting portion for emitting a third color.

11. The method for manufacturing a vertically stacked microdisplay panel according to claim 10, characterized in that, The first LED stack includes a first short channel formed in the third light-emitting portion region, a second short channel formed in a manner that penetrates the second light-emitting portion, and a first light-emitting portion. The second LED stack includes a first short channel formed in the third light-emitting portion region, a second light-emitting portion, and a first short channel formed in the first light-emitting portion region. The third LED stack includes the third light-emitting portion, a second short channel formed in a manner that penetrates the second light-emitting portion, and a first short channel formed in the first light-emitting portion region.

12. The method for manufacturing a vertically stacked microdisplay panel according to claim 9, characterized in that, The common electrode is either an anode or a cathode.

Images