Superconducting quantum computing chip based on corrosion-resistant josephson junction and preparation method thereof

Abstract

The application discloses a superconducting quantum computing chip based on a corrosion-resistant Josephson junction and a preparation method thereof. The superconducting quantum computing chip comprises a substrate, a plurality of superconducting quantum bits arranged periodically on a first surface of the substrate, each of the superconducting quantum bits comprising two capacitive electrodes and a Josephson junction connecting the two capacitive electrodes, and a protective layer on a surface of the Josephson junction.

Description

Technical Field

[0001] This application relates to the field of superconducting quantum computing technology, specifically to a superconducting quantum computing chip based on a corrosion-resistant Josephson junction and its fabrication method. Background Technology

[0002] Josephson junction-based superconducting quantum computing, with its excellent designability, scalability, and ease of coupling and manipulation, has become one of the most promising quantum computing solutions. A crucial indicator of the quality of a superconducting quantum computing chip is the length of the coherence time of its qubits (the fundamental units of quantum computing): a longer coherence time means that the quantum computer can perform more complex calculations. Therefore, optimizing the coherence time of superconducting qubits has become one of the key research focuses in the field of superconducting quantum computing.

[0003] Current research indicates that a major factor causing decoherence in superconducting qubits is microwave loss in the material. Materials located on the surface of superconducting thin films and chip substrates react with atmospheric oxygen upon contact with the environment, forming oxides. Experiments show that this oxide layer introduces significant microwave loss. To eliminate the negative impact of this oxide layer, a common method is to clean the sample with hydrofluoric acid solution after chip fabrication. The chemical reaction between the acid and the oxide dissolves the surface oxide layer.

[0004] Josephson junctions are the core structure of superconducting qubits. Aluminum is a commonly used material in the fabrication of Josephson junctions. However, aluminum is a reactive metal that reacts chemically with acids. Therefore, how to remove the oxide layer from the sample surface without damaging the aluminum-based Josephson junction has become a challenge that needs to be overcome. Summary of the Invention

[0005] To address the aforementioned deficiencies in this field, this application aims to provide a superconducting quantum computing chip based on a corrosion-resistant Josephson junction and its fabrication method.

[0006] According to one aspect of this application, a superconducting quantum computing chip based on a corrosion-resistant Josephson junction is provided, comprising: Substrate; Multiple superconducting qubits are periodically arranged on the first surface of a substrate, and each superconducting qubit includes two capacitor electrodes and a Josephson junction connecting the two capacitor electrodes. The Josephson junction has a protective layer on its surface.

[0007] In some embodiments of this application, the protective layer material is selected from gold, calcium fluoride, or silicon nitride.

[0008] In some embodiments of this application, the thickness of the protective layer is 40-50 nm.

[0009] In some embodiments of this application, an adhesive layer is also provided between the protective layer and the Josephson junction.

[0010] In some embodiments of this application, the adhesive layer material is titanium; the thickness of the adhesive layer is 1-3 nm.

[0011] In some embodiments of this application, the protective layer is prepared using a thermal evaporation process.

[0012] In another aspect of this application, a method for fabricating a superconducting quantum computing chip based on a corrosion-resistant Josephson junction is also provided, comprising: Multiple capacitor electrodes arranged periodically are fabricated on the first surface of the substrate; Photoresist is spin-coated onto the first surface of the substrate on which the capacitor electrode has been fabricated, and a photoresist pattern is prepared. A first aluminum film layer is prepared on a first surface of a substrate by photoresist patterning, the surface of the first aluminum film layer is oxidized to obtain an aluminum oxide layer, and a second aluminum film layer is prepared on the surface of the aluminum oxide layer to obtain a Josephson junction. The substrate with the prepared Josephson junction is placed in a thermal evaporation device to deposit a protective layer; After removing the residual photoresist, a superconducting quantum computing chip based on a corrosion-resistant Josephson junction was fabricated.

[0013] In some embodiments of this application, the preparation method further includes cleaning the superconducting quantum computing chip in a hydrofluoric acid solution.

[0014] In some embodiments of this application, the adhesive layer is deposited first in a thermal evaporation apparatus, followed by the deposition of the protective layer.

[0015] In some embodiments of this application, the protective layer material is selected from gold, calcium fluoride, or silicon nitride; the thickness of the protective layer is 40-50 nm; The adhesive layer material is titanium; the thickness of the adhesive layer is 1-3 nm. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the aluminum-based Josephson junction in an example embodiment of this application. Figure 2 This is a schematic diagram of the fabrication process of an aluminum-based Josephson junction, as shown in an example embodiment of this application. Figure 3 This is a partial scanning electron microscope (SEM) image of a superconducting quantum computing chip according to an example embodiment of this application. Figure 4 This is a partial transmission electron microscope (TEM) image of a superconducting quantum computing chip according to an example embodiment of this application. Figure 5 This is a schematic diagram of the structure of a superconducting quantum computing chip according to an example embodiment of this application. Figure 6 The reading of qubits from a superconducting quantum computing chip, as exemplified in this application. Detailed Implementation The technical solution of this application will be clearly and completely described below with reference to the embodiments of this application. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] It should be particularly noted that similar substitutions and modifications made to this application are obvious to those skilled in the art, and they are all considered to be included in this application. Those skilled in the art can obviously make modifications or appropriate alterations and combinations to the methods and applications described herein without departing from the content, spirit, and scope of this application to implement and apply the technology of this application. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0018] Unless otherwise specified, this application is conducted under standard conditions or conditions recommended by the manufacturer. The raw materials or excipients used, as well as the reagents or instruments used, whose manufacturers are not specified, are all conventional products that can be obtained commercially.

[0019] Josephson junction: A three-layer structure composed of superconductor / insulator / superconductor, widely used in superconducting quantum computing.

[0020] Decoherence: The physical process that affects the coherence time of a qubit. The stronger the decoherence effect, the shorter the coherence time of the qubit.

[0021] In-situ growth: Multiple vacuum devices are interconnected, and samples can be transferred between different vacuum devices to achieve the growth of different materials without disrupting the vacuum.

[0022] Photoresist: A polymer material whose molecular structure changes when exposed to light or an electron beam, thereby altering its solubility. It is a key material used in the semiconductor field to define device structures.

[0023] PMMA: Polymethyl Methacrylate, a common polymer used in photoresists. SEM: Scanning Electron Microscopy TEM: Transmission Electron Microscopy The following is a detailed description of this application.

[0024] In existing technologies, common surface treatment methods for improving the coherence time of superconducting qubits include: Hydrofluoric acid solution cleaning: This method uses a chemical reaction to dissolve the oxide layer.

[0025] In-situ growth protective layer: In a vacuum environment, a protective layer is covered on the surface of the superconducting thin film to prevent the superconducting thin film from reacting with oxygen in the atmosphere.

[0026] Currently, both of these approaches have significant limitations in extending the coherence time of superconducting qubits: While hydrofluoric acid can effectively remove the dielectric layer, the Josephson junction, a key structure of superconducting qubits, is typically made of materials easily corroded by hydrofluoric acid, such as aluminum; aluminum is particularly susceptible to hydrofluoric acid corrosion. Therefore, this method is mainly used to improve the performance of aluminum-free components in superconducting quantum chips, such as tantalum resonant cavities coupled to qubits. For aluminum-based qubits, directly using hydrofluoric acid solution would damage the Josephson junction structure.

[0027] In-situ grown protective layers can prevent the oxidation of superconducting thin films, but this method requires an in-situ growth system, which significantly increases experimental costs. More importantly, what materials can effectively serve as protective layers without affecting the performance of superconducting quantum chips remains a research topic and is still inconclusive.

[0028] To address the aforementioned technical problems, this application presents a superconducting quantum computing chip based on a corrosion-resistant Josephson junction, such as... Figure 1 and Figure 5 As shown, it includes: a substrate X and a plurality of superconducting qubits A arranged periodically on a first surface of the substrate X, each superconducting qubit A including two capacitor electrodes 1 and a Josephson junction 2 connecting the two capacitor electrodes; The Josephson junction may optionally be an aluminum-based Josephson junction, and the surface of the Josephson junction has a protective layer 3.

[0029] Optionally, the protective layer material is selected from gold, calcium fluoride, or silicon nitride.

[0030] The thickness of the protective layer is 40-50nm.

[0031] There is also an adhesive layer (not shown in the figure) between the protective layer 3 and the Josephson junction 2.

[0032] The adhesive layer material is titanium; the thickness of the adhesive layer is 1-3 nm.

[0033] The protective layer is prepared using a thermal evaporation process.

[0034] Alternatively, the aluminum-based Josephson junction is a Josephson junction with an aluminum-alumina-alumina sandwich structure.

[0035] In some examples, the substrate is selected from: sapphire substrate, high-resistivity silicon substrate; the thickness of the substrate is 0.4-0.5 mm.

[0036] Optionally, the material of the capacitor electrode is selected from aluminum, niobium, and tantalum; the thickness is 100-300 nm.

[0037] Optionally, the thickness of the first aluminum film layer is 10-100 nm, the thickness of the aluminum oxide layer is 1-3 nm, and the thickness of the second aluminum film layer is 20-200 nm.

[0038] The method for fabricating the superconducting quantum computing chip based on the corrosion-resistant Josephson junction described in this application, such as... Figure 2 As shown, it includes: Multiple periodically arranged capacitor electrodes 1 are fabricated on the first surface of substrate X; Photoresist a, b, and c are spin-coated onto the first surface of the substrate X after the capacitor electrode 1 has been prepared, and a photoresist pattern is prepared. A first aluminum film layer is prepared on the first surface of the substrate by photoresist patterning, the surface of the first aluminum film layer is oxidized to obtain an aluminum oxide layer, and a second aluminum film layer is prepared on the surface of the aluminum oxide layer to obtain Josephson junction 2. The substrate X, after the Josephson junction 2 has been prepared, is placed in a thermal evaporation device to deposit a protective layer 3; After removing the residual photoresist, a superconducting quantum computing chip based on a corrosion-resistant Josephson junction was fabricated.

[0039] Alternatively, chemical deposition methods, such as atomic layer deposition, can be used to prepare the protective layer structure. Thermal evaporation is carried out in a vacuum, which can minimize contamination of the material. However, when using chemical deposition, the gas composition and chemical reaction products in the environment are more complex, which may cause contamination of the sample, especially the sample surface, and introduce defects. Therefore, this application prefers thermal evaporation in a vacuum.

[0040] The preparation method also includes cleaning the superconducting quantum computing chip based on an aluminum-based Josephson junction in a hydrofluoric acid solution.

[0041] In some examples, the adhesive layer is deposited first in a thermal evaporation apparatus, followed by the protective layer.

[0042] Optionally, a is a release adhesive, b is PMMA adhesive, and c is conductive adhesive.

[0043] Optionally, the protective layer material is selected from gold, calcium fluoride or silicon nitride; the thickness of the protective layer is 40-50 nm; the adhesive layer material is titanium; the thickness of the adhesive layer is 1-3 nm.

[0044] The technical solution of this application will be further described below with reference to specific embodiments. Example 1 A capacitor electrode is fabricated on the first surface of a single-crystal silicon substrate, and then a Josephson junction with an aluminum-alumina-alumina sandwich structure is grown using the Manhattan method.

[0045] After the Josephson junction was prepared, the sample was transferred to a thermal evaporation apparatus.

[0046] In a vacuum environment, a titanium bonding layer with a thickness of about 2 nm is first evaporated, followed by a gold layer with a thickness of about 40 nm.

[0047] After stripping the photoresist, the sample surface is cleaned with a certain concentration of hydrofluoric acid.

[0048] Example 2 A capacitor electrode is fabricated on the first surface of a sapphire substrate, and then a Josephson junction with an aluminum-alumina-alumina sandwich structure is grown using a double tilt process.

[0049] After the Josephson junction was prepared, the sample was transferred to a thermal evaporation apparatus.

[0050] In a vacuum environment, a titanium metal bonding layer with a thickness of about 2 nm is first evaporated, followed by a silicon nitride protective layer with a thickness of about 50 nm.

[0051] After stripping the photoresist, the sample surface is cleaned with a certain concentration of hydrofluoric acid.

[0052] Experimental Example 1. The Josephson junction structure was characterized using scanning electron microscopy (SEM) and transmission electron microscopy (TEM) on the sample of Example 1 after hydrofluoric acid cleaning. Figure 3 Figure 4 As shown in the top view of the SEM, the gold film completely covers the entire Josephson junction structure (dashed line); and in the cross-sectional image of the TEM, the protective layer can also be seen covering the entire upper surface of the Josephson junction. These results demonstrate that the protective layer effectively protects the aluminum metal from corrosion by hydrofluoric acid.

[0053] 2. Test the readout of the qubits with protective layers in the above embodiments. The test results are as follows: Figure 6 As shown, the step-like transitions indicate that the qubits with protective layers in this application can function normally.

[0054] The above description of the embodiments is only for the purpose of helping to understand the method and core ideas of this application. It should be noted that, for those skilled in the art, several improvements and modifications can be made to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A superconducting quantum computing chip based on a corrosion-resistant Josephson junction, characterized in that, include: Substrate; Multiple superconducting qubits are periodically arranged on a first surface of the substrate, and each superconducting qubit includes two capacitor electrodes and a Josephson junction connecting the two capacitor electrodes; The Josephson junction has a protective layer on its surface.

2. The superconducting quantum computing chip based on a corrosion-resistant Josephson junction as described in claim 1, characterized in that, The protective layer material is selected from gold, calcium fluoride, or silicon nitride.

3. The superconducting quantum computing chip based on a corrosion-resistant Josephson junction according to claim 1 or 2, characterized in that, The thickness of the protective layer is 40-50 nm.

4. The superconducting quantum computing chip based on a corrosion-resistant Josephson junction according to claim 1 or 2, characterized in that, An adhesive layer is also present between the protective layer and the Josephson junction.

5. The superconducting quantum computing chip based on a corrosion-resistant Josephson junction according to claim 4, characterized in that, The adhesive layer material is titanium; the thickness of the adhesive layer is 1-3 nm.

6. The superconducting quantum computing chip based on a corrosion-resistant Josephson junction according to claim 1 or 2, characterized in that, The protective layer is prepared using a thermal evaporation process.

7. A method for fabricating a superconducting quantum computing chip based on a corrosion-resistant Josephson junction, characterized in that, include: Multiple capacitor electrodes arranged periodically are fabricated on the first surface of the substrate; Photoresist is spin-coated onto the first surface of the substrate on which the capacitor electrode has been fabricated, and a photoresist pattern is prepared. A first aluminum film layer is prepared on the first surface of the substrate by means of the photoresist pattern, the surface of the first aluminum film layer is oxidized to obtain an aluminum oxide layer, and a second aluminum film layer is prepared on the surface of the aluminum oxide layer to obtain a Josephson junction; The substrate for which the Josephson junction has been prepared is placed in a thermal evaporation apparatus to deposit a protective layer; After removing the residual photoresist, the superconducting quantum computing chip is obtained.

8. The preparation method according to claim 7, characterized in that, It also includes immersing the aluminum-based Josephson junction-based superconducting quantum computing chip in a hydrofluoric acid solution for cleaning.

9. The preparation method according to claim 7, characterized in that, In the thermal evaporation equipment, the adhesive layer is deposited first, followed by the protective layer.

10. The preparation method according to claim 9, characterized in that, The protective layer material is selected from gold, calcium fluoride, or silicon nitride; the thickness of the protective layer is 40-50 nm. The adhesive layer material is titanium; the thickness of the adhesive layer is 1-3 nm.

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