Two-dimensional metasurface with integrated capacitor and active matrix driver wiring

Abstract

The metasurface may include a substrate layer and an array of two-dimensional metal optical columns arranged in rows and columns. A tunable dielectric material having a tunable refractive index is located between adjacent rows of optical resonators. A two-dimensional active matrix driver includes integrated driver wiring layers, capacitor layers, and / or transistor layers. And the driver wiring layer realizes row addressing and column addressing of the two-dimensional metal column array through the row conductor of each row metal column and the column conductor of each column metal column. The transistor layer includes transistor devices connected to and configured to be selectively driven by the row and column conductors. The capacitor layer includes a plurality of storage capacitors. Each metal pillar is connected in parallel to one of the storage capacitors in the capacitor layer and one of the transistor devices in the transistor layer.

Description

[0001] Related applications This application claims priority to U.S. Patent Application No. 18 / 481,936, filed October 5, 2023, entitled “Two-Dimensional Metasurfaces with Integrated Capacitors and Active-MatrixDriver Routing”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to optical metasurfaces, including tunable resonant optical metasurfaces. This disclosure also relates to two-dimensional row and column matrix addressing schemes. Attached Figure Description

[0003] Figure 1A A perspective view of a simplified block diagram of the reflective layer and resonator layer of a two-dimensional optical metasurface according to one embodiment is shown.

[0004] Figure 1B An exploded perspective view of a simplified block diagram of the reflective layer and resonator layer of a two-dimensional optical metasurface according to one embodiment is shown.

[0005] Figure 1C A top perspective view shows a simplified block diagram of the reflective layer and resonator layer of a two-dimensional optical metasurface according to one embodiment.

[0006] Figure 1D A side perspective view of a simplified block diagram of the reflective layer and resonator layer of a two-dimensional optical metasurface according to one embodiment is shown.

[0007] Figure 2 An example diagram of a control layer of a two-dimensional optical metasurface with active matrix addressing according to one embodiment is shown.

[0008] Figure 4 A side view of a tunable optical metasurface partial layer according to one embodiment is shown.

[0009] Figure 5A An example diagram of the optical field in an optical resonator of a resonator layer of a tunable optical metasurface according to one embodiment is shown.

[0010] Figure 5B A tunable dielectric material between two pillars aligned in a first direction is shown according to one embodiment, which provides a first refractive index without any voltage being applied.

[0011] Figure 5CA tunable dielectric material between pillars aligned in a second direction according to one embodiment is shown, which provides a second refractive index when a 5-volt voltage is applied.

[0012] Figure 5D A graph showing the phase response of a resonant unit cell relative to an applied voltage value according to one embodiment is shown.

[0013] Figure 6A A top view is shown of a portion of a tunable optical metasurface with offset rows of pillars according to one embodiment.

[0014] Figure 6B An example diagram is shown of a misaligned non-resonant gap in the reflective layer of a tunable optical metasurface according to one embodiment, used to reduce or eliminate coupling between unit cell lattices.

[0015] Figure 6C An example diagram of aligned non-resonant gaps in a tunable optical metasurface reflective layer according to one embodiment is shown.

[0016] Figure 6D An example diagram of the light field in a tunable optical metasurface resonator layer with staggered rows of pillars according to one embodiment is shown.

[0017] Figure 7A A top view of a portion of a tunable optical metasurface with row-aligned pillars according to one embodiment is shown.

[0018] Figure 7B An example diagram is shown of a non-resonant gap in the reflective layer of a tunable optical metasurface according to one embodiment, used to reduce or eliminate coupling between unit cell lattices.

[0019] Figure 7C An example diagram of the light field in row-aligned pillars in the resonator layer of a tunable optical metasurface according to one embodiment is shown.

[0020] Figure 8 An example diagram of another example of a metasurface according to one implementation is shown.

[0021] Figure 9 An example of an active matrix driver architecture with tiled apertures according to one embodiment is shown, where each tile represents a diffraction-limited, individually addressable component building block.

[0022] Figure 10A A top view of an example of a tunable optical metasurface in the XY plane according to one embodiment is shown.

[0023] Figure 10B An embodiment is shown. Figure 10A Example of a first side cross-section of the XZ plane of the tunable optical metasurface.

[0024] Figure 10C An embodiment is shown. Figure 10A Example of a second side cross-section of the XZ plane of the tunable optical metasurface.

[0025] Figure 10D An embodiment is shown. Figure 10A The light field distribution within the resonator layer in the top view of the XY plane of the tunable optical metasurface shown.

[0026] Figure 11 An example diagram of the control layer of a two-dimensional optical metasurface with active matrix addressing and pixel-level storage capacitance according to one embodiment is shown.

[0027] Figure 12A An example of an active matrix control layer with pixel-level grounded storage capacitance is shown according to one embodiment.

[0028] Figure 12B An example of an active matrix control layer with pixel-level differential storage capacitance is shown according to one embodiment.

[0029] Figure 13A A perspective view of a simplified block diagram of an optical metasurface according to one embodiment is shown, the optical metasurface including an optical layer, a capacitor layer, a driver wiring layer, and a transistor layer.

[0030] Figure 13B Another perspective view showing a simplified block diagram of an optical metasurface according to one embodiment, the optical metasurface including an optical layer, a capacitor layer, a driver wiring layer, and a transistor layer.

[0031] Figure 14A A perspective view of a simplified block diagram of a unit lattice of an optical metasurface according to one embodiment is shown, the unit lattice including two pillars, a storage capacitor, a source driver and a gate driver, and a transistor.

[0032] Figure 14B Another perspective view shows a simplified block diagram of a unit lattice of an optical metasurface according to one embodiment, the unit lattice including two pillars and the gap between them, a storage capacitor, a source driver and a gate driver, and a transistor.

[0033] Figure 15A A top view of the transistor layer, gate driver wiring layer, and source driver wiring layer of a unit lattice of an optical metasurface according to one embodiment is shown.

[0034] Figure 15B A top view of the capacitor layer and optical layer of the unit lattice of an optical metasurface according to one embodiment is shown. Detailed Implementation

[0035] Tunable optical metasurfaces can be dynamically tuned to spatially modulate incident light radiation. Modulating the phase and / or amplitude of the incident light radiation can be used to generate output light radiation with a targeted profile. Spatial light modulation can be used for beam shaping, beam forming, and beam steering. The systems and methods described herein can be applied to tunable metasurfaces with various architectures and designs to deflect light radiation within an operating bandwidth. In various implementations, a controller or metasurface driver selectively applies voltage modes to an array of two-dimensional optical structures located on a reflective layer. The voltage difference between adjacent optical structures alters the refractive index of the dielectric material between them. The combination of phase delays generated by the applied voltage modes can be used to produce constructive interference.

[0036] Examples of various tunable optical metasurfaces are described herein and illustrated in the accompanying drawings. For example, a tunable optical metasurface may comprise a two-dimensional array of metallic optical pillars (e.g., antenna elements, elongated pillar elements, pairs of metal pillars, etc.). Liquid crystals or other dielectric materials with tunable refractive indices are located in the gaps or channels between adjacent metallic optical pillars. Liquid crystals are used in many of the examples provided in this disclosure. However, it should be understood that in many cases, alternative dielectric materials with tunable refractive indices and / or combinations of different dielectric materials with tunable refractive indices may be used instead of liquid crystals. Examples of suitable dielectric materials with tunable refractive indices include liquid crystals, electro-optic polymers, electro-optic crystals, chalcogenides, and / or various semiconductor materials.

[0037] In various implementations, the reflection phase of optical radiation can be altered by biasing the liquid crystal in the metasurface with applied voltage bias modes. For example, each different voltage mode applied to the metasurface corresponds to a different reflection phase mode. Each different reflection phase corresponds to unique spatial modulation, beam manipulation, beamforming, or other controlled optical transmission. Digital or analog controllers (controlling current and / or voltage), such as passive or switch-matrix active drivers, can apply differential voltage bias modes to achieve a target phase modulation mode on a two-dimensional array. The metasurface can be spatially modulated to achieve target beam shaping, one-dimensional beam manipulation (i.e., manipulation along one direction), two-dimensional beam manipulation (i.e., manipulation along two directions), wavelength filtering, beam divergence, beam convergence, beam focusing, and / or controlled deflection, refraction, and / or reflection of incident light radiation.

[0038] For further descriptions, variations, functions, and uses of optical metasurfaces, please see: U.S. Patent No. 10,451,800, granted October 22, 2019, entitled "Plasmonic Surface-Scattering Elements and Metasurfaces for Optical Beam Steering"; U.S. Patent No. 10,665,953, granted May 26, 2020, entitled "Tunable Liquid Crystal Metasurfaces"; U.S. Patent No. 11,092,675, granted August 17, 2021, entitled "Lidar Systems based on Tunable Optical Metasurfaces"; and U.S. Patent No. 11,429,008, granted August 20, 2022, entitled "Liquid Crystal Metasurfaces with Cross-Backplane Optical Reflectors," the entire contents of which are incorporated herein by reference.

[0039] This disclosure includes various embodiments and variations of tunable optical metasurface devices and methods for fabricating the same. It should be understood that the metasurface technology described herein may incorporate or otherwise utilize prior advances in surface scattering antennas, such as those described in U.S. Patent Publication No. 2012 / 0194399, published August 2, 2012, entitled “Surface Scattering Antennas”; U.S. Patent Publication No. 2019 / 0285798, published September 19, 2019, entitled “Plasmonic Surface-Scattering Elements and Metasurfaces for Optical Beam Steering”; and U.S. Patent Publication No. 2018 / 0241131, published August 23, 2018, entitled “Optical Surface-Scattering Elements and Metasurfaces”, all of which are incorporated herein by reference in their entirety.Other components, applications, and features of surface scattering antennas are described in the following: U.S. Patent Publication No. 2014 / 0266946, published September 18, 2014, entitled "Surface Scattering Antenna Improvements"; U.S. Patent Publication No. 2015 / 0318618, published November 5, 2015, entitled "Surface Scattering Antennas with Lumped Elements"; U.S. Patent Publication No. 2015 / 0318620, published November 5, 2015, entitled "Curved Surface Scattering Antennas"; U.S. Patent Publication No. 2015 / 0380828, published December 31, 2015, entitled "Slotted Surface Scattering Antennas"; and U.S. Patent Publication No. 2015 / 0162658, published June 11, 2015, entitled "Surface Scattering Antennas". U.S. Patent No. 2015 / 0372389, published December 24, 2015, entitled “Modulation Patterns for Surface Scattering Antennas”; PCT Application No. PCT / US18 / 19269, filed February 22, 2018, entitled “Control Circuitry and Fabrication Techniques for Optical Metasurfaces”; U.S. Patent No. 2019 / 0301025, published October 3, 2019, entitled “Fabrication of Metallic Optical Metasurfaces”; and U.S. Patent No. 2018 / 0248267, published August 30, 2018, entitled “Optical Beam-Steering Devices and Methods Utilizing Surface Scattering Metasurfaces”, the entire contents of which are incorporated herein by reference.

[0040] In some embodiments, the tunable optics includes a substrate, a reflective layer, and a two-dimensional array of metallic optical pillars. This array of two-dimensional metallic optical pillars can be arranged in parallel rows extending vertically relative to the substrate. In some examples, the width of each pillar along each row is less than half the minimum wavelength of the operating bandwidth, and the length of each pillar perpendicular to the direction of each row is less than the minimum wavelength of the operating bandwidth (referred to as subwavelength spacing). In other embodiments, the spacing between pillars in each row can be greater than the maximum wavelength or multiple wavelengths of the operating bandwidth.

[0041] The gaps between adjacent pillars form optical resonators, such that each row of pillars contains multiple optical resonator gaps or cavities. A tunable dielectric material with a tunable refractive index (e.g., liquid crystal) is located between the pillars, included within the optical resonators formed by the gaps between adjacent pillars. A reflective layer is located between the substrate layer and the two-dimensional pillar array to reflect light radiation.

[0042] The reflective layer may, for example, comprise an array of two-dimensional, elongated rectangular reflector patches arranged in parallel rows. The metasurface may be controlled by a controller. For example, the controller may comprise a passive or active switching matrix of control lines for selectively applying a voltage differential bias mode to a tunable dielectric material between adjacent metallic optical pillars.

[0043] In various embodiments, the metasurface includes integrated active matrix driver components and / or integrated storage capacitors to improve response speed and performance. The metasurface may include an integrated driver wiring layer located between a substrate layer and an optical resonator layer (e.g., metal pillars). The driver wiring layer may include row driver wiring layers and column driver wiring layers. The row driver wiring layer may include row conductors for each row of metal pillars. Similarly, the column driver wiring layer may include column conductors for each column of metal pillars.

[0044] The metasurface may also include an integrated transistor layer with multiple transistor devices, each transistor device being connected to one of the row conductors and one of the column conductors and configured to be selectively driven by them. Each transistor device may be connected (e.g., electrically connected, but not necessarily in direct contact) to one or more metal pillars (e.g., through conductor vias, traces, integrated wires, etc.). The role of each transistor device is to selectively drive a voltage onto the connected metal pillar. For example, each transistor device may be a metal-oxide-semiconductor field-effect transistor (MOSFET). The gate of each MOSFET may be connected to the row conductor associated with the metal pillar, and each corresponding transistor device is connected to that metal pillar. A controller can “turn on” or activate the transistor device associated with the row of metal pillars by driving a voltage (e.g., a digital signal) on the corresponding row conductor.

[0045] Each metal pillar connected to and driven by a transistor device is considered an "active" metal pillar. In some embodiments, each metal pillar is connected to at least one transistor device, such that each metal pillar is an active metal pillar. In other embodiments, only a subset of the metal pillars in the two-dimensional metal pillar array are connected to transistor devices, such that the subset of the two-dimensional metal pillar array is an active metal pillar. In this disclosure, the examples and embodiments described all include the case where all metal pillars are active metal pillars. However, it should be understood that the metal pillar array may contain a combination or mixture of active and passive metal pillars. For the sake of brevity, an active metal pillar is simply referred to as a "metal pillar," wherein a metal pillar connected to a transistor device in a transistor layer is an "active metal pillar."

[0046] The source of each MOSFET can be connected to a column conductor associated with the metal pillar to which the corresponding transistor device is connected. The drain of each MOSFET can be connected to each corresponding metal pillar, such that when the MOSFET is activated through the row conductor, the source of the same MOSFET can be driven through the corresponding column conductor, thereby driving a voltage on the metal pillar. It is understood that the column conductor and row conductor can be interchanged, such that the column conductor is connected to the gate of the respective MOSFET, and the row conductor is connected to the source of the respective MOSFET. Furthermore, although the figures depict MOSFETs, and many embodiments described herein use MOSFETs as example transistor devices, it is understood that various switching devices and / or amplifier devices may be used in place of or supplementing MOSFETs. Thus, the metasurface may include a transistor layer containing transistors, amplifiers, and / or other switching devices, such as, but not limited to, bipolar junction transistors, cascode amplifiers, diodes, insulated-gate bipolar transistors, junction field-effect transistors, MOSFETs, and / or combinations thereof.

[0047] According to various implementations, each metal pillar in the optical resonator layer is connected in parallel with one (or more) storage capacitors in the capacitor layer and one (or more) transistor devices in the transistor layer. In some implementations, multiple metal pillars may be connected to the same storage capacitor and / or the same transistor device.

[0048] A storage capacitor and a metal pillar are connected in parallel to the "output" of the transistor, allowing the storage capacitor to maintain the voltage level of the metal pillar between refresh cycles. Furthermore, the storage capacitor maintains the voltage level of the metal pillar during switching of liquid crystal or other tunable dielectric materials. The capacitance associated with the metal pillar connected to the transistor output varies significantly based on the orientation of the liquid crystal in the resonant unit lattice formed by the metal pillar and its adjacent rows of metal pillars. For example, when the liquid crystal is oriented parallel to the metal pillar walls (e.g., copper pillar walls), its dielectric constant is approximately 4ε, where ε is the vacuum dielectric constant. However, when the liquid crystal is oriented perpendicular to the metal pillar walls, its dielectric constant is approximately 20ε. Assuming the surface area of ​​the metal pillar is approximately 800 nm × 600 nm and the gap between adjacent metal pillars is 250 nm, the capacitance of the metal pillar connected to the transistor output may vary between 0.07 femtofarads (fF) and 0.34 femtofarads (fF).

[0049] The role of the storage capacitor is to maintain the voltage level of the metal pillars between refresh cycles, even if the capacitance of the metal pillars changes during switching. Various integrated circuit (e.g., CMOS-compatible) capacitor architectures can be used, including but not limited to metal-insulator-metal (MIM) capacitors, metal-oxide-metal (MOM) capacitors, and / or metal-oxide-semiconductor (MOS) capacitors. In some embodiments, the capacitor layer comprises one or more interdigitated or staggered storage capacitors or sublayers thereof. It is understood that each metal pillar may be connected to a “single” storage capacitor, but a “single” storage capacitor may include one or more discrete capacitors connected in series and / or parallel. In some embodiments, the capacitor layer is integrated into the same layer as the transistor layer (e.g., the transistor layer and the capacitor layer are the same layer). For example, each of a plurality of storage capacitors may be a trench capacitor formed in the transistor layer and adjacent to one of the transistor devices.

[0050] In some implementations, the storage capacitors in the capacitor layer are grounded. That is, one terminal or connection of the storage capacitor is grounded, while the other terminal or connection is connected to a metal pillar (e.g., in parallel with the connection between the MOSFET drain and the metal pillar). In other implementations, the storage capacitors in the capacitor layer are differentially connected to storage capacitors on adjacent metal pillars. The exact capacitance value of the storage capacitors can be adjusted based on specific operating configurations, target switching performance, the inherent capacitance of the metal pillars, voltage range, refresh rate, leakage current, and refresh cycle time. In some exemplary implementations, the capacitance value of each storage capacitor is between 0.1 femtofarads (fF) and 3.0 femtofarads (fF).

[0051] As described herein, the controller can selectively apply voltage patterns to the metal pillars to achieve a target phase modulation profile. The voltage patterns can be applied to the metal pillars via an active switch matrix driver configuration or a simple “active matrix” configuration that sequentially drives the voltage on each row conductor to temporarily activate the transistor devices in the associated metal pillar row. The controller can sequentially activate the transistor devices in each row according to the refresh rate (duration between 25 microseconds and 100 microseconds, e.g., 50 microseconds). For example, the controller can drive a digital voltage signal to the gate of each transistor device connected to the row conductor. During the refresh cycle of each row of transistor devices, the controller drives each column conductor, applying the target voltage to each metal pillar (and its connected storage capacitor) in the metal pillar row associated with the temporarily activated transistor device. For example, the controller can drive an analog voltage pattern on the column conductor to drive each metal pillar to the target voltage.

[0052] While this document describes a 50-microsecond refresh rate example, faster refresh rates can be used in some implementations. Similarly, slower refresh rates greater than 100 microseconds may be more suitable, or even superior, where slower switching speeds are acceptable and / or power consumption is a priority. The refresh cycle time can be determined based on the time required to drive voltage to the metal pillars and charge the storage capacitors. In some implementations, the rotation of the tunable dielectric material can take up to 50 or even 100 microseconds. Therefore, a faster refresh rate may not necessarily correspond to a faster device switching speed. The refresh rate can be selected based on factors such as the capacitance of the storage capacitors connected to each metal pillar, the applicable leakage current, the target rotation time of the tunable dielectric material, the target switching speed, etc. Generally, larger storage capacitance values ​​allow for slower refresh rates. In one exemplary implementation, a metasurface is designed to achieve 90% rotation of the liquid crystal within the resonator in less than 100 microseconds. The metasurface includes an integrated capacitor layer with independent storage capacitors (e.g., interdigitated capacitors in one or more sublayers) having capacitance values ​​between 0.1 femtofarads (fF) and 1.0 femtofarads (fF). The controller is configured to apply voltage patterns to the metal pillars at a refresh rate of 25 microseconds to 100 microseconds (e.g., 50 microseconds).

[0053] In some implementations, a metasurface may include multiple tiles, each tile of the metasurface including independent or interconnected active matrix drivers and / or integrated storage capacitors. A controller can drive each tile equally or independently by driving independent row and column conductors of integrated transistors connected to each metasurface tile. The integrated capacitors and / or driver wiring layers described herein are applicable to the tile architectures described in U.S. Patent No. 11,493,823, issued November 8, 2022, entitled “Integrated Driver and Heat Control Circuitry in Tunable Optical Devices,” and U.S. Patent No. 11,487,184, issued November 1, 2022, entitled “Integrated Driver and Self-Test Control Circuitry in Tunable Optical Devices,” the entire contents of which are incorporated herein by reference. For example, integrated driver wiring layers and / or capacitors can be used in conjunction with various tile architectures that utilize multiplexers, built-in self-test circuitry, external drivers, integrated drivers, switching circuitry, etc.

[0054] An active switch matrix controller can be switched to individually control each metallic optical structure of the metasurface. For example, each control output of the active switch matrix controller can be dynamically switched to control different control inputs of the tiled metasurface. The active switch matrix controller can dynamically address any number of independent optical structures or optical structure tiles using, for example, AND gates, OR gates, multiplexer digital logic gates, inverse multiplexer digital logic gates, and / or other switching elements. Therefore, the two-dimensional metal pillar array described herein can be arranged into a two-dimensional tiled structure, where T metasurface tiles are arranged into R rows and S columns, and each metasurface tile contains N rows and M columns of metal pillars arranged in a two-dimensional configuration, where T, R, S, N, and M are integer values.

[0055] In another conceptualization, the two-dimensional metal pillar metasurface described herein can be understood as a module of a multi-module metasurface. For example, the metasurface device described herein can be replicated in a one-dimensional or two-dimensional module array to form a multi-module metasurface. Each module can be driven individually, or, as described in the references cited herein, the metal pillars of each module can be driven collectively, or driven by an active switch matrix driver.

[0056] This document describes examples of metasurfaces that can be used for transmission or reception. Systems equipped with the metasurfaces described herein can operate solely as transmitters, solely as receivers, simultaneously as transmitters and receivers, as time-division multiplexed transmitters / receivers, as frequency-division multiplexed transmitters / receivers, with a first metasurface acting as a transmitter and a second metasurface as a receiver, or employ other transmission / reception configurations or operating techniques. The metasurfaces described herein can be used to control, tune, or modify reflection phase modes. For example, one or more metasurfaces can be used to control (i) the reflection phase, (ii) the reflection amplitude, or (iii) both the reflection phase and the reflection / transmission amplitude of an optical signal. Therefore, in any of the embodiments described herein, metasurfaces can be used to control the complex phase and / or complex amplitude of reflected light radiation.

[0057] The various embodiments described herein can be fabricated to dimensions suitable for optical sensing systems such as LiDAR, optical communication systems, optical computing systems, and displays. For example, the systems and methods described herein can be configured to operate using metasurfaces that utilize optical radiation (including, but not limited to, optical wavelengths in the near-infrared, mid-infrared, long-wave infrared, and / or visible light bands). Considering the feature sizes and antenna spacing required for subwavelength optical antennas, the metasurfaces can be fabricated using microlithography and / or nanolithography processes, such as those commonly used in the fabrication of complementary metal-oxide-semiconductor (CMOS) integrated circuits.

[0058] The implementation schemes disclosed herein can utilize some existing infrastructure, such as general-purpose computers, computer programming tools and techniques, digital storage media, and communication links. Many of the systems, subsystems, modules, components, etc., described herein can be implemented in hardware, firmware, and / or software. Because of the variety of possible implementations, this document describes them based on the functions performed by the various systems, subsystems, modules, and components. For example, it will be understood that many existing programming languages, hardware devices, frequency bands, circuits, software platforms, network infrastructure, and / or data storage can be used individually or in combination to achieve specific control functions.

[0059] It is also understood that two or more elements, devices, systems, subsystems, components, modules, etc., described herein can be combined into a single element, device, system, subsystem, module, or component. Furthermore, many elements, devices, systems, subsystems, components, and modules can be reused or further divided into independent elements, devices, systems, subsystems, components, or modules to perform the subtasks described herein. Any aspect of any embodiment described herein may be combined with any other aspect of any other embodiment described herein or in other disclosures incorporated herein by reference, including all permutations and combinations thereof, provided that such combination is understood by a person skilled in the art upon reading this disclosure in conjunction with such other disclosures.

[0060] For the purposes of this document, computing devices, systems, subsystems, modules, drivers, or controllers may include processors, such as microprocessors, microcontrollers, logic circuits, etc. Processors may include one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), programmable array logic (PALs), programmable logic arrays (PLAs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), or other customizable and / or programmable devices. The computing device may also include machine-readable storage devices, such as non-volatile memory, optical memory, flash memory, or other transient or non-transient machine-readable storage media. Various aspects of certain embodiments may be implemented or enhanced using hardware, software, firmware, or a combination thereof.

[0061] The accompanying drawings describe and illustrate components of some of the disclosed embodiments to provide specific examples. Many of these components can be arranged and designed in a variety of different configurations. Furthermore, features, structures, and operations associated with one embodiment can be applied to or combined with features, structures, or operations described in conjunction with another embodiment. In many cases, well-known structures, materials, or operations are not described in detail to avoid obscuring certain aspects of this disclosure.

[0062] Figure 1A A perspective view of a simplified block diagram of a two-dimensional optical metasurface 100 and a resonator layer 120 according to one embodiment is shown. As shown, the resonator layer 120 includes an array 125 of two-dimensional metallic optical pillars arranged in parallel rows. Each pillar 125 in the resonator layer 120 extends vertically relative to an underlying substrate layer (not shown). The spacing between the pillars 125 in each row can be less than the minimum wavelength within the operating bandwidth. The width (W) of each pillar 125 in each row can be less than half the minimum wavelength of the operating bandwidth. The length (L) of each pillar 125 in a direction perpendicular to each row (e.g., along a column) can be less than the minimum wavelength of the operating bandwidth.

[0063] The gaps between adjacent pillars 125 in each row form an optical resonator. A tunable dielectric material may be deposited within the resonator layer to fill all the spaces between the pillars 125, thereby placing the tunable dielectric material within the optical resonator formed by the gaps between adjacent pillars 125. Examples of suitable tunable dielectric materials with tunable refractive indices include liquid crystals, electro-optic polymers, electro-optic crystals, chalcogenides, and / or various semiconductor materials.

[0064] In alternative embodiments, the spacing between posts 125 in each row can be greater than the wavelength within the operating bandwidth (e.g., ten times the maximum wavelength within the operating bandwidth). Similarly, in some embodiments, the width (W) of each post 125 in each row can be greater than half the minimum wavelength, and the length (L) of each post 125 in a direction perpendicular to each row (e.g., along the column direction) can be much greater than the maximum wavelength of the operating bandwidth.

[0065] The reflective layer 110 comprises an array of two-dimensional elongated rectangular reflector patches 115 extending longitudinally along parallel rows. That is, as shown, the reflector patches 115 extend longitudinally in a direction perpendicular to the longitudinal direction of the pillars 125. Electrically isolated gaps 130 separate reflector patches 115 in adjacent rows. Non-resonant gaps 140 separate adjacent reflector patches 115 in the same row. The orientation of the electrically isolated gaps 130 is non-resonant with the incident electric field direction, therefore there is no resonant coupling. The non-resonant gaps 140 between adjacent reflector patches 115 are perpendicular to the incident electric field. Therefore, the size of the non-resonant gaps 140 is chosen to minimize or avoid any resonance that may occur between reflector patches 115 in the same row within a certain wavelength range of optical radiation. The size of the non-resonant gaps 140 may differ from the size of the electrically isolated gaps 130.

[0066] The via layer 150 can be located between the reflector layer 110 and the resonator layer 120. Each pillar 125 can be electrically connected to a reflector patch 115 below it through a conductor via 155 within the via layer 150. The dielectric of the via layer 150 is omitted from the figure for clarity of the location of the conductor via 155.

[0067] Figure 1BAn exploded perspective view of a simplified block diagram of the reflective layer 110 and resonator layer 120 of the two-dimensional optical metasurface 100 is shown. As shown, the parallel rows of reflector patches 115 are staggered from each other, such that the non-resonant gap 140 between adjacent reflector patches 115 in one row is not aligned (e.g., staggered or misaligned) with the non-resonant gap 140 between adjacent reflector patches 115 in adjacent rows. Each conductive via 155 of the dielectric via layer 150 (the dielectric material around the conductive via 155 has been removed in the figure) connects a post 125 to one of the underlying reflector patches 115. Notably, since the posts 125 extend longitudinally and in a direction perpendicular to the extension direction of the underlying reflector patches 115, half of the posts 125 in the first row (alternating every other post) are connected to the reflector patches 115 in the first row of reflector patches 115, while the other half of the posts 125 (alternating) are connected to the reflector patches 115 in the second row of reflector patches 115.

[0068] Figure 1C This is a top perspective view of a simplified block diagram of the reflective layer 110 and resonator layer 120 of a two-dimensional optical metasurface 100. The top perspective view shows that the pillars 125 are aligned in rows and columns, and extend longitudinally along a first direction (e.g., perpendicular to the incident light radiation angle). In the example shown, the length of each pillar 125 is less than the minimum wavelength of the operating bandwidth, and the width is less than half the minimum wavelength. The gaps between adjacent pillars 125 in the same row also have dimensions smaller than the wavelength. As described herein, in some embodiments, the length, width, and spatial dimensions can be larger.

[0069] The specific dimensions of pillar 125, including its height and interelement spacing, are selected based on the target operating bandwidth, as detailed in the patents and patent publications cited herein. For example, for light radiation with a wavelength of 905 nm, the gap between adjacent pillars 125 constituting the unit lattice, filled with tunable dielectric material, can be approximately 150 nm. The height of pillar 125 can be approximately 400 nm, providing a second-order resonance.

[0070] Figure 1D A side perspective view of a simplified block diagram of the reflective layer 110 and resonator layer 120 of the two-dimensional optical metasurface 100 is shown. The view shown is rotated so that the rows of reflector patches 115 and pillars 125 extend from the bottom of the page to the top. As previously described, the reflector patches 115 extend longitudinally along the row direction, while the pillars 125 extend laterally along the row direction. The relative dimensions of the individual pillars 125 and reflector patches 115 are chosen such that there are two rows of reflector patches 115 below each row of pillars 125.

[0071] Figure 2An example diagram of a control layer 200 for a two-dimensional optical metasurface with active matrix addressing according to one embodiment is shown. The active matrix control system includes rows and columns of transistor devices. Each transistor device is connected to a unique metallic optical pillar via a corresponding reflector patch and conductive via. The control lines of the control layer 200 can be integrated within the substrate of the metasurface or within a separate dielectric layer between the substrate and the reflective layer. The active matrix control system can drive voltages on one or more columns and use row selection lines to turn on transistor devices associated with specific pillars. The active matrix architecture enables the resonant unit lattice of the metasurface to exhibit a unique phase response (Φ) mode, which is a function of row drive (x) and column selection (y), and can be expressed as Φ = f(x, y), as shown in Figure 250.

[0072] Figure 3 An example diagram of a control layer 300 for a two-dimensional optical metasurface with active matrix addressing according to one embodiment is shown. The active matrix control system includes rows and columns of transistor devices. Each transistor device is connected to a unique metallic optical pillar via a corresponding reflector patch and conductive via. The control lines of the control layer 300 can be integrated within the substrate of the metasurface or within a separate dielectric layer between the substrate and the reflective layer. The active matrix control system can drive a voltage on one or more rows and use column select lines to turn on the transistor devices associated with a specific pillar. The active matrix structure allows the resonant unit lattice of the metasurface to exhibit a unique phase response mode (Φ), which is a function of row drive (x) and column selection (y), and can be expressed as Φ = f(x, y), as shown in Figure 350.

[0073] As described herein, each resonant unit lattice comprises two metallic optical pillars separated by a subwavelength gap filled (partially, completely, or overflowing) with a tunable dielectric material having a tunable refractive index. The tunable refractive index of the tunable dielectric material in each resonant unit lattice is selected by establishing a voltage difference between the two metallic optical pillars of the unit lattice. This voltage difference is used to tune the phase (and / or amplitude) of incident light radiation (e.g., laser light). The size of each resonant unit lattice in the direction of the incident light radiation plane can be less than half the wavelength of the light, thereby achieving large field-of-view beam modulation without the generation of grating lobes. By configuring the size of the resonant unit lattice (e.g., the width of the two metallic optical pillars and the gap between them) to be less than half the wavelength (λ / 2) of the incident light radiation in the in-plane direction, diffraction by the resonant unit lattice can be prevented. The size of the resonant unit lattice can be larger in the out-of-plane or lateral directions (e.g., up to the maximum wavelength) while still maintaining a large beam modulation field of view without introducing diffraction. In applications where the incident angle is close to the normal to the metasurface plane, the size of the unit cell lattice can be relaxed (e.g., the size in the in-plane direction is greater than half the wavelength (λ / 2), and / or the size in the out-of-plane or lateral direction is greater than one wavelength).

[0074] Figure 4 A side view of a portion of a tunable optical metasurface 400 with active matrix addressing according to one embodiment is shown. In the illustrated cross-sectional view, metallic optical pillars 425 in the resonator layer 420 form a single row of optical resonators. These pillars 425 extend vertically relative to a substrate layer (not shown) and longitudinally toward the plane of the paper. A dielectric via layer 450 includes conductive vias 455 that connect the pillars 425 to reflector patches 415 within a reflective layer 410. As shown, the reflector patches 415 are staggered or misaligned with each other, such that every other pillar 425 of a reflector patch 415 is not visible in the cross-sectional view. The illustrated example includes a second via layer 460 with conductive vias 465 for connecting the pillars 425 to control lines and transistors 475 within a control layer 470.

[0075] The active matrix architecture enables the resonant unit lattice of metasurface 400 to exhibit a unique phase response (Φ) mode, which is a function of row drive (x) and column selection (y), and can be expressed as Φ = f(x,y). The figure depicts the wavefront incident field and k-vector of the incident light radiation 490. The metasurface can be illuminated at any incident angle, and the incident light radiation is not limited to plane waves. Metasurface 400 can be used to perform arbitrary phase modulation of the incident light radiation 490 to achieve beam manipulation, lensing effects, or other optical functions.

[0076] As shown in the figure, the active matrix addressing scheme includes transistors 475 located beneath each resonant unit lattice. In one embodiment, each resonant unit lattice contains only one transistor connected to one of the pillars, while the other pillar is connected to a fixed voltage. In other embodiments, each resonant unit lattice contains two transistors, each connected to a metal optical pillar, such that each metal optical pillar can be driven with a unique voltage. Although an absolute voltage is applied to each metal optical pillar, the phase of each resonant unit lattice depends on the voltage difference between adjacent metal optical pillars.

[0077] According to various embodiments, the dielectric via layer 450 also serves as a waveguide layer between the resonator layer 420 and the reflector layer 410. The thickness of the waveguide layer causes destructive interference at the bottom of the optical resonator (e.g., the gap between adjacent metallic optical pillars), thereby confining most of the light energy within the vertical pillars and minimizing the light energy leaking into the waveguide layer.

[0078] The resonant unit lattice is tuned via a refractive index-tunable material 485 between adjacent metallic optical pillars 425. For example, a liquid crystal with a high refractive index tuning range can be used. As described herein, applying a differential voltage between adjacent metallic optical pillars 425 causes the liquid crystal in the resonant unit lattice to rotate, thereby changing the refractive index sensed by the x-component of the photoelectric field. This, in turn, changes the effective length of the metallic optical pillars 425, and consequently alters the phase experienced by the incident light radiation 490 at that location on the metasurface. Because the resonant unit lattice is resonant, in many embodiments, the phase change is coupled with a change in the amplitude response, consistent with the typical characteristics of a Lorentz-type resonator. In these embodiments, each metallic optical pillar 425 is programmed with a unique voltage difference (thus generating phase) to achieve a desired spatial phase gradient. This gradient can be used for beam manipulation or other optical functions, such as focusing, collimation, or any arbitrary optical transformation.

[0079] Furthermore, the metal optical pillars 425 can be fabricated using conventional CMOS manufacturing processes, such as copper damascene metallization, deposition, etching, photolithography, patterning, and chemical mechanical planarization. Besides copper, other metals, such as aluminum, silver, silver-plated copper, and gold, can also be used to form the metal core of each optical pillar. Copper is attractive because it is widely used in the semiconductor industry to manufacture transistor interconnects, and its dimensions meet the requirements for realizing these resonant unit lattices. In addition, copper exhibits excellent optical properties in the near-infrared (n-IR) and short-wave infrared (short-wave IR) bands.

[0080] Figure 5AAn example diagram of an optical field 590 within a tunable dielectric material 585 is shown, situated in the gap between a pair of metallic optical pillars 525 and 526 forming an optical resonator, with reflector patches 515 and 516 positioned below. In the illustrated example, the heights of the metallic optical pillars 525 and 526 are chosen to produce a second-order resonance with two magnetic field antinodes 590. According to various embodiments, as shown, each metallic optical pillar 525 and 526 includes metallic cores 527 and 528 and passivation coatings 521 and 522.

[0081] Passivation coatings 521 and 522 can be deposited as a single layer or a uniform layer, covering the sidewalls and topwalls of each metal optical pillar 525. Passivation coatings 521 and 522 can be, for example, thin silicon nitride (SiN) layers used to passivate the metal cores 527 and 528 of each metal optical pillar 525. The function of passivation coatings 521 and 522 is to prevent the metal of the metal optical pillars 525 and 526 from diffusing into the tunable dielectric material (e.g., liquid crystal) and / or to prevent corrosion of the metal optical pillars 525 and 526. Passivation coatings 521 and 522 can be SiN, SiCN, alumina, or other suitable passivation materials.

[0082] Passivation coatings 521 and 522 may be optically transparent and / or reflective within the operating bandwidth of the metasurface to complement the underlying reflective conductive metal cores 527 and 528 (e.g., copper). Passivation coatings 521 and 522 may alternatively (or additionally) comprise silicon carbide nitride, silicon carbide, or aluminum oxide (Al₂O₃). x The dielectric material 585 can be made of hafnium oxide (HfO2), silicon dioxide (SiO2), aluminum nitride (AlN), boron nitride (BN), and / or other passivated dielectric materials. A transistor 575 within the control layer is connected to pillar 525 via a reflector patch 515 and intermediate conductor vias 555 and 565 within dielectric vias 550 and 560. The controller can drive pillar 525 to a target voltage via transistor 575, thereby generating a voltage difference within the optical resonator formed by the gap between pillars 525 and 526. The refractive index of the tunable dielectric material 585 can be adjusted to a target refractive index based on the applied voltage difference between pillars 525 and 526.

[0083] Figure 5B A tunable dielectric material 585 located between two pillars 525 and 526 aligned along a first direction is shown according to one embodiment to provide a first refractive index within an optical resonator without any voltage applied (e.g., zero-volt differential, located at 501).

[0084] Figure 5CA tunable dielectric material 585 located between pillars 525 and 526 according to one embodiment is shown to provide a second refractive index within an optical resonator when a 5-volt voltage is applied (located at 502).

[0085] Figure 5D A graph 599 shows the phase response of a resonant unit lattice according to one embodiment versus an applied voltage value. It should be understood that the phase response and voltage range may vary based on the specific dimensions of pillars 525 and 526, the gap width of the optical resonator filled with tunable dielectric material 585, and / or the specific material used as the tunable dielectric material 585 (e.g., liquid crystal).

[0086] Figure 6A A top view of a portion of a tunable optical metasurface 600 with staggered rows of pillars 625 according to one embodiment is shown. Each resonant unit lattice 621 consists of two metallic optical pillars 625 and 626. Each metallic optical pillar 625 and 626 is connected to one of the reflector patches 615 and 616 via conductive vias 655 and 656. The metasurface 600 operates only under transverse magnetic (TM) polarization. Therefore, the x-component of the electric field (perpendicular to the longitudinal or long sidewalls and parallel to the transverse or short sidewalls) is coupled in the metallic optical pillars 625 and 626 of the resonant unit lattice 621. The gap or slot 603 between the metallic optical pillars 625 and 626 along the y-direction is not coupled to this electric field because the electric field is parallel to the walls of the metallic pillars (e.g., copper) and is therefore excluded from the slot 603. Figure 4 As shown in the cross-sectional view, each reflector patch 615 is connected to the transistor below (e.g., via...). Figure 4 Conductor via 465 in the second via layer 460.

[0087] The reflective layer 610 of reflector patches 615 and 616 includes an asynchronous gap 612 in the x-axis direction. The asynchronous gap 612 provides electrical isolation between adjacent reflector patches 615 and 616 in the same row. The width of the asynchronous gap 612 is carefully chosen to be asynchronous with the incident field, thereby limiting the amount of field leaking into the reflector patches 615 and 616 in the reflective layer 610. Furthermore, an electrical isolation gap 613 or channel is provided along the y-axis direction to electrically isolate adjacent reflector patches 615 and 616 in adjacent rows. Because the electric field is parallel to the metal walls of the reflector patches 615 and 616, the light field does not couple into the electrical isolation gap 613; therefore, the size of the electrical isolation gap 613 can differ from (e.g., be smaller) the size of the asynchronous gap 612, which is more finely chosen to be asynchronous.

[0088] Figure 6BAn example diagram is shown of a staggered non-resonant gap 612 between adjacent reflector patches 615 in a reflective layer 610 according to one embodiment. This gap is used to reduce or eliminate coupling between reflector patches 615 in the same row. An electrically isolating gap 613 can be used to electrically isolate reflector patches 615 in different rows without considering the avoidance of resonance. As described herein, reflector patches 615 in one row are staggered or misaligned relative to reflector patches 615 in adjacent rows to ensure that the non-resonant gaps 612 are staggered rather than aligned with each other.

[0089] Figure 6C An example diagram of aligned non-resonant gaps in a tunable optical metasurface reflective layer according to one embodiment is shown. Electrically isolated gap 613 is used to electrically isolate reflector patches 615 in different rows. Reflector patches 615 in the same row are aligned with reflector patches 615 in adjacent rows. Non-resonant gap 612 is used to reduce coupling between reflector patches in the same row.

[0090] Figure 6D An example diagram of the optical field in a tunable optical metasurface resonator layer with staggered rows of pillars according to one embodiment is shown. As shown, metallic optical pillars 625 and 626 are part of a first resonant unit lattice. A first optical field 623 located between metallic optical pillars 625 and 626 is shown in the figure. The example shown includes staggered or misaligned pillars 625 and 626. Therefore, metallic optical pillars 627 and 628 of a second resonant unit lattice are misaligned, staggered, or misaligned relative to metallic optical pillars 625 and 626 of the first resonant unit lattice. Consequently, a second optical field 624 in the second resonant unit lattice is also staggered or misaligned relative to the first optical field 623.

[0091] Figure 7A A top view of a portion of a tunable optical metasurface 700 with row-aligned pillars 725 is shown according to one embodiment. Each resonant unit lattice 721 contains two metallic optical pillars 725 and 726. Each metallic optical pillar 725 and 726 is connected to one of reflector patches 715 and 716 via conductive vias 755 and 756. The metasurface 700 operates only under transverse magnetic (TM) polarization. Therefore, the x-component of the electric field (perpendicular to the longitudinal or long sidewalls and parallel to the transverse or short sidewalls) is coupled in the metallic optical pillars 725 and 726 of the resonant unit lattice 721. The gap or slot 703 between the metallic optical pillars 725 and 726 along the y-direction is not coupled to this field because the field is parallel to the walls of the metallic pillars and is therefore excluded from the slot 703. Figure 4 As shown in the cross-sectional view, each reflector patch 715 is connected to the transistor below (e.g., via...). Figure 4 Conductor via 465 in the second via layer 460.

[0092] The reflective layer 710 of reflector patches 715 and 716 includes a non-resonant gap 712 along the x-axis. The non-resonant gap 712 provides electrical isolation between adjacent reflector patches 715 and 716 in the same row. The width of the non-resonant gap 712 is selected to be non-resonant with the incident field, thereby limiting the amount of field leaking into the reflector patches 715 and 716 of the reflective layer 710. Furthermore, an electrical isolation gap 713, or channel, is provided along the y-axis to electrically isolate adjacent reflector patches 715 and 716 in adjacent rows. Because the electric field is parallel to the metal walls of the reflector patches 715 and 716, the light field does not couple into the electrical isolation gap 713; therefore, the size of the electrical isolation gap 713 can differ from (e.g., be smaller) the size of the more finely selected non-resonant gap 712.

[0093] Figure 7B An example diagram of a non-resonant gap in a tunable optical metasurface reflective layer according to one embodiment is shown, the gap being used to reduce or eliminate coupling between resonant unit lattices. An electrically isolating gap 713 can be used to electrically isolate reflector patches 715 in different rows without considering the avoidance of resonance. As described herein, reflector patches 715 in one row are staggered or misaligned relative to reflector patches 715 in adjacent rows to ensure that the non-resonant gaps 712 are staggered and misaligned with each other.

[0094] Figure 7C An example diagram of the optical field in a row-aligned resonator layer of a tunable optical metasurface with row-aligned pillars according to one embodiment is shown. As shown, metallic optical pillars 725 and 726 are part of a first resonant unit lattice. A first optical field 723 located between metallic optical pillars 725 and 726 is shown in the figure. The example shown includes row-aligned pillars. Therefore, metallic optical pillars 727 and 728 of a second resonant unit lattice are aligned relative to metallic optical pillars 725 and 726 of the first unit lattice. Consequently, a second optical field 724 in the second resonant unit lattice is also aligned relative to the first optical field 723.

[0095] Figure 8A schematic diagram of another example of a metasurface 800 according to one embodiment is shown. In the illustrated example, the metasurface 800 includes multiple panels 801, 802, 803, and 804. Each panel 801, 802, 803, and 804 includes multiple metallic optical pillars 825, the length of which in the out-of-plane direction (vertical axis) is multiple wavelengths. The pitch or element spacing of the metallic optical pillars 825 on the horizontal axis is less than the diffraction limit (e.g., half a working wavelength). The illustrated metasurface 800 can be used to generate grating lobes in the vertical direction. For example, the metasurface 800 can be used to comb discrete beams along the vertical axis, which can then be converged. Because the element spacing of the metallic optical pillars 825 is less than the diffraction limit, the metasurface 800 does not generate grating lobes on the horizontal axis. Each metallic optical pillar 825 is connected to an elongated reflector patch 815 below via a conductive via 855.

[0096] Figure 9 An example of an active matrix driver architecture 900 with a tiled aperture according to one embodiment is shown, where each tile 901 represents a building block of diffraction-limited, individually addressable elements. As the metasurface aperture size increases, the number of tiles also increases, growing at a rate proportional to the square of the linear size. Furthermore, all or most of the voltage-controlled or tunable elements (e.g., metallic optical pillars) may need to be updated for each change in the phase modulation mode (e.g., for a given steering angle). In some copper pillar-based liquid crystal-tuned metasurface embodiments, switching speeds of 25 to 100 microseconds (e.g., 50 microseconds) can be used, and the entire array is updated on this timescale. In the example shown, the tiled metasurface comprises nine tiles (T=9) arranged in three rows (R=3) and three columns (S=3).

[0097] The active matrix driver architecture 900 shown reduces the complexity, power consumption, and / or size of the driver electronics by decoupling the aperture size from the angular resolution. The angular resolution of each axis is determined by the number of individually addressable resonant cell lattices on each axis. For a given optical design, the aperture size is typically much larger than the diffraction-limited aperture determined by the angular resolution requirements. Each panel 901 can share the same set of source drivers, such as a digital-to-analog converter 981 (DAC) for column addressing and a gate driver 982 for row addressing. The active matrix architecture 900 used for the panel metasurface (including various control lines, capacitors, and / or transistors), along with the DAC 981 and gate driver 982, are collectively referred to herein as part of the metasurface's controller or control layer.

[0098] Alternatively, a passive matrix addressing method can be used to implement the unit cell structure. In this case, each unit cell can have two pillars, including a first pillar driven by a conductor propagating along the x-axis (carrying a row drive voltage) and another pillar connected to a conductor propagating along the y-axis (carrying a column drive voltage). If the unit cell is smaller than the diffraction limit, light will be scattered by both pillars (phase delay). Therefore, an optical function of the form phi = f(x) + f(y) can be realized.

[0099] Figure 10A An example top view of the XY plane of a tunable optical metasurface 1000 according to one embodiment is shown. In the example shown, the unit cell lattice 1080 includes four metallic optical pillars, including a metallic optical pillar 1025 connected to a continuous control line 1005 that provides a driving voltage (x-voltage). All metallic optical pillars connected to the continuous control line 1005 (indicated by connection points in the figure) are driven to the same voltage through the continuous control line 1005.

[0100] Figure 10B An embodiment is shown. Figure 10A The diagram shows an example of a first cross-sectional side view 1001 of the XZ plane of the tunable optical metasurface 1000 at the "cutout A" location. As shown, each metal optical pillar 1025 is connected to the reflector patch 1015 below via a conductor via 1055 and to control lines and / or transistors in the "Y-axis voltage layer" 1075.

[0101] Figure 10C An embodiment is shown. Figure 10A An example diagram of the second cross-sectional side view 1002 of the XZ plane of the tunable optical metasurface at the "cutout B" location. As shown, every other (alternating) metallic optical pillar 1026 is connected to the continuous reflector patch 1016 through conductor vias 1055 in the dielectric via layer 1050.

[0102] Figure 10D An embodiment is shown. Figure 10A The light fields 1018 and 1019 between the metal optical pillars 1025 within the resonator layer in the top view of the XY plane of the tunable optical metasurface 1000 shown.

[0103] Figure 11An example diagram of a control layer 1100 of a two-dimensional optical metasurface with active matrix addressing and pixel-level storage capacitance according to one embodiment is shown. The active matrix control system includes rows and columns of transistors. Each transistor is connected to a unique metallic optical pillar (e.g., through a corresponding reflector patch and / or conductive via, as previously described). The row and column conductor lines of the control layer 1100 can be integrated as a single layer between the substrate and the reflective layer. The active matrix control system can sequentially drive digital voltages onto the row conductors of each consecutive (sequential or non-sequential) row of transistors according to a defined refresh rate.

[0104] A digital voltage driven onto the row conductor activates the transistors in that row. The controller then drives various analog voltage values ​​(e.g., voltage value patterns) onto the column conductor lines, thereby driving the target voltage value through the source of each transistor and onto the capacitors and metal pillars connected to the drains of the respective transistors. The active matrix architecture allows the metasurface resonant unit lattice to exhibit a unique phase response mode (Φ), which is a function of row drive (x) and column selection (y), and can be represented as Φ=f(x,y), as shown in Figure 1150. Each “pixel” or “unit lattice” 1110 of the control layer 1100 includes a transistor whose gate is connected to the row conductor, its source to the column conductor, and its drain to the storage capacitor. Although not shown in the figure, the drain of each transistor is connected in parallel with the storage capacitor shown in the figure to a metal pillar of one of the metasurface resonant unit lattices.

[0105] Figure 12A An example of an active matrix control layer 1200 with pixel-level grounded storage capacitance according to one embodiment is shown. The active matrix control layer 1200 shown is simplified to include nine pixels 1210 arranged in a 3×3 configuration. Adjacent pixels alternately display white and shadow to distinguish different pixels 1210. As shown, pixel 1210 contains transistor 1222. The left-hand adjacent pixel of pixel 1210 contains transistor 1221, and the leftmost pixel contains transistor 1220. Each pixel (specifically the pixel containing transistor 1221) contains a pillar capacitance of metal pillar 1260, which represents the capacitive coupling between the metal pillar and the metal pillar of the adjacent pixel. Each pixel also contains a grounded storage capacitor 1250. The gate of transistor 1221 is connected to row conductor 1231, the source is connected to column conductor 1242, and the drain is connected in parallel to metal pillar 1260 and storage capacitor 1250.

[0106] As shown in the figure, each row conductor 1231, 1232, and 1233 is connected to the gate of the transistor in the corresponding row. Similarly, each column conductor 1241, 1242, and 1243 is connected to the source of the transistor in the corresponding column. Applying a digital voltage to row conductor 1231 activates transistors 1220, 1221, and 1222. Once transistors 1220, 1221, and 1222 are activated, the controller can drive an analog voltage across column conductors 1241, 1242, and 1243. This voltage, through the sources of transistors 1220, 1221, and 1222, drives their respective storage capacitors (including storage capacitor 1250) and metal pillars (including metal pillar 1260). Although column conductor 1242 is connected to the source of transistors 1224 and 1227, analog voltage does not flow through transistors 1224 and 1227 because row conductors 1232 and 1233 are not currently driven to activate the gates of transistors 1224 and 1227.

[0107] Figure 12B Another example of an active matrix control layer 1201 with pixel-level differential storage capacitance according to one embodiment is shown. The illustrated embodiment is combined with... Figure 12A The described implementation is similar, except that the storage capacitors 1275 are arranged in a differential configuration, wherein the storage capacitor 1275 of each pixel is connected to the storage capacitors of adjacent pixels in the same row. The drain of transistor 1220 is still connected in parallel with the storage capacitors 1275 to pillar 1260 (represented as pillar capacitor).

[0108] The following illustrates an example of sequentially activating rows according to a 50-microsecond refresh rate. The controller applies a digital voltage to row conductor 1231 to activate transistors 1220, 1221, and 1222 at T=0. The controller drives analog voltage values ​​on column conductors 1241, 1242, and 1243 to apply target voltages (e.g., 2V, 4V, and 1V) to the metal pillars associated with transistors 1220, 1221, and 1222. Using a 900-nanosecond refresh cycle as an example, at T=0.9 microseconds, the controller stops driving row conductor 1231, thus deactivating transistors 1220, 1221, and 1222. Shortly thereafter, the controller begins driving row conductor 1232 to activate transistors 1223, 1224, and 1225. Even with transistors 1220, 1221, and 1222 deactivated, the metal pillars and energy storage capacitors remain at or near the drive voltage.

[0109] Now that transistors 1223, 1224, and 1225 are activated, the controller drives column conductors 1241, 1242, and 1243 to apply target voltages (e.g., 4V, 1V, and 2V) to the metal pillars associated with transistors 1223, 1224, and 1225. The above process is repeated for row conductor 1233 and the metal pillars associated with transistors 1226, 1227, and 1228. The controller may stop driving the row and column conductors for a period of time until the next refresh cycle begins. At T=50 microseconds, based on a 50-microsecond refresh rate, the controller again drives row conductor 1231, activating and refreshing (and selectively changing) the voltages applied to the metal pillars associated with transistors 1220, 1221, and 1222 by driving analog voltages on column conductors 1241, 1242, and 1243.

[0110] As described herein, the storage capacitor 1275 helps drive and maintain the target voltage on the relevant metal pillar between refresh cycles. Without the storage capacitor 1275, a higher refresh rate would be required, the target pillar voltage would not be maintained between refresh cycles, and / or the final voltage value of the metal pillar would deviate significantly from the drive voltage value.

[0111] Figure 13A A perspective view of a simplified block diagram of an optical metasurface according to one embodiment is shown. The metasurface includes an optical layer 1320, a capacitor layer 1330, driver wiring layers 1341 and 1342, and a transistor layer 1350. As shown, the optical layer 1320 includes a two-dimensional array of metal pillars arranged in rows and columns. A column with three metal pillars 1321, 1322, and 1323 and a partial metal pillar 1324 can be seen in the perspective view. In the perspective view, the rows of metal pillars are perpendicular to the paper inwards and outwards. The gaps between adjacent pillars in each row (perpendicular to the paper inwards) form an optical resonator. A tunable dielectric material (e.g., liquid crystal) is deposited within the resonant cavity layer to fill the spaces between the metal pillars in various directions, thereby placing the tunable dielectric material within the optical resonator formed by the gaps between adjacent rows of pillars. Examples of suitable tunable dielectric materials with tunable refractive indices include liquid crystals, electro-optic polymers, electro-optic crystals, chalcogenide glasses, and / or various semiconductor materials.

[0112] Optical layer 1320 includes a two-dimensional arrangement of elongated rectangular reflector patches 1325 (only one is shown in the figure to avoid obscuring the illustration). The rectangular reflector patches 1325 extend longitudinally along parallel rows. The rectangular reflector patches 1325, dielectric vias, and conductor vias can be arranged and configured according to various embodiments described herein. Capacitor layer 1330 includes two layers of interdigital capacitors or interdigital capacitor sublayers. Each metal pillar of optical layer 1320 can be electrically connected to one or more interdigital capacitors within capacitor layer 1330. Driver wiring layer includes source driver wiring layer 1341 and gate driver wiring layer 1342. In the embodiments described above, row conductors are used to drive the gate of the transistor, and column conductors are used to drive the source of the transistor. However, in the block diagram shown, the roles are reversed, with row conductors driving the gate of the transistor and column conductors driving the source of the transistor. Transistor layer 1350 of the metasurface device includes a plurality of transistors (MOSFETs) integrated within the layer. In some embodiments, transistor layer 1350 is integrated with a substrate or base layer. In other embodiments, the metasurface comprises a separate substrate or base layer (not shown).

[0113] Figure 13B Another perspective view showing a simplified block diagram of an optical metasurface according to one embodiment is shown, comprising an optical layer 1320, a capacitor layer 1330, driver wiring layers 1341 and 1342, and a transistor layer 1350. Similarly, the optical layer 1320 comprises a two-dimensional array of metal pillars arranged in rows and columns. In the example shown, the columns of metal pillars are slightly offset or interleaved, such that the pillars within each column are not arranged in a straight line. For example, although metal pillars 1321, 1322, 1323, and 1324 are slightly offset or interleaved, they are still described as being within the same “column.” The systems and methods for row and column addressing of two-dimensional active matrices described herein are compatible with the shown staggered column embodiment and other alternative straight column embodiments. As with other embodiments with aligned metal pillar columns, each metal pillar in the optical layer 1320 is connected in parallel with one or more storage capacitors in one or more capacitor layers 1330 and one transistor device in the transistor layer 1350.

[0114] Figure 14A and 14BA perspective view of a simplified block diagram of an optical metasurface unit cell lattice 1400 is shown. The unit cell lattice 1400 includes two metal pillars 1411 and 1412 located within an optical layer 1410. Although the interlayer connections are not clearly visible in the simplified block diagram, a capacitor layer 1420 includes a first storage capacitor 1421 connected to the first metal pillar 1411 and a second storage capacitor 1422 connected to the second metal pillar 1412. As described in detail herein, the unit cell lattice 1400 also includes driver wiring layers 1431 and 1432, which have row conductors and column conductors. As previously mentioned, the row conductors and column conductors can interchange their roles in driving the gates and sources of the respective transistors. The unit cell lattice 1400 includes two transistors in a transistor layer 1440, comprising a first transistor connected in parallel with the first storage capacitor 1421 to the first metal pillar 1411; and a second transistor connected in parallel with the second storage capacitor 1422 to the second metal pillar 1412.

[0115] Figure 15A A top view of several layers of an optical metasurface unit lattice according to one embodiment is shown. The layout view shown includes the following examples: transistor layer 1510 (containing two transistors), column driver wiring layer 1520 (connected to the transistor gate), and source driver wiring layer 1530 (connected to the transistor source).

[0116] Figure 15B A top view of several layers of an optical metasurface unit lattice according to one embodiment is shown. The layout view shown includes examples of: a first capacitor layer 1540 (containing a first interdigitated storage capacitor) and a second capacitor layer 1550 (containing a second interdigitated storage capacitor). A layout view of an optical layer 1560 is also provided in the figure, which includes two metal pillars 1561 and 1562 from the column metal pillars, and portions of four lower reflector patches 1563, 1564, 1565, and 1566.

[0117] This disclosure has been set forth with reference to various exemplary embodiments, including the preferred embodiment. However, those skilled in the art will understand that changes and modifications can be made to the exemplary embodiments without departing from the scope of this disclosure. While the principles of this disclosure have been shown in various embodiments, numerous modifications can be made to the structure, arrangement, proportions, elements, materials, and components to suit specific environmental and / or operational requirements without departing from the principles and scope of this disclosure. These and other changes or modifications are intended to be included within the scope of this disclosure.

[0118] This disclosure should be considered exemplary and not restrictive, and all such modifications are intended to be included within the scope of this disclosure. Similarly, benefits, other advantages, and solutions to problems have been described above with respect to various embodiments. However, benefits, advantages, solutions to problems, and any elements that may lead to or make more significant any benefit, advantage, or solution should not be construed as critical, essential, or necessary features or elements. The following claims are also incorporated into this disclosure.

Claims

1. An optical metasurface device, comprising: An optical resonator layer having a two-dimensional array of metal pillars arranged in rows and columns, and a tunable dielectric material with a tunable refractive index located in the gaps between adjacent metal pillars in each row of metal pillars. An optical reflective layer located between the substrate layer and the optical resonator layer is used to reflect incident light radiation; The driver wiring layer has row conductors for each row of metal pillars and column conductors for each column of metal pillars; as well as A transistor layer having multiple transistor devices, wherein each transistor device is connected to one of the row conductors and one of the column conductors and is configured to be selectively driven by them, and Wherein, a subset of the metal pillars in the optical resonator layer are active metal pillars, and each active metal pillar is connected to at least one of the transistor devices in the transistor layer.

2. The metasurface device according to claim 1, wherein, All the metal pillars in the optical resonator layer are active metal pillars.

3. The metasurface device as described in claim 1, further comprising: A capacitor layer with multiple storage capacitors, Each active metal pillar in the optical resonator layer is connected to one of the storage capacitors in the capacitor layer and one of the transistor devices in the transistor layer.

4. The metasurface device as described in claim 3, wherein, Each storage capacitor includes at least one of the following: metal-insulator-metal (MIM) capacitor, metal-oxide-metal (MOM) capacitor, and metal-oxide-semiconductor (MOS) capacitor.

5. The metasurface device as described in claim 3, wherein, The capacitor layer includes multiple interdigitated storage capacitor sublayers.

6. The metasurface device as described in claim 3, wherein, Each storage capacitor comprises multiple discrete capacitors connected in parallel.

7. The metasurface device as described in claim 3, wherein, The storage capacitors include grounded storage capacitors, such that one terminal of each storage capacitor is grounded.

8. The metasurface device of claim 3, wherein at least some of the storage capacitors are differential storage capacitors, wherein a first terminal of each differential storage capacitor is connected in parallel with a corresponding transistor device to an active metal pillar, and a second terminal of each differential storage capacitor is connected to an adjacent differential storage capacitor of an adjacent active metal pillar.

9. The metasurface device of claim 3, wherein the capacitance value of each storage capacitor is between 0.1 femtofarads (fF) and 3.0 femtofarads (fF).

10. The metasurface device of claim 3, wherein the capacitor layer is integrated within the same layer as the transistor layer, and wherein each of the plurality of storage capacitors includes a trench capacitor adjacent to one of the transistor devices.

11. The metasurface device of claim 3, wherein the driver wiring layer, the transistor layer, and the capacitor layer are located between the substrate layer and the optical reflective layer.

12. The metasurface device as claimed in claim 11, wherein, The capacitor layer is located between the light-reflecting layer and the driver wiring layer, and the transistor layer is located between the driver wiring layer and the substrate.

13. The metasurface device as described in claim 1 or 12, wherein, Each transistor device includes a metal-oxide-semiconductor field-effect transistor (MOSFET).

14. The metasurface device as claimed in claim 13, wherein, The gate of each MOSFET is connected to the row conductor associated with the active metal pillar to which each corresponding transistor device is connected.

15. The metasurface device as claimed in claim 14, wherein, The source of each MOSFET is connected to the column conductor associated with the active metal pillar to which each corresponding transistor device is connected, and wherein each active metal pillar is connected to the drain of each MOSFET.

16. The metasurface device of claim 13, further comprising: A capacitor layer with multiple storage capacitors, Each active metal pillar in the optical resonator layer is connected in parallel with one of the storage capacitors in the capacitor layer and the drain of each MOSFET.

17. The metasurface device as claimed in claim 1 or 12, wherein, Each transistor device contains a common-source, common-gate amplifier.

18. The metasurface device as claimed in claim 1 or 12, wherein, The driver wiring layer includes: A row driver wiring layer having the row conductor; and A column driver wiring layer having the column conductors.

19. The metasurface device of claim 1 or 12, further comprising a controller for selectively applying a voltage mode to the active metal pillar in such a way as: According to the refresh rate, the voltage on each row conductor is driven sequentially to temporarily activate the transistor device in the metal pillar row associated with each corresponding row conductor during the refresh cycle; and During each corresponding refresh cycle, each column conductor is driven to apply a target voltage to each active metal pillar in the row of metal pillars associated with the temporarily activated transistor device.

20. The metasurface device of claim 19, wherein, The voltages driving each row of conductors sequentially include digital signals used to drive the gates of each corresponding transistor device.

21. The metasurface device as claimed in claim 19, wherein, Each column of metal posts is connected to an independent column conductor, allowing each column of metal posts to be driven individually.

22. The metasurface device of claim 19, wherein at least some of the column conductors are electrically connected such that the column metal pillars associated with the electrically connected column conductors are driven together.

23. The metasurface device of claim 1 or 12, wherein the tunable dielectric material comprises one or more of the following: liquid crystal, electro-optic polymer, electro-optic crystal, and chalcogenide glass.

24. The metasurface device of claim 1 or 12, wherein the optical reflective layer comprises a two-dimensional reflector patch array.

25. The metasurface device of claim 24, wherein each active metal pillar is electrically connected to at least one of the reflector patches.

26. The metasurface device as claimed in claim 1 or 12, wherein, The length of each metal post in the direction perpendicular to each row is less than the minimum wavelength of the working bandwidth, and the width of each metal post along each row is less than half of the minimum wavelength of the working bandwidth.

27. The metasurface device as claimed in claim 1 or 12, wherein, Each metal column contains one of the following materials: copper, silver, gold, aluminum, and silver-plated copper.

28. The metasurface device as claimed in claim 1 or 12, further comprising: A passivation coating of optically transparent dielectric material is applied to each metal pillar.

29. The metasurface device as claimed in claim 1 or 12, wherein, The two-dimensional metal column array is arranged in a two-dimensional tile manner, with T metasurface tiles arranged in R rows and S columns. Each metasurface tile includes a two-dimensional arrangement of metal columns in N rows and M columns, where T, R, S, N, and M are integer values.

30. The metasurface device as claimed in claim 1 or 12, wherein, The metasurface device includes one metasurface module in a multi-module metasurface.

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