Semiconductor device

Abstract

Provided is a semiconductor device in which a resistor and a capacitor can be realized using one chip. The present invention is provided with: a semiconductor substrate (1); a lower layer insulating film (2) provided on the upper surface side of the semiconductor substrate (1); a resistive layer (3) provided on the upper surface side of the lower insulating film (2); an interlayer insulating film (4) provided on the upper surface side of the lower layer insulating film (2) and the resistive layer (3); a first surface electrode (5a) provided on the upper surface side of the interlayer insulating film (4) and electrically connected to one end of the resistive layer (3); a second surface electrode (5b) provided on the upper surface side of the interlayer insulating film (4) so as to be separated from the first surface electrode (5a) and electrically connected to the other end of the resistive layer (3); and a rear surface electrode (9) provided on the lower surface side of the semiconductor substrate (1), in which a resistor (R1) of the resistive layer (3) and a first capacitor (C1) having the lower layer insulating film (2) on the lower side of the resistive layer (3) as a dielectric are connected in parallel to the first surface electrode (5a).

Description

Semiconductor devices Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] Patent Document 1 discloses a resistive element comprising: a first external connection electrode disposed on the upper surface of a chip; a second external connection electrode disposed separately from and in parallel with the first external connection electrode; and a protective film covering the first and second external connection electrodes, wherein a portion of the protective film has a first opening and a second opening that expose portions of the upper surfaces of the first and second external connection electrodes, respectively. The resistive element may also be horizontally constructed.

[0003] Patent Document 2 discloses a resistive element comprising: a lower insulating film; a resistive layer disposed on the lower insulating film; a protective element for the resistive layer disposed side-by-side with one sidewall of the resistive layer on the lower insulating film, the protective element being formed by connecting pn junctions in series through alternating arrangements of n-type strips composed of n-type layers and p-type strips composed of p-type layers; an interlayer insulating film covering the resistive layer and the protective element for the resistive layer; an external connecting electrode disposed on the interlayer insulating film and electrically connected to one terminal of the resistive layer and one terminal of the protective element for the resistive layer, respectively; and an external connecting electrode disposed on the interlayer insulating film and electrically connected to another terminal of the resistive layer and another terminal of the protective element for the resistive layer, respectively. The resistive element may also be a horizontal structure.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2020-98822

[0007] Patent Document 2: Japanese Patent Application Publication No. 2020-98884 Summary of the Invention

[0008] The problem that the invention aims to solve

[0009] Consider the following scenario: applying the resistive elements described in Patent Documents 1 and 2 to the gate resistor of a switching element in a semiconductor module such as an intelligent power module (IPM) that has a control circuit with switching elements and a control circuit for controlling the switching elements. In this case, since a capacitor is connected between the gate of the switching element and the control circuit, not only the gate resistor but also the capacitor, the resistive elements described in Patent Documents 1 and 2 cannot be directly applied. Furthermore, if the gate resistor and capacitor are constructed using separate chips, there are drawbacks such as an increased mounting area.

[0010] In view of the above problems, the purpose of this disclosure is to provide a semiconductor device that can implement resistors and capacitors with a single chip.

[0011] Solution for solving the problem

[0012] One aspect of this disclosure relates to a semiconductor device comprising: a semiconductor substrate; a lower insulating film disposed on an upper surface of the semiconductor substrate; a resistive layer disposed on an upper surface of the lower insulating film; an interlayer insulating film disposed on the upper surfaces of the lower insulating film and the resistive layer; a first surface electrode disposed on an upper surface of the interlayer insulating film and electrically connected to one end of the resistive layer; a second surface electrode disposed on an upper surface of the interlayer insulating film separately from the first surface electrode and electrically connected to the other end of the resistive layer; and a back electrode disposed on a lower surface of the semiconductor substrate, wherein the resistance of the resistive layer and a first capacitance having the lower insulating film below the resistive layer as a dielectric are connected in parallel to the first surface electrode.

[0013] The effects of the invention

[0014] According to this disclosure, a semiconductor device capable of implementing resistors and capacitors using a single chip can be provided. Attached Figure Description

[0015] Figure 1 is a top view showing an example of a semiconductor device according to the first embodiment.

[0016] Figure 2 is a cross-sectional view along line AA′ in Figure 1.

[0017] Figure 3 is a circuit diagram showing the equivalent circuit of the semiconductor device according to the first embodiment.

[0018] Figure 4 is a circuit diagram illustrating an application example of the semiconductor device according to the first embodiment.

[0019] Figure 5 is a cross-sectional view showing the semiconductor device involved in the comparative example.

[0020] Figure 6 is a cross-sectional view of the semiconductor device involved in the comparative example with an additional equivalent circuit.

[0021] Figure 7A is a circuit diagram showing the equivalent circuit of the semiconductor device involved in the comparative example.

[0022] Figure 7B is another circuit diagram showing the equivalent circuit of the semiconductor device involved in the comparative example.

[0023] Figure 8 is a graph showing the relationship between impedance and frequency.

[0024] Figure 9 is a top view showing an example of a semiconductor device according to the second embodiment.

[0025] Figure 10 is a cross-sectional view along line AA′ in Figure 9.

[0026] Figure 11 is a cross-sectional view along line BB′ in Figure 9.

[0027] Figure 12 is a top view showing an example of a semiconductor device according to the third embodiment.

[0028] Figure 13 is a cross-sectional view along line AA′ in Figure 12.

[0029] Figure 14 is a cross-sectional view along line BB′ in Figure 12. Detailed Implementation

[0030] The first to third embodiments will now be described with reference to the accompanying drawings. In the drawings, identical or similar parts are labeled with the same or similar reference numerals, and repeated descriptions are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thicknesses of each layer, etc., may sometimes differ from actual conditions. Furthermore, the drawings may contain parts with different dimensional relationships or ratios. Additionally, the first to third embodiments shown below illustrate apparatus and methods for embodying the technical concept of this disclosure; the technical concept of this disclosure does not specify the materials, shapes, structures, and arrangements of the constituent components as described below.

[0031] Furthermore, the definitions of up and down directions in the following description are merely for illustrative purposes and are not intended to limit the technical concept of this disclosure. For example, if an object is rotated 90° for observation, up and down is read as left and right; if the object is rotated 180° for observation, up and down is read in reverse order. This is self-evident.

[0032] (First Implementation)

[0033] <Structure of Semiconductor Devices>

[0034] Figure 1 shows the planar layout of the semiconductor device (semiconductor chip) according to the first embodiment. In Figure 1, the outlines of the lower insulating film 2, resistive layer 3, a pair of surface electrodes (external connection electrodes) 5a and 5b, and contacts (contact plugs) 6a and 6b, which are hidden under the protective film (passivation film) 7, are schematically shown in dashed lines.

[0035] The semiconductor device according to the first embodiment is, for example, a semiconductor chip having a generally rectangular planar pattern: the long side of the generally rectangular planar pattern is the direction in which the surface electrodes 5a, the resistive layer 3, and the surface electrodes 5b are arranged (the left-right direction in FIG. 1), and the short side is the direction orthogonal to the direction in which the surface electrodes 5a, the resistive layer 3, and the surface electrodes 5b are arranged (the up-down direction in FIG. 1). The chip size of the semiconductor device according to the first embodiment is, for example, about 3.0 mm × 2.5 mm, but is not limited to this.

[0036] The lower insulating film 2 has a rectangular planar pattern with the long side direction (left-right direction in FIG1) of the semiconductor device according to the first embodiment as its long side direction. The resistive layer 3, located above the lower insulating film 2, is disposed on the inner side of the lower insulating film 2. The resistive layer 3 has a rectangular planar pattern with the long side direction (left-right direction in FIG1) of the lower insulating film 2 as its long side direction.

[0037] Surface electrodes 5a and 5b, located above the resistive layer 3, are positioned inside the outer shape of the lower insulating film 2 and are configured to sandwich the resistive layer 3 in between. Surface electrodes 5a and 5b have a generally rectangular planar pattern with the shorter side (vertical direction in FIG. 1) of the lower insulating film 2 as its longer side. Surface electrode 5a is electrically connected to the resistive layer 3 via multiple contacts 6a at a position overlapping with one end of the resistive layer 3 located below it in the long direction. The number and arrangement of contacts 6a are not particularly limited. Surface electrode 5b is electrically connected to the resistive layer 3 via multiple contacts 6b at a position overlapping with the other end of the resistive layer 3 located below it in the long direction. The number and arrangement of contacts 6b are not particularly limited.

[0038] The protective film 7 has generally rectangular openings 7a and 7b. Opening 7a exposes a portion of the upper surface of the surface electrode 5a as a pad area (effective connection area) that can be connected to external connection units such as bonding wires. Opening 7b exposes a portion of the upper surface of the surface electrode 5b as a pad area (effective connection area) that can be connected to external connection units such as bonding wires.

[0039] Figure 2 shows a cross-section along line AA′ of Figure 1, passing through resistive layer 3 and surface electrodes 5a and 5b. As shown in Figure 2, the semiconductor device according to the first embodiment includes a semiconductor substrate 1, a lower insulating film (first insulating film) 2 disposed on the upper surface side of the semiconductor substrate 1, and a resistive layer 3 disposed on the upper surface side of the lower insulating film 2.

[0040] The thickness of the semiconductor substrate 1 is, for example, about 250 μm or more and about 450 μm or less. As the semiconductor substrate 1, a low resistivity substrate such as a silicon substrate with a high concentration of n-type impurities can be used. In addition, as the semiconductor substrate 1, a silicon substrate with a high concentration of p-type impurities or a semiconductor substrate other than silicon can also be used.

[0041] As the lower insulating film 2, a silicon oxide film (SiO2 film), a silicon nitride film (Si3N4 film), or a composite film thereof can be used. To increase the capacitance value of the capacitor (also called a "capacitor") with the lower insulating film 2 as the dielectric, materials with a higher relative permittivity than SiO2 films, such as Si3N4 films, can also be used as the lower insulating film 2. From the viewpoint of reliability and lifespan, a locally oxide film (LOCOS film) formed by the local oxidation (LOCOS) method can be used as the lower insulating film 2. An insulating film (TEOS film) formed by chemical vapor deposition (CVD) using tetraethoxysilane (TEOS) gas, which utilizes organosilicon compounds, can also be used as the lower insulating film 2.

[0042] The thickness of the lower insulating film 2 can be, for example, greater than 15nm and less than 1000nm, greater than 15nm and less than 800nm, greater than 15nm and less than 500nm, greater than 15nm and less than 300nm, or greater than 15nm and less than 100nm. Alternatively, the thickness of the lower insulating film 2 can be greater than 50nm and less than 1000nm, greater than 50nm and less than 800nm, greater than 50nm and less than 500nm, greater than 50nm and less than 300nm, or greater than 50nm and less than 100nm.

[0043] The thinner the lower insulating film 2, the larger the capacitance value of the capacitor with the lower insulating film 2 as the dielectric. From the viewpoint of increasing the capacitance value, the thickness of the lower insulating film 2 is preferably about 800 nm or less, more preferably about 500 nm or less, more preferably about 300 nm or less, and more preferably about 100 nm or less. Furthermore, when the semiconductor device according to the first embodiment is applied to the gate resistor of an IGBT as a switching element, from the viewpoint of ensuring a gate voltage of approximately ±15V for the IGBT, the thickness of the lower insulating film 2 is preferably about 15 nm or more. Additionally, from the viewpoint of reliability and lifespan, when the same design as the gate insulating film is implemented, the thickness of the lower insulating film 2 is preferably about 50 nm or more.

[0044] The larger the area of ​​the lower insulating film 2 directly beneath the resistive layer 3, the larger the capacitance value of the capacitor using the lower insulating film 2 as the dielectric. To achieve a capacitance value of approximately 1nF or higher, the area of ​​the lower insulating film 2 directly beneath the resistive layer 3 is preferably 1.5 mm². 2 About the above.

[0045] The thickness of resistive layer 3 is, for example, 400 nm or more and about 600 nm or less. The sheet resistance of resistive layer 3 is, for example, 100 Ω / □ or more and about 200 Ω / □ or less. The resistance value of resistive layer 3 can be controlled by adjusting the thickness of resistive layer 3, the width of resistive layer 3 in the depth direction of FIG2, the length of resistive layer 3 in the left and right direction of FIG2, the material of resistive layer 3, and the connection position of resistive layer 3 with contacts 6a and 6b.

[0046] As the resistive layer 3, for example, polycrystalline silicon with added n-type or p-type impurities (doped polycrystalline silicon) can be used. Doped polycrystalline silicon can be formed by ion implantation of n-type or p-type impurities into polycrystalline silicon, or by adding n-type or p-type impurities during the deposition of polycrystalline silicon by chemical vapor deposition (CVD). The resistance value of the resistive layer 3 can be controlled by adjusting the dosage, accelerating voltage, heat treatment temperature, and heat treatment time during ion implantation into the resistive layer 3.

[0047] Resistor layer 3 is not limited to doped polycrystalline silicon, but can also be tantalum nitride (TaN). x This includes films of nitrides of transition metals such as chromium (Cr), nickel (Ni), and manganese (Mn), as well as laminated films of high-melting-point metals stacked in the order of chromium (Cr)-nickel (Ni)-manganese (Mn). The resistive layer 3 can also be a thin film of silver palladium (AgPd), ruthenium oxide (RuO2), etc.

[0048] An interlayer insulating film (second insulating film) 4 is provided on the upper surface side of the lower insulating film 2 and the resistive layer 3, covering the lower insulating film 2 and the resistive layer 3. The thickness of the interlayer insulating film 4 is, for example, about 1 μm or more and about 2 μm or less. As the interlayer insulating film 4, a single-layer film of a silicon oxide film (SiO2 film) without phosphorus (P) and boron (B) and called a so-called "NSG film", a silicon oxide film with added phosphorus (PSG film), a silicon oxide film with added boron (BSG film), a silicon oxide film with added phosphorus and boron (BPSG film), or a silicon nitride film (Si3N4 film), or a composite film composed of a combination of several of them can be used.

[0049] On the upper surface of the interlayer insulating film 4, a pair of surface electrodes 5a and 5b are disposed separately from each other. Surface electrode 5a is located above the lower insulating film 2 and overlaps with one end of the long side of the resistive layer 3 in the depth direction. Surface electrode 5a is electrically connected to one end of the long side of the resistive layer 3 via a contact 6a embedded in a contact hole provided in the interlayer insulating film 4. Surface electrode 5b is located above the lower insulating film 2 and overlaps with the other end of the long side of the resistive layer 3 in the depth direction. Surface electrode 5b is electrically connected to the other end of the long side of the resistive layer 3 via a contact 6b embedded in a contact hole provided in the interlayer insulating film 4. The semiconductor device according to the first embodiment is a resistive body with a horizontal structure in which the surface electrode 5a, contact 6a, resistive layer 3, contact 6b, and surface electrode 5b form a current path.

[0050] The thickness of surface electrodes 5a and 5b is, for example, 1 μm or more and about 5 μm or less. Surface electrodes 5a and 5b can be, for example, composed of a stacked film of titanium / titanium nitride (Ti / TiN) as a barrier metal, aluminum-silicon (Al-Si), or TiN / Ti as an antireflective film. Al alloys such as Al, Al-Si-copper (Cu), and Al-Cu can also be used instead of Al-Si.

[0051] A protective film 7 is disposed on the upper surface side of the interlayer insulating film 4 and the surface electrodes 5a and 5b. The protective film 7 can be any insulating film and is not particularly limited, but for example, it can be a composite film formed by sequentially stacking a TEOS film, a Si3N4 film, and a polyimide film. Openings 7a and 7b are provided in the protective film 7. The portions of the surface electrodes 5a and 5b exposed from the openings 7a and 7b become pad areas (electrode pads) for bonding lines (not shown) to aluminum (Al) or the like.

[0052] A back electrode (third electrode) 9, serving as an external connection electrode, is disposed on the lower surface side of the semiconductor substrate 1. The back electrode 9 can be, for example, composed of a single-layer film of gold (Au) or a metal film stacked in the order of titanium (Ti), nickel (Ni), and gold (Au). The outermost layer of the back electrode 9 can be made of a solderable material. In the semiconductor device according to the first embodiment, a capacitor is formed with the resistive layer 3 as one electrode, the lower insulating film 2 directly below the resistive layer 3 as a dielectric (insulator), and the semiconductor substrate 1 and the back electrode 9 as the other electrode. In FIG2, the resistance R1 of the resistive layer 3 and the capacitor C1 with the lower insulating film 2 as the dielectric are schematically shown using circuit symbols.

[0053] Figure 3 shows the equivalent circuit of the semiconductor device according to the first embodiment shown in Figures 1 and 2. Terminal T1, corresponding to the surface electrode 5a shown in Figures 1 and 2, is connected to one end of resistor R1 and one end of capacitor C1. The other end of resistor R1 is connected to terminal T2, corresponding to the surface electrode 5b shown in Figures 1 and 2. The other end of capacitor C1 is connected to terminal T3, corresponding to the back electrode 9 shown in Figures 1 and 2.

[0054] <Methods for Manufacturing Semiconductor Devices>

[0055] Next, referring to Figures 1 and 2, an example of a method for manufacturing a semiconductor device according to the first embodiment will be described. Furthermore, the manufacturing method described below is one example, and it is self-evident that various other manufacturing methods, including variations thereof, can be used as long as they fall within the scope of the claims.

[0056] First, a semiconductor substrate 1, such as a silicon substrate, with a high concentration of n-type impurities is prepared. Next, a lower insulating film 2 is formed on the upper surface side of the semiconductor substrate 1 using methods such as the LOCOS method. Then, as needed, a portion of the outer peripheral side of the lower insulating film 2 is selectively removed using photolithography or dry etching.

[0057] Next, a resistive layer 3 is formed on the upper surface side of the semiconductor substrate 1 and the lower insulating film 2 by means of CVD and ion implantation. Then, a portion of the outer peripheral side of the resistive layer 3 is selectively removed by means of photolithography and dry etching.

[0058] Next, an interlayer insulating film 4 is deposited on the upper surface side of the lower insulating film 2 and the resistive layer 3 using methods such as CVD. Then, a portion of the interlayer insulating film 4 is selectively removed using photolithography and dry etching, and contact holes are formed in the interlayer insulating film 4.

[0059] Next, a metal film is deposited by vacuum evaporation or sputtering to fill the contact holes. Then, a portion of the metal film is selectively removed by photolithography or dry etching to form surface electrodes 5a and 5b on the upper surface of the interlayer insulating film 4.

[0060] Next, a protective film 7 is formed on the upper surface side of the interlayer insulating film 4 and the surface electrodes 5a and 5b. Then, a portion of the protective film 7 is selectively removed by photolithography and dry etching, and openings 7a and 7b are formed in the protective film 7.

[0061] Next, the thickness of the semiconductor substrate 1 is adjusted by grinding from the lower surface side as needed. Then, a back electrode 9 is formed on the lower surface side of the semiconductor substrate 1 by vacuum evaporation or sputtering. Furthermore, a large number of structures identical to those of the semiconductor device according to the first embodiment shown in FIG1 and FIG2 are formed as matrix-shaped chip regions on a single wafer. By dicing, these chip regions are separated into chips of the semiconductor device according to the first embodiment shown in FIG1 and FIG2.

[0062] <Application Example>

[0063] Figure 4 illustrates an example of applying the semiconductor device according to the first embodiment to a semiconductor module 10 for driving a motor 30. The semiconductor module 10 may be an intelligent power module (IPM). The semiconductor module 10 includes switching elements S1-S6, a high-voltage integrated circuit (HVIC) 11 and a low-voltage integrated circuit (LVIC) 12 serving as a control circuit (driver IC) for controlling (driving) the switching elements S1-S6. The switching elements S1-S6 may be, for example, insulated-gate bipolar transistors (IGBTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs). The semiconductor module 10 is connected to the motor 30 and a DC power supply V. DC The system includes a current detection resistor Rdet, power supply capacitors CB(U), CB(V), and CB(W), a signal power supply Vcc, and a controller 20.

[0064] Motor 30 is a three-phase motor, connected to the output terminals U, V, and W of three half-bridge circuits. The positive terminal of the DC power supply VDC is connected to the positive DC terminal P of the three half-bridge circuits. The negative terminal of the DC power supply VDC is connected to the negative DC terminals N(U), N(V), and N(W) of the three half-bridge circuits via a current sensing resistor Rdet. Through these connections, semiconductor module 10 receives DC power from the DC power supply VDC via the positive DC terminal P and the negative DC terminals N(U), N(V), and N(W), thereby supplying power to motor 30 via the output terminals U, V, and W.

[0065] Power supply capacitors CB(U), CB(V), and CB(W) are used as the gate drive power supply for the high-potential-side switching elements S1, S2, and S3. One terminal of the pair of terminals of the power supply capacitor CB(U) is connected to the gate power supply terminal V. BU Connect the other terminal to the reference potential terminal V. S2U Connection. One terminal of the power supply capacitor CB(V) is connected to the gate power supply terminal V. BV Connect the other terminal to the reference potential terminal V. S2VConnection. One terminal of the power supply capacitor CB(W) is connected to the gate power supply terminal V. BW Connect the other terminal to the reference potential terminal V. S2W connect.

[0066] The positive terminal of the signal power supply Vcc is connected to the signal power supply terminal V. CCH and signal power terminal V CCL Connect them separately. Connect the negative terminal of the signal power supply Vcc to the common terminal COM and the ground terminal GND of the controller 20, respectively. Signal power supply terminal V... CCH With gate power supply terminal V BU V BV V BW The anode and signal power terminal V are respectively used. CCH The connection is made via a bootstrap diode (BSD) 13. Thus, the power supply capacitors CB(U), CB(V), and CB(W) are charged using power from the signal power supply Vcc.

[0067] Controller 20 is a microprocessor unit (MPU) for pulse width modulation (PWM) control. Controller 20 is connected to signal input terminal U. INH V INH W INH Common terminal COM, signal input terminal U INL V INL W INL And the current sensing terminal IS connection.

[0068] Controller 20 outputs to signal input terminal U INH V INH W INH and signal input terminal U INL V INL W INL The PWM signals are input separately. Input signal to terminal U. INH V INH W INH The input PWM signal is fed into HVIC 11. The signal input terminal U... INL V INL W INL The input PWM signal is fed into LVIC 12. HVIC 11 and LVIC 12, based on the input PWM signal, output from terminal U... OUT V OUT W OUT The output signals cause changes in the gate potential of the corresponding switching elements S1 to S6. Thus, based on the PWM signal from the controller 20, the switching elements S1 to S6 are switched on and off.

[0069] Semiconductor module 10 has the following functions: based on the resistance value of the current sensing resistor Rdet, it detects the current flowing in each phase of the three half-bridge circuits, and protects semiconductor module 10 from damage when an overcurrent occurs. A current level signal corresponding to the change in the resistance value of the current sensing resistor Rdet is input to LVIC 12 via the current sensing terminal IS, and also input to controller 20. LVIC 12 determines whether an overcurrent has occurred based on the comparison result of this current level signal and a reference value; if an overcurrent has occurred, it cuts off the current of LVIC 12. Additionally, controller 20 determines whether an overcurrent has occurred based on the comparison result of this current level signal and a reference value; if an overcurrent has occurred, it cuts off the current of HVIC 11.

[0070] At the output terminal U of HVIC 11 OUT A resistor R11 is connected between the gate of the switching element S1 and the gate of the switching element. At the output terminal U of HVIC 11... OUT A capacitor C11 is connected between one end of resistor R11 and the output terminal U. Resistor R11 and capacitor C11 are constructed from a single semiconductor chip 41 corresponding to the semiconductor device described in the first embodiment shown in Figures 1 and 2. Resistor R11 functions as a gate resistor to suppress oscillations, etc., when the switching element S1 is short-circuited. Resistors R12 to R16, described below, also have the same function as resistor R11. Capacitor C11 functions to protect the switching element S1 from gate voltage fluctuations and to control the turn-on time. Capacitors C12 to C16, described below, also have the same function as capacitor C11.

[0071] At the output terminal V of HVIC 11 OUT A resistor R12 is connected between the gate of the switching element S2 and the gate of the switching element. At the output terminal V of HVIC 11... OUT A capacitor C12 is connected between one end of resistor R12 and the output terminal V. Resistor R12 and capacitor C12 are composed of a semiconductor chip 42 corresponding to the semiconductor device involved in the first embodiment shown in FIG1 and FIG2.

[0072] At the output terminal W of HVIC 11 OUT A resistor R13 is connected between the gate of the switching element S3 and the gate of the switching element S3. At the output terminal W of HVIC 11... OUT A capacitor C13 is connected between one end of resistor R13 and the output terminal W. Resistor R13 and capacitor C13 are composed of a semiconductor chip 43 corresponding to the semiconductor device involved in the first embodiment shown in FIG1 and FIG2.

[0073] At the output terminal U of LVIC 12 OUTA resistor R14 is connected between the gate of the switching element S4 and the gate of the LVIC 12. At the output terminal U... OUT A capacitor C14 is connected between one end of resistor R14 and the negative DC terminal N(U). Resistor R14 and capacitor C14 are composed of a semiconductor chip 44 corresponding to the semiconductor device involved in the first embodiment shown in FIG1 and FIG2.

[0074] At the output terminal V of LVIC 12 OUT A resistor R15 is connected between the gate of the switching element S5 and the gate of the LVIC 12. At the output terminal V of the LVIC 12... OUT A capacitor C15 is connected between one end of resistor R15 and the negative DC terminal N (V). Resistor R15 and capacitor C15 are composed of a semiconductor chip 45 corresponding to the semiconductor device involved in the first embodiment shown in FIG1 and FIG2.

[0075] At the output terminal W of LVIC 12 OUT A resistor R16 is connected between the gate of the switching element S6 and the gate of the LVIC 12. At the output terminal W... OUT A capacitor C16 is connected between one end of resistor R16 and the negative DC terminal N(W). Resistor R16 and capacitor C16 are composed of a semiconductor chip 46 corresponding to the semiconductor device involved in the first embodiment shown in FIG1 and FIG2.

[0076] <Comparative Example>

[0077] Next, as a comparative example of a semiconductor device, a vertically constructed resistive element will be described. The semiconductor device of the comparative example is used as a gate resistor for suppressing oscillations in a large-capacity IGBT module. As shown in FIG5, the semiconductor device of the comparative example includes a semiconductor substrate 101, lower insulating films 102a and 102b disposed on the upper surface side of the semiconductor substrate 101, and resistive layers 103a and 103b disposed on the upper surface side of the lower insulating films 102a and 102b. An interlayer insulating film 104 is disposed on the upper surface side of the lower insulating films 102a and 102b and the resistive layers 103a and 103b.

[0078] Surface electrodes 105a and 105b and relay wiring 105c are disposed on the upper surface of the interlayer insulating film 104. Surface electrode 105a is connected to resistive layer 103a via contact 106a. Surface electrode 105b is connected to resistive layer 103b via contact 106c. Relay wiring 105c is connected to resistive layer 103a via contact 106b, to resistive layer 103b via contact 106d, and to semiconductor substrate 1 via contact 106e. A protective ring 105d is disposed on the outer periphery of surface electrodes 105a and 105b on the upper surface of the interlayer insulating film 104. Protective ring 105d is connected to semiconductor substrate 1 via contacts 106f and 106g.

[0079] A protective film 107 is provided on the upper surface side of the surface electrodes 105a, 105b and the relay wiring 105c. Openings 107a and 107b are provided in the protective film 107. The openings 107a and 107b expose portions of the surface electrodes 105a and 105b as pad areas. A back electrode 109 is provided on the lower surface side of the semiconductor substrate 101. In the semiconductor device according to the comparative example, a current path is formed from the surface electrodes 105a and 105b through the resistive layers 103a and 103b and the relay wiring 105c, the semiconductor substrate 101, to the back electrode 109.

[0080] Figure 6 is a diagram showing the equivalent circuit superimposed on the left-side cross-sectional structure of the semiconductor device involved in the comparative example shown in Figure 5. The surface electrode 105a is connected to terminal T101, and the back electrode 109 is connected to terminal T102. A parasitic capacitance C is formed under the surface electrode 105a, with the lower insulating film 102a and the interlayer insulating film 104 as dielectrics. pad A parasitic capacitance C is formed beneath the resistive layer 103a, with the underlying insulating film 102a as the dielectric. poly The parasitic capacitance C between the end of surface electrode 105a and the end of relay wiring 105c, with the protective film 107 as the dielectric layer. pmm It is small, therefore negligible.

[0081] Figure 7A shows the equivalent circuit shown in Figure 6. The parasitic capacitance C is calculated using the lower insulating film 102a beneath the resistive layer 103a as the dielectric. poly Considered as the resistance R of the resistive layer 103a poly Connected in parallel. In Figure 7B, the parasitic capacitance C shown in Figure 7A is... pad and parasitic capacitance C poly Together they form the parasitic capacitance C para The current I flowing from terminal T101 to terminal T102 PAD It is decomposed into the chip resistor R poly Current I flowing inR and in parasitic capacitance C para Current I flowing in C When the parasitic capacitance C para The impedance is lower than the chip resistance R. poly At that time, in the parasitic capacitance C para Current I flowing in C When the dominant force is dominant, oscillations will occur.

[0082] Figure 8 shows the parasitic capacitance C. para The relationship between impedance and frequency. The higher the frequency, the greater the parasitic capacitance C. para The lower the impedance, the greater the parasitic capacitance C. para The smaller the capacitance value, the smaller the parasitic capacitance C. para The impedance increases as the impedance increases. Therefore, in the semiconductor device involved in the comparative example, in order to avoid parasitic capacitance C para To reduce the impedance, the parasitic capacitance C needs to be reduced. para To increase the capacitance value, the thickness of the lower insulating film 102 needs to be increased.

[0083] Here, consider the following scenario: instead of using the semiconductor device involved in the comparative example as a gate resistor to suppress oscillations in a large-capacity IGBT module, it is applied to the semiconductor module 10 shown in FIG. 4, which has HVIC 11 and LVIC 12 as control circuits (driver ICs). In this case, since not only are gate resistors R11~R16 connected to HVIC 11 and LVIC 12, but also capacitors C11~C16, the semiconductor device involved in the comparative example cannot be directly applied.

[0084] In contrast, according to the semiconductor device of the first embodiment, as shown in Figures 1 to 3, resistor R1 and capacitor C1 are integrated into a single chip, and resistor R1 and capacitor C1 are connected in parallel to terminal T1 corresponding to surface electrode 5a. Therefore, when applied to the semiconductor module 10 shown in Figure 4, which has HVIC 11 and LVIC 12 as control circuits (driver ICs), a group of gate resistors R11 to R16 and capacitors C11 to C16 connected to HVIC 11 and LVIC 12 can be formed from a single chip of semiconductor chips 41 to 46 corresponding to the semiconductor device of the first embodiment. Therefore, compared to using separate chips to form gate resistors R11 to R16 and capacitors C11 to C16, the mounting size of the semiconductor module 10 can be reduced. Furthermore, if the specifications of switching elements S1 to S6 are changed, only the semiconductor chips 41 to 46 constituting gate resistors R11 to R16 and capacitors C11 to C16 need to be changed, making it easy to handle.

[0085] (Second Implementation)

[0086] Figure 9 is a top view showing an example of the semiconductor device according to the second embodiment. In Figure 9, the lower insulating film 2, resistive layer 3, conductive layer 3x, surface electrodes 5a and 5b, and contacts (contact plugs) 6a to 6c hidden under the protective film 7 are schematically shown in dashed lines. As shown in Figure 9, the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment shown in Figures 1 and 2 in that it also includes a conductive layer 3x disposed around the resistive layer 3 and located in the same layer as the resistive layer 3.

[0087] As shown in Figure 9, the conductive layer 3x is located inside the outer shape of the lower insulating film 2, and is arranged in a ring-shaped (frame-shaped) planar pattern to surround the resistive layer 3. The conductive layer 3x is not limited to a ring-shaped (frame-shaped) planar pattern; for example, it can be a U-shaped planar pattern with a portion of the ring-shaped (frame-shaped) pattern truncated. Alternatively, the conductive layer 3x can be a planar pattern divided into multiple rectangular regions. A portion of the conductive layer 3x overlaps with a portion of the surface electrodes 5a and 5b located above the conductive layer 3x. The conductive layer 3x is electrically connected to the surface electrode 5a via a contact 6c at the location where it overlaps with the surface electrode 5a. There are no particular limitations on the number or arrangement of the contacts 6c.

[0088] Figure 10 shows a cross-section along line AA′ of Figure 9, passing through resistive layer 3, conductive layer 3x, and surface electrodes 5a and 5b. Figure 11 shows a cross-section along line BB′ of Figure 9, passing through conductive layer 3x and surface electrodes 5a and 5b but not through resistive layer 3. As shown in Figures 10 and 11, conductive layer 3x is disposed on the upper surface side of the lower insulating film 2 in a manner separate from resistive layer 3. Conductive layer 3x is located below surface electrodes 5a and 5b. Conductive layer 3x is made of the same material as resistive layer 3 and has the same thickness as resistive layer 3. Conductive layer 3x can be formed by the same process as forming resistive layer 3.

[0089] In the semiconductor device according to the second embodiment, a capacitor C1 is formed with a resistive layer 3 as one electrode, a lower insulating film 2 located below (directly below) the resistive layer 3 as a dielectric (insulator), and a semiconductor substrate 1 and a back electrode 9 as the other electrode. Furthermore, a capacitor C2 is formed with a conductive layer 3x as one electrode, a lower insulating film 2 located below (directly below) the conductive layer 3x as a dielectric, and a semiconductor substrate 1 and a back electrode 9 as the other electrode. Resistor R1, capacitor C1, and capacitor C2 are connected in parallel to the surface electrode 5a. Other structures of the semiconductor device according to the second embodiment are the same as those of the semiconductor device according to the first embodiment shown in Figures 1 and 2, therefore, repeated descriptions are omitted.

[0090] According to the semiconductor device of the second embodiment, a resistor R1 and capacitors C1 and C2 connected in parallel to the surface electrode 5a can be implemented by a single chip. Furthermore, since capacitor C2, which uses the lower insulating film 2 located directly below the conductive layer 3x as a dielectric, is connected in parallel with capacitor C1, the capacitance value can be increased compared to the semiconductor device of the first embodiment.

[0091] (Third Implementation)

[0092] Figure 12 is a top view showing an example of a semiconductor device according to the third embodiment. In Figure 12, the outlines of the lower insulating film 2, resistive layer 3, conductive layer 3x, surface electrodes 5a, 5b, contacts 6a-6c, and trench 8, which are hidden beneath the protective film 7, are schematically shown in dashed lines. As shown in Figure 12, the semiconductor device according to the third embodiment also includes a conductive layer 3x disposed around the resistive layer 3, which is the same as the semiconductor device according to the second embodiment shown in Figures 9-11. However, the semiconductor device according to the third embodiment differs from the semiconductor device according to the second embodiment shown in Figures 9-11 in that a trench 8 is provided at a position lower than the conductive layer 3x.

[0093] As shown in Figure 12, the trench 8 is located inside the outer shape of the conductive layer 3x. The trench 8 is provided as a plurality of strip-shaped planar patterns that are separated from each other and extend parallel to the long side direction (vertical direction in Figure 12) of the surface electrodes 5a and 5b. There are no particular limitations on the spacing, width, or inner position of the trench 8. The trench 8 may also be provided as a plurality of strip-shaped planar patterns that extend parallel to the short side direction (horizontal direction in Figure 12) of the surface electrodes 5a and 5b, or it may be provided as a dot-shaped planar pattern instead of a strip-shaped planar pattern.

[0094] Along the long sides of surface electrodes 5a and 5b (vertical direction in Figure 12), trenches 8 are cut off in such a way that the resistive layer 3 is sandwiched in the middle, and are arranged facing each other. In Figure 12, trenches 8 are not arranged around contact 6c, but they can also be arranged around contact 6c.

[0095] Figure 13 shows a cross-section along line AA′ of Figure 12, passing through resistive layer 3, conductive layer 3x, and surface electrodes 5a and 5b. Figure 14 shows a cross-section along line BB′ of Figure 12, passing through conductive layer 3x and surface electrodes 5a and 5b but not through resistive layer 3. As shown in Figures 13 and 14, a trench 8, formed by digging from the upper surface of semiconductor substrate 1 into the depth direction, is provided on the upper surface side of semiconductor substrate 1. A portion of the lower insulating film 2 is provided inside the trench 8.

[0096] The thickness of the lower insulating film 2 located on the upper surface side of the semiconductor substrate 1 is greater than the thickness of the lower insulating film 2 located inside the trench 8. Alternatively, the thickness of the lower insulating film 2 located on the upper surface side of the semiconductor substrate 1 can be approximately the same as the thickness of the lower insulating film 2 located inside the trench 8. The lower insulating film 2 located inside the trench 8 is formed of the same material as the gate insulating film of the switching element within the semiconductor module of the semiconductor device according to the first embodiment and has the same or greater thickness, thereby ensuring insulation withstand voltage.

[0097] Inside the trench 8, a buried layer (conductive layer) 3y is embedded through the lower insulating film 2. The upper surface of the buried layer 3y is in contact with the lower surface of the conductive layer 3x. The material of the buried layer 3y can be the same as that of the resistive layer 3 and the conductive layer 3x, or it can be a different conductive material. The buried layer 3y can be integrally formed with the conductive layer 3x through the same process as that used to form the resistive layer 3 and the conductive layer 3x.

[0098] In the semiconductor device according to the third embodiment, a capacitor C1 is formed with the lower insulating film 2 located directly below the resistive layer 3 as the dielectric, and a capacitor C2 is formed with the lower insulating film 2 located directly below the conductive layer 3x as the dielectric. Furthermore, a capacitor C3 is connected in parallel with capacitors C1 and C2, with the buried layer 3y embedded in the trench 8 as one electrode, the lower insulating film 2 inside the trench 8 as the dielectric (insulator), and the semiconductor substrate 1 and the back electrode 9 as the other electrode. The other structures of the semiconductor device according to the third embodiment are the same as those of the semiconductor device according to the first embodiment shown in FIGS. 1 and 2, and the semiconductor device according to the second embodiment shown in FIGS. 9 to 11; therefore, repeated descriptions are omitted.

[0099] According to the semiconductor device of the third embodiment, a resistor R1 and capacitors C1 to C3 connected in parallel to the surface electrode 5a can be implemented by a single chip. Furthermore, since capacitor C2, which uses the lower insulating film 2 directly below the conductive layer 3x as a dielectric, and capacitor C3, which uses the lower insulating film 2 inside the trench 8 as a dielectric, are connected in parallel with capacitor C1, the capacitance value can be increased.

[0100] (Other implementation methods)

[0101] As described above, this disclosure has been presented through the first to third embodiments, but the discussions and drawings that constitute a part of this disclosure should not be construed as limiting this disclosure. Those skilled in the art will be able to identify various alternative embodiments, examples, and techniques based on this disclosure.

[0102] For example, the semiconductor device according to the first to third embodiments is illustrated in the case of applying it to the semiconductor module 10 shown in FIG4, but it can be applied to various integrated circuits (ICs) with resistors and capacitors other than the semiconductor module 10.

[0103] Furthermore, the structures disclosed in the first to third embodiments can be appropriately combined within a range that does not create contradictions. Thus, it is self-evident that this disclosure includes various embodiments not described herein. Therefore, the technical scope of this disclosure is determined solely by the inventive features addressed in the claims, which are appropriate according to the foregoing description.

[0104] Explanation of reference numerals in the attached figures

[0105] 1. 101: Semiconductor substrate; 2. 102a, 102b: Lower insulating film; 3. 103a, 103b: Resistive layer; 3x: Conductive layer; 3y: Buried layer; 4. 104: Interlayer insulating film; 5a, 5b, 105a, 105b: Surface electrode; 6a~6c, 106a~106g: Contact; 7. 107: Protective film; 7a, 7b, 107a, 107b: Opening; 8: Trench; 9. 109: Back electrode; 10: Semiconductor module; 11: HVIC; 12: LVIC; 13: BSD; 20: Controller; 30: Motor; 41~46: Semiconductor chip; 105c: Relay wiring; 105d: Protective ring.

Claims

1. A semiconductor device comprising: a semiconductor substrate; a lower insulating film disposed on an upper surface side of the semiconductor substrate; a resistive layer disposed on an upper surface side of the lower insulating film; an interlayer insulating film disposed on an upper surface side of the lower insulating film and the resistive layer; and a first surface electrode disposed on an upper surface side of the interlayer insulating film and electrically connected to one end of the resistive layer. The second surface electrode is disposed on the upper surface of the interlayer insulating film in a manner separate from the first surface electrode and is electrically connected to the other end of the resistive layer. And a back electrode, which is disposed on the lower surface side of the semiconductor substrate, wherein the resistance of the resistive layer and a first capacitor with the lower insulating film on the lower side of the resistive layer as the dielectric are connected in parallel to the first surface electrode.

2. The semiconductor device according to claim 1, wherein, The thickness of the lower insulating film is less than 1000 nm.

3. The semiconductor device according to claim 1 or 2, wherein, It also includes a conductive layer, which is disposed on the upper surface of the lower insulating film in a manner separate from the resistive layer and electrically connected to the first surface electrode. A second capacitor, with the lower insulating film on the lower side of the conductive layer as the dielectric, is connected in parallel with the first capacitor.

4. The semiconductor device according to claim 3, wherein, The conductive layer has a planar pattern that surrounds the resistive layer.

5. The semiconductor device according to claim 3, wherein, It also includes a buried layer, which is disposed in a trench on the upper surface side of the semiconductor substrate through a portion of the lower insulating film and is in contact with the conductive layer. A third capacitor, with the lower insulating film located inside the trench as the dielectric, is connected in parallel with the first capacitor and the second capacitor.

6. The semiconductor device according to claim 5, wherein, The groove has a plurality of strip-shaped planar patterns extending in one direction.

7. The semiconductor device according to claim 6, wherein, The trench has a planar pattern that is cut off in such a way that the resistive layer is sandwiched in the middle.

8. The semiconductor device according to claim 5, wherein, The thickness of the lower insulating film located on the upper surface side of the semiconductor substrate is greater than the thickness of the lower insulating film located on the inner side of the trench.

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