Method for monitoring internal stress of semiconductor device film

Abstract

The invention provides a method for monitoring the film internal stress of a semiconductor device, and the method comprises the steps: sequentially forming a barrier layer and a low-dielectric-constant material layer on the surface of a metal layer on a semiconductor structure, and then etching the barrier layer and the low-dielectric-constant material layer on the surface of the metal layer, so as to form dense holes in array arrangement, and finally, monitoring whether the metal layer is extruded into the hole or not by using dark field detection equipment in combination with a scanning electron microscope so as to judge whether the internal stress of the semiconductor device film is abnormal or not, so that the abnormal condition of the internal stress of the semiconductor device film can be effectively, quickly and accurately monitored on a conventional production line without PWG measurement equipment; the manufacturing cost of the semiconductor device is saved, and the film internal stress monitoring efficiency of the semiconductor device is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and more specifically to a method for monitoring the internal stress of a semiconductor device film. Background Technology

[0002] When the internal stress of the semiconductor device / structure is high, after long-term use, phenomena such as film separation and migration of metal ions (e.g., copper ions) may occur, affecting the yield.

[0003] In semiconductor devices / structures, the difference in thermal expansion coefficients between the metal layer (e.g., copper) and the barrier layer (e.g., NDC (nitrogen-doped silicon carbide) layer) on the surface of the metal layer is significant. Specifically, copper has a thermal expansion coefficient of 17 ppm / ℃, while the NDC layer has a coefficient of thermal expansion of 3 ppm / ℃. During subsequent cooling processes, copper shrinks more than the NDC layer, resulting in substantial compressive stress within the semiconductor device film. This can lead to a decrease in semiconductor device yield after prolonged use.

[0004] In advanced semiconductor manufacturing plants, PWG (Plasma Wave Generation) equipment is typically used to measure internal stress, carrier concentration, and mobility in semiconductor devices / structures, enabling effective and accurate monitoring of abnormal internal stress conditions. However, due to the high cost of PWG measurement equipment, many manufacturing lines are not equipped with it due to cost constraints. Conventional manufacturing plants without PWG measurement equipment cannot effectively and accurately monitor whether there are abnormal internal stresses in semiconductor devices. Summary of the Invention

[0005] This application provides a method for monitoring the internal stress of semiconductor devices, which can solve the problem that conventional manufacturing plants without PWG measurement equipment cannot effectively and accurately monitor abnormal internal stress of semiconductor devices.

[0006] This application provides a method for monitoring the internal stress of a semiconductor device film, including: A semiconductor structure is provided, wherein a metal layer is formed on the semiconductor structure; A barrier layer and a low dielectric constant material layer are formed sequentially, wherein the barrier layer covers the metal layer and the low dielectric constant material layer covers the barrier layer; A photoresist layer is coated on the low dielectric constant material layer; An array of holes is formed on the photoresist layer using photolithography to obtain a patterned photoresist layer. Using a patterned photoresist layer as a mask, the low dielectric constant material layer and the barrier layer are etched and the etching stops on the surface of the metal layer to form an array of holes in the low dielectric constant material layer and the barrier layer. Using a dark-field detection device in conjunction with a scanning electron microscope, monitor whether the metal layer at the bottom of the hole is squeezed into the hole; If the metal layer at the bottom of the hole is squeezed into the hole, it is determined that the internal stress of the semiconductor device is abnormal; if the metal layer at the bottom of the hole is not squeezed into the hole, it is determined that the internal stress of the semiconductor device is normal.

[0007] Optionally, in the method for monitoring the stress within the film of a semiconductor device, the spacing between two adjacent holes in the same row or column of the array of holes is 150 nm to 200 nm.

[0008] Optionally, in the method for monitoring the stress within the film of a semiconductor device, the inner diameter of each hole in the array of holes is 300 nm to 400 nm.

[0009] Optionally, in the method for monitoring intrafilm stress in semiconductor devices, the step of using a dark-field detection device in conjunction with a scanning electron microscope to monitor whether the metal layer at the bottom of the hole is squeezed into the hole includes: Dark field inspection equipment is used to identify potential defect sites such as metal layer extrusion protrusions in semiconductor devices on mass production lines. If there are suspected defect sites with metal layer extrusion protrusions, then a scanning electron microscope is used to further observe all of the suspected defect sites in the semiconductor device. If a microscopic morphology of metal layer extrusion protrusion is observed at the suspected defect site using a scanning electron microscope, it is determined that the metal layer at the bottom of the hole has been extruded into the hole; if no microscopic morphology of metal layer extrusion protrusion is observed at the suspected defect site using a scanning electron microscope, it is determined that the metal layer at the bottom of the hole has not been extruded into the hole.

[0010] Optionally, in the method for monitoring the stress within the film of a semiconductor device, the metal layer is made of copper.

[0011] Optionally, in the method for monitoring the intrafilm stress of a semiconductor device, the ratio of the thickness of the metal layer to the thickness of the barrier layer is 5:1.

[0012] Optionally, in the method for monitoring the stress within the film of a semiconductor device, the barrier layer is made of nitrogen-doped silicon carbide.

[0013] Optionally, in the method for monitoring the stress within the film of a semiconductor device, the thickness of the barrier layer is 30 nm.

[0014] Optionally, in the method for monitoring the stress within the film of a semiconductor device, the material of the low dielectric constant material layer is fluorine-doped silicon dioxide, silicon oxynitride, silicon oxycarbide, or a porous organosilicon low dielectric constant material.

[0015] Optionally, in the method for monitoring the stress within the film of a semiconductor device, a patterned photoresist layer is used as a mask, and a wet etching process is employed to etch the low dielectric constant material layer and the barrier layer and stop at the surface of the metal layer, so as to form an array of holes in the low dielectric constant material layer and the barrier layer.

[0016] The technical solution of this application has at least the following advantages: In the method for monitoring intrafilm stress in semiconductor devices provided in this application, a photoresist layer is first coated on the surface of the semiconductor structure after a metal layer, a barrier layer, and a low-dielectric-constant material layer are formed in sequence. Then, an array of holes is formed on the photoresist layer. Next, using the patterned photoresist layer as a mask, the low-dielectric-constant material layer and the barrier layer are etched and stopped on the surface of the metal layer to form an array of holes. Finally, a dark-field detection device is used in conjunction with a scanning electron microscope to monitor whether the metal layer is squeezed into the holes. If the metal layer at the bottom of the holes is squeezed into the holes, it is determined that the intrafilm stress of the semiconductor device is abnormal. This application forms a dense array of holes in a barrier layer and a low dielectric constant material layer on the surface of a metal layer. By using a dark field testing device in conjunction with a scanning electron microscope, it monitors whether the metal layer is squeezed into the holes to determine whether the internal stress of the semiconductor device is abnormal. This method can effectively, quickly and accurately monitor the abnormal internal stress of semiconductor devices on conventional production lines that are not equipped with PWG measurement equipment, thereby saving the manufacturing cost of semiconductor devices and improving the efficiency of monitoring internal stress of semiconductor devices. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a flowchart of a method for monitoring intrafilm stress in semiconductor devices according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the semiconductor structure after the photoresist layer has been coated, according to an embodiment of this application. Figure 3 This is a schematic diagram of the semiconductor structure after the patterned photoresist layer is formed, according to an embodiment of this application. Figure 4 This is a top view schematic diagram of the patterned photoresist layer in an embodiment of this application; Figure 5 This is a schematic diagram of the semiconductor structure after the array of holes is formed, according to an embodiment of this application. Figure 6 This is a schematic diagram of the semiconductor structure after the patterned photoresist layer has been removed, according to an embodiment of this application. Figure 7 This is a top view of a low dielectric constant material layer after forming an array of holes according to an embodiment of this application. The reference numerals in the attached figures are explained as follows: 10 - Semiconductor structure, 20 - Metal layer, 21 - Extruded metal layer protrusion, 30 - Barrier layer, 40 - Low dielectric constant material layer, 41 - Hole, 50 - Photoresist layer, 51 - Patterned photoresist layer, 52 - Hole pattern. Detailed Implementation

[0019] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0021] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal connection between two components; and they can refer to wireless connections or wired connections. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0022] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0023] This application provides a method for monitoring the intrafilm stress of a semiconductor device, referring to... Figure 1 , Figure 1 This is a flowchart of a method for monitoring the internal stress of a semiconductor device film according to an embodiment of the present invention. The method for monitoring the internal stress of a semiconductor device film includes: First, perform step S1: Refer to Figure 2 , Figure 2 This is a schematic diagram of a semiconductor structure after a photoresist layer has been coated according to an embodiment of this application. A semiconductor structure 10 is provided, on which a metal layer 20 is formed.

[0024] In this embodiment, the metal layer 20 is made of copper.

[0025] Then, proceed to step S2: Continue to refer to Figure 2 A barrier layer 30 and a low dielectric constant material layer 40 are formed sequentially, wherein the barrier layer 30 covers the metal layer 20, and the low dielectric constant material layer 40 covers the barrier layer 30.

[0026] Preferably, the ratio of the thickness of the metal layer 20 to the thickness of the barrier layer 30 is 5:1.

[0027] Furthermore, the ratio of the thickness of the barrier layer 30 to the thickness of the low dielectric constant material layer 40 is (1:8) to (1:12).

[0028] In this embodiment, the barrier layer 30 is made of nitrogen-doped silicon carbide.

[0029] Preferably, the thickness of the barrier layer 30 is 30 nm.

[0030] Furthermore, the low dielectric constant material layer 40 is made of fluorine-doped silicon dioxide, silicon oxynitride, silicon oxycarbide, or porous organosilicon low dielectric constant material. Among these, porous organosilicon low dielectric constant materials include, but are not limited to, hydrogenated organosilicon alkane, methyl organosilicon alkane, etc.

[0031] In this embodiment, the low dielectric constant material layer 40 is made of fluorine-doped silicon dioxide.

[0032] Next, proceed to step S3: Continue to refer to Figure 2 A photoresist layer 50 is coated on the low dielectric constant material layer 40.

[0033] Further, proceed to step S4: (Refer to...) Figure 3 and Figure 4 , Figure 3 This is a schematic diagram of the semiconductor structure after the patterned photoresist layer is formed, according to an embodiment of this application. Figure 4 This is a top view of a patterned photoresist layer according to an embodiment of this application. An array of holes 52 are formed on the photoresist layer 50 by a photolithography process to obtain a patterned photoresist layer 51.

[0034] Next, proceed to step S5: (Refer to...) Figure 5 , Figure 5 This is a schematic diagram of a semiconductor structure after the formation of an array of holes according to an embodiment of this application. Using a patterned photoresist layer 51 as a mask, the low dielectric constant material layer 40 and the barrier layer 30 are etched and the etching stops on the surface of the metal layer 20 to form an array of holes 41 in the low dielectric constant material layer 40 and the barrier layer 30.

[0035] In this embodiment, a patterned photoresist layer 51 is used as a mask, and a wet etching process is employed to etch the low dielectric constant material layer 40 and the barrier layer 30 and stop at the surface of the metal layer 20, so as to form an array of holes 41 in the low dielectric constant material layer 40 and the barrier layer 30.

[0036] In other embodiments, using a patterned photoresist layer 51 as a mask, a dry etching process is employed to etch the low dielectric constant material layer 40 and the barrier layer 30 and stop at the surface of the metal layer 20, so as to form an array of holes 41 in the low dielectric constant material layer 40 and the barrier layer 30.

[0037] Better, for reference Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after removing the patterned photoresist layer according to an embodiment of this application. After forming the array of holes 41, the method for monitoring the stress inside the semiconductor device film may further include: removing the patterned photoresist layer 51.

[0038] Preferred, Reference Figure 7 , Figure 7 This is a top view schematic diagram of the low dielectric constant material layer after the formation of the array of holes according to an embodiment of this application, and... Figure 4 Corresponding to the hole pattern 52, in the array of holes 41, the spacing a between two adjacent holes in the same row or the spacing b between two adjacent holes in the same column is 150nm~200nm.

[0039] Better, for reference Figure 7 ,and Figure 4 The hole pattern 52 corresponds to the array of holes 41, where the inner diameter of each hole 41 is 300nm~400nm.

[0040] This application forms a dense array of holes 41 in the low dielectric constant material layer 40 and the barrier layer 30 on the metal layer 20, which can appropriately amplify the intrafilm stress of the semiconductor device.

[0041] Further, step S6 is performed: using a dark field detection device and a scanning electron microscope, the metal layer 20 at the bottom of the hole 41 is monitored to see if it is squeezed into the hole 41.

[0042] Specifically, step S6, which uses a dark-field detection device in conjunction with a scanning electron microscope to monitor whether the metal layer 20 at the bottom of the hole 41 is squeezed into the hole 41, includes: Step S6.1: Using dark field inspection equipment, identify online whether there are suspected defect sites of metal layer extrusion protrusion 21 in semiconductor devices on the mass production line; Step S6.2: If there are suspected defect sites of metal layer extrusion protrusion 21, then use a scanning electron microscope to further observe all the suspected defect sites in the semiconductor device; Step S6.3: If the microstructure of the metal layer extrusion protrusion 21 is observed at the suspected defect site using a scanning electron microscope, it is determined that the metal layer 20 at the bottom of the hole 41 is extruded into the hole 41; if the microstructure of the metal layer extrusion protrusion 21 is not observed at the suspected defect site using a scanning electron microscope, it is determined that the metal layer 20 at the bottom of the hole 41 is not extruded into the hole 41.

[0043] Finally, step S7 is executed: if the metal layer 20 at the bottom of the hole 41 is squeezed into the hole 41, it is determined that the internal stress of the semiconductor device film is abnormal; if the metal layer 20 at the bottom of the hole 41 is not squeezed into the hole 41, it is determined that the internal stress of the semiconductor device film is normal.

[0044] In this application, by forming a dense array of holes in the barrier layer and the low dielectric constant material layer on the surface of the metal layer, and using a dark field detection device in conjunction with a scanning electron microscope, it is possible to monitor whether the metal layer is squeezed into the holes to determine whether the internal stress of the semiconductor device is abnormal. This method can effectively, quickly and accurately monitor the abnormal internal stress of the semiconductor device on a conventional production line that is not equipped with PWG measurement equipment, thereby saving the manufacturing cost of the semiconductor device and improving the efficiency of monitoring the internal stress of the semiconductor device.

[0045] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for monitoring intrafilm stress in a semiconductor device, characterized in that, include: A semiconductor structure is provided, wherein a metal layer is formed on the semiconductor structure; A barrier layer and a low dielectric constant material layer are formed sequentially, wherein the barrier layer covers the metal layer and the low dielectric constant material layer covers the barrier layer; A photoresist layer is coated on the low dielectric constant material layer; An array of holes is formed on the photoresist layer using photolithography to obtain a patterned photoresist layer. Using a patterned photoresist layer as a mask, the low dielectric constant material layer and the barrier layer are etched and the etching stops on the surface of the metal layer to form an array of holes in the low dielectric constant material layer and the barrier layer. Using a dark-field detection device in conjunction with a scanning electron microscope, monitor whether the metal layer at the bottom of the hole is squeezed into the hole; If the metal layer at the bottom of the hole is squeezed into the hole, then an abnormal intrafilm stress in the semiconductor device is determined. If the metal layer at the bottom of the hole is not squeezed into the hole, it is determined that the internal stress of the semiconductor device is normal.

2. The method for monitoring intrafilm stress in semiconductor devices according to claim 1, characterized in that, In an array of holes, the spacing between two adjacent holes in the same row or column is 150nm~200nm.

3. The method for monitoring intrafilm stress in semiconductor devices according to claim 1, characterized in that, In the array of holes, the inner diameter of each hole is 300nm~400nm.

4. The method for monitoring intrafilm stress in semiconductor devices according to claim 1, characterized in that, The step of using a dark-field detection device in conjunction with a scanning electron microscope to monitor whether the metal layer at the bottom of the hole is squeezed into the hole includes: Dark field inspection equipment is used to identify potential defect sites such as metal layer extrusion protrusions in semiconductor devices on mass production lines. If there are suspected defect sites with metal layer extrusion protrusions, then a scanning electron microscope is used to further observe all of the suspected defect sites in the semiconductor device. If a microscopic morphology of metal layer extrusion protrusion is observed at the suspected defect site using a scanning electron microscope, it is determined that the metal layer at the bottom of the hole has been extruded into the hole; if no microscopic morphology of metal layer extrusion protrusion is observed at the suspected defect site using a scanning electron microscope, it is determined that the metal layer at the bottom of the hole has not been extruded into the hole.

5. The method for monitoring intrafilm stress in semiconductor devices according to claim 1, characterized in that, The metal layer is made of copper.

6. The method for monitoring intrafilm stress in semiconductor devices according to claim 1, characterized in that, The ratio of the thickness of the metal layer to the thickness of the barrier layer is 5:

1.

7. The method for monitoring intrafilm stress in semiconductor devices according to claim 1, characterized in that, The barrier layer is made of nitrogen-doped silicon carbide.

8. The method for monitoring intrafilm stress in semiconductor devices according to claim 1, characterized in that, The thickness of the barrier layer is 30 nm.

9. The method for monitoring intrafilm stress in semiconductor devices according to claim 1, characterized in that, The material layer with low dielectric constant is made of fluorine-doped silicon dioxide, silicon oxynitride, silicon oxycarbonate, or porous organosilicon with low dielectric constant.

10. The method for monitoring intrafilm stress in a semiconductor device according to claim 1, characterized in that, Using a patterned photoresist layer as a mask, a wet etching process is employed to etch the low dielectric constant material layer and the barrier layer, stopping at the surface of the metal layer, to form an array of holes in the low dielectric constant material layer and the barrier layer.

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