Method for testing electrostatic impact resistance of grid electrode of metal oxide semiconductor field effect transistor

Abstract

The invention discloses a method for testing electrostatic shock resistance of a grid electrode of a metal oxide semiconductor field effect transistor, which comprises the following steps of: firstly, testing a maximum voltage value which can be borne between the grid electrode of a device and other electrodes under transient pulse by utilizing a transmission line pulse tester; the maximum voltage value capable of being borne by the device grid and the capacitance of the device grid are substituted into corresponding formulas, and the anti-static impact capacity of the device in the human body mode and the machine mode is calculated respectively. According to the method, only one testing device of the transmission line pulse generator is needed, the grid anti-static impact capacity of the device in the two modes can be obtained through one-time sample testing, the number of needed samples is small, the testing time is short, the testing precision is high, and the defects of a traditional testing method are overcome.

Description

Technical Field

[0001] This invention relates to the field of semiconductor transistor technology, and in particular to a method for testing the electrostatic discharge (ESD) resistance of field-effect transistors. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in power management, industrial control, and other fields due to their ease of driving and fast switching speeds. During transportation and soldering, transistors come into contact with people, machines, or other objects, which can cause electrostatic discharge (ESD) shocks, leading to device damage. Since there is no discharge path between the gate and other electrodes of a MOSFET, its ESD resistance is relatively low. Therefore, accurate testing of the device's gate ESD resistance is necessary to implement appropriate reliability protection measures.

[0003] Existing methods for testing electrostatic discharge (ESD) resistance require the use of a step-type electrostatic gun, which includes modes such as Human Body Discharge (HBM), Machine Discharge (MM), and Charged Device Discharge (CDM). Only one mode can be selected for each test, and only one voltage value can be set for a single test. After the test, a new device is needed to check the damage to the device. The ESD resistance of the device's gate is found by continuously increasing the voltage value. The test steps are cumbersome, the test volume is large, and it is difficult to obtain accurate values. Summary of the Invention

[0004] To address the aforementioned issues, this invention proposes a method for testing the gate electrostatic discharge (ESD) resistance of a metal-oxide-semiconductor field-effect transistor (MOSFET). By using a transmission line pulse generator (TLP) to test the maximum voltage stress that the gate of the device can withstand, and then calculating the ESD resistance of the device under different electrostatic discharge (ESD) modes through a single test, the device's ESD resistance under different ESD modes can be obtained.

[0005] In some implementations, the following technical solutions are adopted: Test method for the gate electrostatic discharge (ESD) immunity of metal-oxide-semiconductor field-effect transistors: Step 1: Connect the output port of the transmission line pulse generator to the gate and source of the metal-oxide-semiconductor field-effect transistor (MOSFET) under test. Test the current-voltage characteristics of the device by gradually increasing the output current at the port. After each pulse, monitor the leakage current between the gate and source. Stop the test when the leakage current exceeds the maximum allowable leakage current. Record the gate voltage under the pulse condition one pulse before the leakage current exceeds the maximum allowable leakage current; this is defined as the maximum transient impulse voltage that the device's gate and source can withstand. Step 2: Replace the source in Step 1 with the drain, and use the same method to test the maximum transient surge voltage that the device's gate and drain can withstand. Step 3: If the device includes electrodes other than the gate, source, and drain, then use the method described in Step 1 to replace the source electrode with another electrode, and test the maximum transient impulse voltage that the gate can withstand between the gate and other electrodes. Step 4: Define the minimum value among the maximum transient impulse voltages that the gate can withstand between the gate and the electrodes outside the gate, as measured in the first three steps, as the maximum transient impulse voltage that the gate can withstand. Step 5: Calculate the magnitude of the human body mode electrostatic discharge (ESD) voltage that the device can withstand, based on the human body mode ESD voltage calculation formula. The formula is as follows: To address the aforementioned issues, this invention proposes a method for testing the gate electrostatic discharge (ESD) resistance of a metal-oxide-semiconductor field-effect transistor (MOSFET). By using a transmission line pulse generator (TLP) to test the maximum voltage stress that the gate of the device can withstand, and then calculating the ESD resistance of the device under different electrostatic discharge (ESD) modes through a single test, the device's ESD resistance under different ESD modes can be obtained.

[0006] In some implementations, the following technical solutions are adopted: Test method for the gate electrostatic discharge (ESD) immunity of metal-oxide-semiconductor field-effect transistors: Step 1: Connect the output port of the transmission line pulse generator to the gate and source of the metal-oxide-semiconductor field-effect transistor (MOSFET) under test. Test the current-voltage characteristics of the device by gradually increasing the output current at the port. After each pulse, monitor the leakage current between the gate and source. Stop the test when the leakage current exceeds the maximum allowable leakage current. Record the gate voltage under the pulse condition one pulse before the leakage current exceeds the maximum allowable leakage current; this is defined as the maximum transient impulse voltage that the device's gate and source can withstand. Step 2: Replace the source in Step 1 with the drain, and use the same method to test the maximum transient surge voltage that the device's gate and drain can withstand. Step 3: If the device includes electrodes other than the gate, source, and drain, then use the method described in Step 1 to replace the source electrode with another electrode, and test the maximum transient impulse voltage that the gate can withstand between the gate and other electrodes. Step 4: Define the minimum value among the maximum transient impulse voltages that the gate can withstand between the gate and the electrodes outside the gate, as measured in the first three steps, as the maximum transient impulse voltage that the gate can withstand. Step 5: Calculate the magnitude of the human body mode electrostatic discharge (ESD) voltage that the device can withstand, based on the human body mode ESD voltage calculation formula. The formula is as follows: in V HBM To enhance the gate's resistance to human body mode electrostatic discharge (ESD) shocks of the device. C HBM This is a simulated human body capacitance value. C gg The gate input capacitance of the device under test. V TLP The maximum transient surge voltage that the gate can withstand, as described in step 4. Step 6: Calculate the magnitude of the human body mode electrostatic discharge (ESD) voltage that the device can withstand based on the machine mode ESD calculation formula, as follows:

[0007] in V MM To improve the gate's resistance to machine-mode electrostatic discharge (ESD) in devices. C MM The simulated machine capacitance value. C gg The gate input capacitance of the device under test. V TLP This refers to the maximum transient impact voltage that the gate can withstand, as described in step 4.

[0008] As a further measure, the rising and falling edges of the output current pulse of the transmission line pulse generator used in the test were set to 10 ns, and the pulse width was set to 100 ns.

[0009] As a further option, the maximum permissible leakage current is set to 10 times the gate leakage current before device stress.

[0010] As a further solution, the simulated human body capacitance C HBM The size is 100 pF, the simulated machine capacitor C MM The size is set to 200 pF.

[0011] Compared with the prior art, the beneficial effects of the present invention are: (1) The method of the present invention can monitor the gate leakage current of the device in real time during the transmission line pulse generator test process, without switching equipment to test whether the device is faulty, and the test speed is fast.

[0012] (2) The minimum adjustable step size of the electrostatic stress output by traditional test equipment is only 10 V, and the test accuracy cannot reach within 10 V. However, the output current of the transmission line pulse generator can be continuously adjusted with a minimum step size of 1 mA, which can achieve a test accuracy within 1 V for a typical 500pF gate input capacitor.

[0013] (3) The method of the present invention can determine the anti-static shock capability of the device in both human body mode and machine mode in one test, requiring less test time, fewer samples, and lower test cost.

[0014] Figure 1 This is a flowchart of the testing process for the present invention. Figure 2 The results of gate and source current-voltage characteristic tests when the method of this invention is applied to the ESD capability test of silicon-based MOSFETs. Figure 3 The results of gate and source leakage current monitoring after each pulse when the method of the present invention is applied to the ESD capability test of silicon-based MOSFET gates are presented.

[0015] Figure 4 The results of gate and drain current-voltage characteristic tests when the method of this invention is applied to the ESD capability test of silicon-based MOSFET gates. Figure 5 The results of gate and drain leakage current monitoring after each pulse when the method of the present invention is applied to the ESD capability test of silicon-based MOSFET gates are presented. Detailed Implementation

[0016] A method for testing the gate electrostatic discharge (ESD) immunity of a metal-oxide-semiconductor field-effect transistor: Step 1: Connect the output port of the transmission line pulse generator to the gate and source of the metal-oxide-semiconductor field-effect transistor (MOSFET) under test. Test the current-voltage characteristics of the device by gradually increasing the output current at the port. After each pulse, monitor the leakage current between the gate and source. Stop the test when the leakage current exceeds the maximum allowable leakage current. Record the gate voltage under the pulse condition one pulse before the leakage current exceeds the maximum allowable leakage current; this is defined as the maximum transient impulse voltage that the device's gate and source can withstand. Step 2: Replace the source in Step 1 with the drain, and use the same method to test the maximum transient surge voltage that the device's gate and drain can withstand. Step 3: If the device includes electrodes other than the gate, source, and drain, then use the method described in Step 1 to replace the source electrode with another electrode, and test the maximum transient impulse voltage that the gate can withstand between the gate and other electrodes. Step 4: Define the minimum value among the maximum transient impulse voltages that the gate can withstand between the gate and the electrodes outside the gate, as measured in the first three steps, as the maximum transient impulse voltage that the gate can withstand. Step 5: Calculate the magnitude of the human body mode electrostatic discharge (ESD) voltage that the device can withstand, based on the human body mode ESD voltage calculation formula. The formula is as follows:

[0017] in V HBM To enhance the gate's resistance to human body mode electrostatic discharge (ESD) shocks of the device. C HBM This is a simulated human body capacitance value. C gg The gate input capacitance of the device under test. V TLP The maximum transient surge voltage that the gate can withstand, as described in step 4. Step 6: Calculate the magnitude of the human body mode electrostatic discharge (ESD) voltage that the device can withstand based on the machine mode ESD calculation formula, as follows:

[0018] in V MM To improve the gate's resistance to machine-mode electrostatic discharge (ESD) in devices. C MM The simulated machine capacitance value. C gg The gate input capacitance of the device under test. V TLP This refers to the maximum transient impact voltage that the gate can withstand, as described in step 4.

[0019] The working principle of this invention is: For MOSFET devices, since there is no discharge path for the charge, the static electricity will accumulate on the gate capacitance of the device, causing the gate voltage to rise. When the charge is too large, the gate oxide layer of the device will break down and be damaged. The failure principle is the same for both human body mode and machine mode ESD. Therefore, the maximum transient voltage that the device gate can withstand becomes the fundamental principle for calculating the ESD resistance of the device gate.

[0020] Transmission line pulse generators can charge the gate of a MOSFET for a short period of time, thereby generating short-term gate voltage stress. When the gate voltage stress exceeds the maximum transient voltage that the gate can withstand, the gate will break down and be damaged. The failure mechanism is the same as the electrostatic discharge (ESD) failure mechanism of the gate. Therefore, the stress generated by the transmission line pulse generator can simulate the ESD process of the device gate, thereby measuring the device's ESD resistance.

[0021] The maximum transient voltage that the gate of a MOSFET device can withstand is measured using a transmission line pulse test instrument. V TLPThen, by applying this to the standard models of electrostatic shock in human and machine modes, the ESD capability VHBM in human mode and the ESD capability VMM in machine mode under the corresponding conditions can be calculated. The specific conversion formulas are as follows:

[0022] in C HBM This refers to the capacitance value used to simulate the capacitance of the human body in the human body model electrostatic shock model; a typical value is 100 pF. C MM This is the capacitance value used to simulate machine capacitance in the machine-mode electrostatic shock model, typically 200 pF.

[0023] The following diagram illustrates the process and results of our ESD capability test for a silicon-based MOSFET gate: Step 1: Connect the output port of the transmission line pulse generator between the gate and source of the device under test (DUT). Set the rising and falling edges of the output pulse to 10ns, the pulse width to 100ns, and the pulse current increment step to 0.15A. Under the initial gate state, the maximum leakage current at a gate-source voltage of 3V is 1nA. Set the test stop criterion to a leakage current greater than 10nA at a gate-source voltage of 3V. The test results are as follows: Figure 2 and Figure 3 As shown, Figure 2 This shows the relationship between the transmission line pulse current and the device gate voltage. Figure 3 The display shows the magnitude of the gate leakage current monitored after the corresponding pulse ends. When the device is subjected to a pulse current stress of 4.3A, the gate leakage current of the device reaches 199.9mA, which far exceeds the limit current of 10nA. Therefore, the test is stopped. The maximum gate-source voltage that the device gate can withstand is the magnitude of the gate-source voltage obtained under the previous pulse, i.e., the pulse current of 4.15A, which is 61.42V.

[0024] Step 2: Replace the source in Step 1 with the drain, and use the same method to test the maximum transient surge voltage that the device gate and drain can withstand. The results are as follows: Figure 4 and Figure 5 As shown, the device fails after a 4.3A pulse current. Therefore, the maximum gate and drain voltage that the device can withstand is the gate and drain voltage obtained under the previous pulse, i.e., a 4.15A pulse current, which is 67.4V. Step 3: The device used in this embodiment has no electrodes other than the gate, source, and drain, therefore no further testing is required. Step 4: In this embodiment, the maximum transient voltage that the device gate and source can withstand is smaller. Therefore, the maximum transient surge voltage that the gate of this device can withstand is also smaller. V TLP It is 61.42V. Step 5: Calculate the electrostatic shock resistance using the following human body model formula:

[0025] in C HBM To simulate the capacitance of the human body, a value of 100 pF is used. C gg Given the gate input capacitance of the device as 4761.6 pF, the calculated human body mode ESD withstand capability of the device is 2986.00 V. Step 6: Calculate the anti-static shock according to the machine mode formula:

[0026] in C MM The simulated machine capacitance value is set to 200 pF. C gg Given the gate input capacitance of the device, which is 596.8pF, the calculated machine-mode ESD tolerance of the device is 1523.71 V.

[0027] Those skilled in the art can implement the present invention in various modified forms without departing from the essence and spirit of the present invention. The above description is only a preferred and feasible embodiment of the present invention and is not intended to limit the scope of the present invention. All equivalent changes made using the accompanying drawings shown in this invention are included within the scope of the present invention.

Claims

1. A method for testing the electrostatic discharge (ESD) immunity of a metal-oxide-semiconductor field-effect transistor (MOSFET), characterized in that, Step 1: Connect the output port of the transmission line pulse generator to the gate and source of the metal-oxide-semiconductor field-effect transistor (MOSFET) under test. Test the current-voltage characteristics of the device by gradually increasing the output current at the port. After each pulse, monitor the leakage current between the gate and source. Stop the test when the leakage current exceeds the maximum allowable leakage current. Record the gate voltage under the pulse condition one pulse before the leakage current exceeds the maximum allowable leakage current; this is defined as the maximum transient impulse voltage that the device's gate and source can withstand. Step 2: Replace the source in Step 1 with the drain, and use the same method to test the maximum transient surge voltage that the device's gate and drain can withstand. Step 3: If the device includes electrodes other than the gate, source, and drain, then use the method described in Step 1 to replace the source electrode with another electrode, and test the maximum transient impulse voltage that the gate can withstand between the gate and other electrodes. Step 4: Define the minimum value among the maximum transient impulse voltages that the gate can withstand between the gate and the electrodes outside the gate, as measured in the first three steps, as the maximum transient impulse voltage that the gate can withstand. Step 5: Calculate the magnitude of the human body mode electrostatic discharge (ESD) voltage that the device can withstand, based on the human body mode ESD voltage calculation formula. The formula is as follows: in V HBM To enhance the gate's resistance to human body mode electrostatic discharge (ESD) shocks of the device. C HBM This is a simulated human body capacitance value. C gg The gate input capacitance of the device under test. V TLP The maximum transient surge voltage that the gate can withstand, as described in step 4. Step 6: Calculate the magnitude of the human body mode electrostatic discharge (ESD) voltage that the device can withstand based on the machine mode ESD calculation formula, as follows: in V MM To improve the gate's resistance to machine-mode electrostatic discharge (ESD) in devices. C MM The simulated machine capacitance value. C gg The gate input capacitance of the device under test. V TLP This refers to the maximum transient impact voltage that the gate can withstand, as described in step 4.

2. The method for testing the gate electrostatic discharge (ESD) resistance of a metal-oxide-semiconductor field-effect transistor as described in claim 1, characterized in that, During the test, the rising and falling edges of the current pulses emitted by the transmission line pulse generator were set to 10ns, and the pulse width was 100ns.

3. The method for testing the gate electrostatic discharge (ESD) resistance of a metal-oxide-semiconductor field-effect transistor as described in claim 1, characterized in that, The maximum permissible leakage current is set to 10 times the gate leakage current before device stress.

4. The method for testing the electrostatic discharge (ESD) immunity of a metal-oxide-semiconductor field-effect transistor gate as described in claim 1, characterized in that, The above C HBM The size is 100pF, the C MM The size is 200pF.

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