Automatic backboard testing system based on upper computer

Abstract

The invention relates to the field of backboard automatic testing, in particular to a backboard automatic testing system based on an upper computer, which comprises an upper computer module used for customizing test items, arranging a test sequence, setting test parameters and judgment rules, sequentially issuing configuration information to a main MCU (Microprogrammed Control Unit) and providing a graphical test configuration interface; and the main MCU module is used for testing and executing the core scheduler and running real-time operating system (RTOS) software. According to the method, a firmware function curing mode is thoroughly changed through software-defined testing and a self-defined testing process of the upper computer, so that the testing tool can quickly adapt to new products and new testing requirements, the flexibility and universality are greatly improved, one-time development and multi-time adaptation are achieved, meanwhile, testing items can be self-defined through the upper computer for testing the type of the backboard, and the testing efficiency is improved. A test instruction set is generated and sequentially issued to the main control module, and the main control module dynamically dispatches and executes an operation instruction and feeds back data.

Description

Technical Field

[0001] This invention belongs to the field of backplane automated testing technology, specifically a host computer-based backplane automated testing system. Background Technology

[0002] In the production and quality inspection of industrial electronic detonator backplates, comprehensive testing of their hardware performance (such as voltage, current, load driving capability, and load-carrying capacity) and software functions (such as serial communication, cascade bus communication, and memory read / write) is required. Currently, most common testing fixtures are dedicated equipment with fixed functions, which still have the following significant defects and limitations:

[0003] Poor flexibility: The testing process and projects are fixed and cannot adapt to rapid changes in different backplane models or new testing requirements; each change requires redevelopment or modification of tooling firmware, which is time-consuming and costly.

[0004] Limited automation: Switching between test items and dynamically adjusting test conditions (such as load mode) rely on manual operation, making it difficult to achieve fully automated testing of complex sequences, resulting in low efficiency and a high risk of errors;

[0005] Insufficient versatility: A set of tooling is usually only for a specific model of backplate, which leads to the need for multiple toolings on the production line, resulting in complex management and low resource utilization.

[0006] Therefore, the present invention provides an automated testing system based on a host computer backplane. Summary of the Invention

[0007] In order to overcome the shortcomings of the prior art, at least one technical problem raised in the background art is solved.

[0008] The technical solution adopted by this invention to solve its technical problem is: an automated testing system based on a host computer backplane, comprising:

[0009] The host computer module is used to customize test items, arrange test sequences, set test parameters and judgment rules, send configuration information to the main MCU in sequence, and provide a graphical test configuration interface.

[0010] Main MCU module: used for core scheduler test execution, running real-time operating system (RTOS) software;

[0011] Test load module: used for two-bus connection between the main MCU and the test backplane MCU. Through the load switching circuit of the main MCU, it can switch between multiple modes such as open circuit, short circuit, fixed resistor, and simulated detonator load according to the instructions of the host computer.

[0012] Test backplane MCU module: used to receive test commands from the main MCU;

[0013] The system's main MCU hardware module is used to test the power supply of the backplane MCU and the cascaded communication between the main MCU and the backplane MCU.

[0014] The main MCU hardware module of the system consists of a backplane voltage and current acquisition circuit unit, an RS485 cascade circuit unit, a load switching circuit unit, and a power supply circuit unit.

[0015] The detonator backplate inspection module is used for inspection and quality control of production backplates.

[0016] Preferably, the RTOS software image consists of two levels of firmware:

[0017] (1) Boot program unit - runs upon power-on, completes minimum initialization of clock / peripherals, application integrity verification and OTA upgrade, and transfers control in a safe jump manner after verification;

[0018] (2) Application Unit – Integrating four collaborative task entities:

[0019] a) The host computer communication task is used to receive and parse the custom instruction set, and trigger local IO (load, buzzer, indicator light) or dispatch asynchronous requests to other tasks according to the instruction code;

[0020] b) Backplane communication task: The test command is forwarded and the response data is collected via a UART link and full-duplex transparent transmission to the backplane under test.

[0021] c) Cascaded bus task, supporting master / slave configurable mode through RS-485 interface, to complete multi-node cascaded communication stress test;

[0022] d) Dynamic task scheduler, based on a priority preemption + time slice round-robin hybrid algorithm, dynamically starts and stops the aforementioned tasks according to the test sequence issued by the host computer, and manages shared resources in a unified manner through mutex semaphores and message queues to ensure zero conflict and zero loss of test actions.

[0023] Preferably, the test backplane MCU module achieves fully automatic adaptation and parallel scheduling through the following steps:

[0024] S1. Test Configuration - After the host computer starts up, it first identifies and binds the target backplane type and automatically loads the corresponding communication protocol stack. The user selects items, execution order, threshold window and hardware parameters as needed in the graphical test unit library (which integrates at least four atomic services: voltage and current acquisition, load switching, serial port pass-through and cascade testing), and generates an extensible marking script with one click.

[0025] S2. Command Issuance—The host computer compiles the script into encrypted command frames and sequentially delivers them to the main MCU via the high-speed bus; the main MCU's built-in protocol parsing task decrypts the frames in real time and maps the commands into several atomic operation commands;

[0026] S3. Dynamic Scheduling - The task scheduler of the main control module is based on a priority-time slice hybrid algorithm to perform zero-blocking dynamic scheduling of operation command sequences, ensuring that multi-channel test actions are executed in parallel strictly in time sequence.

[0027] Preferably, the main control module dynamically schedules the task scheduler operation command sequence sequentially through the following steps:

[0028] a. Call the signal acquisition task to perform multi-channel ADC sampling and process the data using algorithms such as mean filtering;

[0029] b. Invoke the IO control task to drive the load circuit to switch to the specified mode;

[0030] c. Perform functional testing by sending specific protocol frames to the backplane under test via backplane communication task;

[0031] d. Perform configurable cascaded communication tests with the backplane under test via cascade bus tasks in master / slave mode.

[0032] e. Results Summary and Feedback Phase: Each task returns the execution results (raw data, status codes) to the main MCU. The main MCU reports the execution results to the host computer. The host computer analyzes the results according to the custom judgment logic, generates a structured test report (including various data, custom error codes and final conclusions) for display, and sends the test results to the main MCU. The main MCU responds with a buzzer and provides indicator light prompts.

[0033] Preferably, the main control module uses a dynamic task scheduler to perform zero-gap pipeline scheduling on the sequence of operation commands, and the steps are as follows:

[0034] a) Signal acquisition—The scheduler triggers multi-channel ADC tasks and processes the data using algorithms such as mean filtering;

[0035] b) IO control - The IO task is then activated, and the load circuit is switched to the specified operating condition through the MOSFET array without disturbance, driving the load circuit to switch to the specified mode;

[0036] c) Backplane Communication - The scheduler then issues a backplane communication task, which sends a specific protocol frame to the backplane under test for functional testing.

[0037] d) Cascading test – Start cascading bus tasks in parallel or sequentially to complete RS-485 link stress and fault tolerance verification in master / slave configurable roles;

[0038] e) Results Summary - Each task atomically transmits raw data and status codes back, which are then packaged by the main MCU and reported to the host computer at high speed. The host computer generates a structured test report based on the user-defined judgment logic and sends the conclusion frame back. Upon receiving the report, the main MCU immediately drives the buzzer and RGB indicator light to complete a closed-loop feedback using a combination of sound and light.

[0039] Preferably, the backplane voltage and current acquisition circuit unit is responsible for acquiring the power supply, bus communication voltage, and backplane power consumption of the test backplane MCU.

[0040] The RS485 cascade circuit unit is used to perform cascade communication testing between the main MCU and the backplane MCU.

[0041] The load switching circuit unit is used for switching fixed resistors at various levels (255Ω, 1KΩ, 10KΩ), switching between light and heavy loads, and switching between bus short-circuit and open-circuit.

[0042] The power supply circuit unit is used for the main MCU power supply, 2.5V reference power supply, isolation power supply, and backplane MCU power supply.

[0043] Preferably, the detonator backplane detection module includes a semi-finished product detection unit and a finished product detection unit. The semi-finished product detection unit is used to detect the bare PCB of the backplane, mainly detecting the hardware performance of the backplane, such as the power supply and bus communication voltage and current. The finished product detection unit is used to detect the backplane after assembly, mainly detecting the software functions of the backplane, such as serial communication, cascade communication and simulated load communication.

[0044] Preferably, the backplate quality inspection includes the following steps:

[0045] Step 1. Backplane type adaptive recognition - After the host computer is powered on, it automatically enumerates the two topologies of "compatible backplane / group standard backplane" and sends instructions to the main MCU according to the selected type. The main MCU dynamically switches the internal DC-DC converter to output 5V or 8.5V precise power supply, realizing one-click compatibility of JQ and JWT electronic detonator backplanes of the same tooling.

[0046] Step 2. Workstation fingerprint configuration - Enter the workstation number, factory code, product identification number and batch number in the "Workstation Configuration" window of the host computer. The host computer will concatenate the above fields into a unique device number SN according to the established protocol, and write it into the read-only storage area of ​​the backplane MCU in the subsequent test process to complete the solidification of product identity.

[0047] Step 3. Flexible selection of test items - Users can freely select test sub-items through a visual tree menu on the semi-finished or finished website page, and click "Save" to generate an extensible test script immediately;

[0048] Step 4. Online setting of indicator thresholds - Enter the "Test Indicator Configuration" page, enter the upper and lower limits for each sub-item, and at the same time expand the setting of derivative parameters such as delay, number of sampling points, and number of fault tolerance times to realize the standard reuse of the same script for multiple customers;

[0049] Step 5. Link self-test - Select the main MCU serial port of the tool and set the baud rate to 115200bps. Click "Check". The host computer and the main MCU verify each other through handshake frames to ensure zero packet loss in the communication link.

[0050] Step 6. One-click start test and real-time diagnosis - Click "Start". The host computer sends control commands in the order of the script. The RTOS inside the main MCU executes atomic tests such as voltage sampling, load switching, bus cascading, and detonator simulation ignition in a preemptive scheduling manner and sends back the result frame. If a sub-item is abnormal, the host computer will immediately highlight the abnormal code in the corresponding item and output the fault vector in the log window to achieve second-level location.

[0051] Step 7. Batch-level statistics and audio-visual prompts - After all sub-items are completed, the host computer writes the PASS / FAIL result back to the main MCU. The main MCU drives the buzzer to "beep-beep" a number of times and the RGB light color combination to intuitively distinguish between qualified and faulty. At the same time, the interface scrolls and refreshes the cumulative number of tests, the number of qualified tests, and the pass rate to complete the batch-level quality profile.

[0052] Step 8. Report blockchain-based evidence storage – HTML format test report, containing test timestamp, device SN, upper and lower limits of indicators, actual test data and judgment conclusions, and simultaneously archived to the local database and factory MES to achieve full lifecycle traceability.

[0053] Preferably, step 4 further includes the following steps:

[0054] a. Backplane power-on time, and host computer waiting time for communication after backplane power-on;

[0055] b. Backplane voltage adjustment time; the time required for the backplane to adjust the bus voltage. The host computer needs to wait for the backplane voltage adjustment time before reading the bus voltage.

[0056] c. APP jump time: Since the backplane has two applications, JQ and JWT, the initialization time after each application jump is inconsistent when the host computer switches between backplane applications. After switching applications, the host computer needs to wait for the jump time before starting communication.

[0057] Preferably, step 4 further includes the following steps:

[0058] d. Short-circuit stress test time. This parameter is applicable to bus short-circuit testing, i.e., bus short-circuit holding time, which mainly verifies the backplane bus short-circuit protection function.

[0059] e. Number of cascading tests: This parameter is used for cascading communication tests and can be configured according to requirements.

[0060] f.EW software version, JQ software version, hardware version; this parameter configures the software and hardware version indicators of the backplane for this test.

[0061] The beneficial effects of this invention are as follows:

[0062] 1. The host computer-based automated backplane testing system of the present invention, through "software-defined testing" and by customizing the test process through the host computer, completely changes the firmware function solidification mode, enabling the test fixture to quickly adapt to new products and new testing requirements, greatly improving flexibility and versatility, and realizing "develop once, adapt multiple times". At the same time, the test backplane type can be customized by the host computer to generate test instruction sets and send them to the main control module in sequence. The main control module dynamically schedules and executes operation instructions and feeds back data. This method solves the "one machine, one use" solidification mode of traditional fixtures, realizes the hardware performance and software function testing of multiple types of backplanes, and greatly improves the testing flexibility.

[0063] 2. The host computer-based backplane automated testing system described in this invention improves the level of testing automation and intelligence. Based on the multi-task collaboration and dynamic scheduling mechanism of RTOS, it can automatically and reliably execute complex test sequences, reduce manual intervention, and improve testing efficiency and consistency. Moreover, by running software based on the RTOS real-time operating system through the main control module, it creates host computer communication tasks, backplane communication tasks, and cascaded bus communication tasks. It realizes the interaction of instructions and data between tasks through communication mechanisms such as mailboxes, and can support multiple types of backplane protocols, improving compatibility. Attached Figure Description

[0064] The invention will now be further described with reference to the accompanying drawings.

[0065] Figure 1 This is a schematic diagram of the system framework of the present invention;

[0066] Figure 2 This is a schematic diagram of the main MCU software system architecture in this invention;

[0067] Figure 3 This is a schematic diagram of the backplane voltage and current acquisition circuit in this invention;

[0068] Figure 4 This is a schematic diagram of the RS485 cascade circuit in this invention;

[0069] Figure 5 This is a schematic diagram of the load switching circuit in this invention;

[0070] Figure 6This is a schematic diagram of the load switching circuit in this invention;

[0071] Figure 7 This is a schematic diagram of the main MCU power supply circuit in this invention;

[0072] Figure 8 This is a schematic diagram illustrating the detailed description of the test items in this invention. Detailed Implementation

[0073] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0074] like Figures 1 to 8 As shown, an embodiment of the present invention provides an automated testing system for host computer backplanes, comprising:

[0075] The host computer module is used to customize test items, arrange test sequences, set test parameters and judgment rules, send configuration information to the main MCU in sequence, and provide a graphical test configuration interface.

[0076] Main MCU module: used for core scheduler test execution, running real-time operating system (RTOS) software;

[0077] Test load module: used for two-bus connection between the main MCU and the test backplane MCU. Through the load switching circuit of the main MCU, it can switch between multiple modes such as open circuit, short circuit, fixed resistor, and simulated detonator load according to the instructions of the host computer.

[0078] Test backplane MCU module: used to receive test commands from the main MCU;

[0079] The system's main MCU hardware module is used to test the power supply of the backplane MCU and the cascaded communication between the main MCU and the backplane MCU.

[0080] The main MCU hardware module of the system consists of a backplane voltage and current acquisition circuit unit, an RS485 cascade circuit unit, a load switching circuit unit, and a power supply circuit unit.

[0081] The detonator backplate inspection module is used for inspection and quality control of production backplates.

[0082] like Figures 1 to 8 As shown, the RTOS software image consists of two levels of firmware:

[0083] (1) Boot program unit - runs upon power-on, completes minimum initialization of clock / peripherals, application integrity verification and OTA upgrade, and transfers control in a safe jump manner after verification;

[0084] (2) Application Unit – Integrating four collaborative task entities:

[0085] a) The host computer communication task is used to receive and parse the custom instruction set, and trigger local IO (load, buzzer, indicator light) or dispatch asynchronous requests to other tasks according to the instruction code;

[0086] b) Backplane communication task: The test command is forwarded and the response data is collected via a UART link and full-duplex transparent transmission to the backplane under test.

[0087] c) Cascaded bus task, supporting master / slave configurable mode through RS-485 interface, to complete multi-node cascaded communication stress test;

[0088] d) Dynamic task scheduler, based on a priority preemption + time slice round-robin hybrid algorithm, dynamically starts and stops the aforementioned tasks according to the test sequence issued by the host computer, and manages shared resources in a unified manner through mutex semaphores and message queues to ensure zero conflict and zero loss of test actions.

[0089] like Figures 1 to 8 As shown, the test backplane MCU module achieves fully automatic adaptation and parallel scheduling through the following steps:

[0090] S1. Test Configuration - After the host computer starts up, it first identifies and binds the target backplane type and automatically loads the corresponding communication protocol stack. The user selects items, execution order, threshold window and hardware parameters as needed in the graphical test unit library (which integrates at least four atomic services: voltage and current acquisition, load switching, serial port pass-through and cascade testing), and generates an extensible marking script with one click.

[0091] S2. Command Issuance—The host computer compiles the script into encrypted command frames and sequentially delivers them to the main MCU via the high-speed bus; the main MCU's built-in protocol parsing task decrypts the frames in real time and maps the commands into several atomic operation commands;

[0092] S3. Dynamic Scheduling - The task scheduler of the main control module is based on a priority-time slice hybrid algorithm to perform zero-blocking dynamic scheduling of the operation command sequence, ensuring that multi-channel test actions are strictly executed in parallel according to the time sequence.

[0093] The main control module dynamically schedules the task scheduler operation command sequence sequentially through the following steps:

[0094] a. Call the signal acquisition task to perform multi-channel ADC sampling and process the data using algorithms such as mean filtering;

[0095] b. Invoke the IO control task to drive the load circuit to switch to the specified mode;

[0096] c. Perform functional testing by sending specific protocol frames to the backplane under test via backplane communication task;

[0097] d. Perform configurable cascaded communication tests with the backplane under test via cascade bus tasks in master / slave mode.

[0098] e. Results summary and feedback stage: Each task returns the execution results (raw data, status codes) to the main MCU. The main MCU reports the execution results to the host computer. The host computer analyzes the results according to the custom judgment logic, generates a structured test report (including various data, custom error codes and final conclusions) for display, and sends the test results to the main MCU. The main MCU responds with a buzzer and provides indicator light prompts.

[0099] The main control module uses a dynamic task scheduler to perform zero-gap pipeline scheduling on the sequence of operation commands. The steps are as follows:

[0100] a) Signal acquisition—The scheduler triggers multi-channel ADC tasks and processes the data using algorithms such as mean filtering;

[0101] b) IO control - The IO task is then activated, and the load circuit is switched to the specified operating condition through the MOSFET array without disturbance, driving the load circuit to switch to the specified mode;

[0102] c) Backplane Communication - The scheduler then issues a backplane communication task, which sends a specific protocol frame to the backplane under test for functional testing.

[0103] d) Cascading test – Start cascading bus tasks in parallel or sequentially to complete RS-485 link stress and fault tolerance verification in master / slave configurable roles;

[0104] e) Results Summary - Each task atomically transmits raw data and status codes back, which are then packaged by the main MCU and reported to the host computer at high speed. The host computer generates a structured test report based on the user-defined judgment logic and sends the conclusion frame back. Upon receiving the report, the main MCU immediately drives the buzzer and RGB indicator light to complete a closed-loop feedback using a combination of sound and light.

[0105] like Figures 1 to 8 As shown, the backplane voltage and current acquisition circuit unit is responsible for acquiring the power supply, bus communication voltage, and power consumption of the backplane MCU.

[0106] The RS485 cascade circuit unit is used to perform cascade communication testing between the main MCU and the backplane MCU.

[0107] The load switching circuit unit is used for switching fixed resistors at various levels (255Ω, 1KΩ, 10KΩ), switching between light and heavy loads, and switching between bus short-circuit and open-circuit.

[0108] The power supply circuit unit is used for the main MCU power supply, 2.5V reference power supply, isolation power supply, and backplane MCU power supply.

[0109] like Figures 1 to 8 As shown, the detonator backplane detection module includes a semi-finished product detection unit and a finished product detection unit. The semi-finished product detection unit is used to detect the bare PCB of the backplane, mainly detecting the hardware performance of the backplane, such as the power supply and bus communication voltage and current. The finished product detection unit is used to detect the backplane after assembly, mainly detecting the software functions of the backplane, such as serial communication, cascade communication and simulated load communication.

[0110] like Figures 1 to 8 As shown, the back panel quality inspection includes the following steps:

[0111] Step 1. Backplane type adaptive recognition - After the host computer is powered on, it automatically enumerates the two topologies of "compatible backplane / group standard backplane" and sends instructions to the main MCU according to the selected type. The main MCU dynamically switches the internal DC-DC converter to output 5V or 8.5V precise power supply, realizing one-click compatibility of JQ and JWT electronic detonator backplanes of the same tooling.

[0112] Step 2. Workstation fingerprint configuration - Enter the workstation number, factory code, product identification number and batch number in the "Workstation Configuration" window of the host computer. The host computer will concatenate the above fields into a unique device number SN according to the established protocol, and write it into the read-only storage area of ​​the backplane MCU in the subsequent test process to complete the solidification of product identity.

[0113] Step 3. Flexible selection of test items - Users can freely select test sub-items through a visual tree menu on the semi-finished or finished website page, and click "Save" to generate an extensible test script immediately;

[0114] Step 4. Online setting of indicator thresholds - Enter the "Test Indicator Configuration" page, enter the upper and lower limits for each sub-item, and at the same time expand the setting of derivative parameters such as delay, number of sampling points, and number of fault tolerance times to realize the standard reuse of the same script for multiple customers;

[0115] Step 5. Link self-test - Select the main MCU serial port of the tool and set the baud rate to 115200bps. Click "Check". The host computer and the main MCU verify each other through handshake frames to ensure zero packet loss in the communication link.

[0116] Step 6. One-click start test and real-time diagnosis - Click "Start". The host computer sends control commands in the order of the script. The RTOS inside the main MCU executes atomic tests such as voltage sampling, load switching, bus cascading, and detonator simulation ignition in a preemptive scheduling manner and sends back the result frame. If a sub-item is abnormal, the host computer will immediately highlight the abnormal code in the corresponding item and output the fault vector in the log window to achieve second-level location.

[0117] Step 7. Batch-level statistics and audio-visual prompts - After all sub-items are completed, the host computer writes the PASS / FAIL result back to the main MCU. The main MCU drives the buzzer to "beep-beep" a number of times and the RGB light color combination to intuitively distinguish between qualified and faulty. At the same time, the interface scrolls and refreshes the cumulative number of tests, the number of qualified tests, and the pass rate to complete the batch-level quality profile.

[0118] Step 8. Report blockchain-based evidence storage – HTML format test report, containing test timestamp, device SN, upper and lower limits of indicators, actual test data and judgment conclusions, and simultaneously archived to the local database and factory MES to achieve full lifecycle traceability.

[0119] Step 4 also includes the following steps:

[0120] a. Backplane power-on time, and host computer waiting time for communication after backplane power-on;

[0121] b. Backplane voltage adjustment time; the time required for the backplane to adjust the bus voltage. The host computer needs to wait for the backplane voltage adjustment time before reading the bus voltage.

[0122] c. APP jump time: Since the backplane has two applications, JQ and JWT, the initialization time after each application jump is inconsistent when the host computer switches between backplane applications. After switching applications, the host computer needs to wait for the jump time before starting communication.

[0123] Step 4 also includes the following steps:

[0124] d. Short-circuit stress test time. This parameter is applicable to bus short-circuit testing, i.e., bus short-circuit holding time, which mainly verifies the backplane bus short-circuit protection function.

[0125] e. Number of cascading tests: This parameter is used for cascading communication tests and can be configured according to requirements.

[0126] f.EW software version, JQ software version, hardware version; this parameter configures the software and hardware version indicators of the backplane for this test.

[0127] Working principle: Through "software-defined testing," the test process is customized via a host computer, completely changing the firmware function fixation mode. This allows the test fixture to quickly adapt to new products and new testing requirements, greatly improving flexibility and versatility, and achieving "develop once, adapt multiple times." At the same time, the test backplane type can be customized through the host computer to generate test instruction sets, which are then sent to the main control module. The main control module dynamically schedules and executes the operation instructions and feeds back data. This method solves the traditional "one machine, one use" fixation mode of the fixture, enabling hardware performance and software function testing of various types of backplanes, greatly improving testing flexibility.

[0128] To improve the level of test automation and intelligence, the multi-task collaboration and dynamic scheduling mechanism based on RTOS can automatically and reliably execute complex test sequences, reduce manual intervention, and improve test efficiency and consistency. Moreover, by running software based on the RTOS real-time operating system through the main control module, it can create host computer communication tasks, backplane communication tasks, and cascade bus communication tasks, and realize the interaction of instructions and data between tasks through communication mechanisms such as mailboxes. It can also support multiple types of backplane protocols, improving compatibility.

[0129] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. An automated testing system based on a host computer backplane, characterized in that: include: The host computer module is used to customize test items, arrange test sequences, set test parameters and judgment rules, send configuration information to the main MCU in sequence, and provide a graphical test configuration interface. Main MCU module: used for core scheduler test execution, running real-time operating system (RTOS) software; Test load module: used for two-bus connection between the main MCU and the test backplane MCU. Through the load switching circuit of the main MCU, it can switch between multiple modes such as open circuit, short circuit, fixed resistor, and simulated detonator load according to the instructions of the host computer. Test backplane MCU module: used to receive test commands from the main MCU; The system's main MCU hardware module is used to test the power supply of the backplane MCU and the cascaded communication between the main MCU and the backplane MCU. The main MCU hardware module of the system consists of a backplane voltage and current acquisition circuit unit, an RS485 cascade circuit unit, a load switching circuit unit, and a power supply circuit unit. The detonator backplate inspection module is used for inspection and quality control of production backplates.

2. The automated testing system based on a host computer backplane according to claim 1, characterized in that: The RTOS software image consists of two levels of firmware: (1) Boot program unit - runs upon power-on, completes minimum initialization of clock / peripherals, application integrity verification and OTA upgrade, and transfers control in a safe jump manner after verification; (2) Application Unit – Integrating four collaborative task entities: a) The host computer communication task is used to receive and parse the custom instruction set, and trigger local IO (load, buzzer, indicator light) or dispatch asynchronous requests to other tasks according to the instruction code; b) Backplane communication task: The test command is forwarded and the response data is collected via a UART link and full-duplex transparent transmission to the backplane under test. c) Cascaded bus task, supporting master / slave configurable mode through RS-485 interface, to complete multi-node cascaded communication stress test; d) Dynamic task scheduler, based on a priority preemption + time slice round-robin hybrid algorithm, dynamically starts and stops the aforementioned tasks according to the test sequence issued by the host computer, and manages shared resources in a unified manner through mutex semaphores and message queues to ensure zero conflict and zero loss of test actions.

3. The automated testing system based on a host computer backplane according to claim 1, characterized in that: The test backplane MCU module achieves fully automatic adaptation and parallel scheduling through the following steps: S1. Test Configuration - After the host computer starts up, it first identifies and binds the target backplane type and automatically loads the corresponding communication protocol stack. The user selects items, execution order, threshold window and hardware parameters as needed in the graphical test unit library (which integrates at least four atomic services: voltage and current acquisition, load switching, serial port pass-through and cascade testing), and generates an extensible marking script with one click. S2. Command Issuance—The host computer compiles the script into encrypted command frames and sequentially delivers them to the main MCU via the high-speed bus; the main MCU's built-in protocol parsing task decrypts the frames in real time and maps the commands into several atomic operation commands; S3. Dynamic Scheduling - The task scheduler of the main control module is based on a priority-time slice hybrid algorithm to perform zero-blocking dynamic scheduling of operation command sequences, ensuring that multi-channel test actions are executed in parallel strictly in time sequence.

4. The automated testing system based on a host computer backplane according to claim 3, characterized in that: The main control module dynamically schedules the task scheduler operation command sequence sequentially through the following steps: a. Call the signal acquisition task to perform multi-channel ADC sampling and process the data using algorithms such as mean filtering; b. Invoke the IO control task to drive the load circuit to switch to the specified mode; c. Perform functional testing by sending specific protocol frames to the backplane under test via backplane communication task; d. Perform configurable cascaded communication tests with the backplane under test via cascaded bus tasks in master / slave mode; e. Results Summary and Feedback Phase: Each task returns the execution results (raw data, status codes) to the main MCU. The main MCU reports the execution results to the host computer. The host computer analyzes the results according to the custom judgment logic, generates a structured test report (including various data, custom error codes and final conclusions) for display, and sends the test results to the main MCU. The main MCU responds with a buzzer and provides indicator light prompts.

5. The automated testing system based on a host computer backplane according to claim 3, characterized in that: The main control module uses a dynamic task scheduler to perform zero-gap pipeline scheduling on the sequence of operation commands. The steps are as follows: a) Signal acquisition—The scheduler triggers multi-channel ADC tasks and processes the data using algorithms such as mean filtering; b) IO control - The IO task is then activated, and the load circuit is switched to the specified operating condition through the MOSFET array without disturbance, driving the load circuit to switch to the specified mode; c) Backplane Communication - The scheduler then issues a backplane communication task, which sends a specific protocol frame to the backplane under test for functional testing. d) Cascading test – Start cascading bus tasks in parallel or sequentially to complete RS-485 link stress and fault tolerance verification in master / slave configurable roles; e) Results Summary - Each task atomically transmits raw data and status codes back, which are then packaged by the main MCU and reported to the host computer at high speed. The host computer generates a structured test report based on the user-defined judgment logic and sends the conclusion frame back. Upon receiving the report, the main MCU immediately drives the buzzer and RGB indicator light to complete a closed-loop feedback using a combination of sound and light.

6. The automated testing system based on a host computer backplane according to claim 1, characterized in that: The backplane voltage and current acquisition circuit unit is responsible for acquiring the power supply, bus communication voltage, and power consumption of the backplane MCU. The RS485 cascade circuit unit is used to perform cascade communication testing between the main MCU and the backplane MCU. The load switching circuit unit is used for switching fixed resistors at various levels (255Ω, 1KΩ, 10KΩ), switching between light and heavy loads, and switching between bus short-circuit and open-circuit. The power supply circuit unit is used for the main MCU power supply, 2.5V reference power supply, isolation power supply, and backplane MCU power supply.

7. The automated testing system based on a host computer backplane according to claim 1, characterized in that: The detonator backplane detection module includes a semi-finished product detection unit and a finished product detection unit. The semi-finished product detection unit is used to detect the bare PCB of the backplane, mainly detecting the hardware performance of the backplane, such as the power supply and bus communication voltage and current. The finished product detection unit is used to detect the backplane after assembly, mainly detecting the software functions of the backplane, such as serial communication, cascade communication and simulated load communication.

8. The automated testing system based on a host computer backplane according to claim 1, characterized in that: The backplate quality inspection includes the following steps: Step 1. Backplane type adaptive recognition - After the host computer is powered on, it automatically enumerates the two topologies "compatible backplane / group standard backplane" and sends instructions to the main MCU according to the selected type. The main MCU dynamically switches the internal DC-DC converter to output 5V or 8.5V precise power supply, realizing one-click compatibility of JQ and JWT electronic detonator backplanes of the same tooling. Step 2. Workstation fingerprint configuration - Enter the workstation number, factory code, product identification number and batch number in the "Workstation Configuration" window of the host computer. The host computer will concatenate the above fields into a unique device number SN according to the established protocol, and write it into the read-only storage area of ​​the backplane MCU in the subsequent test process to complete the solidification of product identity. Step 3. Flexible selection of test items - Users can freely select test sub-items through a visual tree menu on the semi-finished or finished website page, and click "Save" to generate an extensible test script immediately; Step 4. Online setting of indicator thresholds - Enter the "Test Indicator Configuration" page, enter the upper and lower limits for each sub-item, and at the same time expand the setting of derivative parameters such as delay, number of sampling points, and number of fault tolerance times to realize the standard reuse of the same script for multiple customers; Step 5. Link self-test - Select the main MCU serial port of the tool and set the baud rate to 115200bps. Click "Check". The host computer and the main MCU verify each other through handshake frames to ensure zero packet loss in the communication link. Step 6. One-click start test and real-time diagnosis - Click "Start". The host computer sends control commands in the order of the script. The main MCU's internal RTOS executes atomic tests such as voltage sampling, load switching, bus cascading, and detonator simulation ignition in a preemptive scheduling manner and sends back the result frame. If a sub-item is abnormal, the host computer will immediately highlight the abnormal code in the corresponding item and output the fault vector in the log window to achieve second-level location; Step 7. Batch-level statistics and audio-visual prompts - After all sub-items are completed, the host computer writes the PASS / FAIL result back to the main MCU. The main MCU drives the buzzer to "beep-beep" a number of times and the RGB light color combination to intuitively distinguish between qualified and faulty. At the same time, the interface scrolls and refreshes the cumulative number of tests, the number of qualified tests, and the pass rate to complete the batch-level quality profile. Step 8. Report blockchain-based evidence storage – HTML format test report, containing test timestamp, device SN, upper and lower limits of indicators, actual test data and judgment conclusions, and simultaneously archived to the local database and factory MES to achieve full lifecycle traceability.

9. The automated testing system based on a host computer backplane according to claim 8, characterized in that: Step 4 also includes the following steps: a. Backplane power-on time, and host computer waiting time for communication after backplane power-on; b. Backplane voltage adjustment time; the time required for the backplane to adjust the bus voltage. The host computer needs to wait for the backplane voltage adjustment time before reading the bus voltage. c. APP jump time: Since the backplane has two applications, JQ and JWT, the initialization time after each application jump is inconsistent when the host computer switches between backplane applications. After switching applications, the host computer needs to wait for the jump time before starting communication.

10. The automated testing system based on a host computer backplane according to claim 9, characterized in that: Step 4 also includes the following steps: d. Short-circuit stress test time. This parameter is applicable to bus short-circuit testing, i.e., bus short-circuit holding time, which mainly verifies the backplane bus short-circuit protection function. e. Number of cascading tests: This parameter is used for cascading communication tests and can be configured according to requirements. f.EW software version, JQ software version, hardware version; this parameter configures the software and hardware version indicators of the backplane for this test.

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