Data processing method, electronic equipment, storage medium and photoetching equipment

Abstract

The embodiment of the invention relates to a data processing method, electronic equipment, a storage medium and photoetching equipment. The data processing method comprises the steps that for each block of a target layout, defect values of defect points in each block are sequenced according to defect types, so that sequenced defect data of each block are obtained, and the defect values indicate the severity of defects; grouping the sorted defect data of each block based on a pattern corresponding to the defect points in each block to obtain a plurality of grouped defect data of each block; filtering the plurality of grouped defect data of each block to obtain filtered defect data of each block; and obtaining full layout defect data of the target layout based on the filtered defect data. According to the embodiment of the invention, on the premise of ensuring the analysis precision, the memory and the calculation time required by full-chip defect grouping can be greatly reduced.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of chips, and more specifically, to data processing methods, electronic devices, storage media, and photolithography equipment. Background Technology

[0002] In advanced chip manufacturing, when the critical dimension (CD) of a circuit pattern is significantly smaller than the wavelength of the exposure light source, the actual pattern formed on the photoresist will be severely distorted relative to the mask design due to light diffraction and interference effects. To compensate for this optical proximity effect, optical proximity correction (OPC) technology is used. This involves reverse geometric correction (i.e., pre-distortion) of the mask pattern to make the silicon wafer imaging result as close as possible to the target pattern.

[0003] The OPC process typically involves iterative simulation and verification: in each iteration, defect patterns are identified by comparing the silicon wafer imaging simulation results with the target pattern, and the OPC model parameters (recipe) are adjusted accordingly. However, in the initial OPC debugging phase, due to suboptimal parameters, hundreds of millions to billions of defect data points are often generated across the entire chip. Faced with such massive amounts of defect data, engineers struggle to quickly pinpoint the key patterns causing OPC failure and their root causes. Summary of the Invention

[0004] According to exemplary embodiments of this disclosure, a data processing method, an electronic device, a storage medium, and a lithography apparatus are provided to at least partially solve the above-mentioned or other potential technical problems.

[0005] In a first aspect of this disclosure, a data processing method is provided. The method includes: for each block of a target layout, sorting the defect values ​​of defect points within each block according to defect type to obtain sorted defect data for each block, wherein the defect values ​​indicate the severity of the defect; grouping the sorted defect data for each block based on patterns corresponding to the defect points within each block to obtain multiple groups of defect data for each block; filtering the multiple groups of defect data for each block to obtain filtered defect data for each block; and obtaining full-layout defect data for the target layout based on the filtered defect data. Embodiments of this disclosure, by independently and in parallel performing the sorting, grouping, and filtering of defect data within each block of the target layout, can significantly reduce the memory and computation time required for full-layout defect grouping while maintaining analytical accuracy.

[0006] In a second aspect of this disclosure, an electronic device is provided. The electronic device includes a processor and a memory coupled to the processor, the memory having instructions stored therein, the instructions causing the device to perform actions when executed by the processor. The actions include: for each block of a target layout, sorting defect values ​​of defect points within each block according to defect type to obtain sorted defect data for each block, wherein the defect values ​​indicate the severity of the defect; grouping the sorted defect data for each block based on patterns corresponding to the defect points within each block to obtain multiple groups of defect data for each block; filtering the multiple groups of defect data for each block to obtain filtered defect data for each block; and obtaining full-layout defect data of the target layout based on the filtered defect data.

[0007] In some embodiments of this disclosure, filtering multiple group defect data for each block may include: filtering multiple group defect data for each block except for the predetermined number of group defect data based on a predetermined number of group defect data, so as to obtain a predetermined number of group defect data for each block.

[0008] In some embodiments of this disclosure, filtering multiple grouped defect data for each block may further include: filtering defect data in the grouped defect data of each block based on a predetermined number of retained defect points for each group to obtain filtered defect data for each block.

[0009] In some embodiments of this disclosure, the predetermined number of groups may be determined based on any of the following: one or more defect types of concern selected from all defect types; the top N defect types ranked first (e.g., most concerned) based on the statistical ranking order of historical analysis records, where N is a natural number; and the top K most important defect types obtained according to a preset defect type priority rule, where K is a natural number.

[0010] In some embodiments of this disclosure, the pattern corresponding to the defect point within each block can be generated by cutting each block according to a set window size based on the coordinates of each defect point.

[0011] In some embodiments of this disclosure, grouping the sorted defect data for each block may include: extracting information of the graphic within the pattern corresponding to each sorted defect point in each block as a feature of the pattern; and performing similarity matching on the features of the pattern corresponding to each sorted defect point in each block based on predetermined matching parameters, so as to obtain multiple sets of patterns for each block corresponding to multiple groups of defect data in each block.

[0012] In some embodiments of this disclosure, the information of the graphic within the pattern corresponding to each sorted defect point within each block may include one or more of the following: the width of the graphic within the pattern, the height of the graphic within the pattern, the spacing between the graphics within the pattern, and the proportion of the area of ​​the graphic to the area of ​​the pattern.

[0013] In some embodiments of this disclosure, grouping the sorted defect data for each block may further include: selecting the pattern corresponding to the first defect point in each of the multiple patterns in each block as the feature pattern of each pattern group, so as to merge the defect data of different blocks of the target layout.

[0014] In some embodiments of this disclosure, the defect type may include at least one of the following: bridging risk, open circuit risk, insufficient linewidth, excessive linewidth, spacing violation, insufficient via coverage, and antenna effect violation.

[0015] In some embodiments of this disclosure, the defect data of the defect points within each block may include at least one of the following: coordinates, type, defect value, and simulation parameters.

[0016] In some embodiments of this disclosure, obtaining full-map defect data of a target layout based on filtered defect data may include: merging filtered defect data of different blocks of the target layout based on the similarity of feature patterns of different groups of different blocks, to obtain multiple merged grouped defect data; and filtering the merged grouped defect data to obtain filtered defect data.

[0017] In some embodiments of this disclosure, filtering the merged multiple group defect data may include: filtering the group defect data of the target layout other than the predetermined number of groups based on a predetermined number of groups, so as to obtain filtered group defect data.

[0018] In some embodiments of this disclosure, filtering the merged grouped defect data may further include: filtering the defect data in the grouped defect data of the target layout based on a predetermined number of retained defect points for each group, so as to obtain the final defect data of the target layout.

[0019] In a third aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the method according to a first aspect of this disclosure.

[0020] In a fourth aspect of this disclosure, a photolithography apparatus is provided, which includes electronic equipment according to a second aspect of this disclosure.

[0021] The solution of this disclosure can significantly reduce the memory, computing time and computing resources required for full chip layout defect grouping while ensuring analysis accuracy. It realizes efficient, feasible and scalable intelligent analysis of defect data of large-scale chips or even very large-scale chips, and lays a data foundation for quickly locating the root cause of OPC failure.

[0022] It should be understood that the description in the Summary of the Invention section is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0023] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0024] Figure 1 A schematic diagram of an example environment in which embodiments of the present disclosure can be implemented is shown;

[0025] Figure 2 A flowchart of a data processing method according to an embodiment of the present disclosure is shown;

[0026] Figure 3 A schematic diagram illustrating full-layout defect data processing according to an embodiment of the present disclosure is shown;

[0027] Figure 4 A schematic diagram of a data filter module according to an embodiment of the present disclosure is shown; and

[0028] Figure 5 A block diagram of a computing device capable of implementing embodiments of the present disclosure is shown. Detailed Implementation

[0029] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0030] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0031] As mentioned earlier, during the initial OPC debugging phase, due to suboptimal parameters, hundreds of millions to billions of defect data points are often generated across the entire chip. Faced with such a massive amount of defect data, engineers find it difficult to quickly locate the key patterns causing OPC failures and their root causes.

[0032] To address this challenge, defect data needs to be categorized and grouped so that engineers can solve the common problems represented by the entire group of defects by analyzing only one or a few representative samples from each group.

[0033] Traditional methods involve cutting out the layout of the deviation area across the entire chip, extracting the local patterns around the defect points, and performing similarity grouping. This allows engineers to determine the type of the entire group of defects by analyzing representative patterns. However, as chip complexity increases, this traditional method of grouping directly at the entire chip level faces significant computational challenges: it consumes enormous computational resources, requiring substantial memory and computation time for the grouping process.

[0034] Existing OPC software correction processes are mostly based on tile processing. This involves dividing the entire chip layout into multiple smaller, manageable tiles (usually rectangular tiles), processing these tiles in parallel, calculating defects for each tile separately, and finally integrating the defect data from all tiles and grouping them based on the similarity of patterns near the defects. This approach has the following problems:

[0035] (1) Low computational efficiency: The traditional method of directly grouping similarity data at the whole chip level requires processing hundreds of millions or even billions of defect data, resulting in excessively long computation time.

[0036] (2) High memory consumption: Similarity grouping across the entire chip requires processing massive amounts of pattern data simultaneously, placing extremely high demands on computer memory resources. Especially when dealing with modern large-scale chip designs, insufficient memory often leads to processing interruptions or necessitates reliance on distributed computing systems, increasing hardware costs and system complexity.

[0037] (3) Low grouping quality: In the similarity grouping method across the entire chip, due to the limitation of computing resources, a relatively loose similarity threshold is often required, which leads to a decrease in grouping accuracy.

[0038] In view of this, this disclosure provides an improved solution.

[0039] According to one embodiment of this disclosure, a data processing method is provided. The data processing method includes: for each block of a target layout, sorting the defect values ​​of defect points within each block according to defect type to obtain sorted defect data for each block, wherein the defect values ​​indicate the severity of the defect; grouping the sorted defect data for each block based on patterns corresponding to the defect points within each block to obtain multiple grouped defect data for each block; filtering the multiple grouped defect data for each block to obtain filtered defect data for each block; and obtaining full-layout defect data of the target layout based on the filtered defect data.

[0040] In some embodiments of this disclosure, the target layout may include a chip layout. In some embodiments of this disclosure, the target layout may be referred to as a full layout or a full chip layout.

[0041] In some embodiments of this disclosure, obtaining full-layout defect data of a target layout based on filtered defect data may include: obtaining full-layout defect data of the target layout based on filtered defect data of all blocks or a portion of the target layout. In some embodiments of this disclosure, the full-layout defect data of the target layout obtained based on filtered defect data of all blocks of the target layout may be referred to as full-chip defect data. In other embodiments of this disclosure, the full-layout defect data of the target layout obtained based on filtered defect data of a portion of the target layout may also be referred to as full-chip defect data. It should be understood that, in this disclosure, the full-layout defect data or full-chip defect data may refer to the full-layout defect data of the target layout obtained based on filtered defect data of all blocks or a portion of the target layout.

[0042] In some embodiments of this disclosure, the defect data obtained after processing the full-map defect data of the target map (e.g., directly filtering the full-map defect data, or grouping and filtering the full-map defect data first, etc.) can be referred to as the final defect data of the full map.

[0043] Unlike traditional methods that directly group massive amounts of raw defect data at the whole-chip level, some embodiments of this disclosure decompose the whole-chip defect analysis task into two levels (i.e., intra-block level and whole-chip level). By independently and in parallel completing the sorting, grouping and filtering of defect data within each block, it is possible to significantly reduce the memory and computation time required for whole-chip defect grouping while ensuring analysis accuracy.

[0044] Specifically, according to some embodiments of this disclosure, defect points within each block are first sorted by defect value (which indicates the severity of the defect). This ensures that subsequent grouping and filtering prioritize the most severe problems and provides local continuity of the data, improving the efficiency and effectiveness of the grouping algorithm. Next, within each block, the sorted defect data is grouped based on a pattern corresponding to the defect points within that block. The resulting multiple grouped defect data for each block are then filtered, thereby aggregating and simplifying massive amounts of atomic defect points into a much smaller number of representative, filtered defect data points.

[0045] According to some embodiments of the data processing method disclosed herein, since the most memory-intensive grouping operation (e.g., similarity grouping) is performed independently within each block, the simulation system (e.g., OPC system) only needs to allocate the memory required for grouping for the data of a single block, without having to load all billions of defect data from the entire chip into memory at the same time. Therefore, it fundamentally overcomes one or more of the problems faced by traditional methods that perform grouping at the entire chip level, such as low computational efficiency, large memory consumption, long grouping time, and poor grouping quality due to limitations in computing resources.

[0046] Embodiments of this disclosure will now be described in detail by way of example with reference to the accompanying drawings.

[0047] First refer to Figure 1 This illustrates a schematic diagram of an example environment 100 in which various embodiments of the present disclosure can be implemented. For example... Figure 1 As shown, the example environment 100 includes a processing device 110 and a client 120.

[0048] In some embodiments of this disclosure, the processing device 110 can interact with the client 120. For example, the processing device 110 can receive input information from the client 120 and output feedback information to the client 120. In some embodiments of this disclosure, the input information from the client 120 may include the defect type of defects in the layout, the predetermined number of groups for sorted defects, the number of retained defect points in each group, etc. In some embodiments of this disclosure, the processing device 110 can process the defect data of the entire chip layout according to the input information and output the processing result to the client 120.

[0049] It should be noted that, in the embodiments of this disclosure, the processing of defect data for the entire chip layout includes the following two levels (i.e., intra-block level and full-chip layout level) of processing, and the intra-block level processing and the full-chip layout level processing are executed sequentially.

[0050] In this disclosure, intra-block level processing refers to the processing of defect data within each block of the entire chip layout. In some embodiments of this disclosure, the processing of intra-block defect data may be referred to as intra-block defect data processing.

[0051] In this disclosure, processing at the whole-chip layout level refers to the processing of defect data between individual blocks of the whole-chip layout. In some embodiments of this disclosure, the processing of defect data at the whole-chip layout level may be referred to as whole-chip layout defect data processing.

[0052] In some embodiments of this disclosure, the processing results may include a full-map defect report, a full-map defect data list, etc.

[0053] In some embodiments of this disclosure, the processing result may include at least one of the following: grouped defect data obtained by grouping defect data of each block, grouped defect data of a predetermined number of groups obtained by truncating defect data of each block within groups, filtered defect data obtained by filtering defect data of each block within defect data, grouped defect data obtained by grouping defect data of the entire chip, grouped defect data of a predetermined number of groups obtained by truncating grouped defect data of the entire chip, filtered defect data obtained by filtering grouped defect data of the entire chip, and final defect data of the entire chip obtained by truncating and filtering grouped defect data of the entire chip.

[0054] In some embodiments of this disclosure, "layout" refers to the layout of a chip. In some embodiments of this disclosure, "layout" and "chip" can be used interchangeably. In some embodiments of this disclosure, the chip may include chips applicable to various scenarios, including but not limited to chips applicable to automotive electronics or aerospace, chips applicable to consumer electronic devices (e.g., mobile phones, etc.).

[0055] In some embodiments of this disclosure, the processing device 110 may include, but is not limited to, personal computers, server computers, handheld or laptop devices, mobile devices (such as mobile phones, personal digital assistants (PDAs), media players, etc.), consumer electronics, minicomputers, mainframe computers, cloud computing resources, etc.

[0056] It should be understood that the description of the structure and functionality of example environment 100 for illustrative purposes only is not intended to limit the scope of the topics described herein. The topics described herein may be implemented in different structures and / or functionalities.

[0057] The technical solutions described above are for illustrative purposes only and are not intended to limit this disclosure. It should be understood that the example environment 100 can also have many other implementation methods. To more clearly explain the principles of the solutions disclosed herein, reference will be made below. Figure 2 and Figure 3 Let me describe it in more detail.

[0058] The following is for reference. Figure 2 , Figure 2 A flowchart of a data processing method 200 according to an embodiment of the present disclosure is shown.

[0059] In some embodiments of this disclosure, Figure 2 The data processing method 200 shown can be executed by a simulation tool. In some embodiments of this disclosure, the simulation tool may include simulation software or a simulation program. As an example, the simulation tool may be OPC software. In some embodiments of this disclosure, the OPC software may include Synopsys Proteus, Siemens EDACalibre, ASML Tachyon, etc.

[0060] like Figure 2 As shown, at position 202, for each block of the target layout, the defect values ​​of the defect points within each block are sorted according to the defect type to obtain the sorted defect data for each block, where the defect value indicates the severity of the defect.

[0061] As those skilled in the art will know, defect types may include, but are not limited to, defect types related to circuit connectivity, defect types related to pattern size, and defect types related to process reliability. Further, defect types related to circuit connectivity include bridging risks and open-circuit risks; defect types related to pattern size include insufficient linewidth, excessive linewidth, and spacing violations; and defect types related to process reliability include insufficient via coverage and antenna effect violations.

[0062] In some embodiments of this disclosure, the defect type may include some or all of the defect types present in the target layout. In some embodiments of this disclosure, for a defect point within each block, the defect type may include one or more defect types of interest selected from all defect types present in the target layout. In some embodiments of this disclosure, the defect types of interest may include the following defect types related to circuit connectivity. As examples, defect types of interest may include bridging risks, spacing violations, insufficient via coverage, etc.

[0063] In some embodiments of this disclosure, the defect type may include at least one of the following: bridging risk, open circuit risk, insufficient linewidth, excessive linewidth, spacing violation, insufficient via coverage, and antenna effect violation.

[0064] In some embodiments of this disclosure, the defect values ​​of defect points within each block can be sorted in the order of defect types related to circuit connectivity, defect types related to pattern size, and defect types related to process reliability. According to some embodiments of this disclosure, defect values ​​of defect points related to defect types with relatively higher severity levels can be prioritized for sorting, to facilitate engineers or users in better analyzing defects with relatively higher severity levels.

[0065] In some embodiments of this disclosure, for defect points within each block of the target layout, the defect values ​​of the defect points corresponding to each defect type within each block can be sorted according to each defect type. In some embodiments of this disclosure, the sorting can be performed according to different needs (e.g., adapting to the definition of defect severity for different defect types, or meeting user needs), including sorting in ascending or descending order, sorting based on the absolute value of the data, or rearranging according to a specific pattern (e.g., reorganizing the sorted data in an alternating order of minimum and maximum values). As a preferred embodiment of this disclosure, for scenarios where smaller defect values ​​indicate more severe defects within a block, the defect values ​​of the defect points within the block can be sorted in ascending order according to the defect type. This ensures that the defect points corresponding to the most severe defects are placed at the top, facilitating subsequent filtering.

[0066] In some embodiments of this disclosure, the simulation tool (e.g., OPC software) may have a built-in checker (not shown in the figures). As an example, the checker may be a checker or checker module built into the OPC software.

[0067] In some embodiments of this disclosure, the simulation tool can provide the inspector with simulation results and original design goals, and define inspection rules.

[0068] In some embodiments of this disclosure, before tiling the entire chip layout, the inspector can automatically check whether the layout data conforms to specific rules or requirements. In some embodiments of this disclosure, the inspector performs simulation analysis on the OPC-corrected integrated circuit layout, predicts the morphology formed on the silicon wafer, compares the formed morphology with the design target, and identifies all possible manufacturing defects, risk points, and / or defect points.

[0069] In some embodiments of this disclosure, each defect record output by the inspector may correspond to a specific defect point (or violation instance). In some embodiments of this disclosure, each defect record may include the coordinates of the defect point (i.e., the precise location of the defect point in the layout), type (i.e., the violation type determined according to rules, such as "excessive Edge Placement Error (EPE)" or "insufficient spacing"), simulation parameters (e.g., process conditions), defect value (e.g., EPE value), and other attributes (e.g., layer, cell to which it belongs).

[0070] In some embodiments of this disclosure, the inspector can determine the coordinates of each defect point. For example, if a defect point is located within a block region, it can be retained; if a defect point is located within a Halo region (or context region, further described below), it is automatically discarded. In some embodiments of this disclosure, the inspector can retain only the defect data of the block region itself, while discarding the defect data of the Halo region. According to embodiments of this disclosure, the graphics of the Halo region belong to adjacent blocks, and its defects are formally detected and recorded within its own core region when processing the adjacent block. Therefore, discarding the defect data of the Halo region can prevent the same location from being repeatedly reported in multiple blocks, which is crucial for ensuring data accuracy and avoiding duplicate calculations.

[0071] In some embodiments of this disclosure, for each defect point, the inspector can record information such as the coordinates, type, simulation parameters, and defect value of the defect point. In some embodiments of this disclosure, for each retained defect point, the inspector can generate a data record, such as a structured data record. According to embodiments of this disclosure, unless otherwise specifically stated, the defect point mentioned herein can refer to a retained defect point.

[0072] The following is for reference. Figure 3 , Figure 3 A schematic diagram of full-layout defect data processing according to an embodiment of the present disclosure is shown.

[0073] In some embodiments of this disclosure, the simulation tool first divides the target layout into blocks to obtain each block of the target layout. As an example, the simulation tool first divides the entire target layout into multiple smaller, manageable rectangular blocks. It should be noted that the target layout can refer to the chip layout to be processed, or may include the chip layout to be processed.

[0074] In some embodiments of this disclosure, the simulation tool can perform layout pattern correction before the full chip layout is divided into multiple blocks.

[0075] like Figure 3 As shown, all blocks of the target layout can be saved or stored in block pool 310 for subsequent processing. In some embodiments of this disclosure, block processing can be automatically performed by a block module built into a simulation tool, such as OPC software.

[0076] It should be noted that this is for illustrative purposes only. Figure 3 The diagram shows four individual blocks 320, four compute nodes 330, and four data filter modules 340. The specific structure of the data filter module 340 will be described in reference [reference needed]. Figure 4 Let me describe it in detail.

[0077] According to some embodiments of this disclosure, the number of individual blocks 320, computing nodes 330, and data filter modules 340 may vary depending on the specific application scenario.

[0078] In some embodiments of this disclosure, to ensure the accuracy of simulation results at the boundaries of each block, an additional boundary region (which may be referred to herein as a Halo region or context region) can be added to each block when the target layout is divided or segmented. It should be noted that the Halo region is a portion of the original chip layout; it is necessary context information introduced to ensure simulation accuracy during block processing.

[0079] According to embodiments of this disclosure, the above-described block processing strategy can ensure that during simulation, the graphics located at the edge of the block region can fully take into account the optical proximity effect of their neighboring graphics, thus obtaining accurate results that are highly similar to those of full-chip simulation.

[0080] In some embodiments of this disclosure, each block and its boundary region (e.g., block + Halo region) can form a computing unit. According to embodiments of this disclosure, the actual simulation range of each computing unit may include the block region and its surrounding Halo region. In some embodiments of this disclosure, the computing unit may be referred to as a task unit.

[0081] refer to Figure 3 Each computing unit corresponding to a single block 320 can be assigned to a corresponding computing node 330 for distributed parallel simulation computing. In some embodiments of this disclosure, distributed parallel simulation computing can be implemented or carried out in a manner similar to or the same as that in related technologies, for example, as those skilled in the art can appreciate.

[0082] In some embodiments of this disclosure, the computing node may include a physical / virtual computing node. As an example, a computing node may be a physical / virtual server. For instance, a computing node may be a Central Processing Unit (CPU).

[0083] In some embodiments of this disclosure, after loading the full chip layout (e.g., Graphic Design System II (GDSII) format, Open Artwork System Interchange Standard (OASIS) format, etc.), the user only needs to set parameters such as block size, width of Halo region, number of groups, and number of predetermined retained defect points per group, and the simulation tool can automatically complete the entire process including block division, adding Halo regions, task distribution, parallel computing, and result stitching.

[0084] In some embodiments of this disclosure, the computing node can independently run the lithography simulation engine, load all layout data of the allocated tile and its Halo region, and perform simulations in parallel, such as physical modeling. In some embodiments of this disclosure, the computing node can generate and output two-dimensional distribution predictions of the three-dimensional topography or key dimensions of the silicon wafer surface within the tile region.

[0085] In some embodiments of this disclosure, the simulation tool can submit all partitioned computing units as independent tasks to the scheduler (not shown in the figures). In some embodiments of this disclosure, the scheduler can allocate each computing unit to the corresponding computing nodes in the computing cluster according to the cluster status for distributed parallel simulation computing. In some embodiments of this disclosure, all partitioned computing units can be provided to the scheduler as a whole or in batches. In some embodiments of this disclosure, computing units can be provided to the scheduler in various suitable ways. As an example, computing units can be provided to the scheduler through various interfaces such as standard interfaces (e.g., Application Programming Interfaces, or APIs).

[0086] In some embodiments of this disclosure, the scheduler may be a job scheduler. As an example, the scheduler may be a high-performance computing job scheduler. For instance, the scheduler may be Slurm.

[0087] Back Figure 2 The description is as follows: At position 204, the sorted defect data for each block is grouped based on the pattern corresponding to the defect points within each block to obtain multiple grouped defect data for each block.

[0088] In some embodiments of this disclosure, the defect data of the defect points within each block may include at least one of the following: coordinates, type, defect value, and simulation parameters.

[0089] It should be noted that, in this disclosure, sorting the defect values ​​of defect points can be understood as sorting the defect points themselves.

[0090] In some embodiments of this disclosure, sorted defect point coordinates (e.g., coordinate values) can be obtained, and then the layout can be cut according to a set window size based on the obtained defect point coordinates to generate a pattern corresponding to the defect point. In some embodiments of this disclosure, the pattern corresponding to the defect point in each block is generated by cutting each block according to the set window size based on the coordinates of each defect point. In some embodiments of this disclosure, the set window is rectangular. As an example, each block can be cut according to the set window size with the coordinates of each defect point in each block as the center to generate a pattern corresponding to the defect point in each block. In some embodiments of this disclosure, there is a one-to-one correspondence between defect points and patterns.

[0091] In some embodiments of this disclosure, information about the graphic within a pattern corresponding to each sorted defect point within each block can be extracted as a feature of the pattern. In some embodiments of this disclosure, the information about the graphic within a pattern corresponding to each sorted defect point within each block may include one or more of the following: the width of the graphic within the pattern, the height of the graphic within the pattern, the spacing between the graphics within the pattern, and the proportion of the area of ​​the graphic to the area of ​​the pattern.

[0092] In some embodiments of this disclosure, grouping the sorted defect data for each block may include: extracting information of the graphic within the pattern corresponding to each sorted defect point in each block as a feature of the pattern; and performing similarity matching on the features of the pattern corresponding to each sorted defect point in each block based on predetermined matching parameters, so as to obtain multiple sets of patterns for each block corresponding to multiple groups of defect data in each block.

[0093] In some embodiments of this disclosure, fuzzy or exact matching can be performed by comparing the features of the pattern at each defect point according to set matching parameters. According to some embodiments of this disclosure, the matching parameters may include feature tolerance, similarity threshold, spatial transformation tolerance, distance threshold, etc. In some embodiments of this disclosure, the specific value of the threshold for the matching parameters can be adjusted according to the accuracy of the layout data and the noise level of the simulation calculation.

[0094] In some embodiments of this disclosure, after grouping, defect points can be divided into different groups. According to some embodiments of this disclosure, after grouping, the local patterns corresponding to defect points within each group are determined to belong to the same category based on a similarity measure performed according to matching parameters. According to some embodiments of this disclosure, in precise matching mode, the local patterns corresponding to all defect points within each group satisfy the algorithm-defined condition of being completely identical on the selected feature dimension (e.g., no difference within the range of data precision and calculation error). According to some embodiments of this disclosure, in fuzzy matching mode, the local patterns corresponding to all defect points within each group satisfy the algorithm-defined condition of being similar to each other on the selected feature dimension (e.g., based on a preset feature tolerance and similarity threshold, they form connected regions in the feature space).

[0095] As an example, if the distance / difference between the feature vectors of two patterns is strictly zero (or less than this extremely strict threshold), then the two patterns can be grouped together. As another example, if the line tolerance is set to ±10%, then patterns with linewidths of 90 nm and 100 nm can be considered "similar." It's important to understand that this "similarity" is an equivalence relationship defined based on engineering experience (e.g., process variation range), not absolute mathematical similarity. As yet another example, two patterns that are physically identical can be considered "identical" if the sub-nanometer coordinate offset due to storage or computation is ignored during algorithmic comparison (if the tolerance is set appropriately).

[0096] In some embodiments of this disclosure, both fuzzy matching and exact matching can be performed for pattern grouping. According to some embodiments of this disclosure, after grouping, all patterns within one or more groups may include identical (exact matching) and similar (fuzzy matching) patterns.

[0097] In some embodiments of this disclosure, the execution of fuzzy matching or exact matching may be implemented or realized in the same way as fuzzy matching or exact matching is performed in related technologies, as will be appreciated by those skilled in the art.

[0098] In some embodiments of this disclosure, grouping the sorted defect data for each block may further include: selecting the pattern corresponding to the first defect point in each of the multiple patterns in each block as the feature pattern of each pattern group, so as to merge the defect data of different blocks of the target layout.

[0099] In some embodiments of this disclosure, after grouping, all patterns within each group can be identical (exact match) and / or similar (fuzzy match). In some embodiments of this disclosure, the pattern corresponding to the first defect point within each group can be selected as the feature pattern of that group, and pattern information can be stored for grouping of full-map defect data. According to some embodiments of this disclosure, pattern information can be stored in any manner. As an example, pattern information can be stored using, for example, hash values.

[0100] At position 206, the multiple grouped defect data for each block are filtered to obtain the filtered defect data for each block.

[0101] In some embodiments of this disclosure, filtering multiple group defect data for each block may include: filtering multiple group defect data for each block except for the predetermined number of group defect data based on a predetermined number of group defect data, so as to obtain a predetermined number of group defect data for each block.

[0102] In some embodiments of this disclosure, filtering out a predetermined number of grouped defect data from multiple grouped defect data in each block can be considered or understood as group truncation of the grouped defect data in each block. According to some embodiments of this disclosure, group truncation of the grouped defect data in each block can be referred to as intra-block group truncation.

[0103] In some embodiments of this disclosure, the predetermined number of groups may be determined based on any of the following: one or more concern types selected from all defect types; N defect types ranked first (e.g., most concerned) based on the statistical ranking order of historical analysis records, where N is a natural number; and the top K most important defect types obtained according to a preset defect type priority rule, where K is a natural number.

[0104] In some embodiments of this disclosure, the top N defect types (e.g., the most concerning) obtained based on historical analysis records and the top K most important defect types obtained according to a preset defect type priority rule can exist independently of each other. In some embodiments of this disclosure, one or more of the top N defect types (e.g., the most concerning) obtained based on historical analysis records and the preset defect type priority rule can be included in the top K most important defect types obtained according to the preset defect type priority rule. In some embodiments of this disclosure, one or more of the top K most important defect types obtained according to the preset defect type priority rule can be included in the top N defect types (e.g., the most concerning) obtained based on historical analysis records and the preset defect type priority rule.

[0105] In some embodiments of this disclosure, filtering multiple grouped defect data for each block may further include: filtering defect data in the grouped defect data of each block based on a predetermined number of retained defect points for each group to obtain filtered defect data for each block.

[0106] In some embodiments of this disclosure, filtering defect data in the grouped defect data of each block can be regarded as or understood as truncating the defect data in the grouped defect data of each block. According to some embodiments of this disclosure, truncating defect data in the grouped defect data of each block can be referred to as intra-block intra-group defect data truncation.

[0107] In some embodiments of this disclosure, the predetermined number of defect points to retain in each group can be set as the product of the total number of all defect points contained in the group and a certain predetermined percentage. As an example, for grouped defect data within each block that has been sorted by defect severity (e.g., from high to low), during filtering, only the top-ranked defect data (e.g., the top 80% or 70% of defect data) can be retained, while the remaining defect data ranked lower can be discarded. It should be understood that the 80% and 70% mentioned herein are merely illustrative examples of the predetermined percentages of this disclosure and do not constitute a limitation on the specific value of the predetermined percentages.

[0108] According to some embodiments of this disclosure, when the defect data processing within a block is completed, the patterns corresponding to the defect points (e.g., each sorted defect point) within each block have been grouped according to the similarity of the patterns (e.g., by pattern similarity matching), and each group of patterns uses a feature pattern (e.g., the pattern in each group of patterns corresponding to the first defect point) as the feature pattern of that group.

[0109] In some embodiments of this disclosure, after the defect data within a block is processed, the original defect data of each block can be grouped or grouped and filtered without missing serious defect data, and the characteristic patterns of each group of patterns can be retained to represent the defect type of that group.

[0110] According to some embodiments of this disclosure, by processing defect data within blocks, the most serious and / or relatively serious defects can be prioritized or filtered out while controlling the amount of data to be processed. This ensures that the most critical and / or relatively critical problems are prioritized, which can greatly reduce the number of "noise" or "minor problems" that engineers or users need to analyze and diagnose, allowing them to focus their attention on a few core root cause patterns that cause the vast majority of defects or the most serious risks, thus significantly improving analysis efficiency.

[0111] As described above, the processing involved at positions 202 to 206 is for processing intra-block defect data (i.e., intra-block defect data processing). In some embodiments of this disclosure, the processing involved at positions 202 to 206 may, for example, be performed by... Figure 3 The data filter module 340 shown is executed.

[0112] In some embodiments of this disclosure, each set of defect data within each block of the target layout can be retained in a container. For example, as... Figure 3 As shown, the processed defect data for each block of the target layout can be stored (e.g., temporarily or permanently) in container 370. In some embodiments of this disclosure, the container may include a memory container, a cache container, a buffer container, a persistent container, etc.

[0113] The above mainly describes the processing of defect data within a block. The following section will mainly describe the processing of defect data for the entire target layout (i.e., full layout defect data processing).

[0114] Continue to refer to Figure 2 The description is as follows: At point 208, the full-map defect data of the target layout is obtained based on the filtered defect data of all blocks in the target layout.

[0115] In some embodiments of this disclosure, when starting full-layout defect data processing, it may first be from a container (e.g., Figure 3 The grouped defect data of all blocks of the target layout can be obtained from the container 370 shown, and then full layout defect data processing can be performed.

[0116] In some embodiments of this disclosure, full-map defect data processing may include grouping, filtering, and other processing of the full-map defect data.

[0117] In some embodiments of this disclosure, after obtaining the grouped defect data of all blocks of the target layout, the information of the feature patterns of different groups of different blocks can be compared (e.g., by...). Figure 3 The data similarity matching module 350 shown is used to merge the grouped defect data of different blocks, thereby completing the grouping of defect data for the entire map.

[0118] In some embodiments of this disclosure, the full-layout defect data can be processed in a manner similar to that used for intra-block defect data. In some embodiments of this disclosure, for full-layout defect data, grouped defect data other than the predetermined number of groups can be filtered out from multiple grouped defect data of the full-layout based on a predetermined number of groups. In some embodiments of this disclosure, defect data in the grouped defect data of the target layout can be filtered based on a predetermined number of retained defect points per group to obtain the final defect data of the target layout.

[0119] In some embodiments of this disclosure, the final defect data of the target layout can be output (e.g., by...) after obtaining the final defect data of the target layout. Figure 3 The output module 360 ​​shown is executed for subsequent use.

[0120] It should be understood that the predetermined number of groups involved in full-layout defect data processing is independent of the predetermined number of groups involved in intra-block defect data processing. However, in some embodiments of this disclosure, the predetermined number of groups involved in full-layout defect data processing may also be set in a similar manner to the predetermined number of groups involved in intra-block defect data processing.

[0121] It should be understood that the predetermined number of retained defect points for each group involved in full-map defect data processing is independent of the predetermined number of retained defect points for each group involved in intra-block defect data processing. However, in some embodiments of this disclosure, the predetermined number of retained defect points for each group involved in full-map defect data processing may also be set in a similar manner to the predetermined number of retained defect points for each group involved in intra-block defect data processing.

[0122] In some embodiments of this disclosure, obtaining full-map defect data of a target layout based on filtered defect data of all blocks of the target layout may include: merging the filtered defect data of different blocks of the target layout based on the similarity of feature patterns of different groups of different blocks, to obtain multiple merged grouped defect data; and filtering the merged grouped defect data to obtain filtered defect data. It should be understood that, according to some embodiments of this disclosure, merging the filtered defect data of different blocks of the target layout based on the similarity of feature patterns of different groups of different blocks can refer to defect data grouping performed on the entire layout surface.

[0123] In some embodiments of this disclosure, filtering the merged multiple group defect data may include: filtering the group defect data of the target layout other than the predetermined number of groups based on a predetermined number of groups, so as to obtain filtered group defect data.

[0124] In some embodiments of this disclosure, filtering the merged multiple grouped defect data may include: filtering defect data in the grouped defect data of the target layout based on a predetermined number of retained defect points for each group to obtain the final defect data of the target layout. It should be understood that, according to some embodiments of this disclosure, after merging the filtered defect data of different blocks of the target layout to obtain merged multiple grouped defect data, defect data filtering can be performed directly on the merged grouped defect data without performing filtering based on a predetermined number of groups (i.e., filtering grouped defect data other than the predetermined number of groups based on the predetermined number of groups for the multiple grouped defect data of the target layout).

[0125] In some embodiments of this disclosure, filtering the merged multiple grouped defect data may include: filtering grouped defect data other than the predetermined number of groups for the multiple grouped defect data of the target layout based on a predetermined number of groups, to obtain filtered grouped defect data; and filtering defect data in the merged grouped defect data based on a predetermined number of retained defect points in each group, to obtain the final defect data of the target layout. It should be understood that, according to some embodiments of this disclosure, after merging the filtered defect data of different blocks of the target layout to obtain merged multiple grouped defect data, filtering the merged grouped defect data based on the predetermined number of groups can be performed first, and then filtering the defect data in one or more of the filtered grouped defect data can be performed.

[0126] In some embodiments of this disclosure, information or data on all defects can be aggregated and output (e.g., by...). Figure 3 The output module 360 ​​shown is used to generate full-chip defect data or defect records. In some embodiments of this disclosure, defect records may be output in the form of a structured database (e.g., SQLite) or a specific log file (e.g., Comma-Separated Value (CSV) format, JavaScript Object Notation (JSON) format).

[0127] Compared to existing solutions, the data processing methods of some embodiments of this disclosure do not directly process the defect data of the entire chip. Instead, they first perform intra-block defect data processing for each block of the entire chip layout, then merge the defect data of all blocks of the entire chip layout after intra-block defect data processing, and finally perform full-layout defect data processing to obtain the final full-layout defect data.

[0128] After the data processing stage of intra-block defect data processing, some embodiments of the present disclosure only involve a portion of the defect data in the full-layout defect data processing. In this way, the overall running speed can be greatly improved, and serious defects can be ensured not to be missed.

[0129] Furthermore, the data processing method disclosed herein can further reduce the amount of defect data to be processed when performing full-map defect data processing, thereby further reducing the required memory and computation time.

[0130] The data processing method disclosed herein can significantly reduce the memory and computation time required for full-chip defect grouping while ensuring analysis accuracy.

[0131] The following is for reference. Figure 4 , Figure 4 A schematic diagram of a data filter module 400 according to an embodiment of the present disclosure is shown.

[0132] like Figure 4 As shown, the data filter module 400 may include a data sorting submodule 410, a data similarity matching submodule 420, and a data post-processing submodule 430.

[0133] The data filter module 400 can be configured to perform intra-block defect data processing according to some embodiments of this disclosure. It should be noted that the data filter module 400 can be functionally and configurationally similar to... Figure 3 The data filter module 340 shown is the same as or similar to the one shown.

[0134] Specifically, the data sorting submodule 410 can be configured to execute Figure 2 The processing at point 202 involves sorting the defect values ​​of the defect points within each block of the target layout according to the defect type.

[0135] The data similarity matching submodule 420 can be configured to perform... Figure 2 The processing at point 204 involves grouping the sorted defect data for each block based on the pattern corresponding to the defect points within each block.

[0136] The data sorting submodule 410 can be configured to perform Figure 2 The processing at point 206 involves filtering the multiple grouped defect data for each block.

[0137] The processing of intra-block defect data, including the processing at positions 202 to 206, has been described in detail above and will not be repeated here.

[0138] Figure 4 The configuration of containers in the container can be similar to Figure 3The container 370 is used in the text, so it will not be described further.

[0139] In some embodiments of this disclosure, Figure 4 The data shown may include raw defect data of the target layout.

[0140] It should be noted that the examples illustrated in the above embodiments are only for illustrating the solutions of the present disclosure and are not intended to limit the solutions of the present disclosure.

[0141] This disclosure provides a data processing method for analyzing chip layout defects. By independently and in parallel sorting, grouping, and filtering defect data within each block of the target layout, this method significantly reduces the memory and computation time required to process defect data across the entire target layout, while ensuring that more severe defects are not missed. Furthermore, this method further reduces the required memory and computation time by filtering the number of groups of defect data to be processed and the defect data within those groups during full-layout defect data processing.

[0142] The disclosed solution employs a hierarchical processing approach for defect data of the target layout, first processing within blocks and then processing the entire layout. This approach significantly reduces the memory, computation time, and computational resources required for grouping defects across the entire chip, while ensuring analytical accuracy. It enables efficient, feasible, and scalable intelligent analysis of defect data from large-scale chips or even very large-scale chips, laying a data foundation for rapidly locating the root cause of OPC failures.

[0143] It should be understood that the embodiments shown in the accompanying drawings are merely illustrative of some embodiments of this disclosure and are not intended to limit this disclosure. Embodiments of this disclosure may also have various other forms.

[0144] An electronic device is also disclosed in embodiments of this disclosure. The electronic device includes a processor and a memory coupled to the processor. The memory has instructions stored therein, which, when executed by the processor, cause the device to perform actions including: sorting defect values ​​of defect points within each block of a target layout according to defect type to obtain sorted defect data for each block, wherein the defect values ​​indicate the severity of the defect; grouping the sorted defect data for each block based on patterns corresponding to the defect points within each block to obtain multiple groups of defect data for each block; filtering the multiple groups of defect data for each block to obtain filtered defect data for each block; and obtaining full-layout defect data of the target layout based on the filtered defect data of all blocks of the target layout.

[0145] An embodiment of this disclosure also discloses a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements a data processing method according to an embodiment of this disclosure.

[0146] An embodiment of this disclosure also discloses a lithography apparatus, which includes an electronic device according to an embodiment of this disclosure.

[0147] Figure 5 A schematic block diagram of an example device 500 that can be used to implement embodiments of the present disclosure is shown. As shown, device 500 includes a central processing unit (CPU) 501, which can perform various appropriate actions and processes according to computer program instructions stored in read-only memory (ROM) 502 or loaded from storage unit 508 into random access memory (RAM) 503. The RAM 503 may also store various programs and data required for the operation of device 500. The CPU 501, ROM 502, and RAM 503 are interconnected via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0148] Multiple components in device 500 are connected to I / O interface 505, including: input unit 506, such as keyboard, mouse, etc.; output unit 507, such as various types of monitors, speakers, etc.; storage unit 508, such as disk, optical disk, etc.; and communication unit 509, such as network card, modem, wireless transceiver, etc. Communication unit 509 allows device 500 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0149] CPU 501 executes the various methods and processes described above, such as data processing method 200. For example, in some embodiments of this disclosure, data processing method 200 may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 508. In some embodiments of this disclosure, part or all of the computer program may be loaded and / or installed on device 500 via ROM 502 and / or communication unit 509. When the computer program is loaded into RAM 503 and executed by CPU 501, one or more steps of data processing method 200 described above may be performed. Alternatively, in other embodiments, CPU 501 may be configured to execute data processing method 200 by any other suitable means (e.g., by means of firmware).

[0150] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), Application Specific Standard Product (ASSP), System on Chip (SoC), Complex Programmable Logic Device (CPLD), and so on.

[0151] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0152] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), optical fiber, compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0153] Furthermore, although the operations are described in a specific order, this should be understood as requiring that such operations be performed in the specific order shown or in sequential order, or requiring that all illustrated operations be performed to achieve the desired result. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations.

[0154] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A data processing method, comprising: For each block of the target layout, the defect values ​​of the defect points within each block are sorted according to the defect type to obtain the sorted defect data for each block, where the defect value indicates the severity of the defect; Based on the pattern corresponding to the defect points within each block, the sorted defect data of each block is grouped to obtain multiple grouped defect data for each block; The multiple grouped defect data for each block are filtered to obtain filtered defect data for each block; as well as The full-map defect data of the target layout is obtained based on the filtered defect data.

2. The method of claim 1, wherein filtering the plurality of grouped defect data for each block comprises: Based on a predetermined number of groups, the group defect data of each block is filtered to exclude group defect data of the predetermined number of groups, so as to obtain the predetermined number of group defect data for each block.

3. The method according to claim 1 or 2, wherein filtering the plurality of grouped defect data for each block further comprises: Based on the predetermined number of defect points to be retained in each group, the defect data in the grouped defect data of each block is filtered to obtain the filtered defect data of each block.

4. The method of claim 2, wherein the predetermined number of groups is determined based on any one of the following: Select one or more defect types of interest from all defect types; The top N defect types are determined based on historical analysis and statistical ranking, where N is a natural number; and The top K most important defect types are determined based on a preset defect type priority rule, where K is a natural number.

5. The method of claim 1, wherein the pattern corresponding to the defect point within each block is generated by cutting each block according to a set window size based on the coordinates of each defect point.

6. The method of claim 1, wherein grouping the sorted defect data for each block comprises: Extract information about the graphic within the pattern corresponding to each sorted defect point in each block as a feature of the pattern; as well as Based on predetermined matching parameters, similarity matching is performed on the features of the pattern corresponding to each sorted defect point within each block to obtain multiple sets of patterns for each block corresponding to multiple grouped defect data within each block.

7. The method of claim 6, wherein the information of the graphic within the pattern corresponding to each sorted defect point within each block includes one or more of the following: the width of the graphic within the pattern, the height of the graphic within the pattern, the spacing between the graphics within the pattern, and the proportion of the area of ​​the graphic to the area of ​​the pattern.

8. The method of claim 6, wherein grouping the sorted defect data for each block further comprises: The pattern corresponding to the first defect point in each of the multiple sets of patterns in each block is selected as the feature pattern of each set of patterns for merging defect data of different blocks of the target layout.

9. The method of claim 1, wherein the defect type includes at least one of the following: Bridging risks, open circuit risks, insufficient line width, excessive line width, spacing violations, insufficient via coverage, and antenna effect violations.

10. The method of claim 1, wherein the defect data of the defect points within each block includes at least one of the following: coordinates, type, defect value, and simulation parameters.

11. The method of claim 1, wherein obtaining full-layout defect data of the target layout based on filtered defect data comprises: Based on the similarity of the feature patterns of different groups of different blocks of the target layout, the filtered defect data of different blocks of the target layout are merged to obtain multiple groups of defect data after merging. as well as The merged grouped defect data is filtered to obtain filtered defect data.

12. The method of claim 11, wherein filtering the merged multiple grouped defect data comprises: Based on a predetermined number of groups, filter out group defect data other than the predetermined number of groups for multiple group defect data of the target layout to obtain filtered group defect data.

13. The method according to claim 11 or 12, wherein filtering the merged multiple grouped defect data further comprises: Based on the predetermined number of defect points to be retained in each group, the defect data in the grouped defect data of the target layout is filtered to obtain the final defect data of the target layout.

14. An electronic device comprising: processor; as well as A memory coupled to a processor, the memory having instructions stored therein, which, when executed by the processor, cause the electronic device to perform actions, the actions including: For each block of the target layout, the defect values ​​of the defect points within each block are sorted according to the defect type to obtain the sorted defect data for each block, where the defect value indicates the severity of the defect; Based on the pattern corresponding to the defect points within each block, the sorted defect data of each block is grouped to obtain multiple grouped defect data for each block; The multiple grouped defect data for each block are filtered to obtain filtered defect data for each block; and The full-map defect data of the target layout is obtained based on the filtered defect data.

15. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method according to any one of claims 1 to 13.

16. A photolithography apparatus, comprising the electronic device according to claim 14.

Images