Signal control method, touch display panel and vehicle display device
By prioritizing the activation of control signals for data lines that do not overlap with the conductors and setting a randomized activation sequence, the problem of short vertical lines caused by data signals being coupled to incorrect levels in touch display devices is solved, thus improving display quality.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- AU OPTRONICS CORP
- Filing Date
- 2026-01-23
- Publication Date
- 2026-05-05
AI Technical Summary
In touch display devices, because the data line and the wire transmitting the common electrode signal overlap each other in the vertical direction, the data signal may be coupled to an incorrect level, resulting in a short vertical line problem.
By prioritizing the activation of control signals for data lines that do not overlap with conductors, and setting different activation sequences for control signals in different screens, the data signals are prevented from being affected by the common electrode signal, thus avoiding the instability of the short vertical line position.
This effectively avoids the problem of short vertical lines appearing on the display screen and increases the charging time during the level rise phase, thus reducing the severity of the short vertical lines.
Smart Images
Figure CN121979406A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to a signal control method, a touch display panel, and an automotive display device, and particularly to a signal control method, a touch display panel, and an automotive display device with adjustable control signal switching sequence. Background Technology
[0002] Touchscreen displays are widely used in various electronic products today due to their intuitive and convenient operation. However, in touchscreen displays, the data line and the trace that transmits the common electrode signal may overlap vertically. When the touchscreen display is in operation, the data signal transmitted by the data line may be coupled to an incorrect level by the common electrode signal, resulting in short vertical lines on the display screen. Summary of the Invention
[0003] This disclosure provides, in some embodiments, a signal control method, a touch display panel, and an automotive display device. When a specific data line overlaps vertically with a trace transmitting a common electrode signal, the control signal corresponding to the data line in the display circuit that does not overlap with the trace is preferentially activated. This prevents the data signal of the data line from being affected by the common electrode signal, thus avoiding coupling to an incorrect level by the common electrode signal. This avoids the problem of short vertical lines appearing on the display screen. Alternatively, when the data line corresponding to each control signal may overlap vertically with the trace transmitting the common electrode signal, different activation sequences of the control signals are set in different screens. This causes the data signals of the data lines to be affected by the common electrode signal in an out-of-order manner, thus making the position of the short vertical lines variable. This improves the problem of short vertical lines appearing on the display screen.
[0004] This disclosure provides a signal control method in some embodiments. The signal control method is applicable to a touch display panel, wherein the touch display panel includes a plurality of gate lines, a plurality of data lines, a plurality of wires, a plurality of sensing circuits, peripheral circuits, and a control chip. The peripheral circuits are coupled to the plurality of gate lines, the plurality of sensing circuits are coupled to the plurality of wires, and the control chip is coupled to the plurality of data lines and the plurality of wires respectively. The signal control method includes: during display, sequentially switching the plurality of gate lines to an enable level via the peripheral circuits; when one of the plurality of gate lines has the enable level, transmitting one of a plurality of control signals via the plurality of control chips to one of a plurality of switches of a time-division multiplexer, wherein the plurality of switches... The device described herein is connected to one of the plurality of data lines; when the device described herein has the enable level of the plurality of control signals, the device described herein is turned on to write data to the device described herein on the plurality of data lines; wherein one of the plurality of control signals that preferentially switches to the enable level in one of the plurality of frames is different from another of the plurality of control signals that preferentially switches to the enable level in another of the plurality of frames; and wherein the number of times the device described herein preferentially switches to the enable level in one of the plurality of frames is the same as the number of times the other of the plurality of control signals that preferentially switches to the enable level in another of the plurality of frames.
[0005] According to some embodiments of this disclosure, the plurality of wires are disposed above the plurality of data lines, and each of the plurality of wires overlaps the plurality of data lines corresponding to each of the plurality of control signals.
[0006] According to some embodiments of this disclosure, in the plurality of embodiments, the order in which the plurality of control signals switch to the enable level is out of order.
[0007] According to some embodiments of this disclosure, in the plurality of frames, each of the plurality of control signals preferentially switches to the enable level the same number of times.
[0008] According to some embodiments of this disclosure, in the plurality of frames, the order in which the plurality of control signals preferentially switch to the enable level is arranged randomly.
[0009] According to some embodiments of this disclosure, the enable period of the plurality of gate lines is greater than the enable period of the plurality of control signals.
[0010] According to some embodiments of this disclosure, the enable period of the plurality of gate lines includes a start phase, a plurality of enable phases, a plurality of disable phases, and an end phase, wherein the start phase takes precedence over the plurality of enable phases and the plurality of disable phases, and wherein the sum of the enable period of the start phase and one of the plurality of enable phases is between 1.8 microseconds and 2 microseconds.
[0011] According to some embodiments of this disclosure, the plurality of control signals are separated from each other by data time, wherein the data time is defined as the time during which the peripheral circuit drives the corresponding pixel column in each frame time.
[0012] According to some embodiments of this disclosure, the switching time of the plurality of control signals that preferentially switch to the enable level among the plurality of frames is separated from the switching time of the plurality of gate lines that switch to the enable level by the data time.
[0013] This disclosure provides a touch display panel in some embodiments. The touch display panel includes a substrate, peripheral circuitry, a control chip, and sensing circuitry. The peripheral circuitry is disposed on the substrate and coupled to a plurality of gate lines. The control chip is disposed on the substrate and coupled to a plurality of data lines and a plurality of conductive lines, with the conductive lines positioned above the data lines. A plurality of sensing circuitry is disposed on the substrate and coupled to the conductive lines. During display, the peripheral circuitry sequentially switches the plurality of gate lines to an enable level. The control chip is configured to: when one of the plurality of gate lines has the enable level, transmit one of a plurality of control signals to one of a plurality of switches of a time-division multiplexer, wherein the switch is connected to one of the plurality of data lines. When one of the plurality of control signals has the enable level, the one of the plurality of switches is turned on to write data of the one of the plurality of data lines; wherein one of the plurality of control signals that preferentially switches to the enable level in one of the plurality of frames is different from another of the plurality of control signals that preferentially switches to the enable level in another of the plurality of frames; and the number of times the one of the plurality of control signals that preferentially switches to the enable level in one of the plurality of frames is the same as the number of times the other of the plurality of control signals that preferentially switches to the enable level in another of the plurality of frames.
[0014] According to some embodiments of this disclosure, each of the plurality of conductors overlaps with one of the plurality of data lines corresponding to one of the plurality of control signals.
[0015] According to some embodiments of this disclosure, each of the plurality of conductors overlaps with the plurality of data lines corresponding to each of the plurality of control signals.
[0016] According to some embodiments of this disclosure, in the plurality of frames, the order in which the plurality of control signals switch to the enable level is out of order.
[0017] According to some embodiments of this disclosure, in the plurality of frames, each of the plurality of control signals preferentially switches to the enable level the same number of times.
[0018] According to some embodiments of this disclosure, in the plurality of frames, the order in which the plurality of control signals preferentially switch to the enable level is arranged randomly.
[0019] According to some embodiments of this disclosure, the enable period of the plurality of gate lines is greater than the enable period of the plurality of control signals.
[0020] According to some embodiments of this disclosure, the enable period of the plurality of gate lines includes a start phase, a plurality of enable phases, a plurality of disable phases, and an end phase, wherein the start phase takes precedence over the plurality of enable phases and the plurality of disable phases, and wherein the sum of the enable period of the start phase and one of the plurality of enable phases is between 1.8 microseconds and 2 microseconds.
[0021] According to some embodiments of this disclosure, the plurality of control signals are separated from each other by data time, wherein the data time is defined as the time during which the peripheral circuit drives the corresponding pixel column in each frame time.
[0022] According to some embodiments of this disclosure, the switching time of the plurality of control signals that preferentially switch to the enable level among the plurality of frames is separated from the switching time of the plurality of gate lines that switch to the enable level by the data time.
[0023] This disclosure provides a vehicle display device in some embodiments. The vehicle display device includes a base and the aforementioned touch display panel. The base is disposed on a vehicle. The touch display panel is disposed on the base. Attached Figure Description
[0024] To gain a more complete understanding of the embodiments and their advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, wherein: Figure 1 An example of a touch display panel according to a partial embodiment of the present disclosure; Figure 2 for Figure 1 An example of a cross-sectional view of a touch display panel along line A-A'; Figure 3 An example of a time-division multiplexer connected pixel circuit according to a partial embodiment of this disclosure; Figure 4A for Figure 1 The timing of the touch display panel; Figure 4B for Figure 1 The timing of the touch display panel; Figure 5 for Figure 1 Another example of a cross-sectional view of a touch display panel along line A-A'; Figure 6 A flowchart of a signal control method according to some embodiments of this disclosure; Figure 7A for Figure 5 The timing of the touch display panel; Figure 7B for Figure 5 The timing of the touch display panel; Figure 8 This is an example of an automotive display device according to some embodiments of the present disclosure; Figure 9A for Figure 8 An example of the timing of an automotive display device; and Figure 9B for Figure 8 Top view of the vehicle's display device.
[0025] Explanation of reference numerals in the attached figures: 100: Touchscreen display panel 120: Substrate 140: Peripheral Circuits 160: Control chip 180: Sensing circuit 200, 300, 500, 600, 800: Timing 700: Automotive display device 720: Base 740: Touch display panel 900: Vehicles A-A': line DL, DL1~DL8: Data cables Da1~DaN: Control signals DI1~DI4: Enabling Stage DR1~DR4: Energy-disabling phase DR: Driving Area ET: End Phase FT1~FT4: Level Recovery Phase FR1~FRN: Picture frame GL1~GL4: Gate lines GD, GD1~GDN, GD1A, GD1B, GD2A, GD2B, GD3A, GD3B, GD4A, GD4B: Gate signals H1, H2: Height MUX: Time-sharing multiplexer OP: Signal control method PC: Pixel Circuit RT1~RT4: Level rise phase ST: Initial Stage S1, S2, S3: Steps SL: Short vertical line SO1, SO2: Signal sources SW1~SW4: Switches T V During the recovery period TP: Conductor VCOM: Common Voltage VD: Level Difference WS: Windshield X, Y, Z: Direction Detailed Implementation
[0026] The embodiments of this disclosure are discussed in detail below. However, it should be understood that the embodiments provide many applicable concepts that can be implemented in a wide variety of specific situations. The discussed and disclosed embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.
[0027] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship between one element or feature and another illustrated in the figures. Besides the orientation depicted in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly. As used herein, “approximately,” “about,” “approximately,” or “substantially” generally refers to within 20%, 10%, or 5% of a given value or range. The numerical quantities given herein are approximate, meaning that the terms “approximately,” “about,” “approximately,” or “substantially” may be conjectured unless explicitly specified.
[0028] Figure 1 This is an example of a touch display panel 100 according to a partial embodiment of the present disclosure. The touch display panel 100 includes a substrate 120, peripheral circuitry 140, a control chip 160, and a sensing circuit 180. Peripheral circuitry 140 is disposed on the substrate 120 and coupled to gate lines GL1 to GL4. Control chip 160 is disposed on the substrate 120 and coupled to K data lines DL and M conductors TP (see reference 1) of a 1-to-N time-division multiplexer (not shown). Figure 2 The circuit TP is a touch line used to transmit touch signals. The control chip 160 can be a Touch and Display Driver Integration (TDDI) chip, and can transmit the data to be written to different data lines DL via the 1-to-N time-division multiplexer. The sensing circuit 180 is disposed on the substrate 120 and coupled to its corresponding M wires TP, wherein the sensing circuit 180 can correspond to the pixel circuit PC (see [reference]). Figure 3 ).
[0029] Please refer to this as well. Figure 2 ,in Figure 2 for Figure 1 An example of a cross-sectional view of the touch display panel 100 along line A-A'. In this embodiment, one of the M conductors TP may overlap in direction Z with one of the K data lines DL corresponding to one of the control signals Da1 to Da4. The K data lines DL are used as a 1-to-4 time-division multiplexer MUX (see [reference needed]). Figure 3 Taking data lines DL1~DL8 as an example, data lines DL1~DL8 can be located below the M conductors TP, and some data lines DL1~DL8 (e.g., data lines DL2, DL5 and DL8) can overlap with the M conductors TP in the Z direction.
[0030] Please refer to this as well. Figure 1 , Figure 2 , Figure 3 as well as Figure 4A ,in Figure 3 This is an example of a time-division multiplexer (MUX) connected to a pixel circuit (PC) according to a partial embodiment of the present disclosure. Figure 4A for Figure 1The timing 200 of one of the frames during the display period of the touch display panel 100. The enable period of the gate signal GD of one of the gate lines GL1 to GL4 includes a start phase ST, enable phases DI1 to DI4, disable phases DR1 to DR4, and an end phase ET. Enable phases DI1 to DI4 are the enable phases of multiple switches SW1 to SW4 in the 1-to-4 time-division multiplexer MUX, and disable phases DR1 to DR4 are the disable phases of multiple switches SW1 to SW4 in the 1-to-4 time-division multiplexer MUX.
[0031] For example, enable phase DI1 is the on period of switch SW4, and disable phase DR1 is the off period of switch SW4. Switch SW4 receives control signal Da4 from control chip 160 and controls whether data (e.g., data transmitted by signal source SO1 or signal source SO2) is written to data line DL3 and DL4 according to control signal Da4 to the pixel circuit PC. Enable phase DI2 is the on period of switch SW2, and disable phase DR2 is the off period of switch SW2. Switch SW2 receives control signal Da2 from control chip 160 and controls whether data (e.g., data transmitted by signal source SO1 or signal source SO2) is written to data line DL7 and DL8 according to control signal Da2 to the pixel circuit PC. The enable phase DI3 is the conduction period of switch SW3, and the disable phase DR3 is the deactivation period of switch SW3. Switch SW3 receives control signal Da3 from control chip 160 and controls whether data (e.g., data transmitted from signal source SO1 or signal source SO2) is written to data lines DL1 and DL2 to the pixel circuit PC according to control signal Da3. The enable phase DI4 is the conduction period of switch SW1, and the disable phase DR4 is the deactivation period of switch SW1. Switch SW1 receives control signal Da1 from control chip 160 and controls whether data (e.g., data transmitted from signal source SO1 or signal source SO2) is written to data lines DL5 and DL6 to the pixel circuit PC according to control signal Da1. The operation of switches SW1 to SW4 and control signals Da1 to Da4 will be explained in subsequent paragraphs.
[0032] Furthermore, the initial phase ST takes precedence over the enable phases DI1~DI4 and the disable phases DR1~DR4, and the duration of the disable phase DR4 is shorter than the duration of the disable phases DR1~DR3. The enable period of the initial phase ST is 0.7 microseconds, and the sum of the enable period of the initial phase ST and one of the enable phases DI1~DI4 is between 1.8 microseconds and 2 microseconds. The enable periods of the control signals Da1~Da4 of the 1-to-4 time-division multiplexer MUX include the level rise phase RT1~RT4 and the level recovery phase FT1~FT4, respectively, where the control signals Da1~Da4 are the signals at the gate terminals of the switches SW1~SW4 in the 1-to-4 time-division multiplexer MUX. The duration of the level recovery phase FT1 is shorter than that of the level recovery phases FT2 to FT4. The duration of the level rise phases RT1 to RT4 is the same as that of the enable phases DI1 to DI4. The duration of the level recovery phases FT1 to FT4 is the same as that of the disable phases DR1 to DR4. The level rise phases RT1 to RT4 last for 1.2 microseconds, the level recovery phases FT2 to FT4 last for 0.6 microseconds, and the level recovery phase FT1 lasts for 0.11 microseconds.
[0033] It is worth noting that the enable period of the gate signal GD for one of the gate lines GL1 to GL4 is longer than the enable period of the control signals Da1 to Da4 for the data lines DL1 to DL4. For example, the enable period of the gate signal GD may include the enable period of the control signals Da1 to Da4.
[0034] Operationally, the peripheral circuitry 140 and the control chip 160 can perform various operations during the display period. For example, the peripheral circuitry 140 can sequentially switch gate lines GL1-GL4 to a common enable level to activate the pixel circuit PC. The control chip 160 can activate the corresponding data lines DL1-DL8 via the 1-to-4 time-division multiplexer MUX for screen updates. The control chip 160 can transmit the common voltage VCOM to the sensing circuit 180 via the M wires TP. However, since the sensing circuit 180 spatially overlaps the gate lines GL1-GL4 and the data lines DL1-DL8, it will be coupled when the gate lines GL1-GL4 switch to the enable level or when data is written to the data lines DL1-DL8. After being coupled, the sensing circuit 180 can restore its level to the common voltage VCOM level via the wires TP connected to the control chip 160. If, during the recovery of the common voltage VCOM level, one of the data lines DL1 to DL8 located below the conductor TP happens to be the first switch turned on in the 1-to-4 time-division multiplexer MUX, and the data line DL1 to DL8 (e.g., data line DL2, data line DL5, or data line DL8) is in a floating state, the original data of the data line DL1 to DL8 will be coupled to an incorrect level.
[0035] For example, when data lines DL2, DL5, or DL8 overlap with the M conductors TP in the Z direction, the sensing circuit 180 will be coupled when gate lines GL1~GL4 switch to the enable level to turn on the pixel circuit PC. In other words, when gate lines GL1~GL4 switch to the enable level, the pixel circuit PC corresponding to the sensing circuit 180 is written to a polarity level, and the common voltage VCOM level of the sensing circuit 180 is coupled to the polarity level. Then, the coupled sensing circuit 180 restores the common voltage VCOM level to a preset common voltage VCOM level through the conductor TP connecting to the control chip 160, wherein the recovery period T of the common voltage VCOM is... V Approximately 3 microseconds. At this time, if the control chip 160 stops transmitting control signals Da1~Da4 (for example, after the multiple switches SW1~SW4 in the 1-to-4 time-division multiplexer MUX are turned off), causing data lines DL1~DL8 to float, and data line DL2, which overlaps with the M conductors TP in the Z direction, is the priority data line to be turned on, then the voltage level of data line DL2 is coupled to an incorrect level by the common voltage VCOM, leading to a short vertical line problem. To avoid the short vertical line problem, the control chip 160 can be used to execute a control method that prioritizes the turning on of specific data lines, which will be described below.
[0036] In detail, during the initial stage ST, the peripheral circuit 140 sequentially switches gate lines GL1 to GL4 to the enable level to turn on the pixel circuit PC. Then, after one of the gate lines GL1 to GL4 has the enable level, during the enable stages DI1 to DI4, the control chip 160 transmits control signals Da1 to Da4 to the 1-to-4 time-division multiplexer MUX, prioritizing the transmission of one of the control signals Da1 to Da4, wherein the control signal Da1 to Da4 corresponds to two of the data lines DL1 to DL8 (e.g., data lines DL3 and DL4) that do not overlap with the M conductors TP.
[0037] For example, in the enable phase DI1, when the gate signal GD of one of the gate lines GL1~GL4 changes from a disabled level to an enabled level, the pixel circuit PC coupled to one of the gate lines GL1~GL4 will be turned on, and the control chip 160 will preferentially transmit the control signal Da4, where the control signal Da4 corresponds to the data lines DL3 and DL4 that do not overlap with the M wires TP. Therefore, the switch SW4 of the 1-to-4 time-division multiplexer MUX corresponding to the control signal Da4 can be preferentially turned on, thereby making the data lines DL3 and DL4 preferentially transmit data to the pixel circuit PC. The switching time of the control signal Da4, which preferentially switches to the enabled level, is separated from the data time by the switching time of the gate signal GD switching to the enabled level. Next, in the enable phases DI2-DI4, the control chip 160 can transmit control signals Da1-Da3 to the 1-to-4 time-division multiplexer MUX respectively, to activate the plurality of switches SW1-SW3 corresponding to the control signals Da1-Da3, thereby enabling data lines DL1-DL2 and data lines DL5-DL8 to transmit data to the pixel circuit PC. When any of the plurality of control signals Da1-Da4 has the enable level, the plurality of switches SW1-SW4 are activated to write data to the plurality of data lines DL1-DL8. Therefore, the pixel circuit PC can display a specific brightness to display multiple images.
[0038] In this way, the voltage levels of data lines DL3 and DL4 are not affected by fluctuations in the common voltage VCOM level transmitted by conductor TP, allowing the voltage difference VD between data lines DL3 and DL4 and the common voltage VCOM to be maintained at a preset value, thus avoiding the problem of short vertical lines. In addition, it can also increase the charging time of RT1~RT4 by half during the level rise phase.
[0039] Please refer to the above as well. Figure 4B , Figure 4B for Figure 1An example of timing 300 for a touch display panel 100. Timing 300 is similar to timing 200, but differs from timing 200 in the following ways: The gate signal GD may include control signals Da1 to DaN corresponding to a 1-to-N time-division multiplexer (not shown). Control signals Da1 to DaN are signals at the gate terminals of the plurality of switches in the 1-to-N time-division multiplexer. Control signal DaN corresponds to a data line that does not overlap with the conductor TP, and control signal DaN is preferentially enabled over control signals Da1 to DaN-1. Other features of timing 300 are the same as those of timing 200, and therefore will not be described further here.
[0040] Please refer to the above as well. Figure 5 , Figure 5 for Figure 1 Another example of a cross-sectional view of the touch display panel 100 along line A-A'. Figure 5 and Figure 2 resemblance, Figure 5 and Figure 2 The differences are as follows. For example... Figure 5 As shown, the M conductors TP are positioned above the data lines DL1~DL8, and each of the M conductors TP overlaps along direction Z on the data lines DL1~DL8 corresponding to each of the control signals Da1~Da4. To avoid the aforementioned short vertical line problem, the control chip 160 can be used to execute the signal control method OP, which will be described below. Figure 5 Other features and Figure 2 The same applies, so I will not repeat it here.
[0041] Please refer to the above as well. Figure 6 as well as Figure 7A , Figure 6 This is a flowchart of a signal control method OP according to a partial embodiment of the present disclosure. Figure 7A for Figure 5 An example of timing 500 for a touch display panel 100. The signal control method OP includes steps S1 to S3. It should be understood that additional steps may be added before, during, and after steps S1 to S3, and for another part of the implementation of the method, some of the steps mentioned below may be replaced or cancelled, and the order of steps / procedures may be changed. In addition, for the sake of simplicity of the illustration, Figure 7A The control signals Da1~Da4 are represented by squares, and Figure 7A Other characteristics of control signals Da1~Da4 in the data are similar to those in the data. Figure 4A The control signals Da1 to Da4 are similar, so they will not be described in detail here. Figure 7A The gate signals GD1~GD4 are represented by square waves, and other characteristics of the gate signals GD1~GD4 are the same as those of the gate signals GD1~GD4. Figure 4A The gate signal GD is similar to that in the previous example, so it will not be described in detail here.
[0042] First, refer to Figure 1 , Figure 3 , Figure 5 , Figure 6 as well as Figure 7A The signal control method OP proceeds to step S1. During the display period, the peripheral circuit 140 sequentially switches gate lines GL1 to GL4 to the enable level. Gate line GL1 is used as an example below; gate lines GL2 to GL4 can be derived similarly and will not be described further. For example, in frame FR1 during the display period, the peripheral circuit 140 can switch the gate signal GD1 of gate line GL1 to the enable level. In frame FR2 during the display period, the peripheral circuit 140 can switch the gate signal GD2 of gate line GL1 to the enable level. Frames FR3 and FR4 during the display period can be derived similarly and will not be described further here.
[0043] Next, the signal control method OP proceeds to step S2. When one of the gate lines GL1~GL4 has the enabled level, the control chip 160 transmits one of the control signals Da1~Da4 to one of the multiple switches SW1~SW4 of the 1-to-4 time-division multiplexer MUX to turn on the corresponding switch SW1~SW4, thereby turning on one of the data lines DL1~DL4. For example, the gate signals GD1~GD4 of gate line GL1 are used as an example below; the gate signals of gate lines GL2~GL4 can be deduced by analogy, so they will not be described in detail here.
[0044] In frame FR1, when the gate signal GD1 has the enabled level, the control chip 160 sequentially transmits control signals Da1 to Da4 to the 1-to-4 time-division multiplexer MUX to preferentially turn on the switch SW1 corresponding to control signal Da1, thereby preferentially turning on data lines DL5 and DL6. In frame FR2, when the gate signal GD2 has the enabled level, the control chip 160 sequentially transmits control signals Da2, Da3, Da4, and Da1 to the 1-to-4 time-division multiplexer MUX to preferentially turn on the switch SW2 corresponding to control signal Da2, thereby preferentially turning on data lines DL7 and DL8.
[0045] In frame FR3, when the gate signal GD3 has the enable level, the control chip 160 sequentially transmits control signals Da3, Da4, Da1 and Da2 to the 1-to-4 time-division multiplexer MUX to preferentially turn on the switch SW3 corresponding to the control signal Da3, and then preferentially turn on the data lines DL1 and DL2.
[0046] In frame FR4, when the gate signal GD4 has the enable level, the control chip 160 sequentially transmits control signals Da4, Da1, Da2 and Da3 to the 1-to-4 time-division multiplexer MUX to preferentially turn on the switch SW4 corresponding to the control signal Da4, and then preferentially turn on the corresponding data lines DL3 and DL4.
[0047] Next, the signal control method OP proceeds to step S3. When one of the plurality of control signals Da1~Da4 has the enable level, one of the plurality of switches SW1~SW4 is turned on to write data to the data of the plurality of data lines DL1~DL8. The plurality of control signals Da1~Da4 that preferentially switch to the enable level among one of the plurality of frames FR1~FR4 is different from the other plurality of control signals Da1~Da4 that preferentially switch to the enable level among the other plurality of frames FR1~FR4. Furthermore, the switching time of the control signals Da1~Da4 that preferentially switch to the enable level among the frames FR1~FR4 is separated from the data time by the switching time of one of the gate lines GL1~GL4 that switches to the enable level. For example, the gate signals GD1~GD4 of gate line GL1 are used as an example below; the gate lines GL2~GL4 can be deduced similarly, and therefore will not be elaborated further here.
[0048] In frame FR1, control signal Da1 switches to the enable level preferentially over control signals Da2~Da4, and the switching time of gate signal GD1 to the enable level is separated by the data time. In frame FR2, control signal Da2 switches to the enable level preferentially over control signals Da3, Da4, and Da1, and the switching time of gate signal GD2 to the enable level is separated by the data time. In frame FR3, control signal Da3 switches to the enable level preferentially over control signals Da4, Da1, and Da2, and the switching time of gate signal GD3 to the enable level is separated by the data time. In frame FR4, control signal Da4 switches to the enable level preferentially over control signals Da1~Da3, and the switching time of gate signal GD4 to the enable level is separated by the data time.
[0049] It is worth noting that in frames FR1 to FR4, the order in which control signals Da1 to Da4 switch to the enable level is randomized. For example, in frame FR1, except for control signal Da1 which switches to the enable level first, the order of control signals Da2 to Da4 can be randomized. In frame FR2, except for control signal Da2 which switches to the enable level first, the order of control signals Da1, Da3, and Da4 can be randomized. In frame FR3, except for control signal Da3 which switches to the enable level first, the order of control signals Da1, Da2, and Da4 can be randomized. In frame FR4, except for control signal Da4 which switches to the enable level first, the order of control signals Da1 to Da3 can be randomized.
[0050] Furthermore, within frames FR1 to FR4, the control signals Da1 to Da4 that preferentially switch to the enable level are arranged in a random order, and the number of times each of the control signals Da1 to Da4 preferentially switches to the enable level is the same as the number of times the other of the control signals Da1 to Da4 preferentially switches to the enable level. For example, in other embodiments, within frames FR1 to FR4, the order of the control signals Da1 to Da4 that preferentially switch to the enable level can be control signal Da4, control signal Da1, control signal Da3, and control signal Da2, and is not limited to the order of 1 to 4, and the number of times each of the control signals Da1 to Da4 preferentially switches to the enable level is the same.
[0051] In detail, in other embodiments, in frame FR1, control signal Da4 switches to the enable level preferentially over control signals Da1~Da3, and the order in which control signals Da1~Da3 switch to the enable level can be randomized. In frame FR2, control signal Da1 switches to the enable level preferentially over control signals Da2~Da4, and the order in which control signals Da2~Da4 switch to the enable level can be randomized. In frame FR3, control signal Da3 switches to the enable level preferentially over control signals Da1, Da2, and Da4, and the order in which control signals Da1, Da2, and Da4 switch to the enable level can be randomized. In frame FR4, control signal Da2 switches to the enable level preferentially over control signals Da1, Da3, and Da4, and the order in which control signals Da1, Da3, and Da4 switch to the enable level can be randomized. It is worth mentioning that, in frame FR1 to frame FR4, each of the control signals Da1 to Da4 preferentially switches to the enable level the same number of times.
[0052] In this way, by setting the priority switching order of different control signals Da1 to Da4 in the frame FR1~FR4, the position of the short vertical line SL can be made variable, thereby reducing the severity of the short vertical line SL. Furthermore, the rising phases RT1~RT4 (refer to...) can also be controlled. Figure 4A It adds half the charging time.
[0053] Please refer to the above as well. Figure 7B , Figure 7B for Figure 1 An example of timing 600 of the touch display panel 100. Timing 600 is similar to timing 500, but the difference between timing 600 and timing 500 is as follows: Timing 600 has N gate signals GD1 to GDN corresponding to frames FR1 to FRN, and each gate signal GD1 to GDN includes control signals Da1 to DaN. Other features of timing 600 are the same as those of timing 500, and therefore will not be described further here.
[0054] It is worth noting that this disclosure addresses problems in automotive applications and proposes a solution (MobilitySolution). Please refer to... Figure 8 . Figure 8 This is an example of a vehicle display device 700 according to a partial embodiment of the present disclosure. The vehicle display device 700 can be applied to a head-up display, but is not limited thereto. The vehicle display device 700 may include a base 720 and a touch display panel 740. The base 720 may be disposed in the driver's area (DR) of a vehicle 900. The touch display panel 740 may be disposed on the base 720 for projecting information (e.g., vehicle speed) from a data processing device (not shown) onto the windshield (WS), wherein the touch display panel 740 includes... Figure 1 The touch display panel 100 shown.
[0055] Please refer to the above as well. Figure 9A as well as Figure 9B , Figure 9A for Figure 8 An example of the timing 800 of an automotive display device 700. Figure 9B for Figure 8The image shows a top view of the automotive display device 700. Timing 800 is similar to timing 500, but the differences are as follows: Timing 800 has gate signals GD1A and GD1B, GD2A and GD2B, GD3A and GD3B, and GD4A and GD4B corresponding to frames FR1 to FR4, respectively. Taking gate signals GD1A and GD1B as an example, gate signals GD2A and GD2B, GD3A and GD3B, and GD4A and GD4B can be derived similarly, and will not be described further. Gate signals GD1A and GD1B are front and rear stage signals. For example, in frame FR1, gate signal GD1A is initially at an enabled level. Then, gate signal GD1A switches to a disabled level. In frame FR1, gate signal GD1B is initially at a disabled level. Then, gate signal GD1B switches to an enabled level. Furthermore, the other characteristics of gate signals GD1A and GD1B are the same as those of gate signal GD1, so they will not be described again here.
[0056] Furthermore, such as Figure 9B As shown, a short vertical line SL appears on the sensing circuit 180, and the height H1 of the short vertical line SL is the same as the height H2 of the sensing circuit 180. However, the short vertical line SL is almost invisible to the human eye. Therefore, by employing the signal control method OP and timing 800 described above, the severity of the short vertical line SL in the automotive display device 700 can be effectively and significantly reduced.
[0057] This disclosure provides, in some embodiments, a signal control method, a touch display panel, and an automotive display device. When a specific data line overlaps vertically with a trace transmitting a common electrode signal, the data lines in the display circuit that do not overlap with the trace are preferentially activated. This prevents the data signals of the data lines from being affected by the common electrode signal, thus avoiding coupling to incorrect levels by the common electrode signal. This avoids the problem of short vertical lines appearing on the display screen. Alternatively, when the data line corresponding to each control signal may overlap vertically with the trace transmitting the common electrode signal, different activation sequences of the data lines are set in different screens. This causes the data signals of the data lines to be affected by the common electrode signal in an out-of-order manner, thus making the position of the short vertical lines variable. This improves the problem of short vertical lines appearing on the display screen.
[0058] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand the various implementations of this application. Those skilled in the art will understand that they can readily use this application as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the concept and scope of this application, and that various changes, substitutions, and modifications can be made herein without departing from the concept and scope of this application.
Claims
1. A signal control method applicable to a touch display panel, wherein the touch display panel includes a plurality of gate lines, a plurality of data lines, a plurality of wires, a plurality of sensing circuits, a peripheral circuit, and a control chip, the peripheral circuit being coupled to the gate lines, the sensing circuits being coupled to the wires, and the control chip being coupled to the data lines and the wires respectively, the signal control method comprising: During a display, these gate lines are sequentially switched to a consistent energy level via the peripheral circuitry; When one of the gate lines has the enable level, one of the multiple control signals is transmitted through the control chip to one of the multiple switches of a time-division multiplexer, wherein one of the switches is connected to one of the data lines. When one of the control signals has the enable level, one of the switches is turned on to write data to one of the data lines; Among the multiple picture frames, one of the control signals that preferentially switches to the enable level is different from another of the control signals that preferentially switches to the enable level in another of the picture frames; and In the case of the frames, the number of times the control signals of one of the frames preferentially switch to the enable level is the same as the number of times the control signals of the other of the frames preferentially switch to the enable level.
2. The signal control method of claim 1, wherein the wires are disposed above the data lines, and each of the wires overlaps the data line corresponding to each of the control signals.
3. The signal control method as described in claim 1, wherein the order in which the control signals switch to the enable level in the frames is out of order.
4. The signal control method as claimed in claim 1, wherein in the frames, each of the control signals preferentially switches to the enable level an equal number of times.
5. The signal control method as described in claim 1, wherein the order in which the control signals preferentially switch to the enable level are arranged in random order within the frames.
6. The signal control method of claim 1, wherein the enable period of the gate lines is greater than the enable period of the control signals.
7. The signal control method of claim 1, wherein the enable period of the gate lines includes a start phase, a plurality of enable phases, a plurality of disable phases and an end phase, the start phase taking precedence over the enable phases and the disable phases, wherein the sum of the enable period of the start phase and one of the enable phases is between 1.8 microseconds and 2 microseconds.
8. The signal control method of claim 1, wherein the control signals are separated from each other by a data time, the data time being defined as the time during which the peripheral circuit drives a corresponding column of pixels in each frame time.
9. The signal control method of claim 8, wherein the switching time of the control signals that preferentially switch to the enable level among the frames is separated from the data time by the switching time of the gate lines switching to the enable level.
10. A touch display panel, comprising: One substrate; A peripheral circuit is disposed on the substrate, wherein the peripheral circuit is coupled to a plurality of gate lines; A control chip is disposed on the substrate, wherein the control chip is coupled to multiple data lines and multiple wires, and the wires are located above the data lines; Multiple sensing circuits are disposed on the substrate, wherein the sensing circuits are coupled to the wires; During a display period, the peripheral circuitry is used to sequentially switch the gate lines to a consistent energy level; The control chip is used to transmit one of a plurality of control signals to one of a plurality of switches of a time-division multiplexer when one of the gate lines has the enable level, wherein one of the switches is connected to one of the data lines. When one of the control signals has the enable level, one of the switches is turned on to write data to one of the data lines; Among the multiple picture frames, one of the control signals that preferentially switches to the enable level is different from another of the control signals that preferentially switches to the enable level in another of the picture frames; and In the case of the frames, the number of times the control signals of one of the frames preferentially switch to the enable level is the same as the number of times the control signals of the other of the frames preferentially switch to the enable level.
11. The touch display panel of claim 10, wherein each of the conductors overlaps with one of the data lines corresponding to one of the control signals.
12. The touch display panel of claim 10, wherein each of the wires overlaps with the data lines corresponding to each of the control signals.
13. The touch display panel of claim 10, wherein the order in which the control signals switch to the enable level in the frames is out of order.
14. The touch display panel of claim 10, wherein in the frames, each of the control signals preferentially switches to the enable level an equal number of times.
15. The touch display panel of claim 10, wherein the order in which the control signals preferentially switch to the enable level are arranged in random order within the frames.
16. The touch display panel of claim 10, wherein the enable period of the gate lines is greater than the enable period of the control signals.
17. The touch display panel of claim 10, wherein the enable period of the gate lines includes a start phase, a plurality of enable phases, a plurality of disable phases and an end phase, the start phase taking precedence over the enable phases and the disable phases, wherein the sum of the enable period of the start phase and one of the enable phases is between 1.8 microseconds and 2 microseconds.
18. The touch display panel of claim 10, wherein the control signals are separated from each other by a data time, the data time being defined as the time during which the peripheral circuitry drives a corresponding column of pixels in each frame time.
19. The touch display panel of claim 18, wherein the switching time of the control signals that preferentially switch to the enable level among the frames is separated from the switching time of the gate lines that switch to the enable level by the data time.
20. A vehicle display device, comprising: A base, installed on a vehicle; as well as The touch display panel as described in claim 10 is disposed on the base.