Wafer three-dimensional measurement data analysis method and device, equipment and storage medium

Abstract

The invention discloses a wafer three-dimensional measurement data analysis method and device, equipment and a storage medium. The method comprises the steps of obtaining three-dimensional shape data of each interconnection structure in a wafer; extracting three-dimensional shape characteristic parameters of each interconnection structure and generating a three-dimensional structure model; carrying out statistics on the characteristic parameters of the plurality of interconnection structures in the same Die to obtain Die-level statistics; generating a multi-level visual interface comprising an interconnection structure level view, a Die level view and a wafer level view; and establishing a hierarchical association structure among the three-level views to realize linkage display of different hierarchical views. According to the method, hierarchical association is carried out on microscopic interconnection structure data and macroscopic wafer distribution by constructing interconnection structure level, Die level and wafer level multi-level visual interfaces, so that the defect that a traditional table is separated from red and green image data is effectively overcome, comprehensive process analysis from the whole to the local and from the macroscopic to the microscopic is realized, and the process analysis efficiency is improved. And the depth and efficiency of process defect diagnosis are obviously improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a wafer three-dimensional measurement data analysis method, a wafer three-dimensional measurement data analysis system, an electronic device, a computer-readable storage medium, and a computer program product. Background Technology

[0002] In the field of wafer manufacturing and inspection, three-dimensional measurement and analysis of interconnect structures on wafers is a key step in ensuring packaging quality. The data involved is multi-scale and multi-dimensional, specifically including: the size of individual interconnect structures, the size distribution of all interconnect structures within a single die, and the macroscopic distribution of die quality across the entire wafer.

[0003] Currently, mainstream data analysis systems in the industry typically present and analyze the aforementioned complex multidimensional data using two-dimensional tables and simple statistical charts (e.g., red-green graphs). This traditional method has significant drawbacks: First, tabular data is not intuitive enough, making it difficult to quickly and vividly capture spatial distribution patterns and microscopic anomalies; second, simple statistical charts can only provide die-level pass / fail information, failing to reveal the specific process conditions of each interconnect structure within the die, thus obscuring a large amount of valuable microscopic three-dimensional morphological information. These limitations severely restrict the depth and efficiency of process defect diagnosis, leading to extended process debugging cycles and difficulties in improving yield. Summary of the Invention

[0004] In view of the lack of the above-mentioned related technologies, the purpose of this application is to disclose a wafer three-dimensional measurement data analysis method, a wafer three-dimensional measurement data analysis system, an electronic device, a computer-readable storage medium, and a computer program product to solve various problems in the related technologies.

[0005] This application discloses a method for analyzing three-dimensional measurement data of wafers, including the following steps:

[0006] Acquire three-dimensional morphological data of each interconnect structure in the wafer;

[0007] Based on the three-dimensional topography data of each interconnect structure, at least one three-dimensional topography feature parameter of each interconnect structure is extracted, a three-dimensional structural model corresponding to each interconnect structure is generated, and an interconnect structure-level view is generated based on the three-dimensional structural model.

[0008] According to the preset die division rules, the three-dimensional topographic feature parameters of multiple interconnected structures located in the same die region are statistically analyzed to obtain die-level statistics, and a die-level view is generated based on the die-level statistics.

[0009] Generate a wafer-level view based on the aforementioned die-level statistics;

[0010] Establish a hierarchical relationship structure between the interconnect structure level, the die level, and the wafer level, and realize the linkage display of different level views based on the hierarchical relationship structure.

[0011] In some embodiments of this application, the three-dimensional topography data includes three-dimensional point cloud data; the step of generating a three-dimensional structural model corresponding to each interconnect structure includes: extracting at least one three-dimensional topography feature parameter for each interconnect structure based on the three-dimensional point cloud data, and rendering the three-dimensional point cloud data of the interconnect structure to generate an interactive interconnect structure geometric topography model.

[0012] In some embodiments of this application, based on the interconnect structure geometry model, at least one of the following interactive operations is performed: in response to a viewpoint operation on the interconnect structure geometry model, the interconnect structure geometry model is rotated or scaled; in response to a line drawing operation performed on the interconnect structure geometry model, the pixel coordinates of the drawn line segments are mapped to a three-dimensional point cloud space, and geometric parameters are calculated based on the mapping result; a camera-captured view of the interconnect structure is simultaneously displayed for comparative analysis with the interconnect structure geometry model.

[0013] In some embodiments of this application, the step of mapping the pixel coordinates of the drawn line segment to a three-dimensional point cloud space includes: recording the screen pixel coordinates of the start and end points of the line segment; calculating the three-dimensional spatial ray corresponding to the screen coordinates through inverse transformation based on the projection matrix and model view matrix of the current view; calculating the intersection point of the three-dimensional spatial ray and the three-dimensional structure model to obtain the actual coordinates of the line segment endpoint in the three-dimensional point cloud space.

[0014] In some embodiments of this application, the step of generating a die-level view includes generating a die-level heatmap. The step of generating a die-level heatmap includes: mapping three-dimensional morphological feature parameter values ​​located within a set parameter mapping interval to corresponding gradient colors according to a preset color mapping table, wherein the color mapping table divides the parameter mapping interval into multiple color levels and assigns a corresponding color value to each color level, wherein the color value gradients from a first color to a second color; configuring abnormal color mapping rules to map three-dimensional morphological feature parameter values ​​located outside the parameter mapping interval to abnormal colors; and drawing a graphic area with a corresponding color at the corresponding position for each interconnect structure within the die view area, thereby generating a die-level heatmap.

[0015] In some embodiments of this application, the step of configuring the abnormal color mapping rule includes: mapping parameter values ​​below the parameter mapping range to a first abnormal color, and mapping parameter values ​​above the parameter mapping range to a second abnormal color, so as to distinguish between low-abnormal and high-abnormal regions in the Die-level heatmap.

[0016] In some embodiments of this application, the step of generating a wafer-level view includes at least one of the following: generating a wafer-level heat map based on the statistical parameters of the three-dimensional topographic features of the interconnect structure within the die, and supporting dynamic switching of the statistical parameters used to generate the wafer-level heat map; labeling each die with a pass or fail label according to predefined rules, and generating a wafer-level contrast color view, wherein a first contrast color is used to represent a pass die and a second contrast color is used to represent a fail die, and the first contrast color and the second contrast color are two visually distinguishable colors.

[0017] In some embodiments of this application, the method further includes a view interaction linkage step: in response to the selection operation of a target region in the wafer-level thermal map, switching to the die-level view corresponding to the target region and displaying detailed information of the die; and / or, in response to the selection operation of a failed die in the wafer-level contrast color view, displaying information of all failed interconnect structures within the failed die and linking to the interconnect structure-level view to display the three-dimensional structural model of the corresponding failed interconnect structure.

[0018] In some embodiments of this application, the method further includes a data optimization processing step, which includes: rendering only the interconnect structure data within the current field of view; and hierarchically storing the interconnect structure data, wherein the data storage priority of failed interconnect structures is higher than that of qualified interconnect structures.

[0019] In some embodiments of this application, the interconnect structure includes at least one of the following: bump interconnect structure, via interconnect structure, planar wiring interconnect structure, and pad interconnect structure.

[0020] In some embodiments of this application, the three-dimensional topographic feature parameters are determined according to the type of interconnect structure: when the interconnect structure is a bump interconnect structure, the three-dimensional topographic feature parameters include at least one of height, diameter, and coplanarity; when the interconnect structure is a via interconnect structure, the three-dimensional topographic feature parameters include at least one of aperture, depth, aspect ratio, and sidewall roughness; when the interconnect structure is a planar wiring interconnect structure, the three-dimensional topographic feature parameters include at least one of line width, line thickness, line spacing, and surface roughness; when the interconnect structure is a pad interconnect structure, the three-dimensional topographic feature parameters include at least one of height, diameter, surface roughness, and coplanarity.

[0021] This application also discloses a wafer three-dimensional metrology data analysis device, comprising:

[0022] The data acquisition module is used to acquire the three-dimensional morphology data of each interconnect structure in the wafer;

[0023] The interconnect structure-level analysis module is used to extract at least one three-dimensional morphological feature parameter of each interconnect structure based on the three-dimensional morphological data of each interconnect structure, generate a three-dimensional structural model corresponding to each interconnect structure, and generate an interconnect structure-level view based on the three-dimensional structural model.

[0024] The Die-level analysis module is used to statistically analyze the three-dimensional morphological feature parameters of multiple interconnected structures located in the same Die region according to a preset Die division rule, obtain Die-level statistics, and generate a Die-level view based on the Die-level statistics.

[0025] A wafer-level analysis module is used to generate a wafer-level view based on the die-level statistics;

[0026] The hierarchical association and linkage module is used to establish hierarchical association structures between interconnection structure level, die level, and wafer level, and to realize the linkage display of different hierarchical views based on the hierarchical association structure.

[0027] In some embodiments of this application, the three-dimensional topography data includes three-dimensional point cloud data; the interconnect structure-level analysis module is further configured to process the three-dimensional point cloud data, and is able to extract at least one three-dimensional topography feature parameter of each interconnect structure based on the three-dimensional point cloud data, and render the three-dimensional point cloud data of the interconnect structure to generate an interactive interconnect structure geometric topography model.

[0028] In some embodiments of this application, the generation of the die-level view includes a die-level heatmap; the die-level analysis module includes: a color mapping unit, used to map the three-dimensional morphological feature parameter values ​​located within a set parameter mapping interval to corresponding gradient colors according to a preset color mapping table, wherein the color mapping table divides the parameter mapping interval into multiple color levels, and each color level gradually changes from a first color to a second color; an abnormal color mapping unit, used to configure abnormal color mapping rules to map the three-dimensional morphological feature parameter values ​​located outside the parameter mapping interval to abnormal colors; and a heatmap generation unit, used to draw a graphic area with a corresponding color at the corresponding position for each interconnect structure within the die view area, thereby generating a die-level heatmap.

[0029] In some embodiments of this application, the wafer-level analysis module includes: a wafer-level heat map generation unit, used to generate a wafer-level heat map based on the statistical parameters of the three-dimensional topographic features of the interconnect structure within the die, and supporting dynamic switching of the statistical parameters used to generate the wafer-level heat map; and / or, a wafer-level contrast color view generation unit, used to label each die with a pass or fail label according to predefined rules, and generate a wafer-level contrast color view, wherein a first contrast color is used to represent a pass die and a second contrast color is used to represent a fail die, and the first contrast color and the second contrast color are two visually distinguishable colors.

[0030] In some embodiments of this application, the hierarchical association and linkage module is configured to: in response to a selection operation of a target region in the wafer-level thermal map, switch to the die-level view of the die corresponding to the target region and display detailed information of the die; and / or, in response to a selection operation of a failed die in the wafer-level contrast color view, display information of all failed interconnect structures within the failed die and link to the interconnect structure-level analysis module to display the three-dimensional structural model of the corresponding failed interconnect structure.

[0031] This application discloses another electronic device, including:

[0032] processor;

[0033] The memory stores a computer program that, when executed by the processor, implements the steps of the wafer three-dimensional measurement data analysis method as described above.

[0034] Display devices for presenting interconnect structure-level views, die-level views, and wafer-level views;

[0035] An input device is used to receive operation instructions for the view and trigger cross-level linked display based on the hierarchical relationship structure.

[0036] This application further discloses a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the wafer three-dimensional measurement data analysis method as described above.

[0037] This application also discloses a computer program product, including a computer program that, when executed by a processor, implements the steps of the wafer three-dimensional measurement data analysis method as described above.

[0038] This application discloses a wafer 3D metrology data analysis method, a wafer 3D metrology data analysis system, an electronic device, a computer-readable storage medium, and a computer program product. The analysis method acquires the 3D morphology data of each interconnect structure in the wafer, extracts the 3D morphology feature parameters of each interconnect structure, generates a 3D structural model, and then obtains die-level statistics. It generates a multi-level visualization interface including interconnect structure-level views, die-level views, and wafer-level views, and establishes a hierarchical relationship between the three levels to achieve linked display of different levels of views. This technical solution, by constructing a multi-level visualization interface and hierarchically associating micro-interconnect structure data with macro-wafer distribution, not only transforms the 3D morphology data of a single interconnect structure into an interactive 3D structural model, allowing for intuitive observation and precise measurement of micro-defects, but also intuitively displays the spatial distribution of interconnect structure parameters and failure areas through color mapping and abnormal color rules of the die-level heatmap. Furthermore, it quickly locates failed dies and analyzes the process trends of the entire wafer through wafer-level heatmaps and contrasting color views. By establishing a three-level dynamic hierarchical relationship structure of "interconnect structure - die - wafer," the system enables linked analysis of "wafer positioning → die focusing → interconnect structure verification," completely breaking through the bottlenecks of scale fragmentation and process interruption in traditional analysis. Compared with existing technologies, this solution can significantly improve defect diagnosis efficiency, significantly shorten process debugging cycles, and provide intuitive, accurate, and efficient technical support for quality control and yield improvement in advanced packaging, demonstrating significant application value and economic benefits. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 The diagram shown is a flowchart of one embodiment of the three-dimensional measurement data analysis method of this application.

[0041] Figure 2 A schematic diagram of the interface is shown as an interconnect structure-level view in one embodiment.

[0042] Figure 3 A schematic diagram of the interface shown as a die-level view in one embodiment.

[0043] Figure 4 The diagram shows an interface schematic of a wafer-level thermal map in one embodiment.

[0044] Figure 5The diagram shown is a structural schematic of one embodiment of the wafer three-dimensional measurement data analysis device of this application.

[0045] Figure 6 The diagram shown is a structural schematic of the electronic device of this application in one embodiment. Detailed Implementation

[0046] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0047] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “corresponding,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0048] In advanced packaging, the three-dimensional morphology parameters of interconnect structures are key indicators for evaluating interconnect quality. Different types of interconnect structures have different key characteristic parameters. To achieve high-efficiency, non-contact measurement, optical 3D inspection technologies are widely used, among which equipment such as structured light scanning systems, white light interferometers, or laser confocal microscopes can acquire high-density 3D measurement data of the wafer surface. However, the effective analysis and visualization of massive amounts of 3D measurement data has become a new challenge. Traditional statistical methods based on two-dimensional tables and simple red-green plots can no longer meet the needs of advanced processes for multi-dimensional, multi-scale data analysis.

[0049] Taking bumps as an example, existing technologies typically employ two methods to analyze 3D measurement data of bumps: First, simplifying the 3D point cloud data into a 2D table format, presenting parameters such as the height and diameter of each bump as a numerical list. While this method retains accurate measurement values, it fails to intuitively present the spatial distribution patterns and 3D morphological characteristics of the bumps, making it difficult for users to quickly identify abnormal patterns from the table data. Second, simplifying die-level yield information into a binary "red-green diagram," using red to represent failed dies and green to represent qualified dies for macroscopic statistics. Although this method can quickly locate the position of failed dies, it completely loses the specific process conditions of each bump within the die, failing to reveal the root cause of the failure. This analysis method, which separates multi-scale, multi-dimensional data into tables and red-green diagrams, severs the intrinsic connection between the microscopic bump morphology and the macroscopic wafer distribution, ignoring a large amount of valuable microscopic 3D information, and severely limiting the depth and efficiency of process defect diagnosis.

[0050] In view of this, this application discloses a wafer 3D metrology data analysis method, a wafer 3D metrology data analysis system, an electronic device, a computer-readable storage medium, and a computer program product. The wafer 3D metrology data analysis method acquires the 3D morphology data of each interconnect structure in the wafer, extracts the 3D morphology feature parameters of each interconnect structure, generates a 3D structural model, and then obtains die-level statistics. It generates a multi-level visualization interface including interconnect structure-level views, die-level views, and wafer-level views, and establishes a hierarchical relationship between the three levels to achieve linked display of different levels of views. This technical solution, by constructing a multi-level visualization interface and hierarchically associating micro-interconnect structure data with macro-wafer distribution, effectively overcomes the shortcomings of traditional tables and red-green graphs that separate data, significantly improving the depth and efficiency of process defect diagnosis.

[0051] The following detailed description of the wafer three-dimensional measurement data analysis method of this application is provided in conjunction with specific embodiments.

[0052] It should be noted that, in this application, the interconnect structure includes at least one of the following: bump interconnect structure, via interconnect structure, planar wiring interconnect structure, and pad interconnect structure. Bump interconnect structure can be, for example, a bump, whose three-dimensional morphological parameters may include, but are not limited to, height, diameter, and coplanarity; these parameters directly affect the reliability of flip-chip bonding. Via interconnect structure can be, for example, through-silicon vias (TSVs) and through-glass vias (TGVs); its three-dimensional morphological parameters may include, but are not limited to, aperture, depth, aspect ratio, and sidewall roughness; these parameters determine its electrical performance. Planar wiring interconnect structure can be, for example, a redistribution layer (RDL); its three-dimensional morphological parameters may include, but are not limited to, line width, line thickness, line spacing, and surface roughness; these parameters affect wiring density and signal transmission. Pad-type interconnect structures can be, for example, copper pads or aluminum pads. Their three-dimensional morphological parameters can include, but are not limited to, height, diameter, surface roughness, and coplanarity. These parameters affect the reliability of soldering.

[0053] In the following specific embodiments, we will use a bump as an example for detailed description.

[0054] Please see Figure 1 The diagram shown is a flowchart of the three-dimensional measurement data analysis method of this application in one embodiment.

[0055] like Figure 1 As shown, the wafer three-dimensional measurement data analysis method of this application includes the following steps:

[0056] Step S110: Obtain the three-dimensional morphology data of each interconnect structure in the wafer.

[0057] Taking bumps as an example, bumps in a wafer are three-dimensional interconnect structures formed on the wafer surface using bump fabrication processes in advanced semiconductor packaging. The aim is to utilize bumps to achieve electrical and physical connections between dies, between dies and substrates, between substrates, and between substrates and the motherboard. Common bump fabrication processes include electroplating, ball bonding, printing, or jetting.

[0058] These bumps are not randomly distributed, but strictly follow the design rules of integrated circuits or packages, arranged according to a preset layout. This layout is precisely defined by the wafer's bump layout design file, which defines the theoretical center coordinates, shape, size, and spacing between each bump. These bumps are typically arranged in a regular array, with the arrangement corresponding one-to-one to the input / output pad design of the die (also known as a chip or bare die). Typical bump sizes range from tens of micrometers in diameter to less than 10 micrometers, and the spacing between adjacent bumps can also be reduced from tens of micrometers to less than 10 micrometers.

[0059] Three-dimensional topography data can be acquired through a three-dimensional measurement module, which can employ non-contact optical three-dimensional measurement technology, such as a white light interferometer, laser confocal microscope, or structured light scanning system. Taking a structured light scanning system as an example, its working principle is as follows: The structured light projection module projects an coded grating pattern (e.g., phase-shifted sinusoidal fringe light, Gray code pattern, etc.) onto the wafer surface. After being modulated by the three-dimensional topography of the bumps, the deformed fringe image is simultaneously captured by a structured light camera. Based on algorithms such as phase measurement profilometry, combined with pre-calibrated system parameters, the fringe phase information is calculated to obtain the three-dimensional coordinates (X, Y, Z) corresponding to each pixel, thereby generating a dense three-dimensional point cloud. Each coordinate point in the three-dimensional point cloud contains X, Y, and Z coordinates, where the X, Y, and Z coordinates are mutually perpendicular. The X and Y coordinates constitute the wafer's horizontal plane, and the Z coordinate corresponds to the height information perpendicular to the wafer's horizontal plane.

[0060] Furthermore, in some embodiments, a two-dimensional image acquisition module may be included to simultaneously acquire two-dimensional images of the wafer surface. A pixel-level one-to-one mapping relationship is established between the two-dimensional images and the three-dimensional point cloud data through precise system calibration, ensuring that each pixel in the two-dimensional image corresponds to a spatial coordinate point in the three-dimensional point cloud. This registration mechanism between two-dimensional and three-dimensional data provides a precise spatial reference for subsequent bump recognition, localization, and feature extraction.

[0061] In addition to 3D point cloud data, the acquired 3D topographic data may also include 3D mesh model data and height field image data. The 3D mesh model is a surface mesh representation generated by triangulation of point cloud data, suitable for 3D rendering and visualization; the height field image maps 3D height information to grayscale values ​​of a 2D image, suitable for quick preview and preliminary analysis.

[0062] Step S120: Based on the three-dimensional topography data of each interconnect structure, extract at least one three-dimensional topography feature parameter of each interconnect structure, generate a three-dimensional structural model corresponding to each interconnect structure, and generate an interconnect structure-level view based on the three-dimensional structural model.

[0063] In step S120, the three-dimensional morphology of the interconnect structure is modeled.

[0064] After acquiring the 3D topographic data of each interconnect structure, it is necessary to separate the point cloud subset of each interconnect structure from the massive 3D point cloud data, and then extract its 3D topographic feature parameters and reconstruct the 3D structure model.

[0065] Taking convex blocks as an example, it is necessary to separate the point cloud subset of each convex block from the massive 3D point cloud data.

[0066] The purpose of bump identification and segmentation is to separate point cloud data belonging to different bumps, laying the foundation for subsequent individual bump analysis. Since bumps on the wafer surface are usually arranged in a regular array and each bump has a similar three-dimensional shape, individual bumps on the wafer surface can be identified and segmented.

[0067] In some embodiments, guided segmentation can be implemented based on bump design layout files. Specifically, the bump layout design layout file of the wafer (e.g., GDSII or OASIS format file) is first imported. This file specifies the theoretical center coordinates (Xc, Yc) of each bump, as well as the shape and size of the bump. Based on these theoretical coordinates, a region of interest (ROI) can be defined for each bump in the 3D point cloud data, such as a circular or rectangular region centered on the theoretical center and bounded by the bump spacing. Subsequently, a local point cloud clustering algorithm is performed within this ROI to extract the actual point cloud belonging to that bump. This segmentation method fully utilizes the layout design information, effectively handles cases with small bump position offsets, and offers high computational efficiency and robustness.

[0068] In some embodiments, autonomous segmentation can be implemented based on height thresholds and connected component analysis, suitable for scenarios where there are no design layout files or where it is necessary to verify the deviation between the design and the actual situation. Specifically, the process begins by analyzing the point cloud height distribution of the wafer substrate region to fit a substrate reference surface and setting a height threshold. For example, this height threshold could be the substrate height plus half the minimum bump height. Point clouds exceeding this threshold are marked as bump candidate points. Connected component analysis is then performed on these candidate points, aggregating spatially adjacent point clouds into independent bump point cloud clusters. Considering the potential for small gaps between adjacent bumps, the neighborhood radius used in the connected component analysis should be smaller than the minimum bump spacing. Finally, morphological filtering is applied to each bump point cloud cluster to remove noise points with excessively small areas or abnormal clusters of multiple excessively large bumps that are stuck together.

[0069] In some embodiments, hybrid segmentation can be assisted by two-dimensional images. As mentioned earlier, when a two-dimensional image is synchronously acquired through the equipped two-dimensional image acquisition module, the high-resolution edge information of the two-dimensional image can be used to assist in three-dimensional segmentation. In specific implementation, the planar contours of convexities are first extracted from the two-dimensional image using image processing algorithms such as Canny edge detection and morphological segmentation. Then, based on the pixel-level mapping relationship between the two-dimensional image and the three-dimensional point cloud, the two-dimensional contours are mapped to the three-dimensional point cloud space as boundary constraints for three-dimensional point cloud segmentation. This implementation method is particularly suitable for scenarios where the convex spacing is extremely small and there is occlusion or reflection interference in the point cloud data.

[0070] After obtaining the point cloud of each convex using any of the above segmentation methods, multiple 3D topographic feature parameters can be extracted to quantitatively describe the geometric properties of the convex. The extraction of 3D topographic feature parameters involves various algorithms such as point cloud processing, geometric fitting, and numerical calculation.

[0071] The three-dimensional topographic parameters of the bump, such as height, diameter, and coplanarity, all require the wafer substrate as a reference. Therefore, it is essential to accurately determine the substrate position on the wafer surface first. However, the area surrounding the bump may not be an ideal plane and may contain minor undulations or tilts. To address this, a robust plane fitting algorithm can be employed, such as the plane fitting algorithm based on Random Sample Consensus (RANSAC). This algorithm randomly samples points from the point cloud surrounding the bump to fit a plane, iteratively optimizing to eliminate outliers such as bump sidewall points or substrate defect points, ultimately obtaining a reference plane that best represents the true height of the substrate. This substrate reference plane can be mathematically represented as Ax + By + Cz + D = 0, where A, B, and C determine the tilt direction of the plane, and D determines the elevation position of the plane.

[0072] After obtaining the base reference plane, the height of the bump can be calculated. The bump height is defined as the vertical distance from the highest point of the bump's top to the base reference plane. In practice, this is done by searching for a point or local highest region with the maximum Z-coordinate value in the bump point cloud; let the coordinates of this point be (x0, y0, z0). Then, the vertical distance from this point to the base reference plane is calculated using the following formula:

[0073]

[0074] The geometric meaning of this formula is: substituting the coordinates (x0, y0, z0) of a point into the left side of the equation Ax + By + Cz + D = 0 of the base reference plane, obtaining a numerical value, taking the absolute value, and then dividing by the plane normal vector. The length of the point is the vertical distance from the point to the plane, specifically the height. In some embodiments, to reduce the impact of single-point noise, the average height of multiple high points in the top region can be selected as the bump height.

[0075] The bump diameter is typically defined as the diameter of the transverse cross-section at a specific height, with a commonly used reference height being 50% of the bump height, i.e., the half-height position. That is, a cutting plane parallel to the base reference plane is first generated at 50% of the bump height, and then the point cloud cross-section intersecting this plane is extracted. Taking a circular bump as an example, circle fitting of the cross-sectional point cloud can be performed using the least squares (LS) method or the random sample consensus (RANSAC) algorithm to obtain the diameter of the fitted circle as the bump diameter. For irregularly shaped bumps, the equivalent circular diameter of the cross-section, i.e., the diameter of a circle with the same area as the cross-section, can be calculated as a supplementary parameter. A similar approach can be used for bumps of other shapes.

[0076] Coplanarity is used to characterize the height consistency of the tops of multiple bumps within the same die region. In practice, a plane fitting is performed on the point cloud of the top regions of all bumps within the same die region, for example, the portion above 90% of the bump height, to obtain a top-fitted plane. Then, the vertical distance from the highest point of each bump top to this fitted plane is calculated. The difference between the maximum and minimum values ​​of these vertical distances is the coplanarity value of the die. A smaller coplanarity value indicates a flatter bump top, which is beneficial for subsequent flip-chip bonding processes.

[0077] In addition to the basic parameters mentioned above, various auxiliary parameters can be extracted to comprehensively describe the three-dimensional morphological features of the bump. For example, the bump volume is calculated by triangulating the bump point cloud and calculating the volume enclosed by the mesh. The sidewall inclination angle is calculated by fitting the point cloud of the bump sidewall as a conical or cylindrical surface and calculating the angle between the sidewall and the substrate normal. The surface roughness is calculated by taking the root mean square of the residual of the point cloud in the top region of the bump relative to the fitted spherical cap or fitted plane. The position offset is calculated by deviating between the actual center and the theoretical center of the bump, reflecting the alignment accuracy of the photolithography or electroplating process.

[0078] Based on convex block-based 3D point cloud data, corresponding 3D structural models can be generated for visualization and detailed analysis.

[0079] In some embodiments of this application, the step of generating a three-dimensional structural model corresponding to each interconnect structure includes: rendering the three-dimensional point cloud data of the interconnect structure to generate an interactive geometric model of the interconnect structure.

[0080] Taking a bump as an example, the steps for generating a 3D structural model of the bump are as follows: render the 3D point cloud data of the bump to generate an interactive spherical cap model. The spherical cap model can realistically reflect the 3D morphology of the bump, including the shape of the top spherical cap, the contour of the sidewalls, and the transition area between the bottom and the wafer substrate. For normal bumps, the morphology is usually a combination of a bottom cylinder and a top spherical cap. For bumps with defects, they may exhibit abnormal morphologies such as collapse, bridging, tilting, or uneven surface.

[0081] The generation of a 3D structural model involves steps such as point cloud preprocessing, surface reconstruction, and model optimization.

[0082] Raw point cloud data may contain noise, outliers, or uneven sampling, directly affecting the quality of the reconstructed model. Therefore, preprocessing is necessary. In practice, statistical filtering can be used to remove isolated noise points far from the main point cloud. Then, the point cloud is smoothed using the Moving Least Squares (MLS) algorithm, reducing measurement noise while preserving the geometric features of the convexities. For regions with uneven sampling density, uniform sampling or interpolation can be performed to make the point cloud distribution more uniform.

[0083] After preprocessing, the discrete point cloud is converted into a continuous surface mesh model. This application can employ various surface reconstruction algorithms, the specific choice depending on the point cloud characteristics and application requirements. For example, Poisson surface reconstruction is suitable for closed or nearly closed bump surfaces. By constructing an indicator function and solving the Poisson equation, a smooth and watertight triangular mesh is generated. For cases where there are abrupt changes at the connection between the top spherical cap and the base, the reconstruction depth parameter can be adjusted to balance smoothness and detail preservation. Alternatively, the Ball Pivoting algorithm is suitable for scenarios with uniform point cloud density and gradual surface changes. It generates triangular patches by simulating a rolling ball on the point cloud surface; the radius of the rolling ball needs to be dynamically adjusted according to the bump size and point cloud density.

[0084] The original mesh model generated by surface reconstruction may contain too many triangular faces, which is not conducive to real-time rendering, so optimization and simplification are necessary. Specific measures include one or more of the following: reducing the number of triangular faces through mesh simplification algorithms, filling holes and removing non-popular geometry through mesh repair algorithms, and calculating normal vectors and performing consistent orientation to ensure correct lighting effects.

[0085] Similarly, when a 2D image is simultaneously acquired via the equipped 2D graphics acquisition module, texture mapping can be performed. The 2D image is then mapped as a texture onto the surface of the 3D structural model. Through the pixel-level mapping relationship between the 2D image and the 3D point cloud, the texture coordinates corresponding to each triangular facet are calculated, generating a textured 3D structural model. In this way, the textured 3D structural model can simultaneously present the geometric shape of the bumps and the surface optical properties such as color, reflection, and contamination, providing users with richer information.

[0086] 3D rendering can be achieved in various ways. In some embodiments, the system integrates a mature 3D rendering engine (such as OpenGL, Direct3D, or Unity), encapsulating point cloud data or reconstructed mesh models into the format required by the 3D rendering engine, which then performs rendering, lighting calculations, and viewpoint transformations. These 3D rendering engines and their rendering methods are mature technologies and will not be elaborated upon here. Furthermore, this integration method eliminates the need to develop 3D rendering functionality from the ground up, significantly reducing system development complexity.

[0087] Based on the generated 3D structural model, the system constructs an interconnected structural-level view, providing users with an intuitive environment for viewing and analyzing microscopic morphology.

[0088] Taking convex blocks as an example, a convex block-level view is generated based on the 3D structural model of the convex block.

[0089] In the user interface, the interconnect structure-level view area typically occupies the main display area. When a user selects a specific interconnect structure (e.g., a bump) in the data list or Die view, the system loads the optimized 3D structural model of that interconnect structure and automatically adjusts the camera angle to the optimal viewing position, such as a 45° or 60° overhead angle. At the same time, it loads the corresponding 2D top-down view of the interconnect structure and displays them side by side (e.g., side-by-side, top-bottom), or overlaid on the side or bottom of the view.

[0090] Based on the geometric topography model of the interconnected structure, the system supports various interactive operations to assist users in performing detailed analysis. These interactive operations include at least perspective operations, line drawing and measurement operations, and top-view comparison operations.

[0091] In terms of interaction design, the system adopts standard mouse and / or touch operation modes to reduce the user's learning cost and improve operation efficiency.

[0092] Taking the spherical cap model generated by the bumps as an example, for mouse operation, users can drag and rotate the model at will, such as around the X-axis or Y-axis, to observe the top shape of the bump, the steepness of the side walls, and the transition area between the bottom and the base from different angles. Combined with rotation around the Z-axis, the symmetry of the bump and any potential tilting defects can be examined from all angles. Alternatively, the mouse wheel can be used for continuous zooming, quickly locating the area of ​​interest from a macroscopic perspective, and then gradually zooming in to observe the subtle undulations, depressions, or contaminants on the bump surface. Alternatively, the view can be panned by dragging with the middle mouse button to adjust the observation area, which is particularly useful for panning to view different parts of the bump while in magnified mode. Furthermore, a one-click reset function is provided to quickly restore the initial view, allowing users to reposition after multiple rotations and zooms.

[0093] For touchscreen devices, the system also supports intuitive gesture controls. For example, a single-finger drag rotates the model, a two-finger pinch zooms in and out, and a two-finger pan moves the view area. The system also supports preset view functions, allowing users to switch to standard views such as top view, front view, and side view with a single click, facilitating quick observation of shape features in specific directions.

[0094] To further enhance observation efficiency, the system provides a variety of auxiliary observation tools. For example, the section view function allows the model to be cut along any plane to observe the internal structure or cross-sectional contour of the bump. The transparency adjustment function makes the model semi-transparent, facilitating simultaneous observation of the front and rear structures of the bump. The lighting adjustment function allows adjustment of the light source direction and intensity to highlight detailed features in specific areas. The combined use of these interactive operations enables users to comprehensively examine the three-dimensional morphology of the bump from any angle, scale, and perspective, providing ample observation tools for subsequent defect analysis and process diagnosis.

[0095] Regarding line drawing and measurement operations, the system has a built-in measurement tool that supports users in performing precise geometric measurements. The implementation of this tool involves the conversion between 2D screen coordinates and 3D spatial coordinates. When a line drawing operation is performed on any view of the spherical cap model (including top view, side view, cross-sectional view, or any rotated view) via mouse or gesture operations, the system records the screen pixel coordinates of the line segment's start and end points. Based on the projection matrix of the current view and the model view matrix, it calculates the 3D spatial ray corresponding to the screen coordinates through inverse transformation, and intersects it with the 3D structural model to obtain the actual spatial point coordinates. The system maps the pixel coordinates of the drawn line segment to a 3D point cloud space and calculates the geometric parameters required by the user based on the mapping result. For example, for height measurement, the system calculates the Euclidean distance between the two endpoints of the line segment, or calculates the projected length of the line segment in the vertical direction. For example, for diameter measurement, the system extracts the cross-sectional profile at a specified height, fits a circle, and calculates the diameter. For example, for angle measurement, the system calculates the angle between two line segments. For example, for arc length measurement, the system calculates the curve length along the path on the model surface. The measurement results are displayed on the view in the form of numerical labels and can be exported as needed. In some embodiments, the system can also generate a cutting plane based on the line segment drawn by the user, calculate the intersection line of the plane and the 3D model, and generate a cross-sectional profile for further analysis by the user. The cross-sectional data can be displayed in a separate coordinate system window, and the user can drag the calipers on the X-axis or Y-axis to measure the dimensions at any position.

[0096] Regarding the top-view comparison operation, the system synchronously displays the original camera view (e.g., the original top-view image) corresponding to the bump on the side or below the 3D view for user comparison. The original top-view image clearly shows the bump's planar outline, surface texture, and surrounding environment, providing complementary information to the 3D structural model. Taking surface texture as an example, surface texture is a visual representation of the object's surface optical properties and micro-geometric features, including color and grayscale, brightness variations, patterns, and defects and anomalies. For example, the original top-view image can reveal whether the bump surface has scratches or contaminants (judged by local color or brightness anomalies), whether the material is uniform (judged by overall tone consistency), whether the edges are clear (indirectly reflecting morphological quality through edge sharpness), and whether there are process anomalies such as oxide layer discoloration. Combining this texture information with the geometric information of the 3D structural model allows for a comprehensive assessment of the bump's morphological quality and process status.

[0097] Please see Figure 2 The diagram shows an interface schematic of one embodiment of the interconnect structure level view of this application. Figure 2As shown, this interconnect structure-level view is based on bumps to form a bump-level view. The display interface involving the bump-level view includes a two-dimensional model display area 201, a three-dimensional model display area 202, a line drawing and measurement area 203, and a cross-sectional data display area 204.

[0098] The 2D model display area 201 displays the original top view of the current bump. The original top view of the 2D image clearly shows the planar outline, surface texture, and surrounding environment of the bump, providing complementary information to the 3D model.

[0099] The 3D model display area 202 presents the 3D structural model of the current bump. This 3D structural model is generated based on the 3D point cloud data of the bump and can realistically reflect the shape characteristics of the bump, including the top spherical crown shape, the sidewall contour, and the transition area between the bottom and the wafer substrate. The figure uses a spherical crown model as an example to illustrate the 3D morphology of the bump.

[0100] Meanwhile, interactive operation tools are also provided in the 3D model display area 202, presented as function buttons such as "Rotate," "Zoom In," "Zoom Out," "Switch View," "Shade," and "Reset." Users can flexibly manipulate the 3D model by dragging the mouse or clicking the corresponding function buttons. For example, the "Select" function allows users to rotate the model arbitrarily and observe the bump shape from different angles. "Zoom In" and "Zoom Out" allow users to continuously switch the observation scale from macroscopic shape to microscopic details. "Switch View" allows users to switch to standard viewpoints such as top view, front view, and side view with one click. "Shade" allows users to switch the model's shading mode, such as shading based on height values ​​or displaying realistic textures. "Reset" restores the initial viewpoint with one click, facilitating repositioning. Of course, the functions of the above interactive operation tools are only illustrative and are not limited thereto.

[0101] Measurement and data analysis can also be performed in the two-dimensional model display area 201. For example, as shown in the figure, when a user performs a line drawing operation on the top view through mouse operation or gesture operation, the system will display the line segment on the top view and highlight the start and end points of the line segment (as shown in the line drawing measurement area 203 in the figure). At the same time, the system calculates the length of the line segment based on the drawn line segment and displays the corresponding cross-sectional profile in the independent cross-sectional data display area 204.

[0102] This interface design integrates 3D models, 2D images, measurement tools, and cross-sectional analysis functions, providing users with a comprehensive environment for examining and analyzing microscopic morphology. Through the aforementioned interactive operations, users can perform detailed observation and precise measurement of individual bumps, providing intuitive data support for subsequent defect diagnosis and process analysis.

[0103] Furthermore, in the convex-level view, various feature parameter values ​​of the convex can be displayed synchronously, such as height measurement values, diameter measurement values, and coplanarity contribution values. These parameters can be displayed in a text list or directly labeled at the corresponding positions on the 3D structural model. For example, the height value can be labeled at the top, or a vertical line can be drawn between the top and bottom and the height value can be labeled on the vertical line. When the user performs measurements on the 3D structural model, the measurement results are updated in real time and compared with the preset specification range. If the measurement exceeds the range, a visual prompt is given, for example, the abnormal measurement value is turned red.

[0104] Through the above-mentioned technology, step S120 transforms the abstract interconnected structure point cloud data into an intuitive and interactive three-dimensional structure model, and supports users to perform fine microscopic morphological observation and geometric measurement, providing a solid data foundation and intuitive observation means for subsequent die-level statistical analysis and defect diagnosis.

[0105] Step S130: According to the preset Die division rules, the three-dimensional morphological feature parameters of multiple interconnected structures located in the same Die region are statistically analyzed to obtain Die-level statistics, and a Die-level view is generated based on the Die-level statistics.

[0106] Die partitioning rules are defined by the layout design layout file. This file defines the boundary coordinates of each die, the theoretical center coordinates of interconnect structures, and the shape and dimensions of the interconnect structures. Taking a bump layout design layout file as an example, it defines the boundary coordinates of each die, the theoretical center coordinates of each bump, and the shape and dimensions of the bump. By parsing the bump layout design layout file and establishing the mapping relationship between die regions and bump coordinates, it becomes clear which bumps are contained within each die region.

[0107] Thus, by statistically analyzing the three-dimensional topographic features of all interconnected structures (e.g., bumps) located within the same die region, die-level statistics can be obtained.

[0108] Common statistical measures include, but are not limited to:

[0109] Average height: The average height of all bumps within the die, reflecting the overall height level of the bumps in the die.

[0110] Maximum and minimum height: The maximum and minimum height of the inner bumps in the die, used to identify extreme anomalies.

[0111] Range: The difference between the maximum and minimum height of the bumps inside the die, reflecting the fluctuation range of the bump height inside the die.

[0112] Variance and standard deviation: reflect the consistency and uniformity of the height of the bumps inside the die.

[0113] Coplanarity: Usually defined as the deviation of the height of all bumps within a die from the plane it fits, reflecting the overall flatness of the bump tops.

[0114] Defect count: The number of failed bumps within the die.

[0115] Defect rate: The proportion of failed bumps within a die to the total number of bumps in that die.

[0116] In some embodiments, the step of generating a Die-level view includes generating a Die-level heatmap. The Die-level heatmap visually displays the spatial distribution of interconnect structure parameters by drawing graphic regions with corresponding colors for each interconnect structure location within the Die view area.

[0117] The process of generating a Die-level heatmap is as follows:

[0118] Setting Parameter Mapping Ranges: Users or the system define a parameter mapping range for each 3D topographic feature parameter based on process specifications. This range defines the range of parameter values ​​covered by the gradient color. Parameter values ​​within the mapping range are converted to the corresponding gradient colors using a color mapping table. For example, taking a bump as an example, a height mapping range can be set for the bump height; for instance, this range can be set to 38 micrometers to 72 micrometers. Similarly, a diameter mapping range can be set for the bump diameter; for instance, this range can be set to 25 micrometers to 35 micrometers. Parameter values ​​exceeding this diameter mapping range are considered abnormal, and the corresponding bump can be marked as a failed bump.

[0119] Configure color mapping table: Based on the preset color mapping table, map the 3D shape feature parameter values ​​located within the parameter mapping range to the corresponding gradient colors.

[0120] The color map table divides the parameter mapping range into multiple color levels, with each color level gradually transitioning from the first color to the second color.

[0121] In some specific embodiments, taking the height mapping range of the bump (e.g., 38 micrometers to 72 micrometers) as an example, a gradient color from blue to red is used, with a total of 64 color levels. Blue represents low values ​​(e.g., close to the lower limit of 38 micrometers), red represents high values ​​(e.g., close to the upper limit of 72 micrometers), and intermediate colors represent intermediate values. The color mapping supports customization, and users can adjust the color gamut according to their needs, such as wanting only the blue color gamut or only the red color gamut.

[0122] Configure abnormal color mapping rules: Map 3D shape feature parameter values ​​located outside the parameter mapping range to abnormal colors, which are different from the gradient color gamut used by the color mapping table.

[0123] In some specific embodiments, regardless of whether the parameter value is below the lower limit or above the upper limit of the parameter mapping range, it is uniformly mapped to the same abnormal color. For example, gray (or black) is used as the abnormal color, and all bumps exceeding the parameter mapping range are presented as gray (or black) in the Die-level heatmap.

[0124] In some specific embodiments, parameter values ​​below the parameter mapping range are mapped to a first abnormal color, and parameter values ​​above the parameter mapping range are mapped to a second abnormal color. The first and second abnormal colors are different from each other and both are distinct from the gradient color gamut used in the color mapping table. For example, parameter values ​​below the parameter mapping range are mapped to gray, and parameter values ​​above the parameter mapping range are mapped to black, thereby helping to quickly identify the direction of process deviations: large areas of gray indicate a thin coating or over-etching, while large areas of black indicate a thick coating or the presence of residue. Of course, other colors can also be selected.

[0125] A heatmap is generated by drawing graphic regions: For each interconnect structure within the Die view area, a graphic region with a corresponding color is drawn at its corresponding location, thus generating a Die-level heatmap. In some embodiments, the shape of the graphic region may be, for example, circular; that is, the bumps appear as circles in the top view. Circular regions most intuitively reflect the actual position and shape of the bumps, facilitating visual comparison for users. Of course, the shape of the graphic region is not limited to this; it can also be set to other shapes such as rectangles, hexagons, or dots, depending on actual needs. Furthermore, in scenarios with densely packed bumps, the size of the corresponding bumps can be manually adjusted to avoid graphic overlap.

[0126] In this way, users can immediately identify interconnect structures in different states through the color distribution of the die-level heatmap. Taking bumps as an example, bumps located within the parameter mapping range are displayed in a gradient color from blue to red, where blue represents a lower value close to the lower limit and red represents a higher value close to the upper limit; bumps below the lower limit of the parameter mapping range are displayed in gray, indicating a low-value anomaly; and bumps above the upper limit of the parameter mapping range are displayed in black, indicating a high-value anomaly. Through this color coding, users can quickly locate the position of failed bumps and intuitively determine the direction of their anomalies. For example, gray indicates that the bump height or diameter is too small, and black indicates that the bump height or diameter is too large.

[0127] Furthermore, if a large area of ​​gray or black appears in a certain region of the die, it indicates a potential systemic process defect in that area. For example, if the upper left corner of the die is predominantly gray while the lower right corner is predominantly black, it suggests that the die may be tilted or have a gradient in coating thickness, resulting in one side being lower than the other. If the center of the die is predominantly red and the edges are predominantly blue, it suggests a potential trend of coating thickness being thicker in the center and thinner at the edges. This intuitive information based on color space distribution is far superior to the traditional binary pass / fail judgment, providing crucial clues for process defect analysis.

[0128] Furthermore, as mentioned earlier, the three-dimensional topographic feature parameters may include height, diameter, and coplanarity. Therefore, in some embodiments, users can switch the data source of the heatmap to different three-dimensional topographic feature parameters via a drop-down menu, such as switching from height to diameter, and generate a diameter heatmap for analysis in the same way. By comparing heatmaps with different parameters, the correlation between different defect modes can be discovered.

[0129] In some embodiments of this application, taking a bump as an example, the three-dimensional topography feature parameters also include statistical features for characterizing the degree of surface topography variation of the bump. These statistical features include standard deviation or root mean square error, which can reflect the roughness or topography consistency of an individual bump surface. For example, for each bump, the standard deviation of the residuals of all point cloud heights on its surface relative to the fitted spherical cap can be calculated; a larger value indicates a rougher bump surface. Mapping these statistical features to colors can also generate a die-level heatmap reflecting the surface quality of the bump.

[0130] Please see Figure 3 This is a schematic diagram of the interface in one embodiment of the Die-level view of this application. For example... Figure 3 As shown, the Die-level view is generated based on bumps. In the display interface involving the Die-level view, there are heat map display area 301 on the left and data distribution map display area 302 on the right, which together present the spatial distribution and statistical characteristics of bump parameters within a single Die.

[0131] The heatmap display area 301 shows the color-coded distribution of all bumps within a single die. Each circle in the graph represents the location of a bump, and the color of the circle is determined by a color mapping rule based on the bump's three-dimensional shape feature parameters (such as height and diameter). Specifically, parameter values ​​within the parameter mapping range are mapped to a gradient color from a first color to a second color; for example, blue represents a lower value, red represents a higher value, and intermediate values ​​are represented by corresponding transition colors. Parameter values ​​outside the parameter mapping range are mapped to abnormal colors; for example, gray represents a low abnormality below the lower limit, and black represents a high abnormality above the upper limit.

[0132] By observing the color distribution of the heatmap, the location of failed bumps and potential process defect areas can be visually identified. For example, if the upper left corner of the die shows a large area of ​​red (too high) and the lower right corner shows a large area of ​​blue (too low), it suggests that the die may have tilt or a coating thickness gradient.

[0133] In the data distribution chart display area 302, the statistical distribution information of the bump parameters within the die is presented in chart form, thus forming a data-level comparison with the heatmap on the left. In this data distribution chart, the horizontal axis represents the segmented intervals of the parameter values, consistent with the color mapping intervals of the heatmap on the left, and the vertical axis represents the number or frequency of bumps falling within each interval.

[0134] By using the data distribution map on the right, users can obtain more accurate numerical information, verify the spatial distribution pattern presented by the heat map on the left, such as whether the bump distribution is concentrated, whether there are abnormal areas of bump aggregation, and perform quantitative process analysis.

[0135] Step S140: Generate a wafer-level view based on die-level statistics.

[0136] In this application, a wafer-level view includes at least one of a wafer-level thermal map and a wafer-level contrast color view. In some embodiments, a wafer-level view includes a wafer-level thermal map. In some embodiments, a wafer-level view includes a wafer-level contrast color view. In some embodiments, a wafer-level view includes both a wafer-level thermal map and a wafer-level contrast color view.

[0137] Taking bumps as an example, regarding wafer-level thermal maps, wafer-level thermal maps are generated based on the statistical parameters of the three-dimensional morphological features of the bumps within the die.

[0138] In some embodiments, the process of generating a wafer-level thermal map may further include:

[0139] First, a statistic is calculated for each die on the wafer. This statistic includes at least one of the following: mean, variance, standard deviation, root mean square error, and coplanarity.

[0140] Taking the average height as an example, the height measurements of all bumps within each die are obtained, and their average value is calculated to obtain the average height of the die. This operation is repeated for all dies on the entire wafer to obtain a numerical matrix corresponding to the die array, where each value in the matrix represents the average height of the corresponding die. Similarly, taking the average diameter as an example, the diameter measurements of all bumps within each die are obtained, and their average value is calculated to obtain the average diameter of the die. This operation is repeated for all dies on the entire wafer to obtain a numerical matrix corresponding to the die array, where each value in the matrix represents the average diameter of the corresponding die. However, this is not a limitation; for example, the highest (or lowest) height and the maximum (or minimum) diameter among all bumps within the die can also be used to represent the corresponding die.

[0141] Next, a color map is used to visualize this numerical matrix, generating a wafer-level heatmap. The color map is configured similarly to the die-level heatmap, dividing the numerical range into multiple color levels with a gradient from the first color to the second. For example, a gradient from blue to red could be used, where blue represents a low average value and red represents a high average value.

[0142] In this way, users can clearly see whether there are systematic process trends on the wafer by observing the color gradient of the wafer-level thermal map. For example, if the central area of ​​the wafer is red and the edge area is blue, it indicates a "high center, low edge" process trend, which may be caused by uneven current density distribution during the electroplating process. If there are banded or blocky abnormal color areas on the wafer, it indicates that there may be local process deviations.

[0143] Furthermore, wafer-level thermal mapping supports dynamically switching statistics. These statistics include, but are not limited to: mean, variance or standard deviation, maximum or minimum value, root mean square error (RMSE), coplanarity value, defect count, and defect rate. The mean reflects the overall level of bump height within the die, such as the average height and average diameter. Variance or standard deviation reflects the consistency of bump height within the die; areas with large variance indicate poor process uniformity. Maximum or minimum values ​​reflect the distribution of extreme values ​​for bumps within the die, used to identify potentially risky dies; for example, maximum and minimum height, maximum and minimum diameter. RMSE reflects the overall deviation between the three-dimensional morphological features (e.g., height or diameter) of the bumps within the die and their corresponding target values; a larger RMSE indicates a more severe deviation of the bump dimensions from the target value, comprehensively reflecting the precision control level of the process system. Coplanarity reflects the overall flatness of the bump tops within the die. Defect count reflects the number of failed bumps within the die. Defect rate reflects the proportion of failed bumps within the die.

[0144] Users can select different statistics for visualization via drop-down menus. By switching between different statistics, users can analyze wafer-level process trends from multiple dimensions and comprehensively evaluate process quality.

[0145] Please see Figure 4 The image shown is a schematic diagram of the interface in one embodiment of the wafer-level thermal map of this application. Figure 4 As shown, the wafer-level heat map is generated based on bumps. The display interface involving the wafer-level heat map includes a mode selection area 401, a settings and function selection area 402, a basic information area 403, and a wafer view display area 404.

[0146] In the mode selection area 401, various view mode options are available for switching between different types of analysis views. Users can select the appropriate view mode according to their analysis needs.

[0147] In the settings and function selection area 402, you can set various parameters of the wafer-level view.

[0148] The basic information area 403 displays the basic information of the current wafer, such as wafer ID number and process information.

[0149] In the wafer view display area 404, taking the wafer heat map as an example, the layout of the current wafer is displayed. Each die position corresponds to a color block, and the color of the color block is determined by the statistical value of the die through a color mapping table.

[0150] Wafer-level thermal mapping allows users to visually observe the spatial distribution patterns of various die statistics across the entire wafer. For example, differences in values ​​between the central and edge regions indicate a process trend of higher values ​​at the center and lower values ​​at the edges. The presence of banded or blocky color anomalies suggests localized process deviations. The clustered distribution of failed dies indicates potential systemic defects.

[0151] This visualization method transforms abstract statistical values ​​into intuitive color space distributions, enabling users to quickly locate abnormal areas and identify process trends, providing a powerful tool for systematic process monitoring and optimization.

[0152] Regarding the wafer-level contrast color view, each die is labeled with a pass or fail tag according to predefined rules to generate the wafer-level contrast color view.

[0153] Among them, the predefined rules can be set by users or the system according to product specifications, production process requirements or quality standards.

[0154] Specifically, failure determination rules can be defined individually or in combination based on multiple conditions.

[0155] Exemplarily, if the height of any bump within a Die exceeds the process specification, then this Die is determined to be defective.

[0156] Exemplarily, if the diameter of any bump within a Die exceeds the process specification, then this Die is determined to be defective.

[0157] Exemplarily, if the number or proportion of defective bumps within a Die exceeds a set threshold (such as the number of defective bumps being greater than 2 or the defective proportion exceeding 2%), then this Die is determined to be defective.

[0158] Exemplarily, if the coplanarity value of the bump heights within a Die exceeds a set threshold, then this Die is determined to be defective.

[0159] Exemplarily, multiple conditions need to be met simultaneously to be determined as qualified. For example, both the height and diameter are within the process specification and the coplanarity value is less than the set threshold.

[0160] In practical applications, according to specific process requirements and product quality standards, the above rules can be flexibly configured. After completing the qualification / failure determination at the Die level, the system uses two visually distinguishable colors on the wafer map to represent qualified Dies and defective Dies respectively, generating a wafer-level contrast color view. In some embodiments, green can be used to represent qualified Dies and red to represent defective Dies, generating a wafer-level red-green view. This red-green view is consistent with the visual habit of the yield distribution map that has been used in the semiconductor industry for a long time. Users can intuitively see the position distribution of defective Dies on the entire wafer and quickly locate the areas with a lower yield.

[0161] Step S150: Establish a hierarchical association structure among the interconnect structure level, Die level, and wafer level, and based on the hierarchical association structure, implement the linked display of different hierarchical views.

[0162] In step S150, an association structure among the interconnect structure level, Die level, and wafer level is established, and based on this, a cross-hierarchical linked display is implemented. The establishment of this association structure is based on the internal mapping relationship between data: each interconnect structure belongs to a specific Die, and each Die is located at a specific position on the wafer. By maintaining this hierarchical mapping relationship, cross-hierarchical tracing and positioning can be achieved between views at different levels. <U+

[0163] In this application, the wafer three-dimensional measurement data analysis method further includes a view interaction linkage step.

[0164] In some embodiments, the view interaction linkage step includes: in response to a selection operation on a target area in the wafer-level heat map, switch to the Die-level view corresponding to this target area and display the detailed information of this Die.

[0165] For example, in response to a user's selection of a target area in a wafer-level heatmap (e.g., clicking on a die location in the wafer-level heatmap), the system automatically switches to the die-level view of the corresponding die and displays detailed information about that die. The detailed information may include the die identifier, die location coordinates, and specific values ​​for die-level statistics (such as average height, standard deviation, defect rate, etc.). In the die-level view, a die-level heatmap can be loaded, allowing the user to further view the parameter distribution of each bump within the die.

[0166] In the wafer-level heatmap, users can dynamically switch the displayed statistics via drop-down menus or other interactive methods, such as switching from height mean to height standard deviation, root mean square error, or coplanarity values. When a user switches statistics, the wafer-level heatmap updates in real time to reflect the new statistical distribution. If the user clicks on a die location to switch to a die-level view, the system automatically maintains statistical consistency; that is, the die-level heatmap defaults to displaying the same statistics as the current wafer-level heatmap (for example, if the wafer-level heatmap currently displays height standard deviation, the linked die-level heatmap will also default to displaying the height values ​​of each bump, allowing users to further analyze the specific distribution of that statistic from a die-level perspective). This design ensures continuity in the analytical focus, from macro-level trend analysis to micro-level detail examination.

[0167] In some embodiments, the view interaction linkage step includes: in response to the selection operation of a failed die in the wafer-level contrast color view, displaying information on all failed interconnect structures (e.g., bumps) within the failed die, and linking to the interconnect structure-level view to display the three-dimensional structural model of the corresponding failed interconnect structure.

[0168] Taking bumps as an example, in response to a user's selection of a failed die in the wafer-level color-coded view (e.g., clicking the red square representing a failed die), the system displays summary information on all failed bumps within that failed die. This information may be presented in list or card format, including the bump's identifier, failure parameter type (height failure, diameter failure, coplanarity failure, etc.), failure severity (e.g., deviation between measured values ​​and process specifications), and the bump's relative coordinates within the die. Users can sort failed bumps by severity using the sorting function, prioritizing critical failure points with the largest deviations.

[0169] When a user selects a specific bump in the list of failed bumps, the system switches to the bump-level view of that bump, loading and displaying its 3D structural model. In the bump-level view, the system automatically adjusts the camera perspective; for example, for bumps with insufficient height, it adjusts to a side view to highlight the lack of height; for bumps with abnormal diameters, it adjusts to a top-down view to observe the cross-sectional shape. Users can freely rotate and scale the model to examine the bump's shape details from various angles. The system simultaneously displays the original top-down view of the corresponding bump, presented side-by-side with the 3D model, facilitating user comparison and inspection for surface contamination, scratches, or distortion.

[0170] The bump-level view also includes built-in measurement tools, allowing users to perform precise geometric measurements on failed bumps, such as actual height, diameter, and sidewall tilt angle. Measurement results are displayed in real-time and compared with process specifications. Through this step-by-step linkage—from wafer-level die failure location to die-level failed bump list filtering, and then to bump-level microscopic morphology examination—users can systematically trace the root cause of failures, deeply analyze the specific reasons for die failures, and provide precise decision-making basis for process optimization.

[0171] In addition, in some embodiments, the view interaction linkage step may also include: comparing and displaying a three-dimensional structural model of the failed interconnect structure and a three-dimensional structural model of the qualified interconnect structure.

[0172] Taking bumps as an example, the interactive steps of the view can also include comparing and displaying the three-dimensional structural models of failed bumps and qualified bumps.

[0173] In terms of interaction design, users can select the "Enable Standard Comparison" option or specify a specific comparison object from the preset standard bump library, such as selecting qualified bumps at adjacent positions within the same die, or standard template bumps in the process specification. The system then presents two 3D model windows side by side in the view area: one side displays the 3D shape of the failed bump, and the other side displays the 3D shape of the qualified bump.

[0174] To facilitate intuitive comparison, the system can automatically apply the same camera view and scaling ratio to both models, ensuring that the other model moves in sync when the user rotates or scales either model. For example, for height-failed bumps, the system displays the height difference between the failed and qualified bumps side-by-side from the same side view; for coplanar-failed bumps, it compares the tilt of their top planes from the same top view.

[0175] In addition, the system supports enhanced difference visualization. Users can enable the "Difference Highlighting" mode, which compares the surfaces of failed bumps and qualified bumps point by point, marking areas where the deviation exceeds a set threshold on the failed bump model using a heatmap or pseudo-color. For example, for bumps with a smaller diameter, the area of ​​their outer contour deviation is highlighted in red; for bumps with insufficient height, the recessed area at the top is displayed with a gradient color.

[0176] At the measurement level, users can perform simultaneous geometric measurements on two models. For example, the actual height can be measured on a failed bump, while the standard height can be measured on a qualified bump. The system automatically calculates the deviation and displays the comparison results.

[0177] By comparing the failed interconnect structure side-by-side with the qualified interconnect structure, the specific deviation characteristics of the failed bump in morphology can be intuitively identified.

[0178] This step-by-step analysis process—from wafer-level macroscopic localization to die-level statistical analysis to bump-level microscopic examination—organically connects previously fragmented data. Users can quickly locate specific failed dies from wafer-level anomalies, then quickly locate specific failed bumps from failed dies, and finally examine the microscopic morphology of the bumps through 3D models. This analysis efficiency is far higher than traditional methods that require manually switching and searching between tables, red-green charts, and raw data files.

[0179] Furthermore, in this application, the wafer 3D measurement data analysis method also includes a data optimization processing step to cope with the computational and storage pressure of massive 3D point cloud data and improve system performance and response speed.

[0180] In some embodiments, the data optimization process includes rendering only the interconnect structure data within the current field of view.

[0181] In practical implementation, taking bumps as an example, when a user zooms or pans on the wafer map, the system calculates the area covered by the current field of view in real time, loading and rendering only the bump data within that area from the data source; data for other areas is not loaded or rendered at this time. After the user finishes their operation, the system loads and renders the data based on the new field of view. This on-demand rendering mechanism significantly reduces the rendering load and memory consumption of the graphics processing unit, ensuring smooth interactive operations. For example, when a user views a wafer-level heatmap in a full wafer view, the system only renders the blocks representing the die, without loading any detailed bump data. When the user zooms in to a single die view, the system loads the point cloud data of all bumps within that die for rendering the die-level heatmap. Only when the user zooms further to a single bump view does the system load the high-density point cloud data of that bump for 3D rendering.

[0182] In some embodiments, the data optimization process includes hierarchical storage of interconnect structure data, wherein data of failed interconnect structures is stored with higher priority than data of qualified interconnect structures.

[0183] Taking bumps as an example, since failed bumps are a key focus of process analysis and defect diagnosis, the system stores the 3D point cloud data of failed bumps in a cache or local storage to ensure rapid retrieval for 3D rendering and detailed analysis. For qualified bumps, due to their large number and relatively low analytical value, the system can adopt a lightweight storage strategy. For example, it can store only their statistical characteristic parameters (such as measured values ​​of height and diameter) and necessary identification information, without storing the complete 3D point cloud data. When users occasionally need to view the details of qualified bumps, the system can load them on demand from the original measurement data source. This hierarchical storage strategy significantly reduces the pressure on the storage system while ensuring the accessibility of critical data.

[0184] Through the above data optimization processing, the system's dependence on computing resources is significantly reduced, and it can run smoothly without the need for expensive high-performance graphics workstations, effectively reducing the system's deployment costs and usage threshold.

[0185] This application's wafer 3D metrology data analysis method constructs a multi-level visualization interface at the interconnect structure level, die level, and wafer level, and hierarchically correlates micro-interconnect structure data with macro-wafer distribution, effectively overcoming the shortcomings of traditional tables and red-green graphs that separate data. This method allows users to progress from macro-trend analysis at the wafer level to statistical distribution at the die level, ultimately focusing on the micro-morphological examination of individual interconnect structures. It achieves comprehensive, multi-dimensional process analysis from overall to local, from macro to micro, significantly improving the depth and efficiency of process defect diagnosis.

[0186] This application also discloses a wafer three-dimensional measurement data analysis device.

[0187] Please see Figure 5 The image shown is a schematic diagram of the wafer three-dimensional measurement data analysis device in one embodiment of this application.

[0188] like Figure 5 As shown, the wafer three-dimensional measurement data analysis device of this application includes: a data acquisition module 501, an interconnect structure-level analysis module 503, a die-level analysis module 505, a wafer-level analysis module 507, and a hierarchical association and linkage module 509.

[0189] It should be noted that, in this application, the interconnect structure includes at least one of the following: bump interconnect structure, via interconnect structure, planar wiring interconnect structure, and pad interconnect structure. Bump interconnect structure can be, for example, a bump; via interconnect structure can be, for example, a through silicon via (TSV) or through glass via (TGV); planar wiring interconnect structure can be, for example, a redistribution layer (RDL); and pad interconnect structure can be, for example, a copper pad or an aluminum pad.

[0190] The data acquisition module 501 is used to acquire three-dimensional topographic data of various interconnect structures in the wafer. In some embodiments, taking bumps as an example, the data acquisition module 501 includes a three-dimensional measurement module. The three-dimensional measurement module can employ non-contact optical three-dimensional measurement technology, such as a white light interferometer, a laser confocal microscope, or a structured light scanning system. Taking a structured light scanning system as an example, the three-dimensional measurement module includes a calibrated structured light projection module and a structured light camera. The structured light projection module and the structured light camera are located above the wafer and are used to acquire three-dimensional point cloud data. In some embodiments, the data acquisition module 501 includes a three-dimensional measurement module and a two-dimensional image acquisition module. The two-dimensional image acquisition module is used to simultaneously acquire two-dimensional images of the wafer surface, and the two-dimensional images and the three-dimensional point cloud data are strictly corresponding in space.

[0191] The interconnect structure-level analysis module 503 is used to extract at least one three-dimensional topographic feature parameter of each interconnect structure based on the three-dimensional topographic data of each interconnect structure, generate a three-dimensional structural model corresponding to each interconnect structure, and generate an interconnect structure-level view based on the three-dimensional structural model.

[0192] In some embodiments, the three-dimensional topography data includes three-dimensional point cloud data. The interconnect structure-level analysis module 503 is further configured to process the three-dimensional point cloud data and is able to extract at least one three-dimensional topography feature parameter for each interconnect structure based on the three-dimensional point cloud data, and render the three-dimensional point cloud data of the interconnect structure to generate an interactive interconnect structure geometric topography model.

[0193] The interconnect structure-level analysis module 503 also includes an interactive operation unit for performing at least one of the following interactive operations based on the interconnect structure geometry model: rotating or scaling the interconnect structure geometry model in response to viewpoint operations; mapping the pixel coordinates of the drawn line segments to a 3D point cloud space in response to line drawing operations performed on the interconnect structure geometry model, and calculating geometric parameters based on the mapping results; and synchronously displaying a camera-captured top view of the interconnect structure for comparative analysis with the interconnect structure geometry model.

[0194] The Die-level analysis module 505 is used to statistically analyze the three-dimensional morphological feature parameters of multiple interconnected structures located in the same Die region according to the preset Die division rules, obtain Die-level statistics, and generate Die-level views based on the Die-level statistics.

[0195] In some embodiments, the Die-level analysis module 505 further includes a color mapping unit, an abnormal color mapping unit, and a heatmap generation unit.

[0196] The color mapping unit is used to map the three-dimensional topographic feature parameter values ​​located within a set parameter mapping range to corresponding gradient colors according to a preset color mapping table. The color mapping table divides the parameter mapping range into multiple color levels, and each color level gradually changes from a first color to a second color. The three-dimensional topographic feature parameters include at least one of height, diameter, and coplanarity.

[0197] An abnormal color mapping unit is used to configure abnormal color mapping rules, mapping 3D shape feature parameter values ​​located outside the parameter mapping range to abnormal colors. In some specific embodiments, regardless of whether the parameter value is below the lower limit or above the upper limit of the parameter mapping range, it is uniformly mapped to the same abnormal color. In some specific embodiments, parameter values ​​below the parameter mapping range are mapped to a first abnormal color, and parameter values ​​above the parameter mapping range are mapped to a second abnormal color. The first abnormal color and the second abnormal color are different from each other and both are distinct from the gradient color gamut used in the color mapping table.

[0198] The heatmap generation unit is used to draw a graphic region with a corresponding color at the corresponding position for each interconnect structure within the Die view area, thereby generating a Die-level heatmap. The graphic region can be in the form of a circle, rectangle, hexagon, or other shapes.

[0199] The wafer-level analysis module 507 is used to generate wafer-level views based on die-level statistics.

[0200] In this application, the wafer-level view includes at least one of a wafer-level thermal map and a wafer-level contrast color view. Therefore, the wafer-level analysis module 507 may further include at least one of a wafer-level thermal map generation unit and a wafer-level contrast color view generation unit.

[0201] The wafer-level heatmap generation unit is used to generate wafer-level heatmaps based on the statistical parameters of the three-dimensional topographic features of the interconnect structure within the die, and supports dynamic switching of the statistical parameters used to generate the wafer-level heatmap. These statistical parameters include at least one of the following: mean, variance, standard deviation, root mean square error, and coplanarity. In practice, the currently interested statistical parameter can be selected via a drop-down menu or other interactive methods, and the system updates the heatmap in real time.

[0202] The wafer-level contrast color view generation unit is used to label each die with a pass or fail label according to predefined rules, generating a wafer-level contrast color view. A first contrast color is used to represent a pass die, and a second contrast color is used to represent a fail die; the first and second contrast colors are visually distinguishable.

[0203] The hierarchical association and linkage module 509 is used to establish a hierarchical association structure between the interconnect structure level, the die level, and the wafer level, and to realize the linkage display of different hierarchical views based on the hierarchical association structure.

[0204] In some embodiments, the hierarchical association and linkage module is configured to: in response to the selection operation of a target region in the wafer-level thermal map, switch to the die-level view of the die corresponding to the target region and display detailed information of the die; and / or, in response to the selection operation of a failed die in the wafer-level contrast color view, display information of all failed interconnect structures within the failed die and link to the interconnect structure-level analysis module to display the three-dimensional structural model of the corresponding failed interconnect structure.

[0205] Furthermore, in some embodiments, the wafer 3D metrology data analysis apparatus of this application may also include a data optimization module for implementing field-of-view adaptive rendering and hierarchical data storage. Specifically, the data optimization module may further include a field-of-view adaptive rendering unit and a hierarchical data storage unit. The field-of-view adaptive rendering unit renders only the interconnect structure data within the current field of view, avoiding unnecessary computation and memory consumption. The hierarchical data storage unit implements hierarchical storage management for the interconnect structure data, with data storage priority for failed interconnect structures exceeding that for qualified interconnect structures, ensuring accessibility of critical data while reducing storage pressure.

[0206] It should be noted that the wafer 3D metrology data analysis device disclosed in the above embodiments and the wafer 3D metrology data analysis method disclosed in the above embodiments belong to the same concept. The specific operation methods of each module and unit have been described in detail in the method embodiments and will not be repeated here. In practical applications, the wafer 3D metrology data analysis device disclosed in the above embodiments can be assigned to different functional modules as needed, that is, the internal structure of the system can be divided into different functional modules to complete all or part of the functions described above. This is not a limitation here.

[0207] This application discloses another electronic device; please refer to [link / reference needed]. Figure 6 The diagram shown is a structural schematic of the electronic device of this application in one embodiment.

[0208] like Figure 6As shown, the electronic device includes a processor 601, a memory 603, a display device 605, and an input device 607. The processor 601 and the memory 603 can communicate via a bus 602. The memory 603 can store program instructions. The processor 601 implements the steps of the wafer three-dimensional measurement data analysis method in the previous embodiment by running the program instructions in the memory 603.

[0209] Bus 602 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, although only one thick line is used in the diagram, this does not indicate that there is only one bus or one type of bus.

[0210] The processor 601 can be implemented as a central processing unit (CPU), a microprocessor unit (MCU), a system on chip (System on Chip), or a field-programmable logic array (FPGA).

[0211] The memory 603 may include volatile memory for temporary data storage during operation, such as random access memory (RAM).

[0212] The memory 603 may also include non-volatile memory for data storage, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state disk (SSD).

[0213] Display device 605 is used to present or convey processing results, status information, and interactive feedback to the user, that is, to present interconnect structure-level views, die-level views, and wafer-level views. In specific examples, display device 605 may be, for example, a conventional display screen or a touch display screen.

[0214] Input device 607 is used to receive operation commands on the view and trigger cross-level linked display based on a hierarchical relationship structure. In specific examples, input device 607 may be at least one of the following: keyboard, mouse, touch screen, joystick, optical or trackball, and voice input device (such as microphone).

[0215] In some embodiments, the electronic device may also include a communication interface. The communication interface is used for communication with external devices. In specific instances, the communication interface may include one or more wired and / or wireless communication circuit modules. For example, the communication interface may include one or more of, such as a wired network card, a USB module, a serial interface module, etc. The wireless communication protocols followed by the wireless communication module include, for example, Near Field Communication (NFC) technology, Infrared (IR) technology, Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Time Division Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), Bluetooth (BT), Global Navigation Satellite System (GNSS), etc.

[0216] Specifically, in this embodiment, the processor 601 in the electronic device loads the executable files corresponding to the processes of one or more computer programs into the memory 603 according to the following instructions, and the processor 601 runs the program instructions stored in the memory 603 to realize the various steps of the aforementioned wafer three-dimensional measurement data analysis method.

[0217] For details on the implementation of each of the above steps, please refer to the previous examples, which will not be repeated here.

[0218] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be performed by a computer program, or by a computer program controlling related hardware. The computer program can be stored in a computer-readable storage medium and loaded and executed by a processor.

[0219] Therefore, this application further discloses a computer-readable storage medium storing a computer program that can be loaded by a processor to execute the steps of any of the wafer three-dimensional measurement data analysis methods disclosed in this application.

[0220] The computer-readable storage medium may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0221] Since the computer program stored in the computer-readable storage medium can execute the steps of any of the wafer three-dimensional measurement data analysis methods disclosed in the embodiments of this application, the beneficial effects that any of the wafer three-dimensional measurement data analysis methods disclosed in the embodiments of this application can achieve can be realized, as detailed in the preceding embodiments, and will not be repeated here.

[0222] This application also discloses a computer program product, which includes a computer program stored in a computer-readable storage medium. The computer program is executed by a processor through the steps disclosed in various optional implementations of the above-described wafer 3D metrological data analysis method.

[0223] The foregoing has provided a detailed description of a wafer three-dimensional measurement data analysis method, a wafer three-dimensional measurement data analysis system, an electronic device, a computer-readable storage medium, and a computer program product disclosed in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and its core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for analyzing three-dimensional measurement data of wafers, characterized in that, Includes the following steps: Acquire three-dimensional morphological data of each interconnect structure in the wafer; Based on the three-dimensional topography data of each interconnect structure, at least one three-dimensional topography feature parameter of each interconnect structure is extracted, a three-dimensional structural model corresponding to each interconnect structure is generated, and an interconnect structure-level view is generated based on the three-dimensional structural model. According to the preset die division rules, the three-dimensional topographic feature parameters of multiple interconnected structures located in the same die region are statistically analyzed to obtain die-level statistics, and a die-level view is generated based on the die-level statistics. Generate a wafer-level view based on the aforementioned die-level statistics; as well as Establish a hierarchical relationship structure between the interconnect structure level, the die level, and the wafer level, and realize the linkage display of different level views based on the hierarchical relationship structure.

2. The wafer three-dimensional measurement data analysis method according to claim 1, characterized in that, The three-dimensional topography data includes three-dimensional point cloud data; The step of generating a three-dimensional structural model corresponding to each interconnect structure includes: extracting at least one three-dimensional topographic feature parameter for each interconnect structure based on the three-dimensional point cloud data, and rendering the three-dimensional point cloud data of the interconnect structure to generate an interactive geometric topographic model of the interconnect structure.

3. The wafer three-dimensional measurement data analysis method according to claim 2, characterized in that, Based on the geometric model of the interconnect structure, perform at least one of the following interactive operations: In response to viewpoint operations on the interconnect structure geometry model, the interconnect structure geometry model can be rotated or scaled. In response to a line drawing operation performed on the geometry model of the interconnected structure, the pixel coordinates of the drawn line segment are mapped to a three-dimensional point cloud space, and geometric parameters are calculated based on the mapping result. as well as The camera view of the interconnect structure is displayed synchronously for comparison and analysis with the geometric model of the interconnect structure.

4. The wafer three-dimensional measurement data analysis method according to claim 3, characterized in that, The step of mapping the pixel coordinates of the drawn line segment to the three-dimensional point cloud space includes: Record the screen pixel coordinates of the start and end points of the line segment; Based on the projection matrix and model view matrix of the current view, the 3D spatial ray corresponding to the screen coordinates is calculated through inverse transformation; and The intersection points of the three-dimensional spatial ray and the three-dimensional structural model are calculated to obtain the actual coordinates of the line segment endpoints in the three-dimensional point cloud space.

5. The wafer three-dimensional measurement data analysis method according to claim 1, characterized in that, The step of generating a die-level view includes generating a die-level heatmap, and the step of generating a die-level heatmap includes: According to the preset color mapping table, the three-dimensional shape feature parameter values ​​located within the set parameter mapping range are mapped to the corresponding gradient colors. The color mapping table divides the parameter mapping range into multiple color levels and assigns a corresponding color value to each color level. The color value gradually changes from the first color to the second color. Configure abnormal color mapping rules to map 3D topographic feature parameter values ​​located outside the parameter mapping range to abnormal colors; and For each interconnect structure within the Die view area, a graphic region with the corresponding color is drawn at its corresponding location, thereby generating a Die-level heatmap.

6. The wafer three-dimensional measurement data analysis method according to claim 5, characterized in that, The steps of configuring the abnormal color mapping rules include: mapping parameter values ​​below the parameter mapping range to a first abnormal color, and mapping parameter values ​​above the parameter mapping range to a second abnormal color, so as to distinguish between low-abnormal and high-abnormal regions in the Die-level heatmap.

7. The wafer three-dimensional measurement data analysis method according to claim 1, characterized in that, The step of generating a wafer-level view includes at least one of the following: Wafer-level heatmaps are generated based on the statistical parameters of the three-dimensional topographic features of the die's interconnect structure, and the system supports dynamically switching the statistical parameters used to generate the wafer-level heatmaps; and Each die is labeled as either qualified or unqualified according to predefined rules, generating a wafer-level contrast color view. The first contrast color represents qualified dies, and the second contrast color represents unqualified dies. The first and second contrast colors are two visually distinguishable colors.

8. The wafer three-dimensional measurement data analysis method according to claim 7, characterized in that, The method also includes a view interaction linkage step: In response to a selection operation on a target region in the wafer-level thermal map, switch to the die-level view corresponding to the target region and display detailed information about the die; and / or In response to the selection of a failed die in the wafer-level contrast color view, information on all failed interconnect structures within that failed die is displayed, and the interconnect structure-level view is linked to display the 3D structural model of the corresponding failed interconnect structure.

9. The wafer three-dimensional measurement data analysis method according to claim 1, characterized in that, The method further includes a data optimization processing step, which includes: Only render the interconnect structure data within the current field of view; and Interconnection structure data is stored in a hierarchical manner, with data from failed interconnect structures having higher priority than data from qualified interconnect structures.

10. The wafer three-dimensional measurement data analysis method according to claim 1, characterized in that, The interconnect structure includes at least one of the following: bump interconnect structure, via interconnect structure, planar wiring interconnect structure, and pad interconnect structure.

11. The wafer three-dimensional measurement data analysis method according to claim 1, characterized in that, The three-dimensional topographic feature parameters are determined according to the type of interconnect structure: When the interconnect structure is a bump-type interconnect structure, the three-dimensional topographic feature parameters include at least one of height, diameter, and coplanarity; When the interconnect structure is a through-hole interconnect structure, the three-dimensional morphological feature parameters include at least one of the following: aperture, depth, aspect ratio, and sidewall roughness. When the interconnect structure is a planar wiring interconnect structure, the three-dimensional topography feature parameters include at least one of line width, line thickness, line spacing, and surface roughness; When the interconnect structure is a pad-type interconnect structure, the three-dimensional morphological feature parameters include at least one of height, diameter, surface roughness, and coplanarity.

12. A wafer three-dimensional measurement data analysis device, characterized in that, include: The data acquisition module is used to acquire the three-dimensional morphology data of each interconnect structure in the wafer; The interconnect structure-level analysis module is used to extract at least one three-dimensional morphological feature parameter of each interconnect structure based on the three-dimensional morphological data of each interconnect structure, generate a three-dimensional structural model corresponding to each interconnect structure, and generate an interconnect structure-level view based on the three-dimensional structural model. The Die-level analysis module is used to statistically analyze the three-dimensional morphological feature parameters of multiple interconnected structures located in the same Die region according to a preset Die division rule, obtain Die-level statistics, and generate a Die-level view based on the Die-level statistics. A wafer-level analysis module is used to generate a wafer-level view based on the die-level statistics; as well as The hierarchical association and linkage module is used to establish hierarchical association structures between interconnection structure level, die level, and wafer level, and to realize the linkage display of different hierarchical views based on the hierarchical association structure.

13. The wafer three-dimensional metrology data analysis device according to claim 12, characterized in that, The three-dimensional topography data includes three-dimensional point cloud data; the interconnect structure-level analysis module is further configured to process the three-dimensional point cloud data, and is able to extract at least one three-dimensional topography feature parameter for each interconnect structure based on the three-dimensional point cloud data, and render the three-dimensional point cloud data of the interconnect structure to generate an interactive interconnect structure geometric topography model.

14. The wafer three-dimensional metrology data analysis device according to claim 12, characterized in that, The generated die-level view includes a die-level heatmap; the die-level analysis module includes: The color mapping unit is used to map the three-dimensional shape feature parameter values ​​located within the set parameter mapping range to the corresponding gradient colors according to the preset color mapping table. The color mapping table divides the parameter mapping range into multiple color levels, and each color level gradually changes from the first color to the second color. An abnormal color mapping unit is used to configure abnormal color mapping rules, mapping three-dimensional shape feature parameter values ​​located outside the parameter mapping range to abnormal colors; and The heatmap generation unit is used to draw a graphic area with a corresponding color at the corresponding position for each interconnect structure within the Die view area, thereby generating a Die-level heatmap.

15. The wafer three-dimensional metrology data analysis device according to claim 12, characterized in that, The wafer-level analysis module includes: A wafer-level thermal map generation unit is used to generate wafer-level thermal maps based on the statistical parameters of the three-dimensional topographic features of the interconnect structure within the die, and supports dynamically switching the statistical parameters used to generate the wafer-level thermal maps; and / or The wafer-level contrast color view generation unit is used to mark each die with a qualified or failed label according to predefined rules and generate a wafer-level contrast color view, wherein a first contrast color is used to represent a qualified die and a second contrast color is used to represent a failed die, and the first contrast color and the second contrast color are two colors that can be distinguished visually.

16. The wafer three-dimensional metrology data analysis device according to claim 15, characterized in that, The hierarchical association and linkage module is configured as follows: In response to a selection operation on a target region in the wafer-level thermal map, switch to the die-level view of the corresponding die and display detailed information about that die; and / or In response to the selection operation of the failed die in the wafer-level contrast color view, the information of all failed interconnect structures within the failed die is displayed, and the interconnect structure-level analysis module is linked to display the three-dimensional structural model of the corresponding failed interconnect structure.

17. An electronic device, characterized in that, include: processor; A memory storing a computer program that, when executed by the processor, implements the steps of the wafer three-dimensional metrology data analysis method as described in any one of claims 1 to 11. Display devices for presenting interconnect structure-level views, die-level views, and wafer-level views; as well as An input device is used to receive operation instructions for the view and trigger cross-level linked display based on the hierarchical relationship structure.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the wafer three-dimensional measurement data analysis method as described in any one of claims 1 to 11.

19. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the steps of the wafer three-dimensional metrology data analysis method as described in any one of claims 1 to 11.

Images