Gate drive circuit

Abstract

The invention belongs to the technical field of display driving, and particularly relates to a gate driving circuit which comprises N cascaded gate driving modules, and the nth gate driving module comprises a pre-charging unit which is configured to pre-charge a pre-charging control node; a stage transmission output unit configured to output a stage transmission signal of the current stage; the local refresh control unit is configured to control the pre-charging control node to be conducted with the driving control node if the current level is a refresh row in a local refresh mode; if the current level is a non-refresh row, controlling the pre-charging control node to be disconnected from the driving control node; a driving output unit configured to output a gate driving signal of the current stage; the local refreshing control unit is arranged between the pre-charging unit and the driving output unit, whether the driving output unit outputs the grid driving signal or not is dynamically controlled according to whether the current line is the refreshing line or not, and therefore the error output problem of the local refreshing edge position is solved.

Description

Technical Field

[0001] This disclosure belongs to the field of display driving technology, and specifically relates to a gate driving circuit. Background Technology

[0002] With the increasing demand for large screen sizes, high resolutions, and low power consumption in display devices, progressive scanning using GOA (Gate Driver on Array) technology has become the mainstream driving method. Currently, to reduce display device power consumption, a partial refresh display mode has been proposed, which scans only the area where the image is being updated, rather than refreshing the entire screen, thus significantly reducing the power consumption of the GOA and the driver IC.

[0003] However, in the current partial refresh GOA circuit, under the multi-CK architecture, due to the long timing overlap between adjacent stage transmission signals, erroneous outputs are usually generated at the edge of the refresh area, resulting in display abnormalities and reducing the reliability of partial refresh.

[0004] Therefore, how to improve the erroneous output at the edge of local refresh is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a gate driving circuit that improves the problem of erroneous output at the edge of the local refresh by setting a partial refresh control unit between the pre-charge unit and the drive output unit and dynamically controlling whether the drive output unit outputs a gate driving signal according to whether the current row is a refresh row.

[0006] This application provides a gate driving circuit, including N cascaded gate driving modules. The nth gate driving module includes: a pre-charge unit connected to the pre-charge control node of the current stage, configured to pre-charge the pre-charge control node through a cascade transmission signal from the njth gate driving module; a cascade output unit connected to the pre-charge control node, configured to output the cascade transmission signal of the current stage under voltage control of the pre-charge control node; a partial refresh control unit connected to the pre-charge control node and the drive control node of the current stage, configured to: in partial refresh mode, if the current stage is a refresh row, control the pre-charge control node to be turned on and the drive control node to be turned off; if the current stage is a non-refresh row, control the pre-charge control node to be turned off and the drive control node to be turned off; and a drive output unit connected to the drive control node, configured to output the gate driving signal of the current stage under voltage control of the drive control node.

[0007] Optionally, the local refresh control unit includes: a status response subunit connected to the current level's status node and at least one control signal terminal, configured to respond to the level state of the at least one control signal terminal and form a potential on the status node corresponding to the current level's refresh state; wherein the refresh state includes refresh lines and non-refresh lines; an enable control subunit connected to the status node and the current level's enable node, configured to output a corresponding drive enable signal to the enable node based on the potential on the status node; and a gating switch subunit connected to the enable node, the precharge control node, and the drive control node, configured to be controlled by the drive enable signal on the enable node to turn on or off the electrical connection between the precharge control node and the drive control node.

[0008] Optionally, the state response subunit includes: a first transistor, the control terminal of the first transistor being connected to a first control signal terminal, the first terminal of the first transistor being connected to the state node, and the second terminal of the first transistor being connected to a low-level terminal; a second transistor, the control terminal of the second transistor being connected to a second control signal terminal, and the first terminal of the second transistor being connected to the stage output terminal of the nj-th stage gate drive module; and a first capacitor, the first terminal of the first capacitor being connected to the second terminal of the second transistor, and the second terminal of the first capacitor being connected to the first terminal of the first transistor.

[0009] Optionally, the enable control subunit includes: a third transistor, the control terminal of the third transistor being connected to the state node, the first terminal of the third transistor being connected to the second control signal terminal, and the second terminal of the third transistor being connected to the enable node.

[0010] Optionally, the state response subunit includes: a first transistor, the control terminal of the first transistor being connected to a first control signal terminal, the first terminal of the first transistor being connected to the state node, and the second terminal of the first transistor being connected to a low-level terminal; a second transistor, the control terminal of the second transistor being connected to a second control signal terminal, and the first terminal of the second transistor being connected to the stage output terminal of the (nj-1)th stage gate drive module; and a first capacitor, the first terminal of the first capacitor being connected to the second terminal of the second transistor, and the second terminal of the first capacitor being connected to the first terminal of the first transistor.

[0011] Optionally, the enable control subunit includes: a third transistor, the control terminal of which is connected to the state node, the first terminal of which is connected to the second control signal terminal, and the second terminal of which is connected to the enable node; and a second capacitor, the first terminal of which is connected to the stage output terminal of the nj-3th stage gate drive module, and the second terminal of which is connected to the enable node.

[0012] Optionally, the enable control subunit further includes: a fourth transistor, wherein the control terminal of the fourth transistor is connected to the reset signal terminal, the first terminal of the fourth transistor is connected to the enable node, and the second terminal of the fourth transistor is connected to the low-level terminal.

[0013] Optionally, the gating switch subunit includes: a fifth transistor, the control terminal of the fifth transistor being connected to the enable node, the first terminal of the fifth transistor being connected to the precharge control node, and the second terminal of the fifth transistor being connected to the drive control node.

[0014] Optionally, the pre-charge unit includes a sixth transistor, the control terminal of which is connected to the stage output terminal of the nj-th stage gate drive module, the first terminal of which is connected to the control terminal of the sixth transistor, and the second terminal of which is connected to the pre-charge control node.

[0015] Optionally, the stage output unit includes a seventh transistor and a third capacitor. The control terminal of the seventh transistor is connected to the precharge control node, the first terminal of the seventh transistor is connected to the clock signal terminal of the current stage, and the second terminal of the seventh transistor serves as the stage output terminal of the current stage gate drive module. The first terminal of the third capacitor is connected to the control terminal of the seventh transistor, and the second terminal of the third capacitor is connected to the second terminal of the seventh transistor.

[0016] Optionally, the drive output unit includes an eighth transistor and a fourth capacitor. The control terminal of the eighth transistor is connected to the drive control node, the first terminal of the eighth transistor is connected to the clock signal terminal of the current stage, and the second terminal of the eighth transistor serves as the drive output terminal of the current stage. The first terminal of the fourth capacitor is connected to the control terminal of the eighth transistor, and the second terminal of the fourth capacitor is connected to the second terminal of the eighth transistor.

[0017] Optionally, the nth-stage gate drive module further includes a pull-down unit configured to pull down the precharge control node and the drive output terminal; wherein the pull-down unit includes: a ninth transistor, the control terminal of which is connected to the stage output terminal of the (n+i)th-stage gate drive module, the first terminal of which is connected to the drive output terminal of the drive output unit, and the second terminal of which is connected to a low-level terminal; and a tenth transistor, the control terminal of which is connected to the control terminal of the ninth transistor, the first terminal of which is connected to the precharge control node, and the second terminal of which is connected to the low-level terminal.

[0018] The technical solutions provided in this application have at least the following beneficial effects:

[0019] This application adds a partial refresh control unit between the pre-charge unit and the drive output unit, and dynamically controls the on / off state between the pre-charge control node and the drive control node based on whether the current row is a refresh row in partial refresh mode. This achieves precise gating of the gate drive signal output, effectively eliminating erroneous outputs at the edge of the partial refresh area caused by the timing overlap of adjacent stage transmission signals under the multi-CK architecture, thus ensuring the accuracy of the image display. At the same time, this application achieves on-demand and precise output of the gate drive signal, reducing the scanning power consumption in the non-refresh area while ensuring display quality, and improving the energy efficiency ratio and reliability of the partial refresh function of the display device. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0021] Figure 1 The diagram shown is a schematic diagram of a display partition provided in an embodiment of this application.

[0022] Figure 2 The diagram shown is a schematic diagram of the gate drive module in the related technology.

[0023] Figure 3 The diagram shown is a circuit schematic of a gate drive module in the related art.

[0024] Figure 4 The diagram shown is a circuit schematic of another gate drive module in the related technology.

[0025] Figure 5 The diagram shown is a schematic of the driving timing in the related technology.

[0026] Figure 6 The diagram shown is a structural schematic of the first gate driving module provided in an embodiment of this application.

[0027] Figure 7 The diagram shown is a schematic diagram of the structure of a second gate driving module provided in an embodiment of this application.

[0028] Figure 8 The diagram shown is a circuit diagram of the first type of gate driving module provided in an embodiment of this application.

[0029] Figure 9 The diagram shown is a schematic diagram of the driving timing corresponding to the first type of local brush start position provided in the embodiment of this application.

[0030] Figure 10 The diagram shown is a schematic of the driving timing corresponding to the first type of local brush termination position provided in the embodiment of this application.

[0031] Figure 11 The diagram shown is a circuit diagram of a second type of gate driving module provided in an embodiment of this application.

[0032] Figure 12 The diagram shown is a schematic of the driving timing corresponding to the second type of local brush start position provided in the embodiment of this application.

[0033] Figure 13 The diagram shown is a schematic of the driving timing corresponding to the second type of local brush termination position provided in the embodiment of this application.

[0034] Explanation of reference numerals in the attached figures: 100. Gate drive module; 110. Precharge unit; 120. Stage output unit; 130. Partial brush control unit; 131. Status response subunit; 132. Enable control subunit; 133. Gating switch subunit; 140. Drive output unit; 150. Pull-down unit; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor; Qn, precharge control node; Qsn, drive control node; An, status node; Bn, enable node; Fn, stage transmission output terminal; Gn, drive output terminal; Vin1, first control signal terminal; Vin2, second control signal terminal; VSS, low level terminal; Reset, reset signal terminal. Detailed Implementation

[0035] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0036] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0037] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0038] Most current display devices are active display devices, typically driven by a line-by-line scanning method for pixel setting. Each row of pixels has one scan line, and the scan lines are activated line by line, working in conjunction with data lines to write the target grayscale. The activation of the scan lines is generally achieved using the gate-of-aperture (GOA) method, where the GOA provides the gate drive signal and performs the line-by-line activation function. To save power consumption in display devices, a partial refresh display mode has been proposed, such as... Figure 1 As shown, during normal display, regions A, B, and C all need to be scanned and written line by line. When partial refresh display is used (for example, if only region B has a screen update, region B is partially refreshed), regions A and C are not scanned and written every frame, thereby reducing the output power consumption of GOA and IC. The partial refresh function can be applied to various display devices, such as electronic paper, OLDE, and LCD.

[0039] The inventors of this application have discovered that existing partial refresh GOA technology is generally applied to 2CK circuits in small-sized display devices, and there are no multi-CK GOA circuits. Figure 2The diagram shows a commonly used basic GOA circuit unit, including a precharge unit, a pull-down unit, an output unit, a noise reduction unit, and a reset unit. The precharge unit and the pull-down unit are responsible for precharging and pulling down the Q point in the circuit, respectively. The precharge and pull-down are controlled by receiving stage transmission signals from the preceding and following stages, respectively. The output unit is turned on with the Q point as the gate and outputs using the clock signal as the gate drive signal. The noise reduction unit performs noise reduction processing on important signals in the circuit. The reset unit pulls down and resets the Q point in each frame. Figure 3 The diagram shows the basic components of the pre-charge unit, pull-down unit, and output unit. The diagram uses the first j-stage for pre-charging and the last i-stage for pull-down.

[0040] The inventors of this application have also discovered that when a multi-CK GOA circuit needs to employ a partial refresh function, a relatively simple method is... Figure 4 As shown, the fifth transistor T5 is used to isolate the Q-point (Qn) into a secondary Q-point (Qsn), and the Vin signal is used to control whether the Q-point outputs to Qs, thereby controlling whether the current row is output, to achieve partial refresh. However, due to the long-term overlap between adjacent Q-points in the multi-CK GOA circuit, there is a problem of blurred boundaries in the control of Qs, such as... Figure 5 As shown (hereinafter, 6CK, j=3, i=4 will be used as an example), when the current frame requires brushing at the nth level, the Vin signal controls the Q point to input to Qs. When the nth row requires output, Vin pulls the voltage high at the left shoulder of Qn, which can achieve output for the nth row. However, Qn-1 of the n-1th row also outputs to Qsn-1 when Vin switches, resulting in output for the n-1th row. Only the erroneous output of the n-1th row is shown here. In fact, the previous rows will all have erroneous outputs, resulting in abnormal display at the brush edge. Although the 2CK brush GOA circuit has a fundamental difference from the riser circuit, it will also have erroneous output at the brush edge. Therefore, its design can only be used in 2CK GOA circuits and cannot be directly transplanted to multiCK GOA circuits to achieve brushing.

[0041] To improve the problem of erroneous output at local refresh edge positions, this application provides a new gate drive circuit, specifically including the following embodiments: Figure 6 The diagram shown is a structural schematic of the first type of gate driving module 100 provided in this application embodiment; the gate driving circuit of this embodiment includes N cascaded gate driving modules 100, such as... Figure 6 As shown, the nth stage gate drive module 100 includes a pre-charge unit 110, which is connected to the pre-charge control node Qn of the current stage and is configured to pre-charge the pre-charge control node Qn through the stage transmission signal of the njth stage gate drive module 100; where n≤N.

[0042] It should be noted that before each frame scan begins or before the start of the effective output cycle of the current stage, the pre-charge unit 110, in response to the stage transmission signal from the previous nj stage, pre-charges the pre-charge control node Qn within the current stage, increases the potential of the pre-charge control node Qn, and provides a voltage basis for the control of the stage transmission output unit 120 and the local brush control unit 130.

[0043] like Figure 6 As shown, the nth stage gate drive module 100 also includes a stage transmission output unit 120, which is connected to the precharge control node Qn and is configured to output the stage transmission signal of the current stage under the voltage control of the precharge control node Qn.

[0044] It should be noted that the stage transmission output unit 120 is controlled by the voltage on the precharge control node Qn. When the potential on the precharge control node Qn is precharged to a high level, the stage transmission output unit 120 is turned on, and the received clock signal is output as the stage transmission signal of this stage. The output terminal of the stage transmission output unit 120 serves as the stage transmission output terminal Fn of the gate drive module 100. The stage transmission signal is sent to the precharge unit 110 of subsequent modules such as the (n+j)th stage, realizing the step-by-step transmission of signals. This is a crucial signal for ensuring the normal operation of the gate drive circuit. In this embodiment, regardless of whether the current stage outputs a gate scan signal, the stage transmission signal of the current stage must be output normally.

[0045] like Figure 6 As shown, the nth-stage gate drive module 100 also includes a partial refresh control unit 130, which is connected to the precharge control node Qn and the current stage drive control node Qsn, and is configured to: in partial refresh mode, if the current stage is a refresh row, control the precharge control node Qn and the drive control node Qsn to be turned on; if the current stage is a non-refresh row, control the precharge control node Qn and the drive control node Qsn to be turned off.

[0046] It should be noted that the local refresh control unit 130 is a key unit for achieving reliable local refresh under a multi-CK (multi-clock) architecture, and its operating modes are divided into two types: (1) Refresh mode: When an external system (such as a timing controller) determines and indicates that the nth line is the refresh line that needs to be updated, the local refresh control unit 130 responds to the instruction of the input signal of the external system at this time and turns on the precharge control node Qn and the drive control node Qsn; at this time, the potential change of the precharge control node Qn can be directly transmitted to the drive control node Qsn, so that the current stage can output the gate drive signal normally, thereby realizing the normal refresh of the display data.

[0047] (2) Non-refresh mode: When the nth row is determined to be a non-refresh row that does not need to be updated, the local refresh control unit 130 responds to the instruction of the input signal of the external system at this time and disconnects the precharge control node Qn from the drive control node Qsn. At this time, no matter how the potential of the precharge control node Qn changes, it is isolated and cannot affect the drive control node Qsn, so that the current stage cannot output the gate drive signal, thereby realizing that the pixel row retains the display data of the previous frame.

[0048] Therefore, in this embodiment, the electrical connection between the precharge control node Qn and the drive control node Qsn is controlled by the local refresh control unit 130, thereby controlling whether to output the gate drive signal; and only when refreshing the line can the scan timing of the precharge control node Qn be transmitted to the drive output unit 140, thereby avoiding the problem of incorrect output of non-refresh lines due to timing overlap at the beginning and end edges of the local refresh area, and improving the reliability of local refresh.

[0049] like Figure 6 As shown, the nth stage gate drive module 100 also includes a drive output unit 140, which is connected to the drive control node Qsn and is configured to output the gate drive signal of the current stage under the voltage control of the drive control node Qsn.

[0050] It should be noted that the drive output unit 140 is a gate drive signal output unit, and the potential of the drive control node Qsn determines whether to output. That is, in the refresh mode of the current row, the potential of the drive control node Qsn is pulled high by the potential of the precharge control node Qn, the drive output unit 140 is turned on, and the clock signal is output as a valid gate drive signal to the corresponding scan line, thus enabling the data refresh of the pixel in that row; in the non-refresh mode of the current row, the potential of the drive control node Qsn remains low, the drive output unit 140 is turned off, and the output of a valid gate drive signal to the corresponding gate line is stopped, and the pixel in that row retains the data written in the previous frame.

[0051] In summary, this application adds a partial refresh control unit 130 between the pre-charge unit 110 and the drive output unit 140, and dynamically controls the on / off state between the pre-charge control node Qn and the drive control node Qsn based on whether the current row is a refresh row in partial refresh mode. This achieves precise gating of the gate drive signal output, effectively eliminating erroneous outputs at the edge of the partial refresh area caused by the overlapping of signal transmission timings between adjacent stages in a multi-CK architecture, thus ensuring the accuracy of the image display. At the same time, this application achieves on-demand and precise output of the gate drive signal, reducing the scanning power consumption in non-refresh areas while ensuring display quality, thereby improving the energy efficiency ratio of the display device and the reliability of the partial refresh function.

[0052] Figure 7The diagram shown is a structural schematic of the second type of gate driving module 100 provided in an embodiment of this application; as shown Figure 7 As shown, the local refresh control unit 130 includes a status response subunit 131, which is connected to the current level status node An and at least one control signal terminal. It is configured to respond to the level state of at least one control signal terminal and form a potential on the status node An corresponding to the current level refresh state. The refresh state includes refresh lines and non-refresh lines.

[0053] In this embodiment, the state response subunit 131 is connected to at least one externally provided control signal terminal (e.g., a first signal control terminal, a second signal control terminal, and a stage transmission output terminal of the nj-th stage gate drive module). Its main function is to passively form or maintain a specific potential on the state node An within this stage by responding to the level combination and timing of the corresponding control signal. The level of this potential directly corresponds to the system's determination of the current row refresh state: one potential represents a refreshed row, and the other potential represents a non-refreshed row.

[0054] like Figure 7 As shown, the local brush control unit 130 also includes an enable control subunit 132, which is connected to the state node An and the current-level enable node Bn. It is configured to output a corresponding drive enable signal to the enable node Bn based on the potential on the state node An. It should be noted that the enable control subunit 132 receives the decision result from the state response subunit 131, performs logical processing based on the potential on the state node An, and outputs the corresponding drive enable signal on the enable node Bn.

[0055] like Figure 7 As shown, the local brush control unit 130 also includes a gating switch subunit 133, which is connected to the enable node Bn, the precharge control node Qn and the drive control node Qsn, and is configured to be controlled by the drive enable signal on the enable node Bn to turn on or off the electrical connection between the precharge control node Qn and the drive control node Qsn.

[0056] It should be noted that the gating switch subunit 133 is the final actuator of the local brush control logic. Essentially, it is a voltage-controlled bidirectional switch. Its control terminal is connected to the enable node Bn, receiving the drive enable signal from the enable control subunit 132; its two conducting terminals are connected to the precharge control node Qn and the drive control node Qsn in the gate drive module 100, respectively. Depending on the level of the drive enable signal, this switch is turned on or off, thereby directly determining whether an electrical connection is formed between the precharge control node Qn and the drive control node Qsn.

[0057] In summary, under partial refresh mode, the state response subunit 131, the enable control subunit 132, and the gating switch subunit 133 form a perception-decision-execution control chain. The specific working principle is as follows: (1) State perception and determination stage (state response subunit 131 operation): When the external control system needs to open or close a local refresh area, it will change the level and timing of the control signals input to the local refresh control units 130 at each level. The state response subunit 131 responds to these changes in real time: for a level set as a refresh line, its state response subunit 131 will establish and maintain a valid potential (e.g., high potential) for the state node An; for an adjacent level set as a non-refresh line, its state node An will present an invalid potential (e.g., low potential or locked at low potential).

[0058] (2) Enable signal generation stage (enable control subunit 132 works): The enable control subunit 132 continuously monitors the potential of the state node An connected to it: For refreshed rows, the valid potential of the state node An is recognized by the enable control subunit 132, which is then activated and outputs a valid drive enable signal (e.g., high level) to the enable node Bn; For non-refreshed rows, the invalid potential of the state node An makes the enable control subunit 132 remain inactive, thereby outputting an invalid drive enable signal (e.g., low level or pulling it down to low level) to the enable node Bn.

[0059] (3) Path On / Off Execution Stage (Gating Switch Subunit 133 Operation): The gating switch subunit 133 is a switch controlled by the enable node Bn: In the refresh row, the high level of the enable node Bn (effective drive enable signal) makes the gating switch subunit 133 fully conduct, thereby establishing a low-impedance path between the precharge control node Qn and the drive control node Qsn. At this time, any scan timing voltage change on the precharge control node Qn can be transmitted to the drive control node Qsn without loss, thereby controlling the drive output unit 140 to output the gate drive signal normally; In the non-refresh row, the low level of the enable node Bn (ineffective drive enable signal) makes the gating switch subunit 133 reliably turn off, thereby forming a high-impedance isolation between the precharge control node Qn and the drive control node Qsn; At this time, even if the precharge control node Qn of this stage has normal voltage fluctuations due to the cascade relationship, it will be completely blocked and cannot affect the drive control node Qsn. The drive control node Qsn remains at an invalid potential, and the drive output unit 140 has no output.

[0060] Therefore, this embodiment allows external control signals to independently identify the state of each row through the state response subunit 131; combined with the enable control subunit 132 and the gating switch subunit 133, independent on / off control of the precharge control node Qn and drive control node Qsn path of each row is realized. This enables the non-refreshing row to be turned off and the refreshing row to be turned on at the boundary of the local refresh area, solving the problem of edge row erroneous output caused by multiple CK timing overlap.

[0061] Figure 8 The diagram shown is a circuit schematic of the first type of gate driving module 100 provided in an embodiment of this application; as follows: Figure 8 As shown, the state response subunit 131 includes a first transistor T1, a second transistor T2, and a first capacitor C1; the control terminal of the first transistor T1 is connected to the first control signal terminal Vin1, the first terminal of the first transistor T1 is connected to the state node An, and the second terminal of the first transistor T1 is connected to the low-level terminal VSS; the control terminal of the second transistor T2 is connected to the second control signal terminal Vin2, and the first terminal of the second transistor T2 is connected to the stage transmission output terminal of the nj-th stage gate drive module; the first terminal of the first capacitor C1 is connected to the second terminal of the second transistor T2, and the second terminal of the first capacitor C1 is connected to the first terminal of the first transistor T1.

[0062] like Figure 8 As shown, the enable control subunit 132 includes: a third transistor T3, the control terminal of the third transistor T3 is connected to the state node An, the first terminal of the third transistor T3 is connected to the second control signal terminal Vin2, and the second terminal of the third transistor T3 is connected to the enable node Bn.

[0063] Optionally, the enable control subunit 132 further includes: a fourth transistor T4, the control terminal of the fourth transistor T4 being connected to the reset signal terminal Reset, the first terminal of the fourth transistor T4 being connected to the enable node Bn, and the second terminal of the fourth transistor T4 being connected to the low-level terminal VSS.

[0064] like Figure 8 As shown, the gating switch subunit 133 includes: a fifth transistor T5, the control terminal of the fifth transistor T5 is connected to the enable node Bn, the first terminal of the fifth transistor T5 is connected to the precharge control node Qn, and the second terminal of the fifth transistor T5 is connected to the drive control node Qsn.

[0065] like Figure 8 As shown, the pre-charge unit 110 includes a sixth transistor T6. The control terminal of the sixth transistor T6 is connected to the stage output terminal of the nj-th stage gate drive module. The first terminal of the sixth transistor T6 is connected to the control terminal of the sixth transistor T6, and the second terminal of the sixth transistor T6 is connected to the pre-charge control node Qn. Figure 8In this context, Fn-j represents the stage output terminal of the nj-th stage gate drive module.

[0066] Optionally, the stage output unit 120 includes a seventh transistor T7 and a third capacitor C3. The control terminal of the seventh transistor T7 is connected to the precharge control node Qn, the first terminal of the seventh transistor T7 is connected to the clock signal terminal of the current stage, and the second terminal of the seventh transistor T7 serves as the stage output terminal Fn of the current stage gate drive module. The first terminal of the third capacitor C3 is connected to the control terminal of the seventh transistor T7, and the second terminal of the third capacitor C3 is connected to the second terminal of the seventh transistor T7. It should be noted that the presence of the third capacitor C3 in this embodiment ensures that even if the drive output unit 140 does not output a gate drive signal, the potential of the stage output terminal Fn can still charge the precharge unit of the next j stage, maintaining the potential state of the precharge control node.

[0067] Optionally, the drive output unit 140 includes an eighth transistor T8 and a fourth capacitor C4. The control terminal of the eighth transistor T8 is connected to the drive control node Qsn, the first terminal of the eighth transistor T8 is connected to the clock signal terminal of the current stage, and the second terminal of the eighth transistor T8 serves as the drive output terminal Gn of the current stage. The first terminal of the fourth capacitor C4 is connected to the control terminal of the eighth transistor T8, and the second terminal of the fourth capacitor C4 is connected to the second terminal of the eighth transistor T8.

[0068] like Figure 8 As shown, the nth-stage gate drive module 100 also includes a pull-down unit 150, configured to pull down the precharge control node Qn and the drive output terminal Gn. It should be noted that the pull-down unit 150 is configured to pull down the precharge control node Qn, rather than the drive control node Qsn, so that the precharge control node Qn still maintains the pull-down state of the normal circuit.

[0069] Optionally, the pull-down unit 150 includes a ninth transistor T9 and a tenth transistor T10; the control terminal of the ninth transistor T9 is connected to the stage output terminal of the (n+i)th stage gate drive module 100, the first terminal of the ninth transistor T9 is connected to the drive output terminal Gn of the drive output unit 140, and the second terminal of the ninth transistor T9 is connected to the low-level terminal VSS; the control terminal of the tenth transistor T10 is connected to the control terminal of the ninth transistor T9, the first terminal of the tenth transistor T10 is connected to the precharge control node Qn, and the second terminal of the tenth transistor T10 is connected to the low-level terminal VSS. Figure 8 In this context, Fn+i represents the stage output terminal of the (n+i)th stage gate drive module.

[0070] Here, taking 6CK, j=3, i=4 as an example, combined with Figure 9 The corresponding timing diagram explains the working principle of the two adjacent rows at the start position of the local refresh as follows: 1. Control signal timing settings: Assuming the local refresh area starts from row n, the switching timing of the first control signal terminal Vin1 and the second control signal terminal Vin2 is as follows: Figure 9 As shown: (1) Switching time of the second control signal terminal Vin2: about one clock cycle (1H) before the rising edge of the left shoulder of the precharge control node Qn in the nth row (i.e. the rising edge of the stage transmission output terminal of the n-3th stage gate drive module), the second control signal terminal Vin2 switches from low level to high level.

[0071] (2) Switching time of the first control signal terminal Vin1: After the second control signal terminal Vin2 is switched, and before the rising edge of the left shoulder of the precharge control node Qn, it must be ensured that the first control signal terminal Vin1 switches from high level to low level after the rising edge of the left shoulder of the precharge control node in the n-1 row (i.e. the rising edge of the stage transmission output terminal of the n-4 stage gate drive module).

[0072] (3) Before switching: the first control signal terminal Vin1 is at a high level and the second control signal terminal Vin2 is at a low level.

[0073] 2. Reasoning for the working principle of row n-1 (non-refresh row): Row n-1 is set as a non-refresh row. The drive control node of row n-1 should be kept at a low potential so that the drive output unit 140 has no gate drive signal output.

[0074] Specifically, when the rising edge of the stage transmission signal of the (n-4)th stage gate driver module (i.e., the stage transmission signal of the preceding stage in the (n-1)th row) arrives, the second control signal terminal Vin2 has already switched to a high level, so the second transistor T2 is turned on. The high level output of the stage transmission output terminal of the (n-4)th stage gate driver module charges the first capacitor C1 through the turned-on second transistor T2, pulling up the potential of the state node An. However, at this moment and during the entire high level period of the stage transmission signal of the (n-4)th stage gate driver module, the first control signal terminal Vin1 is still at a high level, so the first transistor T1 continues to be turned on, and the pull-down of the first transistor T1 clamps the state node An at a low level.

[0075] Meanwhile, the control terminal of the third transistor T3 is connected to the low-potential state node An, so the third transistor T3 is in the off state, the enable node Bn is in the low potential, causing the fifth transistor T5 to be in the off state. This cuts off the electrical path between the precharge control node Qn and the drive control node Qsn. Although the GOA timing inside the (n-1)th row is operating normally, because the precharge control node and the drive control node are isolated from each other, and the drive control node itself is at a low potential, the eighth transistor T8 of the drive output unit 140 remains off, and the drive output unit 140 of the (n-1)th row has no output, thus achieving the shutdown of the non-refresh row.

[0076] 3. Reasoning for the working principle of the nth row (the start row of the local refresh): The nth row is set as the refresh row, and its drive control node Qsn should be able to follow the timing of the precharge control node Qn, so that the drive output unit 140 can output the gate drive signal normally.

[0077] Specifically, when the rising edge of the stage transmission signal of the (n-3)th stage gate driver module (i.e., the stage transmission signal of the preceding stage in the nth row) arrives, the second control signal terminal Vin2 is already at a high level, and the first control signal terminal Vin1 has switched to a low level; the second transistor T2 is turned on because the second control signal terminal Vin2 is high. The high level of the stage transmission output terminal of the (n-3)th stage gate driver module charges the first capacitor C1 through the second transistor T2, pulling up the potential of the state node An. At this time, the first control signal terminal Vin1 is at a low level, so the first transistor T1 is turned off, losing its pull-down capability, thus the state node An is successfully pulled up and maintained at a high potential.

[0078] Simultaneously, the control terminal of the third transistor T3 is connected to the high-potential state node An, thus turning on the third transistor T3. Since the second control signal terminal Vin2 is also high at this time, the high-level second control signal terminal Vin2 charges the enable node Bn through the turned-on third transistor T3. The high potential of the enable node Bn turns on the fifth transistor T5, which establishes a low-impedance path between the pre-charge control node Qn and the drive control node Qsn.

[0079] At this time, the GOA timing inside the nth row is operating normally: its precharge control node Qn is precharged by the stage transmission signal of the (n-3)th stage. Due to the conduction of the fifth transistor T5, the voltage on the precharge control node Qn is transferred to the drive control node Qsn. The control terminal of the eighth transistor T8 of the drive output unit 140 is controlled by the high potential on the drive control node Qsn and is turned on. The high potential clock signal is output normally as the gate drive signal of the nth row, and the pixel of that row is enabled to write data.

[0080] It should be noted that, Figure 9 In this diagram, Fn-3 represents the stage output terminal of the (n-3)th stage gate drive module, Fn-4 represents the stage output terminal of the (n-4)th stage gate drive module, Qn-1 represents the precharge control node of the (n-1)th stage, Qsn-1 represents the drive control node of the (n-1)th stage, An-1 represents the status node of the (n-1)th stage, and Bn-1 represents the enable node of the (n-1)th stage.

[0081] In summary, this embodiment achieves precise control of non-refreshing lines and refreshing lines at the start position of local refresh by controlling the timing of the first control signal terminal Vin1 and the second control signal.

[0082] Similarly, taking 6CK, j=3, i=4 as an example, combined with... Figure 10 The corresponding timing diagram explains the working principle of the two adjacent rows at the local refresh termination position as follows: 1. Control signal timing setting (partial refresh termination position): Assume the partial refresh area ends at line m (i.e., line m is the last refresh line, and line m+1 onwards are non-refresh lines); to achieve clear boundaries, the switching timing of the external controller for the first control signal terminal Vin1 and the second control signal terminal Vin2 is as follows: Figure 10 As shown: (1) The switching time of the first control signal terminal Vin1: before the rising edge of the left shoulder of the precharge control node in the m-th row, and at the same time, it must be ensured that the first control signal terminal Vin1 switches from low level to high level after the rising edge of the left shoulder of the precharge control node in the m-1-th row.

[0083] (2) Switching time of the second control signal terminal Vin2: When the first control signal terminal Vin1 switches, the second control signal terminal Vin2 switches from high level to low level.

[0084] (3) Before switching: the first control signal terminal Vin1 is at a low level and the second control signal terminal Vin2 is at a high level.

[0085] 2. Reasoning for the working principle of the (m-1)th row (refresh row, the last row before the end of the local refresh): The (m-1)th row is set as the refresh row, and its drive control node should be able to follow the timing of the precharge control node so that the drive output terminal Gn can output the gate drive signal normally.

[0086] Specifically, when the rising edge of the stage transmission output terminal of the (m-4)th stage gate driver module (i.e., the previous stage transmission signal of the (m-1)th row) arrives, the first control signal terminal Vin1 is low and the second control signal terminal Vin2 is high. The second transistor T2 is turned on because the second control signal terminal Vin2 is high. The high level at the stage transmission output terminal of the (m-4)th stage gate driver module charges the first capacitor C1 through the second transistor T2, pulling the potential of the state node upwards. At this time, the first control signal terminal Vin1 is low, therefore the first transistor T1 is turned off, preventing the state node from being pulled down, thus successfully pulling the state node up and maintaining it at a high potential.

[0087] At this time, the gate of the third transistor T3 is connected to the high-potential state node, so the third transistor T3 is turned on. Since the second control signal terminal Vin2 is also at a high level at this time, the high-level second control signal terminal Vin2 charges the enable node through the turned-on third transistor T3. The gate of the fifth transistor T5 is connected to the high-potential enable node, so the fifth transistor T5 is turned on, thus establishing a low-impedance path between the pre-charge control node and the drive control node.

[0088] With the fifth transistor T5 turned on, the high level on the precharge control node is transmitted to the drive control node, turning on the eighth transistor T8, so that the drive output unit 140 outputs the clock signal as the gate drive signal normally.

[0089] 3. Reasoning for the working principle of the m-th row (non-refresh row, partial refresh termination row): The m-th row is set as a non-refresh row (termination row), and its drive control node should be kept at a low potential so that the drive output unit 140 has no gate drive signal output.

[0090] Specifically, when the rising edge of the stage transmission output terminal of the (m-3)th stage gate drive module (i.e., the stage transmission signal of the previous stage in the m-th row) arrives, the second control signal terminal Vin2 has switched to a low level, and the first control signal terminal Vin1 has switched to a high level. Since the second control signal terminal Vin2 is low, the second transistor T2 is turned off, and the high level of the stage transmission output terminal of the (m-3)th stage gate drive module cannot charge the first capacitor C1 through the second transistor T2. In addition, since the first control signal terminal Vin1 is high, the first transistor T1 remains on, and the state node is pulled down to a low level by the first transistor T1.

[0091] At this time, the gate of the third transistor T3 is connected to the low-potential state node, so the third transistor T3 is in the off state. The enable node is also kept at a low potential, so the fifth transistor T5 is in the off state, resulting in no gate drive signal output for the m-th row, thus achieving precise termination of the local refresh region.

[0092] It should be noted that, Figure 10 In this diagram, Fm-3 represents the stage output terminal of the (m-3)th stage gate driver module, Fm-4 represents the stage output terminal of the (m-4)th stage gate driver module, Qm-1 represents the precharge control node of the (m-1)th stage, Qsm-1 represents the drive control node of the (m-1)th stage, Am-1 represents the status node of the (m-1)th stage, Bm-1 represents the enable node of the (m-1)th stage, Qm represents the precharge control node of the mth stage, Qsm represents the drive control node of the mth stage, Am represents the status node of the mth stage, and Bm represents the enable node of the mth stage.

[0093] Therefore, this embodiment achieves precise control of the state of adjacent rows by using timing control that is complementary to the starting position at the local brush termination position through the first control signal terminal Vin1 and the second control signal terminal Vin2.

[0094] Figure 11 The diagram shown is a circuit diagram of the second type of gate driving module 100 provided in an embodiment of this application; Figure 11 The gate drive module 100 shown is in Figure 8The difference lies in the addition of a second capacitor C2 and a change in the connection relationship of the first terminal of the second transistor T2; specifically as follows: Figure 11 As shown, the state response subunit 131 includes: a first transistor T1, a second transistor T2, and a first capacitor C1; the control terminal of the first transistor T1 is connected to the first control signal terminal Vin1, the first terminal of the first transistor T1 is connected to the state node An, and the second terminal of the first transistor T1 is connected to the low-level terminal VSS; the control terminal of the second transistor T2 is connected to the second control signal terminal Vin2, and the first terminal of the second transistor T2 is connected to the stage transmission output terminal of the (nj-1)th stage gate drive module 100; the first terminal of the first capacitor C1 is connected to the second terminal of the second transistor T2, and the second terminal of the first capacitor C1 is connected to the first terminal of the first transistor T1.

[0095] like Figure 11 As shown, the enable control subunit 132 includes: a third transistor T3 and a second capacitor C2; the control terminal of the third transistor T3 is connected to the state node An, the first terminal of the third transistor T3 is connected to the second control signal terminal Vin2, and the second terminal of the third transistor T3 is connected to the enable node Bn; the first terminal of the second capacitor C2 is connected to the stage output terminal of the (nj-3)th stage gate drive module 100, and the second terminal of the second capacitor C2 is connected to the enable node Bn. Figure 11 In this context, Fn-j-1 represents the stage output terminal of the (nj-1)th stage gate drive module, and Fn-j-3 represents the stage output terminal of the (nj-3)th stage gate drive module.

[0096] It should be noted that the driving timing in this embodiment is as follows: Figure 12 and Figure 13 As shown, this only applies to... Figure 8 The differences will be explained, and the similarities will not be repeated; among them, Figure 12 In this diagram, Fn-7 represents the stage transmission output terminal of the (n-7)th stage gate driver module, Fn-6 represents the stage transmission output terminal of the (n-6)th stage gate driver module, Fn-5 represents the stage transmission output terminal of the (n-5)th stage gate driver module, and Fn-4 represents the stage transmission output terminal of the (n-4)th stage gate driver module. Figure 13 In this embodiment, Fm-7 represents the stage transmission output of the (m-7)th gate driver module, Fm-6 represents the stage transmission output of the (m-6)th gate driver module, Fm-5 represents the stage transmission output of the (m-5)th gate driver module, and Fm-4 represents the stage transmission output of the (m-4)th gate driver module. The two modifications in this embodiment work together to change the generation mechanism and timing relationship of the enable node Bn potential and the state node An potential, as detailed below: (1) Improvement of the pre-coupling mechanism for enabling node Bn exist Figure 8In the process, the potential of the enable node Bn depends entirely on the third transistor T3 being turned on, and then charged by the second control signal terminal Vin2 through the third transistor T3. This involves a charging process caused by the turn-on delay of the third transistor T3 and the channel resistance.

[0097] In this embodiment ( Figure 11 In this circuit, because the second capacitor C2 directly couples the stage transmission signal of stage nj-3 to the enable node Bn, when the preceding stage signal generates a rising edge, the capacitive coupling effect of the second capacitor C2 will prematurely pull up the potential of the enable node Bn. This means that the potential of the enable node Bn may have been pre-raised before the third transistor T3 of this stage is fully turned on, or even before the state node An is fully stable. This is equivalent to providing a pre-charging or auxiliary pull-up path for the enable node Bn, accelerating the establishment speed of the effective enable signal.

[0098] (2) Timing shift of state node An To match the pre-coupling timing of the enable node Bn, this embodiment advances the input signal of the second transistor T2 by one stage, connecting it to the stage output of the (nj-1)th stage gate drive module. This causes the pull-up action of the state node An to be advanced by approximately one clock cycle (1H). This ensures a better timing connection between the establishment and stabilization of the state node An and the pre-coupling of the enable node Bn via the second capacitor C2. The earlier stabilization of the state node An at a high level ensures that the third transistor T3 turns on promptly, allowing continuous charge replenishment through the third transistor T3 path after the enable node Bn is pulled up by the capacitor, maintaining a stable high potential.

[0099] Therefore, this embodiment optimizes the establishment timing of key control signals by introducing a second capacitor C2 and adjusting the timing chain of the second transistor T2, thereby improving the dynamic performance and reliability of the entire local brush control circuit.

[0100] The gate drive circuit provided in this application adds a local refresh control unit controlled by an external timing signal between the precharge control node and the drive control node. This unit, through cascaded logic of state response, enable control, and gating switches, transforms the global refresh command into independent connectivity or isolation control for each row's internal scan timing path. This ensures that the previous row is off and the current row is on at the beginning of the local refresh area, and that the previous row is on and the current row is off at the end of the local refresh area, thereby improving the boundary error output problem caused by timing overlap in multi-CK architectures. Therefore, this application achieves reliable and low-power local refresh functionality on large-size, multi-CK display devices, improving the energy efficiency ratio and dynamic image update quality of the display system, and providing technical support for low power consumption in high-end display products.

[0101] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0102] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0103] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, comprising N cascaded gate driving modules, characterized in that, The nth-stage gate drive module includes: The pre-charge unit, connected to the pre-charge control node of the current stage, is configured to pre-charge the pre-charge control node through the stage transmission signal of the nj stage gate drive module. The stage transmission output unit is connected to the precharge control node and is configured to output the stage transmission signal of the current stage under the voltage control of the precharge control node. The local refresh control unit, connected to the precharge control node and the current level drive control node, is configured to: in local refresh mode, if the current level is a refresh row, control the precharge control node to connect with the drive control node; if the current level is a non-refresh row, control the precharge control node to disconnect from the drive control node. The drive output unit, connected to the drive control node, is configured to output the gate drive signal of the current stage under voltage control at the drive control node.

2. The gate driving circuit according to claim 1, characterized in that, The local brush control unit includes: A state response subunit, connected to the current level's state node and at least one control signal terminal, is configured to respond to the level state of the at least one control signal terminal and form a potential on the state node corresponding to the current level's refresh state; wherein, the refresh state includes refresh rows and non-refresh rows; The enable control subunit, connected to the state node and the current level enable node, is configured to output a corresponding drive enable signal to the enable node based on the potential on the state node. The gating switch subunit, connected to the enable node, the precharge control node, and the drive control node, is configured to be controlled by the drive enable signal on the enable node to turn on or off the electrical connection between the precharge control node and the drive control node.

3. The gate driving circuit according to claim 2, characterized in that, The state response subunit includes: The first transistor has a control terminal connected to a first control signal terminal, a first terminal connected to the state node, and a second terminal connected to a low-level terminal. The second transistor has its control terminal connected to the second control signal terminal, and its first terminal connected to the stage output terminal of the nj-th stage gate drive module. A first capacitor, wherein a first terminal of the first capacitor is connected to a second terminal of the second transistor, and the second terminal of the first capacitor is connected to a first terminal of the first transistor.

4. The gate driving circuit according to claim 3, characterized in that, The enable control subunit includes: The third transistor has a control terminal connected to the state node, a first terminal connected to the second control signal terminal, and a second terminal connected to the enable node.

5. The gate driving circuit according to claim 2, characterized in that, The state response subunit includes: The first transistor has a control terminal connected to a first control signal terminal, a first terminal connected to the state node, and a second terminal connected to a low-level terminal. The second transistor has its control terminal connected to the second control signal terminal, and its first terminal connected to the stage output terminal of the nj-1 stage gate drive module. A first capacitor, wherein a first terminal of the first capacitor is connected to a second terminal of the second transistor, and the second terminal of the first capacitor is connected to a first terminal of the first transistor.

6. The gate driving circuit according to claim 5, characterized in that, The enable control subunit includes: The third transistor has a control terminal connected to the state node, a first terminal connected to the second control signal terminal, and a second terminal connected to the enable node. The second capacitor has its first terminal connected to the stage output terminal of the nj-3 level gate drive module, and its second terminal connected to the enable node.

7. The gate driving circuit according to claim 4 or 6, characterized in that, The enable control subunit further includes: The fourth transistor has its control terminal connected to the reset signal terminal, its first terminal connected to the enable node, and its second terminal connected to the low-level terminal.

8. The gate driving circuit according to any one of claims 2-6, characterized in that, The gating switch subunit includes: The fifth transistor has a control terminal connected to the enable node, a first terminal connected to the precharge control node, and a second terminal connected to the drive control node.

9. The gate driving circuit according to claim 1, characterized in that, The pre-charge unit includes a sixth transistor. The control terminal of the sixth transistor is connected to the stage output terminal of the nj-th stage gate drive module. The first terminal of the sixth transistor is connected to the control terminal of the sixth transistor, and the second terminal of the sixth transistor is connected to the pre-charge control node. Or / and, the stage output unit includes a seventh transistor and a third capacitor. The control terminal of the seventh transistor is connected to the precharge control node. The first terminal of the seventh transistor is connected to the clock signal terminal of the current stage. The second terminal of the seventh transistor serves as the stage output terminal of the current stage gate drive module. The first terminal of the third capacitor is connected to the control terminal of the seventh transistor. The second terminal of the third capacitor is connected to the second terminal of the seventh transistor. Or / and, the drive output unit includes an eighth transistor and a fourth capacitor. The control terminal of the eighth transistor is connected to the drive control node. The first terminal of the eighth transistor is connected to the clock signal terminal of the current stage. The second terminal of the eighth transistor serves as the drive output terminal of the current stage. The first terminal of the fourth capacitor is connected to the control terminal of the eighth transistor. The second terminal of the fourth capacitor is connected to the second terminal of the eighth transistor.

10. The gate driving circuit according to claim 1, characterized in that, The nth-level gate drive module also includes a pull-down unit configured to pull down the precharge control node and the drive output terminal; The pull-down unit includes: The ninth transistor has its control terminal connected to the stage output terminal of the (n+i)th stage gate drive module, its first terminal connected to the drive output terminal of the drive output unit, and its second terminal connected to the low-level terminal. The tenth transistor has its control terminal connected to the control terminal of the ninth transistor, its first terminal connected to the precharge control node, and its second terminal connected to the low-level terminal.

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