Satellite-borne anti-fuse FPGA (Field Programmable Gate Array) reinforcement protection method for avoiding high-power switching damage of PIN (Personal Identification Number) switch

Abstract

The invention discloses a satellite-borne anti-fuse FPGA (Field Programmable Gate Array) reinforcement protection method for avoiding high-power switching damage of a PIN (Personal Identification Number) switch, which comprises the following steps: an original control signal is generated through an SRAM (Static Random Access Memory) type FPGA, and the pulse width of the original control signal is at least the sum of the time of switch switching maximum time delay t1, radio frequency transmission and stabilization time t2, design margin t3 and effective switching window t4; a DA turn-off signal and an effective window signal are obtained from the original control signal in the anti-fuse FPGA. According to the method, a high-reliability scheme is realized by utilizing the satellite-borne anti-fuse FPGA, so that an electronic switch cannot be burnt out due to switching of various reasons when the power amplifier outputs high power. The method has high universality, solves the problems of weight and power consumption of the radio frequency front end of the integrated high-power base station especially in the design of high-integration-level products such as deep space exploration, and has wide application prospects.

Description

Technical Field

[0001] This invention belongs to the field of communication product design, specifically relating to a method for hardening and protecting a spaceborne antifuse FPGA to avoid damage from high-power switching of PIN switches. Background Technology

[0002] To meet the needs of my country's future deep space exploration missions and the construction of extraterrestrial bases, it is necessary to build an extraterrestrial mobile network communication system and develop communication "base stations" within the system. Limited by rocket carrying capacity and other constraints, the engineering implementation faces extremely stringent constraints regarding weight and power consumption. Therefore, adopting the most miniaturized and lightweight "base station" product solution becomes the most critical factor determining the success or failure of the mission.

[0003] Typical scenarios for such missions require establishing a communication network supporting approximately 10 or more communication nodes to transmit services such as images, voice, remote control and telemetry, and video feeds for devices within the network. Traditional terrestrial base station solutions, from 3G, 4G, LTE to 5G, have undergone years of continuous optimization, resulting in a mature, productized, and evolving architecture. To maximize coverage distance, terrestrial base stations typically require large power amplifiers. Simultaneously, to achieve 360-degree omnidirectional coverage, communication across multiple cells needs to be supported, requiring each antenna to have an independent radio frequency front-end (RRU) and an independent digital processing board to cover multiple cells. This solution usually requires an entire ground equipment room and consumes thousands of kilowatts of power. Both in terms of weight and power consumption, this far exceeds the engineering costs that deep space missions can afford.

[0004] To address the challenges of developing communication base station equipment for my country's current extraterrestrial base construction, this paper innovatively proposes a spaceborne antifuse FPGA-based hardened protection method to prevent damage from high-power switching of PIN switches. This method aims to ensure the reliability of electronic switching in high-power systems, thereby meeting the goals of aerospace engineering applications. The design effectively guarantees the realization of a lightweight base station, employing a method with minimal aerospace engineering costs. It prevents the electronic switch, acting as a single point in the system, from burning out due to software malfunctions causing it to operate under high-power signal switching conditions. This significantly improves system reliability and avoids situations that severely impact mission execution. Summary of the Invention

[0005] The technical problem solved by this invention is to overcome the shortcomings of existing technologies and provide a spaceborne antifuse FPGA hardening protection method to avoid damage from high-power switching of PIN switches. This method aims to ensure the reliability of switching using electronic switches in high-power systems, thereby meeting the goals of aerospace engineering applications. The design of this scheme effectively ensures the realization of a lightweight base station, employing a method with minimal aerospace engineering costs. It prevents the electronic switch, as a single point in the system, from burning out due to software malfunctions causing it to operate under high-power signal switching conditions. This significantly improves system reliability and avoids situations that seriously affect mission execution.

[0006] To achieve the above objectives, the technical solution adopted by the present invention includes: A method for hardening and protecting a spaceborne antifuse FPGA to avoid damage from high-power switching of PIN switches includes the following steps: The "original control signal" is generated by an SRAM-type FPGA. The pulse width of the "original control signal" is at least the sum of the maximum switching delay Δt1, the RF transmission and settling time Δt2, the design margin Δt3, and the effective switching window Δt4. The "original control signal" is converted into the "DA turn-off signal" and the "valid window signal" within the antifuse FPGA; The “DA turn-off signal” is used to turn off the input signal of the DA device for a period of time. The "valid window signal" cuts off or connects the latch, so that the electronic switch control signal sent by the SRAM-type FPGA within the "valid window signal" can be sent to the electronic switch drive circuit, while the control signal sent by the SRAM-type FPGA outside the gate control signal cannot be sent to the electronic switch drive circuit.

[0007] Optionally, the "valid window signal" is a signal with a strictly limited pulse width obtained from the "original control signal" and is used to enable the LE pin of the latch, so that the input signal within the pulse width of the "valid window signal" can pass normally, while the input signal outside the pulse width of the "window signal" cannot pass.

[0008] Optionally, obtaining the maximum delay of the switch switching includes: We need to obtain the maximum power amplifier shutdown time Δt_RFoff, the maximum power amplifier startup time Δt_RFon, and the steady-state settling time of the electronic switch Δt_switch, which are related to the hardware. The maximum delay for switching is Δt1, where Δt1 = max[Δt_RFoff, Δt_RFon, Δt_switch].

[0009] Optionally, the design margin needs to take into account the processor's minimum processing clock cycle and additional margin protection. The processing speed of the antifuse FPGA processor is higher than 1MHz, the clock cycle is 1us, and the additional margin protection is 0.5us. 1.5us is selected as the design margin.

[0010] Optionally, the effective switching window is generated by the antifuse FPGA. Considering the minimum processing clock cycle of the processor, the processing speed of the antifuse FPGA processor is higher than 1MHz, the clock cycle is 1us, and the minimum effective switching window is one clock cycle, i.e., 1us.

[0011] Optionally, the RF transmission and stabilization time is obtained by taking the greater of the time delay between the power switching from DA to switch 2 and the power switching from switch 1 to switch 2.

[0012] Optionally, the “original control signal” is high within its width and low outside its width.

[0013] Optionally, the specific method for obtaining the "DA turn-off signal" from the "original control signal" is as follows: The antifuse FPGA samples the "original control signal" and then uses internal logic to delay the signal by Δt1 time to obtain the "DA turn-off signal". This signal turns off the input signal of the external DA device for a period of time.

[0014] Optionally, the "valid window signal" is generated based on the "original control signal". The leading edge of the window signal is the leading edge of the "original control signal" delayed by △t1+△t2, and the width of the window signal lasts for △t3+△t4. The "valid window signal" is used to enable the latch pin, so that the signal inside the window can pass normally, while the signal outside the window cannot pass.

[0015] The advantages of this invention compared to the prior art are: (1) This invention can solve the problem that when designing a communication “base station” in the construction of a deep space exploration extraterrestrial base, due to the requirement of ultra-high integration, the use of a radio frequency architecture that places the electronic switch at the end of the power amplifier to reduce system overhead can easily lead to the electronic switch burning out due to high power switching.

[0016] (2) This method is based on a pulse control signal designed by a programmable logic device (SRAM type FPGA). After a series of logic operations in the antifuse type FPGA, the required safe switching window is obtained to support the switching of different branches of the electronic switch and the switching of large and small power modes within the window. The signal of different branches of the electronic switch and the switching signal of large and small power modes can pass through the window, while the signal of different branches of the electronic switch and the switching signal of large and small power modes outside the window cannot pass through.

[0017] (3) Since the antifuse type FPGA is equivalent to a hardware circuit with fixed wiring after programming, this method is a hardware hardening scheme. Even if the software of the SRAM type FPGA is abnormal due to single particle or other reasons, it can ensure that the electronic switch will never be powered to switch.

[0018] (4) By adopting this method, under the premise of meeting the high reliability requirements of aerospace, it is possible to support the product architecture of using electronic switches in the final stage of the power amplifier. It is particularly suitable for reducing the complexity of ultra-high integration product design in deep space exploration and has strong versatility. Attached Figure Description

[0019] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the implementation architecture of the spaceborne antifuse FPGA hardening protection method for avoiding damage during high-power switching of PIN switches according to the present invention. Figure 2 This is the first common "TDD radio frequency (with built-in electronic switch) + baseband" communication transceiver architecture; Figure 3 This is the second common type of "electronic switch + TDD RF + baseband" communication transceiver architecture; Figure 4 This is a diagram illustrating an implementation of the first communication transceiver architecture of the present invention. Figure 5 This is a diagram illustrating an implementation of the invention in the second type of communication transceiver architecture; Figure 6 This invention utilizes an external processor to generate the required "raw control signals"; Figure 7 This is a flowchart of the delayed operation of the protection method of the present invention; Figure 8 This is a schematic diagram of the effective switching that occurs within the protection method window of the present invention. Figure 8 The two images on the left and right are joined together at the large black arrow to form a long image. Detailed Implementation

[0020] To facilitate understanding of the present invention, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0021] It should be noted that, unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0022] This invention relates to a method for hardening and protecting a spaceborne antifuse FPGA to avoid damage during high-power switching of PIN switches, belonging to the field of communication product design. The invention generates a "raw control signal" using an SRAM-type FPGA (the SRAM-type FPGA needs to complete the rapid selection and disconnection of each level of PIN switches in the electronic switch matrix on the order of microseconds). The pulse width of this signal needs to be the sum of at least the maximum switching delay, RF transmission and stabilization time, a certain design margin (including antifuse FPGA sampling jitter + additional margin), and the effective switching window time. This signal undergoes logical operations within the radiation-resistant antifuse FPGA on the satellite, using a specific algorithm to obtain a new "DA shutdown signal" and "effective window signal." The "DA shutdown signal" is used to turn off the input signal of the DA device for a period of time, while the "effective window signal" cuts off or connects the latch, ensuring that electronic switch control signals sent by the SRAM-type FPGA within the "effective window signal" can be sent to the electronic switch drive circuit, while control signals sent by the SRAM-type FPGA outside the gated signal cannot be sent to the electronic switch drive circuit. This method is a high-reliability solution implemented using a spaceborne antifuse FPGA. It ensures that the electronic switch will not burn out due to switching caused by various reasons when the power amplifier is outputting high power. This method has strong versatility, especially in the design of highly integrated products such as deep space exploration, solving the weight and power consumption problems of the RF front-end of integrated high-power base stations, and has broad application prospects. This method is a high-reliability hardening solution that ensures the electronic switch cannot switch when the power amplifier is outputting high power. It has strong versatility, especially in the design of highly integrated products such as deep space exploration, solving the weight and power consumption problems of the RF front-end of integrated high-power base stations, and has broad application prospects.

[0023] Combination Figure 1The technical solution of this invention is as follows: A "raw control signal" is generated by an SRAM-type FPGA (the SRAM-type FPGA needs to complete the rapid selection and disconnection of each PIN switch in the electronic switch matrix on the order of microseconds). The pulse width of this signal needs to be at least the sum of the maximum switching delay, RF transmission and stabilization time, a certain design margin (including antifuse FPGA sampling jitter + additional margin), and the effective switching window time. This signal completes logical operations in the radiation-resistant antifuse FPGA on the satellite, and obtains a new "DA shutdown signal" and "effective window signal" using a certain algorithm. The "DA shutdown signal" is used to turn off the input signal of the DA device for a period of time, and the "effective window signal" cuts off or connects the latch, so that the electronic switch control signal sent by the SRAM-type FPGA within the "effective window signal" can be sent to the electronic switch drive circuit, while the control signal sent by the SRAM-type FPGA outside the gate signal cannot be sent to the electronic switch drive circuit.

[0024] Specifically, it includes the following steps: (1) The upper limit of the RF stabilization time Δt1 is obtained by taking the larger of the maximum power amplifier shutdown time Δt_RFoff, the maximum power amplifier startup time Δt_RFon, and the steady-state establishment time of switch 1 Δt_switch.

[0025] Specifically: △t1=max[△t_RFoff, △t_RFon, △t_switch]; (2) Regarding Figure 2 The architecture, based on different transmission modes (low-power transmission mode / high-power transmission mode), uses the greater of the power switching times from switch 1 to switch 2 to obtain the RF transmission and settling time Δt2. This is for... Figure 3 The architecture has only one mode, which is to obtain the RF transmission and settling time Δt2 by the greater of the power switching time from DA to switch 1 to the power switching time of switch 2.

[0026] Specifically: Figure 2 Architecture △t2=max[△t_DA off_small , △t_DA on_small , △t_DA off_big , △t_DA on_big ]; Wherein, △t_DA off_small : Figure 2 In low-power mode, after the power supplied to switch 1 by DA is normally set to 0, the output of switch 2 also decreases until it stabilizes; △t_DA on_small : Figure 2In low-power mode, after the power supplied to switch 1 by DA returns to normal from 0, the output power of switch 2 also increases to a stable level within a certain time; △t_DA off_big : Figure 2 In high-power mode, after the power supplied by DA to switch 1 is normally set to 0, the output of switch 2 also decreases until it stabilizes; △t_DA on_big : Figure 2 In high-power mode, after the power supplied by DA to switch 1 returns to normal from 0, the output power of switch 2 also increases to a stable level within a certain time.

[0027] Figure 3 Architecture Figure 3 It does not distinguish between low-power and high-power transmission modes.

[0028] △t2=max[△t_DA off , △t_DA on ]; Wherein, △t_DA off : Figure 3 The time it takes for the power supplied to switch 1 by DA to decrease from its normal value of 0, and for the output of switch 2 to also decrease until it stabilizes; △t_DA on : Figure 3 After the power supplied to switch 1 by DA returns to normal from 0, the output power of switch 2 also increases to a stable level within a certain time.

[0029] (1) Generate the “original control signal” based on the maximum switching delay, RF transmission and stabilization time, design margin (including antifuse FPGA sampling jitter + extra margin) and effective switching window.

[0030] (2) Obtain the "DA turn-off signal" (used to turn off the input signal of the DA device for a period of time) based on the "original control signal".

[0031] (3) Based on the “original control signal”, a “valid window signal” with a strictly limited pulse width is obtained and used to enable the LE pin of the latch, so that the input signal within the pulse width of the “valid window signal” can pass normally, and the input signal outside the pulse width of the “window signal” cannot pass.

[0032] The maximum switching delay, RF transmission time, and settling time are common known information in communication equipment and can be determined in advance through testing. Design margins need to account for antifuse FPGA sampling jitter and additional safety margins. Common antifuse FPGA processors typically have processing speeds higher than 1MHz, therefore a clock cycle of 1µs. An additional safety margin of 0.5µs is considered, so 1.5µs is chosen as a typical design margin value. The "effective switching window" is also generated by the antifuse FPGA, so the processor's minimum processing clock cycle also needs to be considered. Common antifuse FPGA processors have processing speeds higher than 1MHz, therefore a clock cycle of 1µs. Thus, the minimum effective switching window is one clock cycle, i.e., 1µs.

[0033] In step (3), the "original control signal" is generated based on the maximum switching delay, RF transmission and settling time, design margin (including antifuse FPGA sampling jitter + additional margin) and effective switching window, including: (1) Obtain the width of the “original control signal”: △t=△t1+△t2+△t3+△t4; where △t1 is the maximum delay of switching; △t2 is the radio frequency transmission and stabilization time; △t3 is the design margin; and △t4 is the effective switching window.

[0034] (2) The original signal pulse width is high level and the pulse width is low level; the time of the rising edge of the pulse relative to the rising edge of the next pulse is determined by the switching interval of the electronic switch.

[0035] The electronic switch switching interval varies depending on the specific system requirements in a given system. However, this time is not the focus of this patent. It is sufficient to perform the operation required by this patent at each electronic switch switching moment.

[0036] Step (4) Obtain the "DA turn-off signal" (used to turn off the input signal of the DA device for a period of time) based on the "original control signal", including: The antifuse FPGA samples the "original control signal" and then uses internal logic (in any form) to delay the signal by Δt1 time to obtain the "DA turn-off signal". This signal turns off the input signal of the external DA device for a period of time. Step (5) performs an AND operation on the original control signal and the delay signal to obtain the "effective window signal", including: (1) Generate an effective window signal based on the original control signal. The leading edge of the window signal is the delay of the leading edge of the original control signal by Δt1 + Δt2. (2) The width of the “effective window signal” lasts for △t3+△t4, that is, the high level lasts for △t3+△t4, and then it is pulled low.

[0037] (3) Send the “valid window signal” to the enable pin (LE) of the latch (hardware circuit) so that the input signal within the pulse width of the “valid window signal” can pass normally, and the input signal outside the pulse width of the “window signal” cannot pass.

[0038] The specific implementation steps of this invention are as follows Figure 7 conduct.

[0039] Step 1: Generate the raw control signal S_ctrl Generates the raw control signal S_ctrl, which references... Figure 6 Pulse width: Δt = Δt1 + Δt2 + Δt3 + Δt4; where Δt1 is the maximum switching delay; Δt2 is the RF transmission and settling time; Δt3 is the design margin; and Δt4 is the effective switching window.

[0040] Step 2: Obtain the "DA turn-off signal" based on the original control signal S_ctrl.

[0041] The "DA off signal" is obtained: S_output, which is the input signal S_ctrl delayed for a time Δt1. Step 3: Perform logical operations on the input signal S_ctrl to obtain the "valid window signal" S_LE. The "effective window signal" is generated based on the "original control signal". The leading edge of the window signal is the leading edge delay of the "original control signal" by Δt1 + Δt2. The width of the "effective window signal" lasts for △t3+△t4, that is, the high level lasts for △t3+△t4, and then it is pulled low.

[0042] Step 4: Drive the latch's enable pin LE via S_LE, so that signals within the high-level window of S_LE can pass normally, while signals outside the high-level window cannot pass.

[0043] The following is an example of implementing "A ruggedized protection method for spaceborne antifuse FPGA to avoid damage from high-power switching of PIN switches" following the above process, resulting in a ruggedized circuit.

[0044] A typical "TDD RF + baseband" communication transceiver architecture is as follows: Figure 2 .

[0045] The transmitter uses a combination switch consisting of switch 1 and switch 2 to select between "Mode 1": low-power transmission mode and "Mode 2": high-power transmission mode.

[0046] enter: In low-power transmission mode, after the power supplied by DA to switch 1 is set from 0 to normal, the output of switch 2 also decreases until it stabilizes in the time Δt_DAoff=0.5us; after the power supplied by DA to switch 1 returns to normal from 0, the output power of switch 2 also increases until it stabilizes in the time Δt_DAon=0.5us.

[0047] In high-power transmission mode, after the power supplied by DA to switch 1 is set from 0 to normal, the output of switch 2 also decreases until it stabilizes in the time Δt_DAoff=1us; after the power supplied by DA to switch 1 returns to normal from 0, the output power of switch 2 also increases until it stabilizes in the time Δt_DAon=1us.

[0048] The maximum power amplifier shutdown time is Δt_RFoff = 3.5µs; The maximum power-on time of the power amplifier is Δt_RFon = 3.5µs; The steady-state settling time of switch 1 is Δt_switch = 4µs.

[0049] Following the design method described above, we can obtain: △t1=max[△t_switch, △t_RFon, △t_RFoff]=4us, △t2=max[△t_DA off , △t_DA on =1us (higher in high-power mode); Δt3 can be considered based on a typical value of 1.5us (it is generally not recommended that Δt3 < 1us, and the larger Δt3 is, the greater the overhead).

[0050] △t4 can be considered based on a typical value of 1 us (it is generally not recommended that △t3 < 1 us, and the larger △t3 is, the greater the overhead).

[0051] The final required pulse width of the pulse control signal is Δt = Δt1 + Δt2 + Δt3 + Δt4 = 7.5 μs.

[0052] Therefore, a raw control signal with a pulse width of 7.5µs needs to be generated, and the pulse period depends on the electronic switch switching period, for example, 1ms.

[0053] Original pulse signal such as Figure 6 .

[0054] Logical operation flow as follows Figure 7 .

[0055] The relative relationships between the "raw control signal" (input signal, generated by the SRAM-type FPGA processor), the "DA shutdown signal," and the "effective window signal" are as follows: Figure 7 .

[0056] When the switching occurs within the window where the "effective window signal" is high, normal switching can be achieved, such as... Figure 8 .

[0057] 1) When the electronic switch's selection signal (e.g.) Figure 8 When the change of switch strobe signal 1 or switch strobe signal 2 occurs within the high-level pulse range of the "effective window signal", the latch can transmit the change of switch strobe signal 1 or switch strobe signal 2 from port Ia to port Oa.

[0058] 2) When the electronic switch's selection signal (e.g.) Figure 8 If the change of the switch strobe signal 1 or switch strobe signal 2 does not occur within the high-level pulse range of the "valid window signal", the latch will not transmit the change of the switch strobe signal 1 or switch strobe signal 2 from port Ia to port Oa, that is, it will not respond to the change.

[0059] 3) The above design ensures that after the "effective window signal" ends, a time interval of Δt1 is reserved to allow the electronic switch to reach a steady state. Figure 8 It takes 4µs for the input signal of the DA device to be turned on and amplified by radio frequency before it can be sent to the electronic switch input. This is because the typical characteristic of electronic switches is that they cannot tolerate high power during the establishment of steady state.

[0060] The contents not described in detail in this specification are common knowledge to those skilled in the art.

[0061] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for hardening and protecting spaceborne antifuse FPGAs to avoid damage from high-power switching of PIN switches, characterized in that, Includes the following steps: The "original control signal" is generated by an SRAM-type FPGA. The pulse width of the "original control signal" is at least the sum of the maximum switching delay Δt1, the RF transmission and settling time Δt2, the design margin Δt3, and the effective switching window Δt4. The "original control signal" is converted into the "DA shutdown signal" and the "valid window signal" within the antifuse FPGA; The "DA shutdown signal" is used to turn off the input signal of the DA device for a period of time. The "valid window signal" cuts off or connects the latch, so that the electronic switch control signal sent by the SRAM-type FPGA within the "valid window signal" can be sent to the electronic switch drive circuit, while the control signal sent by the SRAM-type FPGA outside the gate control signal cannot be sent to the electronic switch drive circuit.

2. The method for hardening and protecting spaceborne antifuse FPGAs to avoid damage during high-power switching of PIN switches according to claim 1, characterized in that, The "valid window signal" is a signal with a strictly limited pulse width obtained from the "original control signal". It is used to enable the LE pin of the latch, so that the input signal within the pulse width of the "valid window signal" can pass through normally, and the input signal outside the pulse width of the "window signal" cannot pass through.

3. The method for hardening and protecting spaceborne antifuse FPGAs to avoid damage during high-power switching of PIN switches according to claim 1, characterized in that, The acquisition of the maximum delay for switch switching includes: We need to obtain the maximum power amplifier shutdown time Δt_RFoff, the maximum power amplifier startup time Δt_RFon, and the steady-state settling time of the electronic switch Δt_switch, which are related to the hardware. The maximum delay for switching is Δt1, where Δt1 = max[Δt_RFoff, Δt_RFon, Δt_switch].

4. The method for hardening and protecting spaceborne antifuse FPGAs to avoid damage during high-power switching of PIN switches according to claim 1 or 2, characterized in that, The design margin needs to take into account the processor's minimum processing clock cycle and additional margin protection. The processing speed of the antifuse FPGA processor is higher than 1MHz, the clock cycle is 1us, and the additional margin protection is 0.5us. 1.5us is selected as the design margin.

5. The method for hardening and protecting spaceborne antifuse FPGAs to avoid damage during high-power switching of PIN switches according to claim 1 or 2, characterized in that, The effective switching window is generated by the antifuse FPGA. Considering the minimum processing clock cycle of the processor, the processing speed of the antifuse FPGA processor is higher than 1MHz, the clock cycle is 1us, and the minimum effective switching window is one clock cycle, i.e., 1us.

6. The method for hardening and protecting spaceborne antifuse FPGAs to avoid damage during high-power switching of PIN switches according to claim 1 or 2, characterized in that, The radio frequency transmission and stabilization time is obtained by taking the greater of the time delay between the power switching from DA to switch 2 and the power switching from switch 1.

7. The method for hardening and protecting spaceborne antifuse FPGAs to avoid damage during high-power switching of PIN switches according to claim 1 or 2, characterized in that, The "original control signal" is high within its width and low outside its width.

8. The method for hardening and protecting spaceborne antifuse FPGAs to avoid damage during high-power switching of PIN switches according to claim 1 or 2, characterized in that, The specific method for obtaining the "DA turn-off signal" from the "original control signal" is as follows: The antifuse FPGA samples the "original control signal" and then uses internal logic to delay the signal by Δt1 time to obtain the "DA turn-off signal". This signal turns off the input signal of the external DA device for a period of time.

9. The method for hardening and protecting spaceborne antifuse FPGAs to avoid damage during high-power switching of PIN switches according to claim 1, characterized in that, The "valid window signal" is generated based on the "original control signal". The leading edge of the window signal is the leading edge of the "original control signal" delayed by △t1+△t2, and the width of the window signal lasts for △t3+△t4. The "valid window signal" is used to enable the latch pin, so that the signal inside the window can pass normally, while the signal outside the window cannot pass.

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