Low-cost rapid test system for ultra-high-precision analog-to-digital converter

Abstract

The invention discloses a low-cost rapid test system for an ultrahigh-precision analog-to-digital converter, and the system comprises an upper computer which is used for generating and outputting a test instruction; according to analog-to-digital conversion results output by the to-be-tested ADC under different excitation voltages, differential linear errors and integral linear errors of the to-be-tested ADC are obtained through calculation; the test evaluation board is used for applying different excitation voltages to the to-be-tested ADC according to the test instruction; analog-to-digital conversion results output by the ADC to be tested under different excitation voltages are uploaded to the upper computer; and the power supply module is used for supplying power to the test evaluation board. According to the test system, the requirement that the resolution ratio of the excitation source is higher than that of the to-be-tested ADC is not put forward, and compared with a histogram method, the number of required samples is greatly reduced, so that the economic cost and the time cost can be reduced, and the test efficiency of the ultra-high-precision ADC is improved.

Description

Technical Field

[0001] This invention belongs to the field of analog-to-digital converter technology, and particularly relates to a low-cost, rapid testing system for ultra-high precision analog-to-digital converters. Background Technology

[0002] As ADC resolution increases, histogram methods become impractical. Generally, the average number of samples collected per digit code using histogram methods is 30 to 40. To ensure test quality, hundreds of samples per code may be required. A 24-bit resolution ADC consists of over 16 million digit output codes (16,777,216 codes). When testing a 24-bit resolution ADC using histogram methods by collecting an average of 100 samples per code, over 1.6 billion samples need to be measured, resulting in enormous data storage costs. Furthermore, high-precision ADCs typically have much lower sampling rates than high-speed, low-precision ADCs, so collecting such a large number of samples at a low sampling rate means long test times. Therefore, histogram testing is unsuitable for high-precision ADC linearity testing due to its long testing time. Moreover, histogram methods require the excitation source to have a resolution 3 to 4 bits higher than the ADC under test, making the required audio source increasingly high-quality and expensive. Therefore, traditional histogram methods are prohibitively expensive in terms of both time and cost. Summary of the Invention

[0003] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a low-cost and fast testing system for ultra-high precision analog-to-digital converters. This system aims to overcome the problems of high time and equipment costs required for testing the static parameters of ultra-high precision ADCs using the existing histogram method, and can effectively save testing costs and testing time.

[0004] To address the aforementioned technical problems, this invention discloses a low-cost, rapid testing system for ultra-high precision analog-to-digital converters, comprising: The host computer is used to generate and output test commands; based on the analog-to-digital conversion results output by the ADC under test under different excitation voltages, the differential linearity error and integral linearity error of the ADC under test are calculated; where the ADC under test is... N ADC with 1-bit precision; The test evaluation board is used to apply different excitation voltages to the ADC under test according to the test instructions; and upload the analog-to-digital conversion results output by the ADC under test under different excitation voltages to the host computer. The power module is used to power the test and evaluation board.

[0005] In the aforementioned low-cost, rapid testing system for ultra-high precision analog-to-digital converters, the test evaluation board includes: The FPGA module is used to control the ramp voltage generator and offset voltage generator to apply different excitation voltages to the ADC under test (DUT) through an analog adder according to test commands; and to receive the DUT's output voltages at different excitation voltages. The output of the analog-to-digital conversion result ,Will Upload to the host computer; A ramp voltage generator is used to produce ramp voltage under the control of an FPGA module. ; An offset voltage generator is used to generate an offset voltage under the control of an FPGA module. ; Analog adder for ramp voltage and offset voltage After forward and reverse scaling, the output excitation voltage is... To the ADC under test; The reference source circuit is used to provide a reference voltage for the ADC under test.

[0006] In the aforementioned low-cost, rapid test system for ultra-high precision analog-to-digital converters, the ramp voltage generator employs... M A bit-precision DAC, with an offset voltage generator employing L A bit-precision DAC; where M < N , L < N .

[0007] In the aforementioned low-cost, rapid testing system for ultra-high precision analog-to-digital converters, M The range of the bit-precision DAC is the same as the range of the ADC under test. L The range of a bit-precision DAC is half the range of the ADC under test.

[0008] In the aforementioned low-cost, rapid testing system for ultra-high precision analog-to-digital converters, when the host computer calculates the differential linearity error and integral linearity error of the ADC under test based on the analog-to-digital conversion results output by the ADC under test under different excitation voltages, it includes: Based on polynomial fitting, establish and Nonlinear relationship between them: ···(1) in, Represents polynomial fitting coefficient of the secondary term; according to and The nonlinear relationship between them yields the transfer function coefficients used to describe the conversion characteristics of the ADC under test. : ···(2) in, This represents the numerical polynomial difference of the output of the ADC under test at different offset voltages; Then we have: ···(3) in, This represents the full-scale voltage of the ADC under test. express N The full-scale voltage of an ideal ADC with 1-bit accuracy. This represents a scaling constant. Indicates transpose; Based on transfer function coefficients The actual fitted transfer function of the ADC under test is obtained. ; Based on the actual fitted transfer function of the ADC under test. , combined N Transfer function of an ideal ADC with bit accuracy The differential linearity error and integral linearity error of the ADC under test are calculated.

[0009] In the aforementioned low-cost, fast test system for ultra-high precision analog-to-digital converters, the actual fitted transfer function of the ADC under test... , N Transfer function of an ideal ADC with bit accuracy They are respectively represented as follows ···(4) ···(5) in, This indicates the input voltage.

[0010] In the aforementioned low-cost, fast testing system for ultra-high precision analog-to-digital converters, the transfer function of the actual fitted ADC under test is obtained. , combined N Transfer function of an ideal ADC with bit accuracy The differential linearity error and integral linearity error of the ADC under test are calculated, including: For each digital code, the transfer function is based on the actual fit of the ADC under test. The maximum input voltage under the same digital code output is obtained. and minimum input voltage ;according to and The solution yields the first digit of the ADC under test. k Voltage at the midpoint of each transition : ···(6) according to N Transfer function of an ideal ADC with bit accuracy The solution is obtained N The ideal ADC with 1-bit accuracy k Voltage at the midpoint of each transition : ···(7) in, express N The voltage difference between two adjacent digital codes in an ideal ADC with bit precision; according to and The solution yields the first... k Differential linearity error of each conversion code : ···(8) according to The solution yields the first... k Integral linearity error of each conversion code : ···(9).

[0011] In the aforementioned low-cost, rapid testing system for ultra-high precision analog-to-digital converters, .

[0012] In the aforementioned low-cost, rapid testing system for ultra-high precision analog-to-digital converters, The host computer is also used to generate and output operating mode control instructions; The FPGA module is also used to generate SPI control codes for configuring the operating modes of the ramp voltage generator, offset voltage generator, and ADC under test, based on the operating mode control instructions.

[0013] In the aforementioned low-cost, rapid testing system for ultra-high precision analog-to-digital converters, the power supply module includes: A power supply is used to provide a stable voltage output; The low dropout linear regulator is used to convert the voltage output by the power supply to the operating voltage required by each module in the test and evaluation board, thereby powering each module in the test and evaluation board.

[0014] The present invention has the following advantages: (1) This invention discloses a low-cost and fast test system for ultra-high precision analog-to-digital converters. It does not impose higher requirements on the excitation source than the resolution of the ADC under test, and the number of samples required is significantly reduced compared to the histogram method. Therefore, it can reduce economic and time costs and improve the test efficiency of ultra-high precision ADCs.

[0015] (2) This invention discloses a low-cost and fast test system for ultra-high precision analog-to-digital converters. The required test equipment is simple and the economic cost is low. The sample size is small and the time cost is low. It is highly adaptable and can be easily transferred to other circuits. Attached Figure Description

[0016] Figure 1 This is a block diagram of a low-cost, rapid testing system for an ultra-high precision analog-to-digital converter according to an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments disclosed in the present invention will be described in further detail below with reference to the accompanying drawings.

[0018] Besides the long testing time of traditional histogram tests, generating a pure analog input signal for the ADC under test (DUT) is another problem. The analog input signal stimulating the DUT must have a resolution and linearity at least 3 bits higher than the DUT. This means that testing a 24-bit ADC requires an analog input signal with a minimum resolution of 27 bits. Generating an analog signal with 27 bits or higher precision is extremely challenging and costly. This high-performance and expensive test platform leads to complex test solutions and significantly increases the overall manufacturing cost of the product. The linearity testing scheme proposed in this invention can use a low-precision DAC to test a high-precision ADC. First, the ADC under test is placed on a test evaluation board. The host computer controls the FPGA module to send commands to the ramp voltage generator and the offset voltage generator, so that they generate output voltages and scale them through an analog adder, which are used as the excitation voltages for the ADC under test. Under different excitation voltages, the ADC under test will output different digital codes. The FPGA module will decode these digital codes and store them in SDRAM. After the test is completed, the data is uploaded to the host computer. Then, the host computer uses least squares polynomial fitting technology and estimates the transfer function of the ADC under test by measuring the output code at intermediate code points. The calculated transfer function is used to accurately estimate the integral linearity error (INL) and differential linearity error (DNL) of the ADC under test. The solution described in this invention uses an analog input signal with lower precision than the ADC under test, and requires fewer measurements than histogram testing. Compared to histogram testing, the solution described in this invention does not require expensive testing equipment or a large number of output samples. The solution described in this invention estimates the transfer function of the ADC under test by measuring at intermediate code points and using a polynomial least squares fitting method, and all code widths are accurately defined.

[0019] Reference Figure 1In this embodiment, the low-cost, rapid testing system for the ultra-high precision analog-to-digital converter includes: a host computer, a test evaluation board, and a power supply module. The host computer generates and outputs test commands; the test evaluation board applies different excitation voltages to the ADC under test according to the test commands; the ADC under test outputs different analog-to-digital conversion results under different excitation voltages; the test evaluation board uploads each analog-to-digital conversion result output by the ADC under test under different excitation voltages to the host computer; the host computer calculates the differential linearity error and integral linearity error of the ADC under test based on the various analog-to-digital conversion results output by the ADC under test under different excitation voltages, completing the low-cost, rapid testing of the ultra-high precision analog-to-digital converter; the power supply module supplies power to the test evaluation board. The ADC under test is the ultra-high precision analog-to-digital converter. N ADC with 1-bit precision.

[0020] In this embodiment, the test evaluation board mainly includes: an FPGA module, a ramp voltage generator, an offset voltage generator, an analog adder, and a reference source circuit. The host computer is connected to the FPGA module via USB. The FPGA module first decodes the digital code obtained by the analog-to-digital conversion of the ADC under test and stores the data in SDRAM. After all the digital codes are decoded, the data is uploaded to the host computer via FIFO as the calculation data for the differential linearity error and integral linearity error of the ADC under test.

[0021] Preferably, the FPGA module is used to control the ramp voltage generator and the offset voltage generator to apply different excitation voltages to the ADC under test through an analog adder according to test commands; and to receive the ADC under test under different excitation voltages. The output of the analog-to-digital conversion result ,Will Upload to the host computer. A ramp voltage generator, used to generate ramp voltage under the control of the FPGA module. An offset voltage generator is used to produce an offset voltage under the control of the FPGA module. Analog adder for ramp voltage and offset voltage After forward and reverse scaling, the output excitation voltage is... The reference source circuit is used to provide a reference voltage to the ADC under test.

[0022] Preferably, for N For an ADC with a certain accuracy, a ramp voltage generator of the same range can be used. M A DAC with higher bit accuracy can be used instead, and a half-range offset voltage generator can be employed. L A bit-precision DAC replacement, that is, M The range of the bit-precision DAC is the same as the range of the ADC under test.L The range of a bit-precision DAC is half the range of the ADC under test. M < N , L < N .

[0023] Ultra-high precision ADCs often output millions of codes. Using only a single basis function to estimate the integral linearity error (INL) over the entire output range has accuracy limitations, and high-order polynomial basis functions may lead to overfitting. For a given number of samples, the overall transfer function can be divided into several segments, and the polynomial transfer function of each segment can be solved separately, further improving the accuracy of the estimation results. In this embodiment, the host computer calculates the differential linearity error and integral linearity error of the ADC under test based on the analog-to-digital conversion results output by the ADC under test under different excitation voltages, as follows: Based on polynomial fitting, establish and Nonlinear relationship between them: ···(1) in, Represents polynomial fitting coefficient of the secondary term.

[0024] according to and The nonlinear relationship between them yields the transfer function coefficients used to describe the conversion characteristics of the ADC under test. : ···(2) in, This represents the numerical polynomial difference of the output of the ADC under test at different offset voltages.

[0025] Within the full-scale range of the ADC under test, the overall transfer function is divided into an appropriate number of windows. Then, within each window, a scaling method is used to solve for the optimal coefficients in the polynomial function. The number of windows must ensure that the highest degree of the polynomial function is finite, and that each window has a sufficient number of samples to solve for the polynomial transfer function. Assume the scaling constant is... b Then we have: ···(3) in, This represents the full-scale voltage of the ADC under test. express N The full-scale voltage of an ideal ADC with 1-bit accuracy. This indicates transpose.

[0026] Based on transfer function coefficients The actual fitted transfer function of the ADC under test is obtained. : ···(4) in, This indicates the input voltage.

[0027] Sure N Transfer function of an ideal ADC with bit accuracy : ···(5) Based on the actual fitted transfer function of the ADC under test. , combined N Transfer function of an ideal ADC with bit accuracy The differential linearity error and integral linearity error of the ADC under test are calculated: For each digital code, the transfer function is based on the actual fit of the ADC under test. The maximum input voltage under the same digital code output is obtained. and minimum input voltage ;according to and The solution yields the first digit of the ADC under test. k Voltage at the midpoint of each transition : ···(6) according to N Transfer function of an ideal ADC with bit accuracy The solution is obtained N The ideal ADC with 1-bit accuracy k Voltage at the midpoint of each transition : ···(7) in, express N The voltage difference between two adjacent digital codes in an ideal bit-precision ADC. .

[0028] according to and The solution yields the first... k Differential linearity error of each conversion code : ···(8) according to The solution yields the first... k Integral linearity error of each conversion code : ···(9) In this embodiment, the host computer is also used to generate and output operating mode control instructions; the FPGA module is also used to generate SPI control codes for configuring the operating modes of the ramp voltage generator, offset voltage generator and the ADC under test according to the operating mode control instructions.

[0029] In this embodiment, the power supply module includes a power supply and a low-dropout linear regulator (LDO). The power supply provides a stable voltage output; the LDO converts the voltage output by the power supply into the operating voltage required by each module in the test and evaluation board, thus powering the modules in the test and evaluation board.

[0030] Preferably, the low-dropout linear regulator can be model LT1764, which can be controlled by a host computer.

[0031] Using a 24-bit resolution 2.5MSPS ADC as the ADC under test, an 18-bit 1MSPS DAC as the ramp voltage generator, and a 20-bit 400KSPS DAC as the offset voltage generator, the following steps are taken: The ADC under test is fixed on a test evaluation board, which is powered by a 5V power supply. An external reference chip provides a 2.5V reference voltage to the ADC under test. The host computer controls the power module to power on the entire test system. After power-on, the ADC under test is first reset. Then, the host computer controls the FPGA module to configure SPI to determine whether the read / write function of the ADC under test register is normal. After the test system is connected correctly and the read / write function of the ADC under test register is normal, the FPGA module controls the ramp voltage generator to generate a ramp voltage and controls the offset voltage generator to generate an offset voltage. The offset voltage is added to the generated ramp voltage through an analog adder. Then, the two sets of scaled ramp voltages are applied to a set of 24-bit resolution ADCs under test. In one test, 100 windows with second-order polynomial basis functions were used. To compensate for the noise effects of the 20-bit input signal, each ADC under test was tested 30 times. The output codes of each device were averaged across the 30 repeated test measurements. Therefore, the total number of output samples for each device was 2*2. 20 *30=62914560; In the traditional histogram method, testing a 24-bit resolution ADC typically requires a 28-bit resolution excitation source. Assuming 200 samples are tested for each digital code, the required number of test samples is 2. 24 *200=3355443200; It can be seen that the number of test samples required by this invention is 1.875% of that of the histogram method, and the required sampling time is significantly reduced. In the test results of both the histogram method and the scheme described in this invention, the maximum INL error is less than 0.7151138 LSB, meeting the requirements for evaluating an ADC.

[0032] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

[0033] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A low-cost, rapid testing system for ultra-high precision analog-to-digital converters, characterized in that, include: The host computer is used to generate and output test commands; Based on the analog-to-digital conversion results of the ADC under test under different excitation voltages, the differential linearity error and integral linearity error of the ADC under test are calculated; where, the ADC under test is... N ADC with 1-bit precision; The test evaluation board is used to apply different excitation voltages to the ADC under test according to the test instructions; and upload the analog-to-digital conversion results output by the ADC under test under different excitation voltages to the host computer. The power module is used to power the test and evaluation board.

2. The low-cost, rapid testing system for ultra-high precision analog-to-digital converters according to claim 1, characterized in that, Test evaluation board, including: The FPGA module is used to control the ramp voltage generator and offset voltage generator to apply different excitation voltages to the ADC under test (DUT) through an analog adder according to test commands; and to receive the DUT's output voltages at different excitation voltages. The output of the analog-to-digital conversion result ,Will Upload to the host computer; A ramp voltage generator is used to produce ramp voltage under the control of an FPGA module. ; An offset voltage generator is used to generate an offset voltage under the control of an FPGA module. ; Analog adder for ramp voltage and offset voltage After forward and reverse scaling, the output excitation voltage is... To the ADC under test; The reference source circuit is used to provide a reference voltage for the ADC under test.

3. The low-cost, rapid testing system for ultra-high precision analog-to-digital converters according to claim 2, characterized in that, The ramp voltage generator uses M A bit-precision DAC, with an offset voltage generator employing L A bit-precision DAC; where M < N , L < N .

4. The low-cost, rapid testing system for ultra-high precision analog-to-digital converters according to claim 3, characterized in that, M The range of the bit-precision DAC is the same as the range of the ADC under test. L The range of a bit-precision DAC is half the range of the ADC under test.

5. The low-cost, rapid testing system for ultra-high precision analog-to-digital converters according to claim 2, characterized in that, When the host computer calculates the differential linearity error and integral linearity error of the ADC under test based on the analog-to-digital conversion results output by the ADC under test under different excitation voltages, it includes: Based on polynomial fitting, establish and Nonlinear relationship between them: ···（1） in, Represents polynomial fitting coefficient of the secondary term; according to and The nonlinear relationship between them yields the transfer function coefficients used to describe the conversion characteristics of the ADC under test. : ···（2） in, This represents the numerical polynomial difference of the output of the ADC under test at different offset voltages; Then we have: ···（3） in, This represents the full-scale voltage of the ADC under test. express N The full-scale voltage of an ideal ADC with 1-bit accuracy. This represents a scaling constant. Indicates transpose; Based on transfer function coefficients The actual fitted transfer function of the ADC under test is obtained. ; Based on the actual fitted transfer function of the ADC under test. , combined N Transfer function of an ideal ADC with bit accuracy The differential linearity error and integral linearity error of the ADC under test are calculated.

6. The low-cost, rapid testing system for ultra-high precision analog-to-digital converters according to claim 5, characterized in that, The actual fit transfer function of the ADC under test , N Transfer function of an ideal ADC with bit accuracy They are respectively represented as follows ···（4） ···（5） in, This indicates the input voltage.

7. The low-cost, rapid testing system for ultra-high precision analog-to-digital converters according to claim 6, characterized in that, Based on the actual fitted transfer function of the ADC under test. , combined N Transfer function of an ideal ADC with bit accuracy The differential linearity error and integral linearity error of the ADC under test are calculated, including: For each digital code, the transfer function is based on the actual fit of the ADC under test. The maximum input voltage under the same digital code output is obtained. and minimum input voltage ;according to and The solution yields the first digit of the ADC under test. k Voltage at the midpoint of each transition : ···（6） according to N Transfer function of an ideal ADC with bit accuracy The solution is obtained N The ideal ADC with 1-bit accuracy k Voltage at the midpoint of each transition : ···（7） in, express N The voltage difference between two adjacent digital codes in an ideal ADC with bit precision; according to and The solution yields the first... k Differential linearity error of each conversion code : ···（8） according to The solution yields the first... k Integral linearity error of each conversion code : ···（9）。 8. The low-cost, rapid testing system for ultra-high precision analog-to-digital converters according to claim 7, characterized in that, 。 9. The low-cost, rapid testing system for ultra-high precision analog-to-digital converters according to claim 2, characterized in that, The host computer is also used to generate and output operating mode control instructions; The FPGA module is also used to generate SPI control codes for configuring the operating modes of the ramp voltage generator, offset voltage generator, and ADC under test, based on the operating mode control instructions.

10. The low-cost, rapid testing system for ultra-high precision analog-to-digital converters according to claim 1, characterized in that, The power module includes: A power supply is used to provide a stable voltage output; The low dropout linear regulator is used to convert the voltage output by the power supply to the operating voltage required by each module in the test and evaluation board, thereby powering each module in the test and evaluation board.

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