Optical communication method based on hybrid multiplexing and security isolation and OEO optical transceiver plug-in

Abstract

The invention discloses an optical communication method based on hybrid multiplexing and security isolation and an OEO optical transceiver plug-in, and relates to the technical field of optical communication, and the method comprises the steps: carrying out the classification preprocessing of electric signals from different service sources at a transmitting end; multiplexing the low-speed serial signal and the official telephone signal into a first multiplexing electric signal according to a preset time slot allocation strategy; enabling the Ethernet signal to form a second electric signal through the switching module; converting the high-speed serial optical signal into a third optical signal; the first multiplexing electric signal and the second electric signal are converted into a C-band optical signal through a physically isolated SFP optical module, and the C-band optical signal and a third optical signal are input into a wavelength division multiplexer together to be synthesized into a single-path composite optical signal; amplifying the power of the composite optical signal and transmitting the composite optical signal to a receiving end through a single optical fiber; and separating the C-band optical signal at a receiving end, and restoring the C-band optical signal to an original service signal. According to the invention, low-delay access, high-density integration and anti-interference transmission capabilities of multiple services can be realized in a single-board scale.

Description

Technical Field

[0001] This application relates to the field of optical communication technology, and in particular to an optical communication method based on hybrid multiplexing and security isolation, and an OEO optical transceiver plug-in. Background Technology

[0002] Currently, in modern dedicated communication systems, service types are becoming increasingly diversified. Typical services include low-speed serial data (such as RS-232 / RS-422), analog business telephone voice, Ethernet monitoring data, and high-speed radar or sensor serial optical signals. Traditional architectures typically adopt a distributed design of "one service, one board": that is, each type of service is configured with an independent processing board, and each board is connected to the system backplane through a dedicated interface and transmitted to remote devices via multiple copper cables or optical fibers.

[0003] While such solutions offer advantages like ease of implementation and debugging in single-service scenarios, they reveal significant drawbacks in multi-service converged applications. First, the parallel deployment of multiple physical boards results in bulky equipment and increased power consumption, making it difficult to meet the stringent requirements of compact, low-power communication platforms in automotive environments. Second, each board requires independent power supply, cooling, and management, increasing hardware costs and introducing more connectors, cables, and potential points of failure, thus reducing overall system reliability. Third, the lack of a unified scheduling mechanism prevents different services from sharing transmission resources, leading to low bandwidth utilization and hindering cross-service synchronization, alarm linkage, or security policy coordination.

[0004] In recent years, with the development of optical communication technology, optical transceivers and their pluggable modules have been introduced into the field of dedicated communications, aiming to achieve multi-service convergence through optoelectronic integration. However, existing optical transceiver plug-ins mostly focus on a single service type, such as only supporting Ethernet or only supporting E1 / T1, or although integrating multiple electrical / optical interfaces, they still suffer from rigid resource scheduling and low transmission efficiency when multiple services are transmitted concurrently. Especially in communication scenarios with high reliability and high security requirements, how to achieve low-latency access, high-density integration, and anti-interference transmission capabilities for multiple services within a single board scale remains a technical bottleneck that urgently needs to be overcome by those skilled in the art. Summary of the Invention

[0005] To overcome the shortcomings of existing technologies and achieve low-latency access, high-density integration, and anti-interference transmission capabilities for multiple services within a single board scale in communication scenarios with high reliability and high security requirements, this application provides an optical communication method based on hybrid multiplexing and secure isolation, as well as an OEO optical transceiver plug-in.

[0006] Firstly, the objective of this invention is achieved through the following technical solution: Optical communication methods based on hybrid multiplexing and secure isolation include: At the transmitting end, electrical signals from different service sources are classified and preprocessed. These service sources include multiple low-speed serial signals of different rates, analog voice signals from government telephones, Ethernet signals, and high-speed serial optical signals. The low-speed serial signal and the official telephone signal are multiplexed into a first multiplexed electrical signal through the time-division multiplexing module in the field programmable gate array according to a preset time slot allocation strategy. The Ethernet signal is aggregated by the switching module to form a second electrical signal; The high-speed serial optical signal is converted by OEO and used as the third optical signal; The first multiplexed electrical signal and the second electrical signal are converted into C-band optical signals through physically isolated SFP optical modules, and the C-band optical signal and the third optical signal are input together into a wavelength division multiplexer to synthesize a single composite optical signal. The composite optical signal is amplified and then transmitted to the receiving end via a single optical fiber. At the receiving end, three C-band optical signals are separated by a wavelength demultiplexer. The three C-band optical signals are then restored to the original service signals by the corresponding SFP modules. Based on the monitored bit error rate, the primary SFP channel or the backup SFP channel is dynamically selected to complete the signal recovery.

[0007] By adopting the above technical solution, this invention provides a multi-service OEO optical transceiver plug-in communication method based on hybrid multiplexing and secure isolation. The low-speed serial signal includes at least one RS-232 signal and multiple RS-422 signals of different rates. In order to achieve low-latency access, high-density integration and anti-interference transmission capabilities of multiple services within a single board in communication scenarios with high reliability and high security requirements, this invention integrates multiple service processing capabilities such as RS-232, RS-422, public telephone, Ethernet and high-speed serial optical signals on a single OEO optical transceiver plug-in, completely abandoning the traditional distributed architecture of "one service, one board" to achieve the advanced level and miniaturization of the OEO optical transceiver plug-in. By employing a hybrid multiplexing transmission strategy combining Time Division Multiplexing (TDM) and Wavelength Division Multiplexing (WDM), low-speed asynchronous services (such as serial ports and telephones) and clock-synchronous services (such as Ethernet and high-speed serial data) are optimized and scheduled in the electrical and optical domains respectively. This ensures deterministic latency for low-speed services while fully utilizing C-band spectral resources, enabling multiple services to be carried on a single fiber with high transmission resource utilization. Simultaneously, physically isolated SFP optical modules are allocated to TDM multiplexed signals and Ethernet signals, and different wavelengths are used for transmission in the optical domain. This effectively blocks electrical crosstalk and fault propagation paths between different service types, achieving channel-level secure isolation. Furthermore, a dynamic switching mechanism for primary and backup SFP channels based on real-time bit error rate monitoring is introduced. This automatically avoids degraded links without interrupting services. Combined with optical power amplification and forward error correction design, it ensures stable transmission of critical services under long-distance, harsh channel conditions, meeting the stringent requirements of dedicated communication for "zero-perception fault recovery." In other words, the OEO optical transceiver plug-in of this invention possesses high-reliability transmission and self-healing capabilities. All services are accessed, reused, converted from photoelectric to electrical, and monitored within a unified plugin, reducing the number of external cables, connectors, and independent power modules.

[0008] In a preferred embodiment of this application: the time-division multiplexing module includes a multiplexing circuit and a demultiplexing circuit built based on a field-programmable gate array; the time-division multiplexing module uses a 50MHz reference clock to divide into 10 time slots, of which 6 time slots are allocated to one RS-232 signal, three RS-422 signals and two public telephone signals respectively, and the remaining 4 time slots are reserved for extended service access.

[0009] By adopting the above technical solution, taking the precise division of a 50MHz clock into 10 fixed time slots as an example, deterministic scheduling and latency guarantee of low-speed asynchronous services are achieved. The time slot allocation strategy takes into account both existing dedicated interface standards and future expansion needs.

[0010] In a preferred embodiment of this application: during time division multiplexing, each service signal is subjected to real-time encryption processing based on a key, and a corresponding decryption operation is performed at the receiving end; the original wavelength of the high-speed serial optical signal is 1310nm, the rate range is 1.6Gbps to 2.5Gbps, and after OEO conversion, it is mapped to the ITU-T channel in the C-band to participate in wavelength division multiplexing.

[0011] By adopting the above technical solutions, a key-based real-time encryption and decryption mechanism is introduced in the TDM multiplexing process to ensure the confidentiality of low-speed service data from the source and prevent serial port commands or telephone voice from being eavesdropped on and tampered with. At the same time, the high-speed serial optical signal with a wavelength of 1310nm and a rate of 1.6–2.5Gbps is mapped to the ITU-T standard C-band channel after OEO conversion, so that it can be seamlessly integrated into the WDM system.

[0012] In a preferred embodiment of this application, the method further includes: configuring a primary SFP1 channel and a backup SFP2 channel for the first multiplexed electrical signal, and synchronously transmitting the same content; the receiving end continuously monitors the bit error rate and signal loss alarm status of the two channel signals, and determines the channel degradation status based on the bit error rate and signal loss alarm status; when the primary SFP1 channel is determined to be degraded, switching to the backup SFP2 channel and triggering an alarm command.

[0013] By adopting the above technical solution, the signal loss alarm status is in the LOS state; for the critical first multiplexed electrical signal, the primary and backup SFP dual channels are configured to transmit synchronously, and the link health is evaluated in real time based on the dual criteria of bit error rate and LOS alarm. Once the primary channel deteriorates, it will seamlessly switch to the backup channel, effectively overcoming the risk of service interruption caused by single-point optical module failure.

[0014] In a preferred embodiment of this application: the Ethernet signal includes 10 / 100 / 1000Mbps auto-negotiation rate levels and performs photoelectric conversion through the same SFP channel; the wavelength division multiplexer operates in the C-band with a channel spacing of 100GHz.

[0015] By adopting the above technical solution, Ethernet multi-rate auto-negotiation services are aggregated and then share a single SFP channel to complete photoelectric conversion, reducing the number of optical modules and power consumption; at the same time, the WDM channel spacing is limited to 100GHz, which complies with the ITU-T G.694.1 standard and ensures compatibility with existing DWDM equipment.

[0016] Secondly, the objective of this invention is achieved through the following technical solution: A multi-service OEO optical transceiver plug-in based on hybrid multiplexing and security isolation is used to implement the optical communication method based on hybrid multiplexing and security isolation as described above. The multi-service OEO optical transceiver plug-in includes an FPGA main control unit, a multi-channel Ethernet physical layer interface module, an SFP optical transceiver module, a voice codec module, and a microcontroller monitoring unit. The multi-channel Ethernet physical layer interface module includes at least four Ethernet PHY chips. The MII data interface of each PHY chip is connected to different I / O banks of the FPGA main control unit, and the management data input / output interface and management clock interface are connected to the FPGA main control unit. The FPGA main control unit is configured as follows: During the power-on initialization phase, the working mode register of each Ethernet PHY chip is written through the management data input / output interface and the management clock interface to set it to MII interface mode and enable the auto-negotiation function. During operation, it receives received data signals [0:3], valid signals and link status signals from each Ethernet PHY chip, and encapsulates the received Ethernet frame data into fixed-length TDM service frames. After parsing the TDM service frame to be sent, the data transmission signal [0:3] and the transmission enable signal are output to the corresponding Ethernet PHY chip. The time slot allocation of the TDM service frame is dynamically generated by the TDM scheduler inside the FPGA main control unit according to a preset priority.

[0017] By adopting the above technical solution, a dedicated OEO optical transceiver plug-in hardware platform is provided. This platform connects multiple independent I / O Bank PHY chips via an FPGA main control unit, enabling bidirectional encapsulation / parsing of Ethernet frames to TDM service frames, with time slots dynamically allocated by an internal TDM scheduler. This architecture eliminates the need for general-purpose switching chip solutions, avoiding backplane bus bottlenecks. The multi-PHY physical isolation design suppresses crosstalk between ports, while MII mode auto-negotiation ensures compatibility with various terminals. Overall, it achieves high-throughput, low-latency Ethernet service access.

[0018] In a preferred embodiment of this application, the SFP optical transceiver module includes at least one SFP cage socket and a corresponding SFP controller chip; The differential receiving positive terminal signal and differential receiving negative terminal signal of the SFP Cage socket are isolated by a differential transformer and then connected to the high-speed serial receiving pin of the FPGA main control unit. The high-speed serial transmission pin of the FPGA main control unit is connected to the differential transmission positive terminal signal and the differential transmission negative terminal signal of the SFP Cage socket after being driven by the differential transformer. The signal loss alarm signal, transmission fault signal and module presence signal of the SFP controller chip are connected to the general GPIO terminal of the FPGA main control unit. The FPGA main control unit is configured as follows: In response to the valid presence signal of the module, the rate flag in the EEPROM of the SFP optical transceiver module is read; If the 2.5Gbps OTU mode is identified, the corresponding high-speed serial channel is enabled, and the received OTU frame is descrambled, the payload is extracted, and injected into the specified high-speed time slot of the TDM service frame.

[0019] By adopting the above technical solution, the differential transformer performs common-mode rejection and impedance matching for SFP high-speed signals, improving signal integrity; the FPGA reads the EEPROM identification rate based on the module's in-situ signal and automatically enables the corresponding channel when a 2.5Gbps OTU mode is detected, injecting the payload into the TDM high-speed timeslot. This achieves plug-and-play and seamless electrical layer integration of OTN services without the need for an external protocol converter.

[0020] In a preferred embodiment of this application, the multi-service OEO optical transceiver plug-in also includes a dual-channel PCM codec and a business telephone interface; The analog transmission signal of the official telephone interface is output to the analog input terminal of the first PCM codec, and the analog reception signal is output to the analog output terminal of the first PCM codec. The voice transmission data signal, voice reception data signal, 8kHz frame synchronization signal and bit clock signal of the first PCM codec are connected to the first audio interface group of the FPGA main control unit. The FPGA main control unit is configured as follows: Based on the 8kHz frame synchronization signal, 8-bit μ-Law compressed voice data is read from the voice received data signal in each sampling period; The compressed voice data is packaged into a fixed-rate sub-stream and mapped to a predefined voice time slot of a TDM service frame; The target voice time slot data is extracted from the TDM service frame and output as a voice transmission data signal to the first PCM codec for digital-to-analog conversion. The TDM service frames share the same optical fiber transmission channel with the Ethernet service frames and OTU service frames, and the time slot allocation is uniformly scheduled by the FPGA main control unit.

[0021] By adopting the above technical solution, a dual-channel PCM codec and a business telephone interface are integrated. The FPGA synchronously and accurately samples μ-Law compressed voice at 8kHz frames and maps it to a fixed time slot of TDM frames to achieve deterministic transmission of 64kbps telephone services. The receiving end extracts and reconstructs the data using D / A converters to ensure voice clarity. By digitizing analog telephones and scheduling them uniformly with other services, the wiring complexity of traditional E&M interfaces is avoided.

[0022] In a preferred embodiment, this application includes an EDFA optical amplifier interface; The microcontroller monitoring unit is connected to the FPGA main control unit through a universal asynchronous transceiver interface, and receives system status messages containing signal loss alarm status, power abnormality alarm and link failure information. The general-purpose input / output pins of the microcontroller monitoring unit are connected to the amplifier enable control pins of the EDFA optical amplifier interface; When the microcontroller monitoring unit detects that the signal loss alarm status in the system status message has been valid for a period of time exceeding a preset threshold, it controls the amplifier to output a high-level enable control signal to turn off the EDFA optical amplifier output; and after the signal loss alarm status is restored and the link status is normal, it delays for a preset safety interval and then controls the amplifier to output a low-level enable control signal to re-enable the EDFA optical amplifier.

[0023] By adopting the above technical solution, the microcontroller monitoring unit receives the LOS, power supply, and link status reported by the FPGA, and intelligently controls the EDFA enable signal: when the LOS continuously exceeds the limit, the amplifier is shut down to prevent surge damage, and after recovery, a delayed restart is performed to ensure stability. The closed-loop protection mechanism of this invention avoids the reflection noise or device aging caused by fiber breakage in the traditional EDFA normally open mode.

[0024] In a preferred embodiment, this application includes an AC / DC power supply module and a DC voltage regulator assembly; The AC / DC power module receives external AC power supply signals and converts them into multiple independent DC output rails, namely +12V, +5V, and +3.3V. Each output rail is equipped with a corresponding TVS diode as an overvoltage protection element. The DC regulator group has an embedded temperature sensor and a load voltage detection unit, which are used to feed back real-time voltage and temperature data to the analog-to-digital conversion sampling channel of the FPGA main control unit. The FPGA main control unit periodically collects the voltage and temperature data of each DC power rail. When it detects that the voltage of any rail is lower than the preset voltage threshold or the temperature exceeds the safe range, it outputs a power alarm signal. Based on the status of the power alarm signal, it controls the power status indicator to display the current power health status.

[0025] By adopting the above technical solution, a multi-rail AC / DC power supply is used in conjunction with a TVS diode array to implement graded power supply and ±48V clamping surge protection for +12V (SFP), +5V (PHY / audio), and +3.3V (FPGA); the FPGA main control unit monitors the voltage and temperature of each rail in real time through ADC, and triggers power alarm and drives status lights when abnormality occurs.

[0026] In summary, this application includes at least one of the following beneficial technical effects: 1. This invention classifies and preprocesses low-speed serial, telephone, Ethernet, and high-speed optical signals at the transmitting end, and adopts a hybrid multiplexing architecture of "electrical domain TDM + optical domain WDM" to convert heterogeneous services into C-band optical signals via physically isolated SFPs before multiplexing and transmission. At the receiving end, the signals are demultiplexed and the primary and backup channels are dynamically switched. This method overcomes the limitations of traditional multi-board separate transmission, achieving high-density multi-service transmission on a single fiber, significantly saving fiber resources. 2. Physical isolation and error rate-driven self-healing mechanisms effectively block fault propagation paths; 3. This invention not only meets industrial-grade EMC requirements, but also prevents FPGA logic malfunctions or PHY errors caused by voltage drops through hardware-level power health management. Attached Figure Description

[0027] Figure 1 This is a block diagram illustrating the implementation principle of an optical communication method based on hybrid multiplexing and secure isolation in one embodiment of this application; Figure 2 This is a circuit diagram of the configuration circuit of the FPGA main control unit and the QSPI Flash storage module in a multi-service OEO optical transceiver plug-in based on hybrid multiplexing and security isolation in one embodiment of this application; Figure 3 This is a configuration circuit diagram of the FPGA main control unit in a multi-service OEO optical transceiver plug-in based on hybrid multiplexing and security isolation in one embodiment of this application; Figure 4 This is a high-speed serial interface and TDM scheduling control circuit diagram in a multi-service OEO optical transceiver plug-in based on hybrid multiplexing and security isolation in one embodiment of this application; Figure 5 This is a circuit diagram of a multi-channel Ethernet physical layer interface module in a multi-service OEO optical transceiver plug-in based on hybrid multiplexing and security isolation in one embodiment of this application; Figure 6 This is a high-speed SFP optical module interface and OEO photoelectric conversion control circuit diagram in a multi-service OEO optical transceiver plug-in based on hybrid multiplexing and security isolation in one embodiment of this application; Figure 7This is a diagram of the SFP4 optical module interface and high-speed differential signal conditioning circuit in a multi-service OEO optical transceiver plug-in based on hybrid multiplexing and security isolation in one embodiment of this application; Figure 8 This is a circuit diagram of the official telephone interface and dual-channel PCM audio codec in a multi-service OEO optical transceiver plug-in based on hybrid multiplexing and security isolation in one embodiment of this application; Figure 9 This is a circuit diagram of the microcontroller monitoring unit and EDFA optical amplifier interface in a multi-service OEO optical transceiver plug-in based on hybrid multiplexing and security isolation in one embodiment of this application; Figure 10 This is a circuit diagram of the TTL signal isolation and Ethernet lightning protection module in a multi-service OEO optical transceiver plug-in based on hybrid multiplexing and security isolation in one embodiment of this application. Detailed Implementation

[0028] The following is in conjunction with the appendix Figures 1 to 10 This application will be described in further detail.

[0029] In one embodiment, such as Figure 1 As shown, this application discloses an optical communication method based on hybrid multiplexing and secure isolation, which specifically includes the following steps: S1: At the transmitting end, electrical signals from different service sources are classified and preprocessed. The service sources include multiple low-speed serial signals of different rates, analog voice signals from government telephones, Ethernet signals, and high-speed serial optical signals.

[0030] In this embodiment, the low-speed serial signal refers to an asynchronous serial interface signal conforming to the EIA standard, including one RS-232 signal (rate 128kb / s) and three RS-422 signals (rates of 128kb / s, 512kb / s, and 2Mb / s respectively); the analog voice signal for official telephones refers to analog audio input through an RJ14 two-wire interface, with a frequency band of 300Hz–3.4kHz; the Ethernet signal refers to a 10 / 100 / 1000Mbps auto-negotiation Ethernet signal conforming to the IEEE 802.3 standard; and the high-speed serial optical signal refers to an optical signal with a wavelength of 1310nm and a rate of 1.6Gbps, originating from radar or high-speed acquisition equipment. All of the above signals are connected through a dedicated connector on the front panel of the plug-in module, and the physical interfaces are isolated from each other.

[0031] Specifically, this embodiment is implemented using an OEO optical transceiver module. After the OEO optical transceiver module is powered on, the FPGA main control unit first identifies the presence status of each service interface through the configuration register: for example, detecting the carrier detection (CD) pin level of the RS-232 interface, the terminating resistor matching status of the RS-422 interface, the off-hook / on-hook detection circuit output of the RJ14 interface, the LINK signal of the Ethernet PHY chip, and the Module_Present signal of the SFP Cage. If an interface is valid, the corresponding preprocessing module is started—such as performing Schmitt trigger shaping and parity checking on the RS-232 / 422 signals, sending the public telephone signal to the PCM codec for A / D conversion, buffering the Ethernet frame to the MAC layer buffer, and sending the 1310nm optical signal to the OEO conversion circuit. For example, when a 512kb / s continuous data stream with no frame errors is detected on the RS-422_2 interface, it is marked as "monitoring video control signaling" and high-reliability time slots are allocated preferentially.

[0032] Furthermore, the Ethernet signal includes 10 / 100 / 1000Mbps auto-negotiation rate levels, and photoelectric conversion is completed through the same SFP channel; the wavelength division multiplexer operates in the C-band, with a channel spacing of 100GHz. Ethernet PHY chips include, for example, the DP83848VCC; the same SFP channel refers to a single SFP cage and its associated differential transformer (GST5009LF) and FPGA transceiver.

[0033] For example, two Ethernet interfaces are connected to Port1 and Port2 of the 88E6122 switching chip, respectively. Upon power-up, the switching chip negotiates with the terminal devices (such as surveillance cameras and command terminals): if ETH1 is connected to a gigabit switch, it negotiates to 1000BASE-T; if ETH2 is connected to a 100Mbps sensor, it negotiates to 100BASE-TX. The switching chip forwards the two traffic streams based on the MAC address table and aggregates them into a single gigabit electrical signal output to the FPGA. The FPGA does not perform rate conversion; it directly sends this electrical signal to the SFP2 to complete photoelectric conversion and emit a 1550.12nm optical signal.

[0034] S2: The low-speed serial signal and the official telephone signal are multiplexed into a first multiplexed electrical signal by the time division multiplexing module in the field programmable gate array according to the preset time slot allocation strategy; the Ethernet signal is aggregated by the switching module to form a second electrical signal; and the high-speed serial optical signal is converted into a third optical signal by OEO.

[0035] In this embodiment, the time-division multiplexing module is a hard-wired multiplexing / demultiplexing circuit built from the internal logic resources of the Xilinx Artix-7 series FPGA, including 6 independent data sampling FIFOs, 1 10-slot TDM scheduler, and 1 6B / 10B encoder; the switching module is a built-in 88E6122 Ethernet switching chip, which supports the aggregation of two 100Mbps network ports into a single gigabit uplink; the OEO conversion circuit is composed of a cascaded 1310nm SFP receiver, signal conditioning circuit, and C-band SFP transmitter to realize wavelength conversion from 1310nm to C-band.

[0036] Specifically, the FPGA uses a 50MHz system clock as a reference, dividing each 20ns into a basic time unit, and each 200ns (i.e., 10 units) constitutes a TDM frame cycle. Within each cycle, the TDM scheduler enables 6 service channels in a fixed order (the TDM frame cycle is 200ns, divided into 17 basic time units): the first time slot reads RS-232 data (1 byte), the second and third time slots read RS-422_1 (128kb / s, 2 bytes), the fourth and fifth time slots read RS-422_2 (512kb / s, 4 bytes), the sixth and ninth time slots read RS-422_3 (2Mb / s, 8 bytes), the tenth and eleventh time slots read the first telephone PCM data (8 bits), the twelfth and thirteenth time slots read the second telephone PCM data (8 bits) – the remaining four time slots (14th–17th) remain idle, reserved for future expansion such as BeiDou timing pulses. Meanwhile, the 88E6122 switching chip forwards two 100Mbps Ethernet traffic streams based on the MAC address table and aggregates them into a single gigabit electrical signal output to the FPGA; the 1310nm optical signal is received by the SFP, converted into an electrical signal, and then drives the C-band SFP to emit a 1550.12nm optical signal, which is directly output as the third optical signal.

[0037] Furthermore, during time-division multiplexing, key-based real-time encryption is implemented for each service signal, and decryption is performed at the receiving end accordingly. The original wavelength of the high-speed serial optical signal is 1310nm, with a rate range of 1.6Gbps to 2.5Gbps. After OEO conversion, it is mapped to the ITU-T channel in the C-band to participate in wavelength division multiplexing. In this embodiment, key-based real-time encryption refers to integrating a lightweight stream encryption engine inside the FPGA, using the AES-128 algorithm. The key is dynamically generated by a security chip (such as ATECC608A) when the plug-in is powered on and stored in the FPGA's Block RAM. Only the data payload of low-speed service time slots (RS-232 / RS-422 / telephone) in the TDM frame is encrypted byte by byte, while the frame header and time slot identifier remain in plaintext for scheduling. The ATECC608A communicates with the FPGA through a dedicated SPI bus. The key is encrypted using a temporary session key during transmission, and the Block RAM is configured in an unreadable debug mode. OEO conversion refers to converting a 1310nm input optical signal into an electrical signal via a PIN photodiode, which then drives a DFB laser to emit a C-band optical signal; "ITU-T channel" specifically refers to a 100GHz interval wavelength conforming to the G.694.1 standard.

[0038] Specifically, after TDM multiplexing is completed at the transmitting end and before SFP transmission, the FPGA reads the current session key (e.g., 0x3A7F...) and performs AES-128 encryption on the valid data bytes of each service time slot. For example, when RS-422_3 (2Mb / s) transmits the radar azimuth command "0x55AA", it is encrypted as "0xC2D9", and this ciphertext is written into time slots 6-9 of the TDM frame. The receiving FPGA uses the same key to synchronously decrypt and restore the original command. The key is automatically rotated every 24 hours, or forcibly updated by a remote management station through a secure channel. Simultaneously, after the 1310nm high-speed optical signal enters the OEO circuit, its electrical signal drives a C-band SFP module with a center wavelength of 1550.12nm, which is strictly aligned with the ITU-T 100GHz grid.

[0039] S3: The first multiplexed electrical signal and the second electrical signal are converted into C-band optical signals through physically isolated SFP optical modules, and the C-band optical signal and the third optical signal are input together into a wavelength division multiplexer to synthesize a single composite optical signal.

[0040] In this embodiment, physically isolated SFP optical modules refer to two independent SFP cage sockets, such as SFP1 and SFP2, each equipped with a dedicated power filter circuit, differential transformer (GST5009LF), and LOS monitoring circuit to ensure electrical and thermal isolation; C-band optical signals refer to optical carriers with wavelengths in the range of 1530–1565nm, specifically allocated as follows: the first multiplexed electrical signal is 1552.52nm (λ1), the second electrical signal is 1550.12nm (λ2), and the third optical signal is 1548.51nm (λ3); the wavelength division multiplexer is a 100GHz channel-spaced CWDM multiplexer with a center wavelength conforming to the ITU-T G.694.1 standard. Specifically, the TDM primary and backup channels are SFP_A (primary) and SFP_B (backup), both operating at 1552.52nm; the Ethernet channel is SFP_C, operating at 1550.12nm; and the high-speed OTU channel is SFP_D, operating at 1548.51nm.

[0041] Specifically, the FPGA outputs the first multiplexed electrical signal to the TX_P / TX_N pins of SFP1. After being driven by a differential transformer, SFP1 emits a 1552.52nm optical signal. It also outputs the Ethernet aggregation electrical signal to the TX_P / TX_N pins of SFP2, emitting a 1550.12nm optical signal. The third optical signal (1548.51nm) is directly output from the OEO circuit. These three optical signals are connected to the λ1, λ2, and λ3 ports of a CWDM multiplexer via single-mode fiber optic pigtails. The multiplexer uses thin-film filter technology to couple the three wavelengths to a common port, outputting a single composite optical signal. For example, when the system is operating at full load, the measured values ​​are: multiplexing insertion loss <1.2dB, and inter-channel crosstalk <-30dB.

[0042] S4: After power amplification of the composite optical signal, it is transmitted to the receiving end through a single optical fiber.

[0043] In this embodiment, power amplification is performed by an EDFA (Erbium-doped Fiber Amplifier) ​​module, with an input optical power range of -10dBm to +3dBm and an output optical power adjustable to +17dBm. The noise figure is <5dB. The single fiber refers to a single-mode fiber conforming to the G.652.D standard.

[0044] Specifically, the combined optical signal after multiplexing first enters the input of the EDFA. The STM32 microcontroller dynamically controls the DIS enable pin of the EDFA based on the link status reported by the FPGA. Under normal conditions, the DIS enable pin is low, and the EDFA is amplified. If an upstream fiber break is detected (when the LOS state lasts for >500ms), the DIS enable pin is set high to shut down the EDFA, preventing reflected light from damaging the device. The amplified optical signal (typically +15dBm) is injected into a single optical fiber via the LC / APC connector and transmitted to the remote receiving plug. In a 40km link test, the optical power at the receiving end stabilized at -8dBm, and the bit error rate was less than 1×10⁻⁶. -12 .

[0045] In this embodiment, the optical communication method based on hybrid multiplexing and secure isolation further includes: configuring a primary SFP1 channel and a backup SFP2 channel for the first multiplexed electrical signal, and synchronously transmitting the same content; the receiving end continuously monitors the bit error rate and signal loss alarm status of the two channel signals, and determines the channel degradation status based on the bit error rate and signal loss alarm status; when it is determined that the primary SFP1 channel is degraded, it switches to the backup SFP2 channel and triggers an alarm command.

[0046] Specifically, both the primary SFP1 channel and the backup SFP2 channel are configured to receive 1552.52nm wavelength optical signals and are connected to different high-speed transceivers (GTPE2_CHANNEL) on the FPGA. Bit error rate monitoring is implemented by the PRBS31 checker built into the FPGA, which counts the number of bit errors per second and calculates the BER. The signal loss alarm status (LOS) is output by the comparator inside the SFP module, and the LOS pin is pulled high when the received optical power is <-30dBm.

[0047] For example, at the transmitting end, the FPGA simultaneously drives the TX ports of SFP1 and SFP2 with the same first multiplexed electrical signal, achieving dual transmission of the same content. At the receiving end, the two 1552.52nm optical signals are sent to SFP_A (primary) and SFP_B (backup) respectively via wavelength division multiplexers. The FPGA continuously acquires the BER and LOS of the two signals: if the BER of SFP_A is >1×10⁻ for 2 consecutive seconds... 9 If LOS=1, it is determined that the primary channel is degraded (e.g., due to fiber micro-bending or connector contamination). At this time, the TDM demultiplexer immediately switches the data source to SFP_B and sends a "CH1_FAIL" command to the STM32 via GPIO, triggering the red LED to flash at a frequency of 1Hz. The switching process is completed within 200ns, which is less than one TDM frame period.

[0048] S5: At the receiving end, three C-band optical signals are separated by a wavelength demultiplexer. The three C-band optical signals are restored to the original service signals by the corresponding SFP modules. Based on the monitored bit error rate, the primary SFP channel or the backup SFP channel is dynamically selected to complete the signal recovery.

[0049] In this embodiment, the wavelength demultiplexer is a CWDM demultiplexer paired with the transmitter, which separates the composite optical signal into three output ports according to wavelength; the primary and backup SFP channels refer to the SFP1 (primary) channel and SFP2 (backup) channel configured for the first multiplexed electrical signal, both of which synchronously receive optical signals of the same wavelength (1552.52nm); the bit error rate monitoring is implemented by the PRBS (pseudo-random code) verification module built into the FPGA, with a sampling period of 1 second.

[0050] For example, the receiver demultiplexer sends three optical signals—1552.52nm, 1550.12nm, and 1548.51nm—to SFP_A, SFP_B, and SFP_C, respectively. SFP_A and SFP_D (as a spare) simultaneously receive the 1552.52nm signal. The FPGA continuously counts the bit error rate (BER) of both signals: if the BER of SFP_A is > 1 × 10⁻⁻⁻⁶, the signal is considered normal. 9 If the primary channel is degraded and the LOS signal remains valid for two consecutive sampling cycles, the system immediately switches to the SFP_D data stream and sends an alarm command to the STM32 microcontroller via UART, illuminating the red ERR_LED connected to the STM32 microcontroller. The switching process is completed within one TDM frame cycle (200ns), with no noticeable service interruption.

[0051] In one embodiment, such as Figures 2 to 10 As shown in the embodiments, this application also discloses a multi-service OEO optical transceiver plug-in based on hybrid multiplexing and security isolation. It should be noted that: Figures 2 to 10 This is merely a simplified circuit diagram of a multi-service OEO optical transceiver plug-in based on hybrid multiplexing and security isolation, as described in this application. Only a portion of the core circuit diagram is shown in the diagram; repetitive or similar circuit connections or non-critical parts are not included. Figures 2 to 10 Not shown in the diagram. The multi-service OEO optical transceiver plug-in based on hybrid multiplexing and security isolation is used to implement the optical communication method based on hybrid multiplexing and security isolation as described above. For example... Figures 2 to 10 As shown, the multi-service OEO optical transceiver module includes an FPGA main control unit, a multi-channel Ethernet physical layer interface module, an SFP optical transceiver module, a voice codec module, and a microcontroller monitoring unit.

[0052] like Figure 2 and Figure 3 As shown, with Figure 2 and Figure 3 Taking the circuit diagram shown as an example, Figure 2 The circuit diagram shows the configuration circuit of the FPGA main control unit and the QSPI Flash memory module, including the JTAG debug interface circuit, the FPGA Bank0 power supply pin, and the QSPI Flash memory circuit (U8); the memory model is N25Q256A13EF84G. Figure 2 U7 is a high-speed tri-state buffer (8-bit) used for JTAG signal level conversion and drive enhancement, model number SN74LV541APWR. U6 is the FPGA main control chip of the FPGA main control unit, model number xc7a35t-1fgg484. Red and green dual-color indicator lights D1 and D2 are used for FPGA configuration status feedback (red = configuration failure, green = success). High-speed buffer U7 is used to drive JTAG signals, improving signal driving capability and common-mode interference immunity; all JTAG signals are pulled up to VDD33 (3.3V) through pull-up resistors to ensure a default high level when floating; the JTAG_TDO pin is connected to a pull-up resistor + ground to form an open-drain output structure, compatible with various debugging devices.

[0053] Figure 2 In the middle, the FPGA BANK0 configuration and status feedback circuit (top right) enters configuration mode after power-on; if PROG_B is pulled low, it starts reading the configuration file from QSPI Flash; the FPGA is set to QSPI mode through M0 / M1 (based on the voltage division ratio of resistors R82 and R83); before INIT_B is pulled high, the FPGA is in a reset state; DONE being pulled high indicates that the configuration is complete; FPGA_DONE illuminates LED_G via an inverter, indicating successful configuration.

[0054] The multi-service OEO optical transceiver module includes an AC / DC power supply module (not shown in the figure) and a DC regulator group; the AC / DC power supply module is such as the MORNSUN LHE15-20B12; the DC regulator group is such as the TPS7A4700. The AC / DC power supply module receives external AC power supply signals and converts them into multiple independent DC output rails, namely +12V, +5V, and +3.3V. The +12V output rail is connected to the power input terminal of the SFP optical transceiver module; the +5V output rail directly supplies the Ethernet PHY chipset and is connected to the analog power terminal of the voice codec after being filtered by a ferrite bead; the +3.3V output rail is regulated by a low-noise LDO and then supplied to the FPGA core logic and I / O bank; each output rail is equipped with a corresponding TVS diode as an overvoltage protection element, such as the SMBJ12CA TVS diode.

[0055] The DC regulator assembly incorporates a temperature sensor and a load voltage detection unit to feed real-time voltage and temperature data back to the analog-to-digital conversion sampling channel of the FPGA main control unit. The temperature sensor is an example of an LM75. The load voltage detection unit uses a high-precision resistor divider to reduce the voltage value to a range acceptable to the FPGA main control unit. Specifically, the load voltage detection unit includes a first voltage divider resistor with a resistance of 20 kg and a second voltage divider resistor with a resistance of 5.1 kg, connected in series. In another embodiment, the load voltage detection unit can also use a multi-channel voltage monitor such as the Maxim MAX1619 / MAX6820. The FPGA main control unit periodically collects voltage and temperature data from each DC power rail. When any voltage is detected to be below a preset threshold or the temperature exceeds a safe range, a power alarm signal is triggered. Based on the status of the power alarm signal, the power status indicator light displays the current power health status.

[0056] like Figure 3 As shown, with Figure 3 Taking the circuit diagram shown as an example, Figure 3 Pin assignment and interface design for the Ethernet PHY chip U6C configured for the I / O of FPGAs BANK14 and BANK15. PHY_MDC and PHY_MDIO are the Ethernet management buses; SW1_RXD0~RXD7 and TXD0~TXD7 are the first Ethernet switch chip interfaces; SW2_RXD0~RXD7 and TXD0~TXD7 are the second Ethernet switch chip interfaces. LEDs LED_L1~LED_L6 are used to display the status of each Ethernet port and the system's operating status.

[0057] like Figure 4 and Figure 5 As shown, with Figure 4 Taking the circuit diagram shown as an example, Figure 4 It is a high-speed serial interface and TDM scheduling control circuit. Figure 4 The U20 in the configuration is a Marvell 8E6122 Gigabit Ethernet switch chip, supporting eight RJ45 ports or SFP optical ports. The BCP6911 Q1 forms the power-on control and voltage feedback circuit. Q1 is a PWM controller used to generate the VCC_1.8V power rail, which works with a low-dropout linear regulator (LDO) to achieve efficient voltage regulation. The LDO generates the VCC_1.2V power rail. The P1_MDIN and P1_MDIP pins of the U20 are MDI inputs, connected to the RJ45 or SFP module to receive Ethernet signals. The P1_SPEED pin is the speed detection pin. P1_LINK is the link status detection pin, and P1_MODE, P2_MODE, and P3_MODE are the operating mode selection pins.

[0058] like Figure 5 As shown, with Figure 5 Taking the circuit diagram shown as an example, the multi-channel Ethernet physical layer interface module includes at least four Ethernet PHY chips (U2, U46, U6, U7, model DP83848VCC), labeled PHY0, PHY1, PHY2, and PHY3 respectively. The MII data interface (TXD[0:3], RXD[0:3], TX_EN, RX_CLK, etc.) of each PHY chip is connected to different I / O banks (such as Bank 0~3) of the FPGA main control unit. The management data input / output interface (MDIO / MDC interface in the figure) and the management clock interface are connected to the FPGA main control unit. The clock input (PHY_CLK_0~PHY_CLK_3) of each PHY chip is provided by frequency division of an external crystal oscillator, where PHY0 and PHY1 use a 50MHz clock, and PHY2 and PHY3 use a 25MHz clock. The power rails (VCC3_SW1, VCC3_SW2) of all PHY chips are decoupled through independent filter capacitors.

[0059] The FPGA main control unit is configured as follows: During the power-on initialization phase, it writes the working mode register to each Ethernet PHY chip through the management data input / output interface and the management clock interface, sets it to MII interface mode and enables the automatic negotiation function; During the operation phase, it receives the receive data signal [0:3] (RXD[0:3]), the receive valid signal (RXDV) and the link status signal (LINK) from each Ethernet PHY chip, and encapsulates the received Ethernet frame data into fixed-length TDM service frames; After parsing the TDM service frame to be sent, it outputs the transmit data signal [0:3] and the transmit enable signal to the corresponding Ethernet PHY chip; The time slot allocation of the TDM service frame is dynamically generated by the TDM scheduler inside the FPGA main control unit according to the preset priority. For example, in the Vivado project, the MII interface is instantiated through the Xilinx IP core "AXI Ethernet Subsystem", and MDIO / MDC is bound to the GPIO of Bank14 [10:11]. After power-on, the ARM Cortex-M1 soft core executes the initialization script, writes 0x1140 to the PHY0 register 0x0, and enables MII mode and auto-negotiation.

[0060] like Figure 6 As shown, with Figure 6 Taking the circuit diagram shown as an example, Figure 6 For high-speed SFP optical module interface and OEO photoelectric conversion control circuit; Figure 6It includes two SFP optical module interfaces (U13A, U17A) and a corresponding SFP Cage (U13B); the SFP optical transceiver module includes at least one SFP Cage socket and a corresponding SFP controller chip; the SFP controller chip model is LQM18PN4R7MFRL. SFP1_TX_Fault, SFP1_TX_Disable, SFP1_SDA, and SFP1_SCL are control signals generated by the FPGA or STM32 and used to configure the SFP module. The differential receive positive and differential receive negative signals (RX_P / RX_N) of the SFP Cage socket are isolated by a differential transformer and then connected to the high-speed serial receive pin of the FPGA main control unit. The high-speed serial transmit pin of the FPGA main control unit is driven by a differential transformer and then connected to the differential transmit positive and differential transmit negative signals of the SFP Cage socket. The differential transformer is a GST5009LF. The signal loss alarm signal (LOS), transmit fault signal (TxFault), and module present signal (Module_Present) of the SFP controller chip are connected to the general-purpose GPIO pins of the FPGA main control unit. The FPGA main control unit is configured to: in response to a valid module-in-presence signal, read the rate identifier from the SFP optical transceiver module's EEPROM; if it identifies a 2.5Gbps OTU mode, enable the corresponding high-speed serial channel, descramble the received OTU frame, extract the payload, and inject it into the designated high-speed timeslot of the TDM service frame. The FPGA, through its built-in I²C controller, accesses EEPROM address 0xA0 via the SFP's MOD_DEF0 / 1 pin after the Module_Present signal is valid, reading the 36th byte (rate identifier field). If the value is 0x19, it is determined to be in 2.5Gbps OTU mode. The RS-422 interface termination resistor status is detected by a high-resistance state detection circuit (e.g., ...). Figure 5 The voltage is determined by the R_TERM and ADC sampling. When the voltage is >2.0V, it is considered a terminal match.

[0061] like Figure 7 As shown, with Figure 7 Taking the circuit diagram shown as an example, Figure 7The core component of the SFP4 optical module interface and high-speed differential signal conditioning circuit is U21, a GST5009LF differential transformer array. U21 provides four-channel differential signal isolation and impedance matching; each channel contains one transformer (TD1~TD4). TPI_LINK_SI and TPI_FDX_SI are dual-color LED status indicators (IP2 in the diagram). U23A is the SFP optical module controller chip; U23B is the physical interface for inserting SFP optical modules, supporting 2.5Gbps OTUs. In the SFP4 optical module interface structure, TX_P / N represents the transmit differential signal; RX_P / N represents the receive differential signal sent to the FPGA. MOD_DEF_0~2 are module definition pins used to identify the module type.

[0062] like Figure 8 As shown, with Figure 8 Taking the circuit diagram shown as an example, Figure 8 This diagram shows the circuitry for a business telephone interface and a dual-channel PCM audio codec, including a J14X2 business telephone interface (JP1A), dual W681512WG PCM codec chips (U10, U11), and an FPGA control interface (P1: SHL603C). The W681512WG chip supports both μ-Law and A-Law voice compression algorithms, selectable via the Select A Law signal. Figure 8 D13~D15 are TVS transient voltage suppression diodes. The multi-service OEO optical transceiver module also includes dual-channel PCM codecs (U10, U11) and a public telephone interface (RJ14); the analog transmit signal A_T and analog receive signal A_R of the public telephone interface are output to the analog input and analog output terminals of the first PCM codec, respectively; the voice transmit data signal (PCMT), voice receive data signal (PCMR), 8kHz frame synchronization signal (FSR), and bit clock signal (BCLKT) of the first PCM codec are connected to the first audio interface group of the FPGA main control unit. P1 is a 20-pin connector of model SHL603C, used for the digital interface between the FPGA and the PCM chip. A_VX / B_VX and A_VR / B_VR pins are analog voltage input and output terminals. PCM codec chip U10 is channel A, used for the main line; PCM codec chip U11 is channel B, used for backup lines or expansion. The FPGA main control unit reads digital voice data through A_PCM_RX / B_PCM_RX. After PCM encoding, the voice signal is included in the TDM time slot pool by the FPGA main control unit and shares the same fiber optic channel with other service signals.

[0063] The FPGA main control unit uses an 8kHz frame synchronization signal as a reference to read 8-bit μ-Law compressed voice data from the voice reception data signal in each sampling period; it packages the compressed voice data into a fixed-rate sub-stream and maps it to a predefined voice time slot of the TDM service frame; it extracts the target voice time slot data from the TDM service frame and outputs it to the first PCM codec for digital-to-analog conversion via a voice transmission data signal; the TDM service frame shares the same optical fiber transmission channel with the Ethernet service frame and the OTU service frame, and the FPGA main control unit uniformly schedules the time slot allocation.

[0064] like Figure 9 As shown, with Figure 9 Taking the circuit diagram shown as an example, the multi-service OEO optical transceiver plug-in also includes a microcontroller monitoring unit and an EDFA optical amplifier interface (P3); the microcontroller monitoring unit is an STM32F103VC microcontroller (U26). The microcontroller monitoring unit connects to the FPGA main control unit via a universal asynchronous transceiver interface, receiving system status messages containing signal loss alarm status, power failure alarm, and link fault information; the general-purpose input / output pins of the microcontroller monitoring unit are connected to the amplifier enable control pin of the EDFA optical amplifier interface; if the signal loss alarm status in the received system status message remains valid for more than a preset threshold time, the microcontroller monitoring unit controls the amplifier to output a high-level enable control signal to disable the EDFA optical amplifier output; after the signal loss alarm status recovers and the link status returns to normal, it delays for a preset safety interval before controlling the amplifier to output a low-level enable control signal to re-enable the EDFA optical amplifier. Simultaneously, it drives the ERR_STATUS_G / R dual-color LED indicator; a solid green light indicates normal system operation, while a flashing red light indicates the presence of an unrecovered alarm.

[0065] like Figure 10 As shown, with Figure 10 Taking the circuit diagram shown as an example, Figure 10This is the circuit diagram for the system-level status indication, TTL signal isolation, and Ethernet surge protection module in the OEO optical transceiver plug-in. LED status indicators (D7~D9, D12~D14) are used to display the system status; all LEDs are common cathode structures, controlled by FPGA or STM32 via GPIO. LED_RADAR_LINK: yellow, indicating radar link established; LED_MON_LINK: green, indicating monitoring link normal; LED_ERR_STATUS_G / R: red and green, indicating error status respectively; LED_OPTICAL_STATUS: blue, indicating optical path normal. U30, U31, and U32 are UNSR5485-2HL tri-state buffers and inverters used for TTL level conversion and signal isolation. G1~G5 are UN250-060 TVS transient voltage suppressor diodes used for lightning and electrostatic discharge protection.

[0066] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0067] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An optical communication method based on hybrid multiplexing and secure isolation, characterized in that, include: At the transmitting end, electrical signals from different service sources are classified and preprocessed. These service sources include multiple low-speed serial signals of different rates, analog voice signals from government telephones, Ethernet signals, and high-speed serial optical signals. The low-speed serial signal and the official telephone signal are multiplexed into a first multiplexed electrical signal through the time-division multiplexing module in the field programmable gate array according to a preset time slot allocation strategy. The Ethernet signal is aggregated by the switching module to form a second electrical signal; The high-speed serial optical signal is converted by OEO and used as the third optical signal; The first multiplexed electrical signal and the second electrical signal are converted into C-band optical signals through physically isolated SFP optical modules, and the C-band optical signal and the third optical signal are input together into a wavelength division multiplexer to synthesize a single composite optical signal. The composite optical signal is amplified and then transmitted to the receiving end via a single optical fiber. At the receiving end, three C-band optical signals are separated by a wavelength demultiplexer. The three C-band optical signals are then restored to the original service signals by the corresponding SFP modules. Based on the monitored bit error rate, the primary SFP channel or the backup SFP channel is dynamically selected to complete the signal recovery.

2. The optical communication method based on hybrid multiplexing and secure isolation according to claim 1, characterized in that, The time-division multiplexing module includes multiplexing circuits and demultiplexing circuits built on a field-programmable gate array. The time-division multiplexing module uses a 50 MHz reference clock to divide the clock into 10 time slots. Six time slots are allocated to one RS-232 signal, three RS-422 signals and two business telephone signals, respectively. The remaining four time slots are reserved for expanding service access.

3. The optical communication method based on hybrid multiplexing and secure isolation according to claim 1, characterized in that, During time division multiplexing, each service signal is encrypted in real time based on a key, and a corresponding decryption operation is performed at the receiving end. The original wavelength of the high-speed serial optical signal is 1310nm, and the rate range is 1.6Gbps to 2.5Gbps. After OEO conversion, it is mapped to the ITU-T channel in the C-band to participate in wavelength division multiplexing.

4. The optical communication method based on hybrid multiplexing and secure isolation according to claim 1, characterized in that, The method further includes: configuring a primary SFP1 channel and a backup SFP2 channel for the first multiplexed electrical signal, and synchronously sending the same content; the receiving end continuously monitors the bit error rate and signal loss alarm status of the two channel signals, and judges the channel degradation status based on the bit error rate and signal loss alarm status; when the primary SFP1 channel is determined to be degraded, switching to the backup SFP2 channel and triggering an alarm command.

5. The optical communication method based on hybrid multiplexing and secure isolation according to claim 1, characterized in that, The Ethernet signal includes 10 / 100 / 1000Mbps auto-negotiation rate levels and completes photoelectric conversion through the same SFP channel; the wavelength division multiplexer operates in the C-band with a channel spacing of 100GHz.

6. A multi-service OEO optical transceiver plug-in based on hybrid multiplexing and security isolation, characterized in that: For implementing the optical communication method based on hybrid multiplexing and security isolation as described in any one of claims 1 to 5, the multi-service OEO optical terminal plug-in includes an FPGA main control unit, a multi-channel Ethernet physical layer interface module, an SFP optical transceiver module, a voice codec module, and a microcontroller monitoring unit; The multi-channel Ethernet physical layer interface module includes at least four Ethernet PHY chips. The MII data interface of each PHY chip is connected to different I / O banks of the FPGA main control unit, and the management data input / output interface and management clock interface are connected to the FPGA main control unit. The FPGA main control unit is configured as follows: During the power-on initialization phase, the working mode register of each Ethernet PHY chip is written through the management data input / output interface and the management clock interface to set it to MII interface mode and enable the auto-negotiation function. During operation, it receives received data signals [0:3], valid signals and link status signals from each Ethernet PHY chip, and encapsulates the received Ethernet frame data into fixed-length TDM service frames. After parsing the TDM service frame to be sent, the data transmission signal [0:3] and the transmission enable signal are output to the corresponding Ethernet PHY chip. The time slot allocation of the TDM service frame is dynamically generated by the TDM scheduler inside the FPGA main control unit according to a preset priority.

7. The multi-service OEO optical transceiver plug-in based on hybrid multiplexing and security isolation according to claim 6, characterized in that, The SFP optical transceiver module includes at least one SFP Cage socket and a corresponding SFP controller chip; The differential receiving positive terminal signal and differential receiving negative terminal signal of the SFP Cage socket are isolated by a differential transformer and then connected to the high-speed serial receiving pin of the FPGA main control unit. The high-speed serial transmission pin of the FPGA main control unit is driven by the differential transformer and connected to the differential transmission positive terminal signal and differential transmission negative terminal signal of the SFPCage socket. The signal loss alarm signal, transmission fault signal and module presence signal of the SFP controller chip are connected to the general GPIO terminal of the FPGA main control unit. The FPGA main control unit is configured as follows: In response to the valid presence signal of the module, the rate flag in the EEPROM of the SFP optical transceiver module is read; If the 2.5Gbps OTU mode is identified, the corresponding high-speed serial channel is enabled, and the received OTU frame is descrambled, the payload is extracted, and injected into the specified high-speed time slot of the TDM service frame.

8. The multi-service OEO optical transceiver plug-in based on hybrid multiplexing and security isolation according to claim 6, characterized in that, The multi-service OEO optical transceiver plug-in also includes a dual-channel PCM codec and a business telephone interface; The analog transmission signal of the official telephone interface is output to the analog input terminal of the first PCM codec, and the analog reception signal is output to the analog output terminal of the first PCM codec. The voice transmission data signal, voice reception data signal, 8kHz frame synchronization signal and bit clock signal of the first PCM codec are connected to the first audio interface group of the FPGA main control unit. The FPGA main control unit is configured as follows: Based on the 8kHz frame synchronization signal, 8-bit μ-Law compressed voice data is read from the voice received data signal in each sampling period; The compressed voice data is packaged into a fixed-rate sub-stream and mapped to a predefined voice time slot of a TDM service frame; The target voice time slot data is extracted from the TDM service frame and output as a voice transmission data signal to the first PCM codec for digital-to-analog conversion. The TDM service frames share the same optical fiber transmission channel with the Ethernet service frames and OTU service frames, and the time slot allocation is uniformly scheduled by the FPGA main control unit.

9. The multi-service OEO optical transceiver plug-in based on hybrid multiplexing and security isolation according to claim 6, characterized in that, Including the EDFA optical amplifier interface; The microcontroller monitoring unit is connected to the FPGA main control unit through a universal asynchronous transceiver interface, and receives system status messages containing signal loss alarm status, power abnormality alarm and link failure information. The general-purpose input / output pins of the microcontroller monitoring unit are connected to the amplifier enable control pins of the EDFA optical amplifier interface; When the microcontroller monitoring unit detects that the signal loss alarm status in the system status message has been valid for a period of time exceeding a preset threshold, it controls the amplifier to output a high-level enable control signal to turn off the EDFA optical amplifier output; and after the signal loss alarm status is restored and the link status is normal, it delays for a preset safety interval and then controls the amplifier to output a low-level enable control signal to re-enable the EDFA optical amplifier.

10. The multi-service OEO optical transceiver plug-in based on hybrid multiplexing and security isolation according to claim 6, characterized in that, Includes AC / DC power modules and DC voltage regulator sets; The AC / DC power module receives external AC power supply signals and converts them into multiple independent DC output rails, namely +12V, +5V, and +3.3V. Each output rail is equipped with a corresponding TVS diode as an overvoltage protection element. The DC regulator group has an embedded temperature sensor and a load voltage detection unit, which are used to feed back real-time voltage and temperature data to the analog-to-digital conversion sampling channel of the FPGA main control unit. The FPGA main control unit periodically collects the voltage and temperature data of each DC power rail. When it detects that the voltage of any rail is lower than the preset voltage threshold or the temperature exceeds the safe range, it outputs a power alarm signal. Based on the status of the power alarm signal, it controls the power status indicator to display the current power health status.

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