Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes a first memory chip; the first memory chip comprises a first transistor, a first conductive structure and a second conductive structure; the first transistor comprises a first active region located in a first semiconductor layer and a first gate structure located on the first side of the first semiconductor layer; the first conductive structure extends through the first semiconductor layer and the first dielectric layer covering the first transistor along the thickness direction of the first semiconductor layer, and is connected with the source electrode of the first active region; the second conductive structure extends through the first dielectric layer and the first semiconductor layer along the thickness direction of the first semiconductor layer and is connected with the drain electrode of the first active region.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and includes, but is not limited to, a semiconductor device and a method for manufacturing the same. Background Technology

[0002] High-bandwidth memory (HBM) stacks multiple dynamic random access memory (DRAM) chips and packages them together with logic chips using advanced packaging technologies (such as through silicon vias (TSV), microbumps, etc.), which can improve storage capacity, bandwidth and transmission speed.

[0003] To achieve electrical connections between adjacent DRAM chips, TSVs need to be formed in the DRAM. However, the large depth and radial dimensions of TSVs in DRAM will limit data transmission in the input / output (I / O) channels of HBM. Summary of the Invention

[0004] A first aspect of this disclosure provides a semiconductor device, including: a first memory chip; the first memory chip includes:

[0005] The first transistor includes: a first active region located in a first semiconductor layer and a first gate structure located on a first side of the first semiconductor layer;

[0006] A first conductive structure extends along the thickness direction of the first semiconductor layer through the first semiconductor layer and the first dielectric layer covering the first transistor, and is connected to the source of the first active region.

[0007] The second conductive structure extends along the thickness direction of the first semiconductor layer through the first dielectric layer and the first semiconductor layer, and is connected to the drain of the first active region.

[0008] In some embodiments, the first memory chip further includes:

[0009] The first gate contact extends through the first dielectric layer along the thickness direction of the first semiconductor layer and is connected to the first gate structure.

[0010] A third conductive structure extends along the thickness direction of the first semiconductor layer through the first dielectric layer and the first semiconductor layer; wherein the third conductive structure is connected to the first gate contact through a conductive layer, the conductive layer being located on the side of the first dielectric layer that is relatively far away from the first semiconductor layer.

[0011] In some embodiments, the first conductive structure includes: a first contact portion and a first connection portion; wherein the first contact portion and the first connection portion extend through the first dielectric layer and the first semiconductor layer, respectively; the second conductive structure includes: a second contact portion and a second connection portion; wherein the second contact portion and the second connection portion extend through the first dielectric layer and the first semiconductor layer, respectively; the third conductive structure includes: a third contact portion and a third connection portion; wherein the third contact portion and the third connection portion extend through the first dielectric layer and the first semiconductor layer, respectively.

[0012] In some embodiments, the first contact portion, the second contact portion, and the third contact portion have substantially the same dimensions in the thickness direction of the first semiconductor layer.

[0013] In some embodiments, the first connecting portion, the second connecting portion, and the third connecting portion have substantially the same dimensions in the thickness direction of the first semiconductor layer.

[0014] In some embodiments, the cross-sectional dimension of the first contact portion relative to the surface near the first semiconductor layer is less than or equal to the cross-sectional dimension of the first contact portion relative to the surface far from the first semiconductor layer; the cross-sectional dimension of the second contact portion relative to the surface near the first semiconductor layer is less than or equal to the cross-sectional dimension of the second contact portion relative to the surface far from the first semiconductor layer; and the cross-sectional dimension of the third contact portion relative to the surface near the first semiconductor layer is less than or equal to the cross-sectional dimension of the third contact portion relative to the surface far from the first semiconductor layer.

[0015] In some embodiments, the cross-sectional dimension of the first connection portion relative to the surface near the first dielectric layer is less than or equal to the cross-sectional dimension of the first connection portion relative to the surface far from the first dielectric layer; the cross-sectional dimension of the second connection portion relative to the surface near the first dielectric layer is less than or equal to the cross-sectional dimension of the second connection portion relative to the surface far from the first dielectric layer; and the cross-sectional dimension of the third connection portion relative to the surface near the first dielectric layer is less than or equal to the cross-sectional dimension of the third connection portion relative to the surface far from the first dielectric layer.

[0016] In some embodiments, the dimension of the first gate contact in the thickness direction of the first semiconductor layer is smaller than the dimensions of the first contact, the second contact, and the third contact in the thickness direction of the first semiconductor layer.

[0017] In some embodiments, the semiconductor device further includes a logic chip and a plurality of first memory chips stacked on one side of the logic chip; wherein the first conductive structures of the plurality of first memory chips are connected in sequence, the second conductive structures of the plurality of first memory chips are connected in sequence, the third conductive structures of the plurality of first memory chips are connected in sequence, and the first conductive structure, the second conductive structure and the third conductive structure of the first memory chip closest to the logic chip are all connected to the logic chip.

[0018] In some embodiments, the semiconductor device further includes a second memory chip located on the side of the plurality of first memory chips that is relatively far away from the logic chip; the second memory chip includes:

[0019] The second transistor includes: a second active region located in the second semiconductor layer and a second gate structure located on a first side of the second semiconductor layer, wherein the second gate structure is located between the second semiconductor layer and the first memory chip;

[0020] The fourth contact extends along the thickness direction of the second semiconductor layer through the second dielectric layer covering the second transistor and is connected to the source of the second active region.

[0021] The fifth contact extends through the second dielectric layer along the thickness direction of the second semiconductor layer and is connected to the drain of the second active region;

[0022] The first conductive structure and the second conductive structure of the first memory chip, which is furthest from the logic chip, are respectively connected to the fourth contact portion and the fifth contact portion.

[0023] In some embodiments, the second memory chip further includes: a second gate contact extending through the second dielectric layer along the thickness direction of the second semiconductor layer and connected to the second gate structure; wherein the second gate contact is connected to the conductive layer of the first memory chip that is furthest from the logic chip.

[0024] In some embodiments, the first memory chip further includes: a first dummy conductive structure extending through the first dielectric layer and the first semiconductor layer along the thickness direction of the first semiconductor layer;

[0025] The second memory chip also includes:

[0026] The second dummy conductive structure extends along the thickness direction of the second semiconductor layer through the second dielectric layer and the second semiconductor layer;

[0027] A thermally conductive structure is located on the second side of the second semiconductor layer and connected to the second dummy conductive structure; wherein the second side of the second semiconductor layer and the first side of the second semiconductor layer are opposite to each other along the thickness direction of the second semiconductor layer;

[0028] In this configuration, the first dummy conductive structures of multiple first memory chips are connected sequentially, the first dummy conductive structure of the first memory chip closest to the logic chip is connected to the logic chip, and the first dummy conductive structure of the first memory chip farthest from the logic chip is connected to the second dummy conductive structure.

[0029] In some embodiments, the first dummy conductive structure includes: a first dummy contact portion and a first dummy connection portion; wherein the first dummy contact portion and the first dummy connection portion extend through the first dielectric layer and the first semiconductor layer, respectively.

[0030] In some embodiments, the second dummy conductive structure includes: a second dummy contact portion and a second dummy connection portion; wherein the second dummy contact portion and the second dummy connection portion extend through the second dielectric layer and the second semiconductor layer respectively; the second dummy contact portion, the fourth contact portion, and the fifth contact portion have substantially the same dimensions in the thickness direction of the second semiconductor layer.

[0031] In some embodiments, the first memory chip includes a plurality of first dummy conductive structures; the second memory chip includes a plurality of second dummy conductive structures; wherein the plurality of first dummy conductive structures and the plurality of second dummy conductive structures are all located in a first region of the semiconductor device, and the first conductive structure, the second conductive structure, and the third conductive structure are all located in a second region of the semiconductor device, and the first region surrounds the second region.

[0032] In some embodiments, the semiconductor device further includes a heat dissipation structure located on the side of the thermally conductive structure that is relatively far from the second semiconductor layer.

[0033] In some embodiments, the semiconductor device further includes a processing chip disposed side-by-side with the logic chip on one side of the substrate; wherein the heat dissipation structure covers the processing chip.

[0034] In some embodiments, the first memory chip further includes: a first bonding layer located on a second side of the first semiconductor layer and a second bonding layer located on a side of the first dielectric layer that is relatively far from the first semiconductor layer; wherein, the first bonding layer of one of two adjacent first memory chips is bonded to the second bonding layer of the other first memory chip, the first bonding layer of the first memory chip closest to the logic chip is bonded to the logic chip, and the second bonding layer of the first memory chip farthest from the logic chip is bonded to the second memory chip.

[0035] A second aspect of this disclosure provides a method for fabricating a semiconductor device, comprising: forming a first memory chip; wherein the first memory chip includes a first transistor, a first conductive structure, and a second conductive structure; the first transistor includes a first active region located in a first semiconductor layer and a first gate structure located on a first side of the first semiconductor layer; the first conductive structure and the second conductive structure both extend along the thickness direction of the first semiconductor layer through the first semiconductor layer and a first dielectric layer covering the first transistor, the first conductive structure being connected to the source of the first active region, and the second conductive structure being connected to the drain of the first active region.

[0036] In some embodiments, forming the first memory chip includes: providing an initial first semiconductor layer; forming a first transistor and a first dielectric layer on a first side of the initial first semiconductor layer; forming a first contact portion, a second contact portion, a third contact portion, and a first gate contact portion extending through the first dielectric layer along the thickness direction of the initial first semiconductor layer, such that the first contact portion connects to the source of the first active region, the second contact portion connects to the drain of the first active region, the third contact portion extends to a first side of the initial first semiconductor layer, and the first gate contact portion connects to the first gate structure; forming a conductive layer on the side of the first dielectric layer relatively away from the initial first semiconductor layer. A conductive layer connects the third contact portion and the first gate contact portion respectively; a first connection portion, a second connection portion, and a third connection portion are formed on the second side of the initial first semiconductor layer, extending through the initial first semiconductor layer along the thickness direction of the initial first semiconductor layer, such that the first connection portion connects to the first contact portion, the second connection portion connects to the second contact portion, and the third connection portion connects to the third contact portion; wherein, the retained initial first semiconductor layer constitutes the first semiconductor layer, the first connection portion and the first contact portion constitute the first conductive structure, the second connection portion and the second contact portion constitute the second conductive structure, and the third connection portion and the third contact portion constitute the third conductive structure.

[0037] In some embodiments, the first contact portion, the second contact portion, and the third contact portion are formed simultaneously; the first connecting portion, the second connecting portion, and the third connecting portion are formed simultaneously.

[0038] In some embodiments, the fabrication method further includes: forming a logic chip; forming a plurality of stacked first memory chips on one side of the logic chip, such that a first conductive structure of the plurality of first memory chips is connected in sequence, a second conductive structure of the plurality of first memory chips is connected in sequence, and a third conductive structure of the plurality of first memory chips is connected in sequence; wherein the first conductive structure, the second conductive structure, and the third conductive structure of the first memory chip closest to the logic chip are all connected to the logic chip.

[0039] In some embodiments, the fabrication method further includes: forming a second memory chip on the side of the plurality of first memory chips relatively far from the logic chip, such that the first conductive structure and the second conductive structure of the first memory chip farthest from the logic chip are respectively connected to the fourth contact portion and the fifth contact portion of the second memory chip; wherein, the second memory chip includes a second transistor, the fourth contact portion and the fifth contact portion; the second transistor includes a second active region located in a second semiconductor layer and a second gate structure located on a first side of the second semiconductor layer, the second gate structure being located between the second semiconductor layer and the first memory chip; the fourth contact portion and the fifth contact portion both extend along the thickness direction of the second semiconductor layer through a second dielectric layer covering the second transistor, the fourth contact portion being connected to the source of the second active region, and the fifth contact portion being connected to the drain of the second active region.

[0040] In some embodiments, forming the second memory chip includes: providing an initial second semiconductor layer; forming a second transistor and a second dielectric layer on a first side of the initial second semiconductor layer; forming a fourth contact, a fifth contact, a second dummy contact, and a second gate contact extending through the second dielectric layer along the thickness direction of the initial second semiconductor layer, such that the fourth contact is connected to the source of the second active region, the fifth contact is connected to the drain of the second active region, the second dummy contact extends to the first side of the initial second semiconductor layer, and the second gate contact is connected to the second gate structure; forming a second dummy connection extending through the initial second semiconductor layer along the thickness direction on a second side of the initial second semiconductor layer, such that the second dummy connection is connected to the second dummy contact; wherein the retained initial second semiconductor layer constitutes the second semiconductor layer, and the second dummy connection and the second dummy contact constitute a second dummy conductive structure; forming a thermally conductive structure on a second side of the second semiconductor layer; wherein the thermally conductive structure is connected to the second dummy conductive structure.

[0041] In some embodiments, forming a second memory chip on the side of the plurality of first memory chips that is relatively far from the logic chip includes: bonding the second memory chip to the first memory chip that is farthest from the logic chip, such that the second gate contact is connected to the conductive layer of the first memory chip that is farthest from the logic chip.

[0042] In some embodiments, forming the first memory chip further includes: forming a first dummy contact portion extending through the first dielectric layer along the thickness direction of the first semiconductor layer, such that the first dummy contact portion extends to a first side of the initial first semiconductor layer; forming a first dummy connection portion extending through the initial first semiconductor layer along the thickness direction of the initial first semiconductor layer on a second side of the initial first semiconductor layer, such that the first dummy connection portion connects to the first dummy contact portion; wherein the first dummy connection portion and the first dummy contact portion constitute a first dummy conductive structure; the first dummy conductive structures of a plurality of first memory chips are connected sequentially, the first dummy conductive structure of the first memory chip closest to the logic chip is connected to the logic chip, and the first dummy conductive structure of the first memory chip farthest from the logic chip is connected to a second dummy conductive structure.

[0043] In some embodiments, forming the first memory chip further includes: thinning a second side of the initial first semiconductor layer to form the first semiconductor layer; forming the second memory chip further includes: thinning a second side of the initial second semiconductor layer to form the second semiconductor layer.

[0044] In this disclosure, the semiconductor device includes a first memory chip; the first memory chip includes a first transistor, a first conductive structure, and a second conductive structure; the first transistor includes a first active region located in a first semiconductor layer and a first gate structure located on a first side of the first semiconductor layer; the first conductive structure extends along the thickness direction of the first semiconductor layer through the first semiconductor layer and a first dielectric layer covering the first transistor, and is connected to the source of the first active region; the second conductive structure extends along the thickness direction of the first semiconductor layer through the first dielectric layer and the first semiconductor layer, and is connected to the drain of the first active region. Thus, firstly, the depth and size of the first and second conductive structures formed from the back side can be reduced, which is beneficial for improving the data transmission performance of the semiconductor device's I / O channels; secondly, since the size of the first and second conductive structures formed from the back side can be reduced, it is beneficial for improving chip area utilization and reducing chip size. Attached Figure Description

[0045] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0046] Figure 1 This is a schematic diagram of a high-bandwidth memory provided in an embodiment of this disclosure.

[0047] Figure 2 This is a schematic diagram of a memory chip provided in an embodiment of this disclosure.

[0048] Figure 3 This is a schematic diagram of the heat distribution of multiple memory chips provided in an embodiment of this disclosure.

[0049] Figure 4 This is a schematic diagram of a semiconductor device provided in an embodiment of this disclosure.

[0050] Figure 5 This is a schematic diagram of a semiconductor device including a logic chip and multiple memory chips provided in an embodiment of this disclosure.

[0051] Figure 6 This is a schematic diagram of a second memory chip provided in an embodiment of this disclosure.

[0052] Figure 7 This is a perspective view of a semiconductor device including a logic chip and multiple memory chips provided in an embodiment of this disclosure.

[0053] Figure 8 This is a schematic diagram of a packaged semiconductor device provided in an embodiment of this disclosure.

[0054] Figure 9 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of this disclosure.

[0055] Figures 10 to 13 This is a schematic diagram illustrating the manufacturing process of a first memory chip provided in an embodiment of this disclosure.

[0056] Figure 14 This is a schematic diagram of a stack of multiple first memory chips provided in an embodiment of this disclosure.

[0057] Figure 15 This is a schematic diagram of a second memory chip and a stack of multiple first memory chips provided in an embodiment of this disclosure. Detailed Implementation

[0058] To facilitate understanding of this disclosure, exemplary embodiments of the disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the disclosure are shown in the drawings, it should be understood that the disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the disclosure and to fully convey the scope of the disclosure to those skilled in the art.

[0059] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, certain technical features well-known in the art are not described; that is, not all features of the actual embodiments, nor well-known functions and structures, may be described herein.

[0060] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0061] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0062] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0063] Figure 1 This is a schematic diagram of a high-bandwidth memory provided in an embodiment of this disclosure. Figure 2 This is a schematic diagram of a memory chip provided in an embodiment of this disclosure. (Refer to...) Figure 1 As shown, the high-bandwidth memory 100 includes a logic chip 110 and multiple memory chips 120. The multiple memory chips 120 are located on one side of the logic chip 110 and are stacked sequentially. Adjacent memory chips 120 are electrically connected through TSVs 123 and microbumps 124. The memory chips 120 include, but are not limited to, DRAM chips. (Refer to...) Figure 2 As shown, the memory chip 120 includes a semiconductor layer 121, an interconnect structure 122, and a TSV 123. The interconnect structure 122 is located on one side of the semiconductor layer 121. The TSV 123 extends through the semiconductor layer 121 and the dielectric layer covering the transistor until it connects to the interconnect structure 122. The TSV 123 can be connected to the transistor through the interconnect structure 122. It should be noted that in practical applications, the number of TSVs in each memory chip is not limited to... Figure 2The three shown can be more than three.

[0064] However, Figure 2 The memory chip shown has a large depth and radial dimensions (e.g., diameter or radius) of the TSV, making... Figure 1 The large connection size and contact resistance of the HBM shown limit the number of stacked memory chips and data transmission through I / O channels, and also restricts the miniaturization of memory chips due to the packaging architecture. Furthermore, heat dissipation of the underlying memory chips in the HBM stack is limited, which will be discussed below. Figure 3 An exemplary illustration of the heat distribution of multiple memory chips is provided.

[0065] Figure 3 This is a schematic diagram of the heat distribution of multiple memory chips according to an embodiment of this disclosure. (Refer to...) Figure 3 As shown, as the distance between the memory chips Die1 to Die19 and the logic chip increases sequentially, for example, from 50μm to 950μm, the heat generated by the memory chips Die1 to Die19 decreases sequentially. That is, the memory chip Die1, which is closest to the logic chip, generates the most heat, while the memory chip Die19, which is furthest from the logic chip, generates the least heat. Because heat is dissipated from the top of the HBM to the heatsink through the package, the heat from the underlying memory chips cannot be effectively dissipated, affecting the heat dissipation efficiency of the bottom memory chips. Figure 3 As shown, the temperatures corresponding to Die1 to Die5 of the memory chips exceed 105℃. Excessive temperature will damage the underlying memory chips Die1 to Die5. For ease of explanation, Figure 3 The diagram shows 19 memory chips, Die1 to Die19. In practical applications, the number of memory chips may be more or less than 19, and this disclosure does not impose any special restrictions on this.

[0066] Based on one or more of the above-mentioned technical problems, this disclosure provides a semiconductor device. Figure 4 This is a schematic diagram of a semiconductor device provided in an embodiment of this disclosure. In this embodiment, the semiconductor device may be a first memory chip, which includes, but is not limited to, a DRAM chip. (Refer to...) Figure 4As shown, the first memory chip 200 includes a first transistor, a first conductive structure 230, and a second conductive structure 240. The first transistor includes a first active region 211 located in the first semiconductor layer 210 and a first gate structure located on a first side of the first semiconductor layer 210. The first conductive structure 230 extends along the thickness direction of the first semiconductor layer 210, passes through the first semiconductor layer 210 and the first dielectric layer 220 covering the first transistor, and is connected to the source of the first active region 211. The second conductive structure 240 extends along the thickness direction of the first semiconductor layer 210, passes through the first dielectric layer 220 and the first semiconductor layer 210, and is connected to the drain of the first active region 211.

[0067] The first memory chip 200 may include one or more first transistors. The first transistors may be located in the array region and / or peripheral region of the DRAM chip. Wherein, if the first transistor is located in the array region, it may be configured as a selection transistor, connected to a capacitor to form a memory cell of the DRAM chip; if the first transistor is located in the peripheral region, it may be configured as a driving transistor, connected to other transistors or electronic components to form the peripheral circuitry of the DRAM chip. The first transistor may include a PMOS transistor or an NMOS transistor.

[0068] The first semiconductor layer 210 can be a first substrate or a thinned first substrate. In this embodiment, the first semiconductor layer 210 can be a thinned first substrate, thereby reducing the depth of the first conductive structure 230 extending through the first semiconductor layer 210. The material of the first substrate includes elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art. By ion doping or ion implantation of the first semiconductor layer 210, a plurality of first active regions 211 can be formed in the first semiconductor layer 210, and adjacent first active regions 211 are isolated by a first isolation structure 212. The first active region 211 includes a source (S), a drain (D), and a channel located between the source and the drain.

[0069] The first gate structure is located on the first side of the first semiconductor layer 210. The first gate structure may include a first gate (G) and a first gate dielectric layer (not shown in the figure). The first gate dielectric layer is located between the first gate and the channel. The first gate structure and the first active region 211 constitute the first transistor. The material of the first gate includes conductive materials, such as one or more of the following conductive materials: polysilicon, doped polysilicon, tungsten silicide, titanium silicide, tantalum silicide, tungsten, titanium, and tantalum. The material of the first gate dielectric layer includes dielectric materials, such as one or more of the following dielectric materials: silicon oxide, silicon nitride, and silicon oxide nitride. The first substrate may include a front side and a back side opposite each other along the thickness direction. The first side of the first semiconductor layer 210 may be the front side of the first substrate, and the second side of the first semiconductor layer 210 may be the back side of the thinned first substrate. Therefore, the first transistor is formed on the front side of the first substrate, and the first bonding layer 280 (hereinafter referred to as the first bonding layer 280) is formed on the back side of the thinned first substrate.

[0070] The first conductive structure 230 may include multiple portions, which may be formed in stages, for example, from the front and back sides of the first substrate, respectively. For example, the first conductive structure 230 includes a first contact portion 231 and a first connection portion 232; wherein the first contact portion 231 and the first connection portion 232 extend through the first dielectric layer 220 and the first semiconductor layer 210, respectively. The first contact portion 231 may be formed from the front side of the first substrate, and the first connection portion 232 may be formed from the back side of the first substrate and connected to the source of the first active region 211. That is, the first connection portion 232 formed on the back side only needs to extend through the first semiconductor layer 210, which helps to reduce the depth and size of the TSV.

[0071] The second conductive structure 240 may include multiple portions, which may be formed in stages, for example, from the front and back sides of the first substrate, respectively. For example, the second conductive structure 240 includes a second contact portion 241 and a second connection portion 242; wherein the second contact portion 241 and the second connection portion 242 extend through the first dielectric layer 220 and the first semiconductor layer 210, respectively. The second contact portion 241 may be formed from the front side of the first substrate, and the second connection portion 242 may be formed from the back side of the first substrate and connected to the drain of the first active region 211. That is, the second connection portion 242 formed on the back side only needs to extend through the first semiconductor layer 210, which helps to reduce the depth and size of the TSV.

[0072] The materials of both the first conductive structure 230 and the second conductive structure 240 include conductive materials, such as one or more of the following: polycrystalline silicon, doped polycrystalline silicon, tungsten silicide, titanium silicide, tantalum silicide, tungsten, titanium, and tantalum. In one example, the materials of the first contact portion 231 and the second contact portion 241 are the same, for example, when the first contact portion 231 and the second contact portion 241 are formed simultaneously on the front side; the materials of the first connecting portion 232 and the second connecting portion 242 are the same, for example, when the first connecting portion 232 and the second connecting portion 242 are formed simultaneously on the back side. This can save processes and reduce production costs. Of course, in other examples, the materials of the first contact portion 231 and the second contact portion 241 may be different, and the materials of the first connecting portion 232 and the second connecting portion 242 may also be different; this disclosure does not impose any special limitations on this.

[0073] It should be noted that TSV technology is used to achieve interconnection of three-dimensional stacked chips. This is achieved by forming vias within the chip and filling them with conductive material to enable vertical interconnection between chips. There is a certain constraint between the depth and diameter of the vias. Specifically, on the one hand, deeper vias require larger diameters to fill with conductive material to achieve good electrical performance. On the other hand, smaller diameters can improve chip area utilization and reduce chip size, but they also pose challenges to manufacturing and reliability. Therefore, a trade-off needs to be made between the depth and radial dimensions of the vias to optimize performance and reliability.

[0074] In this embodiment, the portions of the first conductive structure extending through the first dielectric layer and the portions extending through the first semiconductor layer can be formed from the front and back sides, respectively, and directly connected to the source of the first active region; the portions of the second conductive structure extending through the first dielectric layer and the portions extending through the first semiconductor layer can be formed from the front and back sides, respectively, and directly connected to the drain of the first active region. Thus, firstly, the depth and size of the first and second conductive structures formed from the back side can be reduced, which is beneficial for improving the data transmission performance of the semiconductor device's I / O channels; secondly, since the sizes of the first and second conductive structures formed from the back side can be reduced, it is beneficial for improving chip area utilization and reducing chip size.

[0075] In some embodiments, refer to Figure 4As shown, the first memory chip 200 further includes a first gate contact 261 and a third conductive structure 250; the first gate contact 261 extends through the first dielectric layer 220 along the thickness direction of the first semiconductor layer 210 and is connected to the first gate structure; the third conductive structure 250 extends through the first dielectric layer 220 and the first semiconductor layer 210 along the thickness direction of the first semiconductor layer 210; wherein, the third conductive structure 250 is connected to the first gate contact 261 through a conductive layer 273, and the conductive layer 273 is located on the side of the first dielectric layer 220 that is relatively far away from the first semiconductor layer 210.

[0076] The first gate contact 261 can be connected to the third conductive structure 250 via the conductive layer 273, thereby electrically leading out the first gate. The material of the first gate contact 261 includes conductive materials, such as one or more of the following conductive materials: polycrystalline silicon, doped polycrystalline silicon, tungsten silicide, titanium silicide, tantalum silicide, tungsten, titanium, tantalum, etc. The conductive layer 273 may be located in the first interconnect dielectric layer 271. The first interconnect dielectric layer 271 and the first interconnect structure 272 may constitute the first interconnect layer 270. By patterning the first interconnect structure 272 in the first interconnect layer 270, the conductive layer 273 shown in Figure 4 can be formed. The materials of both the conductive layer 273 and the first interconnect structure 272 include conductive materials, such as one or more of the following conductive materials: polycrystalline silicon, doped polycrystalline silicon, tungsten silicide, titanium silicide, tantalum silicide, tungsten, titanium, tantalum, etc. The material of the first interconnect dielectric layer 271 includes dielectric materials, such as one or more of the following dielectric materials: silicon oxide, silicon nitride, silicon oxide nitride, etc.

[0077] The third conductive structure 250 may include multiple portions, which may be formed in stages, for example, from the front and back sides of the first substrate, respectively. Exemplarily, the third conductive structure 250 includes a third contact portion 251 and a third connection portion 252; wherein the third contact portion 251 and the third connection portion 252 extend through the first dielectric layer 220 and the first semiconductor layer 210, respectively. The third contact portion 251 may be formed from the front side of the first substrate, and the third connection portion 252 may be formed from the back side of the first substrate and connected to the third contact portion 251. That is, the third connection portion 252 formed on the back side only needs to extend through the first semiconductor layer 210, which is beneficial for reducing the depth and size of the TSV. The material of the third conductive structure 250 includes conductive materials, such as one or more of polycrystalline silicon, doped polycrystalline silicon, tungsten silicide, titanium silicide, tantalum silicide, tungsten, titanium, tantalum, etc.

[0078] In this embodiment of the present disclosure, by providing a conductive layer in the first interconnect layer, the first gate can be connected to one end of the conductive layer through the first gate contact portion, and the third conductive structure can be connected to the other end of the conductive layer. The portion of the third conductive structure extending through the first dielectric layer and the portion extending through the first semiconductor layer can be formed from the front and back sides, respectively. This not only enables the electrical lead-out of the first gate, but also reduces the depth and size of the third conductive structure formed from the back side, thereby improving the data transmission performance of the semiconductor device I / O channel and reducing the chip size.

[0079] In some embodiments, the dimension of the first gate contact 261 in the thickness direction of the first semiconductor layer 210 is smaller than the dimensions of the first contact 231, the second contact 241, and the third contact 251 in the thickness direction of the first semiconductor layer 210. For example, see... Figure 4 As shown, the dimensions of the first contact portion 231, the second contact portion 241, the third contact portion 251, and the first gate contact portion 261 in the thickness direction of the first semiconductor layer 210 are h1, h2, h3, and h4, respectively, i.e., h4 < h1, h4 < h2, and h4 < h3.

[0080] It should be noted that the first dielectric layer 220 may include a first isolation layer 221 and a first insulating layer 222. The first isolation layer 221 conformally covers the first semiconductor layer 210, the first isolation structure 212, and the first gate structure. The first insulating layer 222 covers the first isolation layer 221. The first isolation layer 221 includes, but is not limited to, silicon nitride, and the first insulating layer 222 includes, but is not limited to, silicon oxide. Since the first gate protrudes from the surface of the first semiconductor layer 210, the thickness of the first dielectric layer 220 covering the first gate can be less than the thickness of the first dielectric layer 220 covering the first semiconductor layer 210. Therefore, the dimension of the first gate contact portion 261 in the thickness direction of the first semiconductor layer 210 is smaller than the dimensions of the first contact portion 231, the second contact portion 241, and the third contact portion 251 in the thickness direction of the first semiconductor layer 210.

[0081] In some embodiments, the dimensions of the first contact portion 231, the second contact portion 241, and the third contact portion 251 are substantially the same in the thickness direction of the first semiconductor layer 210, i.e., h1 = h2 = h3. Since the dimensions of the first contact portion 231, the second contact portion 241, and the third contact portion 251 are substantially the same in the thickness direction of the first semiconductor layer 210, holes can be simultaneously etched and conductive material filled towards the front side of the first substrate, thereby saving processes and reducing production costs.

[0082] In some embodiments, the first connection portion 232, the second connection portion 242, and the third connection portion 252 have substantially the same dimensions in the thickness direction of the first semiconductor layer 210. For example, refer to... Figure 4 As shown, the dimensions of the first connecting portion 232, the second connecting portion 242, and the third connecting portion 252 in the thickness direction of the first semiconductor layer 210 are h5, h6, and h7, respectively, i.e., h5 = h6 = h7. Since the dimensions of the first connecting portion 232, the second connecting portion 242, and the third connecting portion 252 in the thickness direction of the first semiconductor layer 210 are basically the same, holes can be simultaneously etched and conductive materials filled towards the back side of the thinned first substrate, thereby further saving processes and reducing production costs.

[0083] It should be noted that, in the embodiments of this disclosure, the dimension of a certain contact portion or a certain connection portion in the thickness direction of the first semiconductor layer 210 can be the depth (or height) of the contact portion or the connection portion. The use of substantially the same dimensions in this disclosure includes two situations: the first is that the dimensions of multiple contacts (or multiple connections) are exactly the same; the second is that the dimensions of multiple contacts (or multiple connections) have deviations, which are within the allowable error range, and the error range can be designed according to the tolerance of the actual semiconductor device.

[0084] In some embodiments, the cross-sectional dimension of the first contact portion 231 relative to the surface near the first semiconductor layer 210 is less than or equal to the cross-sectional dimension of the first contact portion 231 relative to the surface away from the first semiconductor layer 210; the cross-sectional dimension of the second contact portion 241 relative to the surface near the first semiconductor layer 210 is less than or equal to the cross-sectional dimension of the second contact portion 241 relative to the surface away from the first semiconductor layer 210; and the cross-sectional dimension of the third contact portion 251 relative to the surface near the first semiconductor layer 210 is less than or equal to the cross-sectional dimension of the third contact portion 251 relative to the surface away from the first semiconductor layer 210. It is understood that the cross-sectional dimension includes the radial dimension, which depends on the cross-sectional shape of the contact portion or the connection portion. For example, if the cross-sectional shape of the contact portion or the connection portion is circular, the cross-sectional dimension can be the diameter or the radius.

[0085] In practical applications, the first dielectric layer 220 can be etched along the direction facing the front of the first substrate to form multiple contact holes. The multiple contact holes include a first contact hole that exposes the source of the first transistor, a second contact hole that exposes the drain of the first transistor, and a third contact hole that exposes the first semiconductor layer 210. Conductive materials are filled into the multiple contact holes to form a first contact portion 231, a second contact portion 241, and a third contact portion 251.

[0086] In one example, the sidewalls of the contact holes are completely perpendicular to the surface of the first substrate, such that the cross-sectional dimensions of the contact portions in each contact hole are the same at different horizontal positions. That is, the cross-sectional dimension of the first contact portion 231 relative to the surface close to the first semiconductor layer 210 is equal to the cross-sectional dimension of the first contact portion 231 relative to the surface far from the first semiconductor layer 210, the cross-sectional dimension of the second contact portion 241 relative to the surface close to the first semiconductor layer 210 is equal to the cross-sectional dimension of the second contact portion 241 relative to the surface far from the first semiconductor layer 210, and the cross-sectional dimension of the third contact portion 251 relative to the surface close to the first semiconductor layer 210 is equal to the cross-sectional dimension of the third contact portion 251 relative to the surface far from the first semiconductor layer 210.

[0087] In the above example, forming sidewalls completely perpendicular to the surface of the first substrate during etching is an ideal etching pattern, enabling precise transfer of the mask pattern on the mask. However, considering that the sidewalls of the contact holes may develop an inverted conical profile due to the passivation effect of etching byproducts during etching, in another example, the sidewall profile of the contact holes is inverted conical, causing the cross-sectional dimensions of the contact portions in each contact hole to gradually decrease along the direction towards the first semiconductor layer 210. Specifically, the cross-sectional dimension of the first contact portion 231 relative to the surface closer to the first semiconductor layer 210 is smaller than the cross-sectional dimension of the first contact portion 231 relative to the surface farther from the first semiconductor layer 210, the cross-sectional dimension of the second contact portion 241 relative to the surface closer to the first semiconductor layer 210 is smaller than the cross-sectional dimension of the second contact portion 241 relative to the surface farther from the first semiconductor layer 210, and the cross-sectional dimension of the third contact portion 251 relative to the surface closer to the first semiconductor layer 210 is smaller than the cross-sectional dimension of the third contact portion 251 relative to the surface farther from the first semiconductor layer 210.

[0088] In some embodiments, the cross-sectional dimension of the first connection portion 232 relative to the surface near the first dielectric layer 220 is less than or equal to the cross-sectional dimension of the first connection portion 232 relative to the surface far from the first dielectric layer 220; the cross-sectional dimension of the second connection portion 242 relative to the surface near the first dielectric layer 220 is less than or equal to the cross-sectional dimension of the second connection portion 242 relative to the surface far from the first dielectric layer 220; and the cross-sectional dimension of the third connection portion 252 relative to the surface near the first dielectric layer 220 is less than or equal to the cross-sectional dimension of the third connection portion 252 relative to the surface far from the first dielectric layer 220.

[0089] In practical applications, the first semiconductor layer 210 can be etched along the direction toward the back side of the first substrate to form a plurality of connection holes (e.g., TSV holes). The plurality of connection holes include a first connection hole exposing a first contact portion 231, a second connection hole exposing a second contact portion 241, and a third connection hole exposing a third contact portion 251. Conductive materials are filled into the plurality of connection holes respectively to form a first connection portion 232, a second connection portion 242, and a third connection portion 252.

[0090] In one example, the sidewalls of the connection holes are completely perpendicular to the surface of the first substrate, such that the cross-sectional dimensions of the connection portions in each connection hole are the same at different horizontal positions. That is, the cross-sectional dimension of the first connection portion 232 relative to the surface close to the first dielectric layer 220 is equal to the cross-sectional dimension of the first connection portion 232 relative to the surface far from the first dielectric layer 220, the cross-sectional dimension of the second connection portion 242 relative to the surface close to the first dielectric layer 220 is equal to the cross-sectional dimension of the second connection portion 242 relative to the surface far from the first dielectric layer 220, and the cross-sectional dimension of the third connection portion 252 relative to the surface close to the first dielectric layer 220 is equal to the cross-sectional dimension of the third connection portion 252 relative to the surface far from the first dielectric layer 220.

[0091] In the above example, forming sidewalls completely perpendicular to the surface of the first substrate during etching is an ideal etching pattern, enabling precise transfer of the mask pattern on the mask. However, considering that the sidewalls of the connecting holes may develop an inverted conical profile due to the passivation effect of etching byproducts during etching, in another example, the sidewall profile of the connecting holes is inverted conical, causing the cross-sectional dimensions of the connecting portions in each connecting hole to gradually decrease along the direction towards the first dielectric layer 220. Specifically, the cross-sectional dimension of the first connecting portion 232 relative to the surface near the first dielectric layer 220 is smaller than the cross-sectional dimension of the first connecting portion 232 relative to the surface far from the first dielectric layer 220, the cross-sectional dimension of the second connecting portion 242 relative to the surface near the first dielectric layer 220 is smaller than the cross-sectional dimension of the second connecting portion 242 relative to the surface far from the first dielectric layer 220, and the cross-sectional dimension of the third connecting portion 252 relative to the surface near the first dielectric layer 220 is smaller than the cross-sectional dimension of the third connecting portion 252 relative to the surface far from the first dielectric layer 220.

[0092] In other words, in this embodiment of the present disclosure, the multiple connection holes etched from the back side of the thinned first substrate only need to extend through the first semiconductor layer 210. In this way, the depth and size of the TSV holes can be reduced, which is beneficial to improving the data transmission performance of the semiconductor device I / O channel.

[0093] Figure 5 This is a schematic diagram of a semiconductor device including a logic chip and multiple memory chips, provided in an embodiment of this disclosure. (Refer to...) Figure 5As shown, the semiconductor device also includes a logic chip 300 and a plurality of first memory chips stacked on one side of the logic chip 300; wherein, the first conductive structures 230 of the plurality of first memory chips are connected in sequence, the second conductive structures 240 of the plurality of first memory chips are connected in sequence, the third conductive structures 250 of the plurality of first memory chips are connected in sequence, and the first conductive structures 230, second conductive structures 240 and third conductive structures 250 of the first memory chip closest to the logic chip 300 are all connected to the logic chip 300.

[0094] Figure 5 The diagram shows three first memory chips stacked sequentially: first memory chip 200a, first memory chip 200b, and first memory chip 200c. In practical applications, the number of first memory chips is not limited to three. The first conductive structures 230, second conductive structures 240, and third conductive structures 250 of the three first memory chips are connected sequentially. The first conductive structures 230, second conductive structures 240, and third conductive structures 250 of first memory chip 200a are all connected to logic chip 300, thereby achieving internal interconnection of the three-dimensional stacked chips. Logic chip 300 can serve as a control unit for multiple memory chips.

[0095] In some embodiments, refer to Figure 5 As shown, the semiconductor device also includes a second memory chip 400 located on the side of the plurality of first memory chips that is relatively far away from the logic chip 300. The second memory chip 400 can be flip-chip bonded to the first memory chip 200c and serves as the top-layer memory chip. Of course, in other embodiments, the second memory chip 400 may be omitted.

[0096] Figure 6 This is a schematic diagram of a second memory chip provided in an embodiment of this disclosure. The second memory chip 400 includes, but is not limited to, a DRAM chip. (Refer to...) Figure 5 and Figure 6 As shown, the second memory chip 400 includes a second transistor, a fourth contact 431, and a fifth contact 441. The second transistor includes a second active region 411 located in the second semiconductor layer 410 and a second gate structure located on the first side of the second semiconductor layer 410. The second gate structure is located between the second semiconductor layer 410 and the first memory chip. The fourth contact 431 extends along the thickness direction of the second semiconductor layer 410 through the second dielectric layer 420 covering the second transistor and is connected to the source of the second active region 411. The fifth contact 441 extends along the thickness direction of the second semiconductor layer 410 through the second dielectric layer 420 and is connected to the drain of the second active region 411. The first conductive structure 230 and the second conductive structure 240 of the first memory chip, which are furthest from the logic chip 300, are respectively connected to the fourth contact 431 and the fifth contact 441.

[0097] The second memory chip 400 may include one or more second transistors. The second transistors may be located in the array region and / or peripheral region of the DRAM chip. Wherein, if the second transistor is located in the array region, it may be configured as a selection transistor, connected to a capacitor to form a memory cell of the DRAM chip; if the second transistor is located in the peripheral region, it may be configured as a driving transistor, connected to other transistors or electronic components to form the peripheral circuitry of the DRAM chip. The second transistor may include a PMOS transistor or an NMOS transistor.

[0098] The second semiconductor layer 410 can be a second substrate or a thinned second substrate. In this embodiment, the second semiconductor layer 410 can be a thinned second substrate, and the material of the second substrate can be similar to that of the first substrate. By ion doping or ion implantation, a plurality of second active regions 411 can be formed in the second semiconductor layer 410, and adjacent second active regions 411 are isolated by a second isolation structure 412. The second active region 411 includes a source, a drain, and a channel located between the source and the drain.

[0099] The second gate structure is located on the first side of the second semiconductor layer 410. The second gate structure may include a second gate and a second gate dielectric layer (not shown in the figure). The second gate dielectric layer is located between the second gate and the channel. The second gate structure and the second active region 411 constitute the second transistor. The material of the second gate may be similar to that of the first gate. The material of the second gate dielectric layer may be similar to that of the first gate dielectric layer. The second substrate may include a front side and a back side opposite to each other along the thickness direction. The first side of the second semiconductor layer 410 may be the front side of the second substrate, and the second side of the second semiconductor layer 410 may be the back side of the thinned second substrate. Therefore, the second transistor is formed on the front side of the second substrate, and the thermally conductive structure 480 described below is formed on the back side of the thinned second substrate.

[0100] A fourth contact 431 may be formed from the front side of the second substrate and connected to the source of the second active region 411. A fifth contact 441 may be formed from the front side of the second substrate and connected to the source of the second active region 411. After the second memory chip 400 is flip-chip bonded to the first memory chip 200c, the fourth contact 431 is connected to the first conductive structure 230 of the first memory chip 200c, and the fifth contact 441 is connected to the second conductive structure 240 of the first memory chip 200c. The materials of the fourth contact 431 and the fifth contact 441 may be similar to the materials of the first contact 231 and the second contact 241. In one example, the materials of the fourth contact 431 and the fifth contact 441 are the same, for example, when the fourth contact 431 and the fifth contact 441 are formed simultaneously on the front side. Of course, in other examples, the materials of the fourth contact 431 and the fifth contact 441 may be different, and this disclosure does not impose any particular limitation on this.

[0101] It is understood that in this embodiment of the present disclosure, the second memory chip 400 is the top layer memory chip. By flip-chip bonding the second memory chip 400 to the first memory chip 200c, it is not necessary to bring out the second memory chip 400 from the back side of the second substrate. Therefore, it can save processes and reduce production costs.

[0102] In some embodiments, refer to Figure 5 and Figure 6 As shown, the second memory chip 400 further includes a second gate contact 461; the second gate contact 461 extends along the thickness direction of the second semiconductor layer 410 through the second dielectric layer 420 and is connected to the second gate structure; wherein, the second gate contact 461 is connected to the conductive layer 273 of the first memory chip 200, which is furthest from the logic chip 300. The second gate contact 461 can be connected to the conductive layer 273 and the third conductive structure 250 of the first memory chip 200c through the second interconnect structure 472, thereby bringing out the second gate electrical circuitry. The second interconnect structure 472 may be located in the second interconnect dielectric layer 471, and the second interconnect dielectric layer 471 and the second interconnect structure 472 may constitute the second interconnect layer 470. The material of the second gate contact 461 may be similar to the material of the first gate contact 261, the material of the second interconnect structure 472 may be similar to the material of the first interconnect structure 272, and the material of the second interconnect dielectric layer 471 may be similar to the material of the first interconnect dielectric layer 271.

[0103] In some embodiments, the second gate contact 461 has a smaller dimension in the thickness direction of the second semiconductor layer 410 than the fourth contact 431 and the fifth contact 441 have in the thickness direction of the second semiconductor layer 410.

[0104] It should be noted that the second dielectric layer 420 may include a second isolation layer 421 and a second insulating layer 422. The second isolation layer 421 conformally covers the second semiconductor layer 410, the second isolation structure 412, and the second gate structure, and the second insulating layer 422 covers the second isolation layer 421. Since the second gate protrudes from the surface of the second semiconductor layer 410, the thickness of the second dielectric layer 420 covering the second gate can be less than the thickness of the second dielectric layer 420 covering the second semiconductor layer 410. Therefore, the dimension of the second gate contact portion 461 in the thickness direction of the second semiconductor layer 410 is smaller than the dimensions of the fourth contact portion 431 and the fifth contact portion 441 in the thickness direction of the second semiconductor layer 410.

[0105] In some embodiments, refer to Figure 5 As shown, the first memory chip 200 further includes a first dummy conductive structure 290, which extends along the thickness direction of the first semiconductor layer 210 and passes through the first dielectric layer 220 and the first semiconductor layer 210; wherein, the first dummy conductive structures 290 of multiple first memory chips 200 are connected in sequence, the first dummy conductive structure 290 of the first memory chip 200 closest to the logic chip 300 is connected to the logic chip 300, and the first dummy conductive structure 290 of the first memory chip 200 farthest from the logic chip 300 is connected to the second dummy conductive structure 490 of the second memory chip 400.

[0106] The first dummy conductive structure 290 may include multiple portions, which may be formed stepwise, for example, formed from the front and back sides of the first substrate, respectively. For example, see reference... Figure 5 As shown, the first dummy conductive structure 290 includes a first dummy contact portion 291 and a first dummy connection portion 292; wherein the first dummy contact portion 291 and the first dummy connection portion 292 extend through the first dielectric layer 220 and the first semiconductor layer 210, respectively. The first dummy contact portion 291 can be formed from the front side of the first substrate, and the first dummy connection portion 292 can be formed from the back side of the first substrate and connected to the first dummy contact portion 291. That is, the first dummy connection portion 292 formed on the back side only needs to extend through the first semiconductor layer 210, which is beneficial to reducing the depth and size of the TSV.

[0107] In this embodiment, each memory chip has a dummy conductive structure, which serves as a support and heat dissipation mechanism during the manufacturing process. The dummy conductive structures of each memory chip are connected sequentially. This sequential connection allows for timely dissipation of heat generated by the logic chip 300 and each memory chip during the use of the semiconductor device. Even the heat from the underlying memory chip and logic chip 300 can be effectively dissipated, thus improving the heat dissipation efficiency of the semiconductor device.

[0108] In some embodiments, refer to Figure 5 and Figure 6 As shown, the second memory chip 400 further includes a second dummy conductive structure 490 and a heat-conducting structure 480; the second dummy conductive structure 490 extends along the thickness direction of the second semiconductor layer 410 through the second dielectric layer 420 and the second semiconductor layer 410; the heat-conducting structure 480 is located on the second side of the second semiconductor layer 410 and is connected to the second dummy conductive structure 490; wherein, the second side of the second semiconductor layer 410 and the first side of the second semiconductor layer 410 are opposite to each other along the thickness direction of the second semiconductor layer 410.

[0109] The second dummy conductive structure 490 may include multiple portions, which may be formed stepwise, for example, formed from the front and back sides of the second substrate respectively. For example, see reference... Figure 6 As shown, the second dummy conductive structure 490 includes a second dummy contact portion 491 and a second dummy connection portion 492; wherein the second dummy contact portion 491 and the second dummy connection portion 492 extend through the second dielectric layer 420 and the second semiconductor layer 410, respectively. The second dummy contact portion 491 can be formed from the front side of the second substrate, and the second dummy connection portion 492 can be formed from the back side of the second substrate and connected to the second dummy contact portion 491. That is, the second dummy connection portion 492 formed on the back side only needs to extend through the second semiconductor layer 410, which is beneficial to reducing the depth and size of the TSV.

[0110] In this embodiment of the disclosure, the heat generated by the logic chip and each memory chip can be dissipated to a heat-conducting structure closer to the heat sink (i.e., the top of the semiconductor device) through a series of sequentially connected dummy conductive structures, thereby enabling effective heat dissipation. For example, the heat can be dissipated through a cooling medium in the heat sink, which may include a cooling liquid or a cooling gas.

[0111] In some embodiments, the second dummy contact 491, the fourth contact 431, and the fifth contact 441 have substantially the same dimensions in the thickness direction of the second semiconductor layer 410. Since the second dummy contact 491, the fourth contact 431, and the fifth contact 441 have substantially the same dimensions in the thickness direction of the second semiconductor layer 410, holes can be simultaneously etched and conductive material filled towards the front side of the second substrate, thereby saving processes and reducing production costs.

[0112] Figure 7 This is a perspective view of a semiconductor device including a logic chip and multiple memory chips, provided in an embodiment of this disclosure. (Refer to...) Figure 7As shown, the first memory chip 200 includes multiple first dummy conductive structures 290; the second memory chip 400 includes multiple second dummy conductive structures 490. The multiple first dummy conductive structures 290 and the multiple second dummy conductive structures 490 are all located in a first region of the semiconductor device, while the first conductive structure 230, the second conductive structure 240, and the third conductive structure 250 are all located in a second region of the semiconductor device, with the first region surrounding the second region. Here, the second region can be the core region of the semiconductor device, and the first region can be other regions surrounding the core region. By placing the sequentially connected dummy conductive structures in the first region and connecting them to the annular heat-conducting structure 480, heat dissipation is more efficient, thereby accelerating heat dissipation.

[0113] Figure 8 This is a schematic diagram of a packaged semiconductor device provided in an embodiment of this disclosure. (Refer to...) Figure 8 As shown, the semiconductor device includes a logic chip 300 and a plurality of memory chips stacked on the logic chip 300, such as first memory chips 200a to 200e and a second memory chip 400. In some embodiments, the semiconductor device further includes a heat dissipation structure 600 located on the side of the thermally conductive structure 480 relatively away from the second semiconductor layer 410, i.e., the heat dissipation structure 600 is located on top of the semiconductor device. The heat dissipation structure 600 may be the heat sink described above.

[0114] In some embodiments, the semiconductor device further includes a processing chip 500, which is disposed side-by-side with the logic chip 300 on one side of the substrate; wherein a heat dissipation structure 600 covers the processing chip 500. The heat dissipation structure 600 can dissipate interface heat generated by the interface of the logic chip 300, memory chip heat generated by the memory chip, and processing chip heat generated by the processing chip 500, thereby reducing or avoiding the risk of damage to the semiconductor device due to overheating. Here, the processing chip 500 and the logic chip 300 are electrically connected through wiring in a silicon interposer.

[0115] In some embodiments, combined with Figure 4 and Figure 5 As shown, the first memory chip 200 further includes: a first bonding layer 280 located on the second side of the first semiconductor layer 210 and a second bonding layer (not shown in the figure) located on the side of the first dielectric layer 220 that is relatively far away from the first semiconductor layer 210; wherein, the first bonding layer 280 of one of the two adjacent first memory chips 200 is bonded to the second bonding layer of the other first memory chip 200, the first bonding layer 280 of the first memory chip 200 closest to the logic chip 300 is bonded to the logic chip 300, and the second bonding layer of the first memory chip 200 farthest from the logic chip 300 is bonded to the second memory chip 400.

[0116] For example, refer to Figure 4 As shown, the first bonding layer 280 includes a third dielectric layer 281 and a plurality of first bonding structures 282 located in the third dielectric layer 281. The plurality of first bonding structures 282 are respectively connected to the first conductive structure 230, the second conductive structure 240, and the third conductive structure 250. The second bonding layer may be located above the first interconnect layer 270. The second bonding layer includes a fourth dielectric layer and a plurality of second bonding structures located in the fourth dielectric layer. The plurality of second bonding structures are respectively connected to the plurality of first interconnect structures 272. The materials of the third dielectric layer 281 and the fourth dielectric layer both include dielectric materials, such as one or more of dielectric materials such as silicon oxide, silicon nitride, and silicon nitride. The materials of the first bonding structures 282 and the second bonding structures both include conductive materials, such as one or more of conductive materials such as copper, nickel, tin, and silver. For example, the first bonding structure 282 and the second bonding structure are copper-copper metal hybrid bonding or nickel-tin-silver alloy-nickel bump bonding. Of course, in other embodiments, the second bonding layer can be omitted, and the first interconnect structure 272 exposed on the surface of the first interconnect layer 270 can be used as the bonding layer.

[0117] In this embodiment of the disclosure, by providing a first bonding layer 280 and a second bonding layer on opposite sides of the first memory chip 200, electrical connections can be achieved between two adjacent first memory chips 200, between the bottom first memory chip 200 and the logic chip 300, and between the top first memory chip 200 and the second memory chip 400 through bonding processes, thereby realizing three-dimensional interconnection between multiple memory chips and the logic chip 300.

[0118] Based on the above-described semiconductor device, this disclosure provides a method for fabricating a semiconductor device, which can be used to form the semiconductor device in any of the above embodiments.

[0119] Figure 9 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure. It should be noted that... Figure 9 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 9 The steps shown can be rearranged in order according to actual needs. (Refer to...) Figure 9 As shown, the manufacturing method includes at least the following steps:

[0120] S910: Form a first memory chip; wherein the first memory chip includes a first transistor, a first conductive structure, and a second conductive structure; the first transistor includes a first active region located in a first semiconductor layer and a first gate structure located on a first side of the first semiconductor layer; the first conductive structure and the second conductive structure both extend along the thickness direction of the first semiconductor layer through the first semiconductor layer and the first dielectric layer covering the first transistor, the first conductive structure is connected to the source of the first active region, and the second conductive structure is connected to the drain of the first active region.

[0121] Figures 10 to 13 This is a schematic diagram illustrating the fabrication process of a first memory chip according to an embodiment of this disclosure. The following will be combined with... Figure 9 , Figures 10 to 13 The fabrication process of the first memory chip provided in the embodiments of this disclosure will be described exemplarily.

[0122] Reference Figure 10 As shown, step S910 includes: providing an initial first semiconductor layer 210S, wherein the initial first semiconductor layer 210S may be the first substrate.

[0123] Reference Figure 10 As shown, step S910 further includes: forming a first transistor and a first dielectric layer 220 on a first side of the initial first semiconductor layer 210S. Specifically, the initial first semiconductor layer 210S is etched to form multiple isolation trenches, and dielectric material is filled into the isolation trenches to form a first isolation structure 212; the initial first semiconductor layer 210S between adjacent first isolation structures 212 is ion-doped or ion-implanted to form a first active region 211; a first gate dielectric layer and a first gate are formed on the channel of the first active region 211, the first gate dielectric layer and the first gate constituting a first gate structure, and the first gate structure and the first active region 211 constituting a first transistor; a first isolation layer covering the initial first semiconductor layer 210S, the first isolation structure 212 and the first gate structure are formed, and a first insulating layer covering the first isolation layer is formed, the first insulating layer and the first isolation layer constituting the first dielectric layer 220. In practical applications, the first insulating layer can be planarized.

[0124] Reference Figure 10 As shown, step S910 further includes: forming a first contact portion, a second contact portion, a third contact portion, and a first gate contact portion extending through the first dielectric layer along the thickness direction of the initial first semiconductor layer, such that the first contact portion is connected to the source of the first active region, the second contact portion is connected to the drain of the first active region, the third contact portion extends to the first side of the initial first semiconductor layer, and the first gate contact portion is connected to the first gate structure; and forming a conductive layer on the side of the first dielectric layer that is relatively far from the initial first semiconductor layer, wherein the conductive layer is connected to the third contact portion and the first gate contact portion respectively.

[0125] Specifically, the first dielectric layer 220 is etched along the direction facing the initial first semiconductor layer 210S to form a plurality of contact holes. These contact holes include a first contact hole exposing the source of the first transistor, a second contact hole exposing the drain of the first transistor, a third contact hole exposing the first semiconductor layer 210, and a gate contact hole exposing the first gate. Conductive material is then filled into the contact holes to form a first contact portion 231, a second contact portion 241, a third contact portion 251, and a first gate contact portion 261. Here, the first contact hole, the second contact hole, and the third contact hole can be filled simultaneously, meaning that the first contact portion 231, the second contact portion 241, and the third contact portion 251 are formed simultaneously. Of course, in other embodiments, the first contact portion 231, the second contact portion 241, and the third contact portion 251 can also be formed individually.

[0126] A first interconnect dielectric layer is formed, covering a first dielectric layer 220, a first contact portion 231, a second contact portion 241, a third contact portion 251, and a first gate contact portion 261. The first interconnect dielectric layer is etched to form trenches. Conductive material is filled into the trenches to form a first interconnect structure. The first interconnect structure and the first interconnect dielectric layer constitute a first interconnect layer 270. Here, the first interconnect structure in the first interconnect layer 270 can be patterned to form a conductive layer 273 as shown in Figure 10.

[0127] Reference Figures 10 to 12 As shown, step S910 further includes: forming a first connection portion 232, a second connection portion 242, and a third connection portion 252 extending through the initial first semiconductor layer 210S along the thickness direction of the initial first semiconductor layer 210S on the second side, such that the first connection portion 232 is connected to the first contact portion 231, the second connection portion 242 is connected to the second contact portion 241, and the third connection portion 252 is connected to the third contact portion 251; wherein, the retained initial first semiconductor layer 210S constitutes the first semiconductor layer 210, the first connection portion 232 and the first contact portion 231 constitute the first conductive structure 230, the second connection portion 242 and the second contact portion 241 constitute the second conductive structure 240, and the third connection portion 252 and the third contact portion 251 constitute the third conductive structure 250.

[0128] Specifically, it can be Figure 10 The structure shown is inverted, such that the back side of the initial first semiconductor layer 210S faces upwards, as... Figure 11As shown; a mask layer 701 and a patterned photoresist layer (not shown) are formed on the back side of the initial first semiconductor layer 210S; the initial first semiconductor layer 210S is etched along the direction toward the back side of the initial first semiconductor layer 210S to form a plurality of connection holes (e.g., TSV holes), the plurality of connection holes including a first connection hole exposing a first contact portion 231, a second connection hole exposing a second contact portion 241, and a third connection hole exposing a third contact portion 251; conductive materials are filled into the plurality of connection holes respectively to form a first connection portion 232, a second connection portion 242, and a third connection portion 252, as shown. Figure 12 As shown. Here, the first connecting hole, the second connecting hole, and the third connecting hole can be filled simultaneously, that is, the first connecting portion 232, the second connecting portion 242, and the third connecting portion 252 are formed at the same time. Of course, in other embodiments, the first connecting portion 232, the second connecting portion 242, and the third connecting portion 252 can also be formed separately.

[0129] In some embodiments, the above manufacturing method further includes: forming a logic chip; forming a plurality of stacked first memory chips on one side of the logic chip, such that the first conductive structures of the plurality of first memory chips are connected in sequence, the second conductive structures of the plurality of first memory chips are connected in sequence, and the third conductive structures of the plurality of first memory chips are connected in sequence; wherein the first conductive structure, the second conductive structure, and the third conductive structure of the first memory chip closest to the logic chip are all connected to the logic chip. Figure 14 This is a schematic diagram of a stack of multiple first memory chips provided in an embodiment of this disclosure. The following will be combined with... Figure 5 and Figure 14 An illustrative example is provided.

[0130] Specifically, refer to Figure 14 As shown, the first memory chips 200a to 200d can be bonded sequentially, such that the first conductive structures 230 of the first memory chips 200a to 200d are connected sequentially, the second conductive structures 240 of the first memory chips 200a to 200d are connected sequentially, and the third conductive structures 250 of the first memory chips 200a to 200d are connected sequentially, thereby forming a structure as shown in the figure. Figure 14 The stacked structure shown; will Figure 5 The logic chip 300 shown is Figure 14 The stacked structure shown is bonded to form a semiconductor device comprising a logic chip and multiple first memory chips.

[0131] In some embodiments, the above-described fabrication method further includes: forming a second memory chip on the side of a plurality of first memory chips relatively far from the logic chip, such that the first conductive structure and the second conductive structure of the first memory chip farthest from the logic chip are respectively connected to the fourth contact portion and the fifth contact portion of the second memory chip; wherein the second memory chip includes a second transistor, a fourth contact portion, and a fifth contact portion; the second transistor includes a second active region located in a second semiconductor layer and a second gate structure located on a first side of the second semiconductor layer, the second gate structure being located between the second semiconductor layer and the first memory chip; the fourth contact portion and the fifth contact portion both extend along the thickness direction of the second semiconductor layer through a second dielectric layer covering the second transistor, the fourth contact portion being connected to the source of the second active region, and the fifth contact portion being connected to the drain of the second active region. Figure 15 This is a schematic diagram of a second memory chip and a stack of multiple first memory chips provided in an embodiment of this disclosure. The following will be combined with... Figure 5 , Figure 6 and Figure 15 An illustrative example is provided.

[0132] Specifically, refer to Figure 15 As shown, the second memory chip 400 can be flip-bonded onto the first memory chip 200d, such that the first conductive structure 230 and the second conductive structure 240 of the first memory chip 200d are respectively connected to the fourth contact portion and the fifth contact portion of the second memory chip 400, thereby forming a... Figure 15 The stacked structure shown; will Figure 5 The logic chip 300 shown is Figure 15 The stacked structure shown is bonded to form a semiconductor device comprising a logic chip, a second memory chip, and multiple first memory chips. For details on the second memory chip, please refer to... Figure 6 Related descriptions.

[0133] In some embodiments, forming a second memory chip includes: providing an initial second semiconductor layer; forming a second transistor and a second dielectric layer on a first side of the initial second semiconductor layer; forming a fourth contact portion, a fifth contact portion, a second dummy contact portion, and a second gate contact portion extending through the second dielectric layer along the thickness direction of the initial second semiconductor layer, such that the fourth contact portion connects to the source of a second active region, the fifth contact portion connects to the drain of the second active region, the second dummy contact portion extends to the first side of the initial second semiconductor layer, and the second gate contact portion connects to a second gate structure; forming a second dummy connection portion extending through the initial second semiconductor layer along the thickness direction of the initial second semiconductor layer on a second side of the initial second semiconductor layer, such that the second dummy connection portion connects to the second dummy contact portion; wherein the retained initial second semiconductor layer constitutes the second semiconductor layer, and the second dummy connection portion and the second dummy contact portion constitute a second dummy conductive structure; forming a thermally conductive structure on a second side of the second semiconductor layer; wherein the thermally conductive structure connects to the second dummy conductive structure.

[0134] The manufacturing process of the second memory chip 400 is similar to that of the first memory chip 200, and can be referred to... Figures 10 to 13 The difference lies in that a heat-conducting structure is formed on the back side of the second memory chip 400, and only a second dummy connection portion needs to be formed on the back side of the second memory chip 400 to lead the first dummy contact portion to the heat-conducting structure, without the need to form other contact portions on the back side to lead out the fourth and fifth contact portions.

[0135] In some embodiments, forming a second memory chip on the side of the plurality of first memory chips relatively far from the logic chip includes: bonding the second memory chip to the first memory chip farthest from the logic chip, such that the second gate contact is connected to the conductive layer of the first memory chip farthest from the logic chip, as shown below. Figure 15 As shown

[0136] In some embodiments, S910 further includes: forming a first dummy contact portion extending through a first dielectric layer along the thickness direction of a first semiconductor layer, such that the first dummy contact portion extends to a first side of an initial first semiconductor layer; forming a first dummy connection portion extending through an initial first semiconductor layer along the thickness direction of a first semiconductor layer on a second side of the initial first semiconductor layer, such that the first dummy connection portion connects to the first dummy contact portion; wherein the first dummy connection portion and the first dummy contact portion constitute a first dummy conductive structure; the first dummy conductive structures of a plurality of first memory chips are connected sequentially, the first dummy conductive structure of the first memory chip closest to the logic chip is connected to the logic chip, and the first dummy conductive structure of the first memory chip farthest from the logic chip is connected to a second dummy conductive structure.

[0137] Specifically, refer to Figure 14As shown, the first dummy contact portion 291 can interact with... Figure 10 The first contact portion 231, the second contact portion 241, and the third contact portion 251 are formed simultaneously; the first dummy connection portion 292 can be connected with... Figure 12 The first connecting portion 232, the second connecting portion 242, and the third connecting portion 252 are formed simultaneously, and the first dummy connecting portion 292 and the first dummy contact portion 291 constitute the first dummy conductive structure 290. After the first memory chips 200a to 200d are bonded sequentially, the first dummy conductive structures 290 of the first memory chips 200a to 200d are connected sequentially, as follows: Figure 14 and Figure 15 As shown; after the second memory chip 400 is flip-bonded onto the first memory chip 200d, the second dummy conductive structure 490 is connected to the first dummy conductive structure 290 of the first memory chip 200d, as shown. Figure 15 As shown; in the Figure 5 The logic chip 300 shown is Figure 15 After the stacked structure shown is bonded, the first dummy conductive structure 290 of the first memory chip 200a is connected to the logic chip 300, as shown. Figure 5 As shown.

[0138] In some embodiments, S910 further includes: thinning the second side of the initial first semiconductor layer to form the first semiconductor layer; the formation of the second memory chip further includes: thinning the second side of the initial second semiconductor layer to form the second semiconductor layer.

[0139] Specifically, in combination Figure 12 As shown, before forming multiple interconnects, the initial first semiconductor layer 210S can be thinned to reduce the etching depth and size of the TSV holes; after forming multiple interconnects, the remaining mask layer can be removed. Similarly, combined with Figure 15 As shown, the initial second semiconductor layer can be thinned before forming the dummy connection via extending through the initial second semiconductor layer, thereby reducing the etching depth and size of the dummy connection via (i.e., TSV via).

[0140] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0141] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0142] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0143] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes a first memory chip; the first memory chip includes: The first transistor includes: a first active region located in a first semiconductor layer and a first gate structure located on a first side of the first semiconductor layer; A first conductive structure extends along the thickness direction of the first semiconductor layer through the first semiconductor layer and the first dielectric layer covering the first transistor, and is connected to the source of the first active region. The second conductive structure extends along the thickness direction of the first semiconductor layer through the first dielectric layer and the first semiconductor layer, and is connected to the drain of the first active region.

2. The semiconductor device according to claim 1, characterized in that, The first memory chip also includes: The first gate contact extends through the first dielectric layer along the thickness direction of the first semiconductor layer and is connected to the first gate structure. A third conductive structure extends along the thickness direction of the first semiconductor layer through the first dielectric layer and the first semiconductor layer; wherein the third conductive structure is connected to the first gate contact through a conductive layer, the conductive layer being located on the side of the first dielectric layer that is relatively far away from the first semiconductor layer.

3. The semiconductor device according to claim 2, characterized in that, The first conductive structure includes: a first contact portion and a first connection portion; wherein the first contact portion and the first connection portion extend through the first dielectric layer and the first semiconductor layer, respectively; The second conductive structure includes: a second contact portion and a second connection portion; wherein the second contact portion and the second connection portion extend through the first dielectric layer and the first semiconductor layer, respectively; The third conductive structure includes a third contact portion and a third connection portion; wherein the third contact portion and the third connection portion extend through the first dielectric layer and the first semiconductor layer, respectively.

4. The semiconductor device according to claim 3, characterized in that, The first contact portion, the second contact portion, and the third contact portion have substantially the same dimensions in the thickness direction of the first semiconductor layer.

5. The semiconductor device according to claim 3, characterized in that, The first connecting portion, the second connecting portion, and the third connecting portion have substantially the same dimensions in the thickness direction of the first semiconductor layer.

6. The semiconductor device according to claim 3, characterized in that, The cross-sectional dimension of the first contact portion relative to the surface of the first semiconductor layer is less than or equal to the cross-sectional dimension of the first contact portion relative to the surface of the first semiconductor layer; The cross-sectional dimension of the second contact portion relative to the surface of the first semiconductor layer is less than or equal to the cross-sectional dimension of the second contact portion relative to the surface of the first semiconductor layer; The cross-sectional dimension of the third contact portion relative to the surface of the first semiconductor layer is less than or equal to the cross-sectional dimension of the third contact portion relative to the surface of the first semiconductor layer.

7. The semiconductor device according to claim 3, characterized in that, The cross-sectional dimension of the first connecting portion relative to the surface of the first dielectric layer is less than or equal to the cross-sectional dimension of the first connecting portion relative to the surface of the first dielectric layer; the cross-sectional dimension of the second connecting portion relative to the surface of the first dielectric layer is less than or equal to the cross-sectional dimension of the second connecting portion relative to the surface of the first dielectric layer; the cross-sectional dimension of the third connecting portion relative to the surface of the first dielectric layer is less than or equal to the cross-sectional dimension of the third connecting portion relative to the surface of the first dielectric layer.

8. The semiconductor device according to claim 3, characterized in that, The dimension of the first gate contact in the thickness direction of the first semiconductor layer is smaller than the dimensions of the first contact, the second contact, and the third contact in the thickness direction of the first semiconductor layer.

9. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes a logic chip and a plurality of first memory chips stacked on one side of the logic chip; wherein the first conductive structures of the plurality of first memory chips are connected in sequence, the second conductive structures of the plurality of first memory chips are connected in sequence, the third conductive structures of the plurality of first memory chips are connected in sequence, and the first conductive structure, the second conductive structure and the third conductive structure of the first memory chip closest to the logic chip are all connected to the logic chip.

10. The semiconductor device according to claim 9, characterized in that, The semiconductor device further includes a second memory chip located on the side of the plurality of first memory chips that is relatively far away from the logic chip; The second memory chip includes: The second transistor includes: a second active region located in the second semiconductor layer and a second gate structure located on a first side of the second semiconductor layer, wherein the second gate structure is located between the second semiconductor layer and the first memory chip; The fourth contact extends along the thickness direction of the second semiconductor layer through the second dielectric layer covering the second transistor and is connected to the source of the second active region. The fifth contact extends through the second dielectric layer along the thickness direction of the second semiconductor layer and is connected to the drain of the second active region; The first conductive structure and the second conductive structure of the first memory chip, which is furthest from the logic chip, are respectively connected to the fourth contact portion and the fifth contact portion.

11. The semiconductor device according to claim 10, characterized in that, The second memory chip also includes: The second gate contact extends along the thickness direction of the second semiconductor layer through the second dielectric layer and is connected to the second gate structure; wherein the second gate contact is connected to the conductive layer of the first memory chip that is furthest from the logic chip.

12. The semiconductor device according to claim 10 or 11, characterized in that, The first memory chip also includes: The first dummy conductive structure extends along the thickness direction of the first semiconductor layer through the first dielectric layer and the first semiconductor layer; The second memory chip also includes: The second dummy conductive structure extends along the thickness direction of the second semiconductor layer through the second dielectric layer and the second semiconductor layer; A thermally conductive structure is located on the second side of the second semiconductor layer and connected to the second dummy conductive structure; wherein the second side of the second semiconductor layer and the first side of the second semiconductor layer are opposite to each other along the thickness direction of the second semiconductor layer; In this configuration, the first dummy conductive structures of multiple first memory chips are connected in sequence, the first dummy conductive structure of the first memory chip closest to the logic chip is connected to the logic chip, and the first dummy conductive structure of the first memory chip farthest from the logic chip is connected to the second dummy conductive structure.

13. The semiconductor device according to claim 12, characterized in that, The first dummy conductive structure includes: a first dummy contact portion and a first dummy connection portion; wherein the first dummy contact portion and the first dummy connection portion extend through the first dielectric layer and the first semiconductor layer, respectively.

14. The semiconductor device according to claim 12, characterized in that, The second dummy conductive structure includes: a second dummy contact portion and a second dummy connection portion; wherein the second dummy contact portion and the second dummy connection portion extend through the second dielectric layer and the second semiconductor layer respectively; the second dummy contact portion, the fourth contact portion, and the fifth contact portion have substantially the same dimensions in the thickness direction of the second semiconductor layer.

15. The semiconductor device according to claim 12, characterized in that, The first memory chip includes a plurality of the first dummy conductive structures; the second memory chip includes a plurality of the second dummy conductive structures; In this configuration, multiple first dummy conductive structures and multiple second dummy conductive structures are located in a first region of the semiconductor device, and the first conductive structure, the second conductive structure, and the third conductive structure are located in a second region of the semiconductor device, with the first region surrounding the second region.

16. The semiconductor device according to claim 12, characterized in that, The semiconductor device also includes a heat dissipation structure located on the side of the thermally conductive structure that is relatively far from the second semiconductor layer.

17. The semiconductor device according to claim 16, characterized in that, The semiconductor device further includes: A processing chip is disposed side-by-side with the logic chip on one side of the substrate; wherein the heat dissipation structure covers the processing chip.

18. The semiconductor device according to claim 9, characterized in that, The first memory chip further includes: a first bonding layer located on a second side of the first semiconductor layer and a second bonding layer located on a side of the first dielectric layer that is relatively far away from the first semiconductor layer; In this configuration, the first bonding layer of one of two adjacent first memory chips is bonded to the second bonding layer of the other first memory chip; the first bonding layer of the first memory chip closest to the logic chip is bonded to the logic chip; and the second bonding layer of the first memory chip furthest from the logic chip is bonded to the second memory chip.

19. A method for fabricating a semiconductor device, characterized in that, include: A first memory chip is formed; wherein the first memory chip includes a first transistor, a first conductive structure, and a second conductive structure; the first transistor includes a first active region located in a first semiconductor layer and a first gate structure located on a first side of the first semiconductor layer; the first conductive structure and the second conductive structure both extend along the thickness direction of the first semiconductor layer through the first semiconductor layer and a first dielectric layer covering the first transistor, the first conductive structure is connected to the source of the first active region, and the second conductive structure is connected to the drain of the first active region.

20. The manufacturing method according to claim 19, characterized in that, The process of forming the first memory chip includes: Provide the initial first semiconductor layer; The first transistor and the first dielectric layer are formed on a first side of the initial first semiconductor layer; A first contact portion, a second contact portion, a third contact portion, and a first gate contact portion are formed extending through the first dielectric layer along the thickness direction of the initial first semiconductor layer, such that the first contact portion is connected to the source of the first active region, the second contact portion is connected to the drain of the first active region, the third contact portion extends to the first side of the initial first semiconductor layer, and the first gate contact portion is connected to the first gate structure. A conductive layer is formed on the side of the first dielectric layer that is relatively far from the initial first semiconductor layer, and the conductive layer is respectively connected to the third contact portion and the first gate contact portion; A first connection portion, a second connection portion, and a third connection portion are formed on the second side of the initial first semiconductor layer, extending through the initial first semiconductor layer along its thickness direction, such that the first connection portion connects to the first contact portion, the second connection portion connects to the second contact portion, and the third connection portion connects to the third contact portion; wherein, the retained initial first semiconductor layer constitutes the first semiconductor layer, the first connection portion and the first contact portion constitute the first conductive structure, the second connection portion and the second contact portion constitute the second conductive structure, and the third connection portion and the third contact portion constitute the third conductive structure.

21. The manufacturing method according to claim 20, characterized in that, The first contact portion, the second contact portion, and the third contact portion are formed simultaneously; the first connecting portion, the second connecting portion, and the third connecting portion are formed simultaneously.

22. The manufacturing method according to claim 20, characterized in that, The manufacturing method further includes: Forming logic chips; Multiple first memory chips are stacked on one side of the logic chip, such that the first conductive structures of the multiple first memory chips are connected in sequence, the second conductive structures of the multiple first memory chips are connected in sequence, and the third conductive structures of the multiple first memory chips are connected in sequence; wherein, the first conductive structure, the second conductive structure, and the third conductive structure of the first memory chip closest to the logic chip are all connected to the logic chip.

23. The manufacturing method according to claim 22, characterized in that, The manufacturing method further includes: A second memory chip is formed on the side of the plurality of first memory chips that is relatively far away from the logic chip, such that the first conductive structure and the second conductive structure of the first memory chip farthest from the logic chip are respectively connected to the fourth contact portion and the fifth contact portion of the second memory chip; wherein, the second memory chip includes a second transistor, the fourth contact portion and the fifth contact portion; the second transistor includes a second active region located in a second semiconductor layer and a second gate structure located on a first side of the second semiconductor layer, the second gate structure being located between the second semiconductor layer and the first memory chip; the fourth contact portion and the fifth contact portion both extend along the thickness direction of the second semiconductor layer through a second dielectric layer covering the second transistor, the fourth contact portion being connected to the source of the second active region, and the fifth contact portion being connected to the drain of the second active region.

24. The manufacturing method according to claim 23, characterized in that, The process of forming the second memory chip includes: Provide an initial second semiconductor layer; The second transistor and the second dielectric layer are formed on the first side of the initial second semiconductor layer; A fourth contact portion, a fifth contact portion, a second dummy contact portion, and a second gate contact portion are formed extending through the second dielectric layer along the thickness direction of the initial second semiconductor layer, such that the fourth contact portion is connected to the source of the second active region, the fifth contact portion is connected to the drain of the second active region, the second dummy contact portion extends to the first side of the initial second semiconductor layer, and the second gate contact portion is connected to the second gate structure. A second dummy connection portion is formed on the second side of the initial second semiconductor layer, extending through the initial second semiconductor layer along the thickness direction of the initial second semiconductor layer, such that the second dummy connection portion connects to the second dummy contact portion; wherein, the retained initial second semiconductor layer constitutes the second semiconductor layer, and the second dummy connection portion and the second dummy contact portion constitute the second dummy conductive structure; A thermally conductive structure is formed on the second side of the second semiconductor layer; wherein the thermally conductive structure is connected to the second dummy conductive structure.

25. The manufacturing method according to claim 24, characterized in that, The step of forming a second memory chip on the side of the plurality of first memory chips that is relatively far away from the logic chip includes: The second memory chip is bonded to the first memory chip that is furthest from the logic chip, such that the second gate contact is connected to the conductive layer of the first memory chip that is furthest from the logic chip.

26. The manufacturing method according to claim 24, characterized in that, The process of forming the first memory chip further includes: A first dummy contact portion is formed that extends through the first dielectric layer along the thickness direction of the first semiconductor layer, such that the first dummy contact portion extends to a first side of the initial first semiconductor layer; A first dummy connection portion is formed on the second side of the initial first semiconductor layer, extending through the initial first semiconductor layer along the thickness direction of the initial first semiconductor layer, such that the first dummy connection portion connects to the first dummy contact portion; wherein, the first dummy connection portion and the first dummy contact portion constitute a first dummy conductive structure; the first dummy conductive structures of a plurality of first memory chips are connected sequentially, the first dummy conductive structure of the first memory chip closest to the logic chip is connected to the logic chip, and the first dummy conductive structure of the first memory chip farthest from the logic chip is connected to the second dummy conductive structure.

27. The manufacturing method according to claim 24, characterized in that, The process of forming the first memory chip further includes: The second side of the initial first semiconductor layer is thinned to form the first semiconductor layer; The process of forming the second memory chip also includes: The second side of the initial second semiconductor layer is thinned to form the second semiconductor layer.

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