Display panel, preparation method of display panel and display device

Abstract

According to the display panel, the preparation method of the display panel and the display panel, the laminated structure of the film layer is adjusted, so that the distance between the active layer and the light shielding layer in the display panel is close, the influence of the distance on the shielding effect of the light shielding layer is reduced, the light shielding effect of the light shielding layer on the active layer can be improved, and the adverse influence of illumination on the active layer is reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display panel, a method for manufacturing the display panel, and the display panel itself. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the Invention

[0004] To overcome the aforementioned shortcomings in the prior art, the purpose of this application is to provide a display panel, the display panel comprising... Substrate; A first light-shielding layer is located on one side of the substrate, and the first light-shielding layer includes a first light-shielding structure; A first active layer is located on the side of the first light-shielding layer away from the substrate, and the first active layer is provided with a first channel; A first metal layer is located on the side of the first active layer away from the substrate, and a first gate is disposed on the first metal layer. Wherein, in the direction perpendicular to the substrate, the distance between the first light-shielding structure and the first channel is less than 5000 angstroms. In some optional embodiments, the display panel further includes: A first insulating layer is located between the first light-shielding structure and the first channel, and the thickness of the first insulating layer is less than 5000 angstroms; Preferably, the distance between the surface of the first light-shielding structure away from the substrate and the surface of the first channel near the substrate is less than 5000 angstroms; Preferably, the first channel is located on the surface of the first insulating layer away from the substrate; Preferably, the first insulating layer covers the sidewalls of the first light-shielding structure and the surface away from the substrate.

[0005] In some alternative embodiments, the first active layer material is an oxide semiconductor; Preferably, the first active layer material is an oxide of at least one of indium, gallium, and zinc.

[0006] In some optional embodiments, the distance between the projection boundary of the first light-shielding structure on the substrate and the projection boundary of the first channel on the substrate is greater than 0.5 μm; Preferably, in the first direction, the distance between the projection boundary of the first light-shielding structure on the substrate and the projection boundary of the first active layer on the substrate is greater than 0.5 μm, and the first direction is the width direction of the first active layer; Preferably, in the second direction, the distance between the projection boundary of the first light-shielding structure on the substrate and the projection boundary of the first gate on the substrate is greater than 0.5 μm, and the second direction is the width direction of the first gate; Preferably, the first active layer extends along the second direction, the first gate extends along the first direction, the projection of the first active layer on the substrate and the projection of the first gate on the substrate have an overlapping portion, the overlapping portion is the projection of the first channel on the substrate, and the first direction and the second direction intersect on a plane parallel to the substrate. Preferably, the first gate and the first channel constitute a first transistor, the first transistor is located in the display area, and the first transistor is a switching transistor.

[0007] In some optional embodiments, the display panel further includes a second transistor located in the non-display area. The second transistor includes a second channel and a second gate, both of which are located on the side of the first light-shielding layer closest to the substrate; Preferably, the display panel further includes a second light-shielding structure located on the side of the second channel near the substrate; Preferably, the material of the second channel is different from the material of the first channel; Preferably, the material of the second channel includes polycrystalline silicon.

[0008] In some alternative embodiments, the second gate is located in a third metal layer, which is located on the side of the first light-shielding layer closer to the substrate; A dielectric layer is disposed between the third metal layer and the first light-shielding layer.

[0009] In some optional embodiments, the display panel further includes a second transistor located in the non-display area. The second transistor includes a second channel and a second gate, wherein the second channel is disposed in the same layer and with the same material as the first channel, and the second gate is disposed in the same layer and with the same material as the first gate; Preferably, the display panel further includes a second light-shielding structure, wherein the second light-shielding structure and the first light-shielding structure are disposed in the same layer and made of the same material.

[0010] In some optional embodiments, the display panel further includes: A second metal layer is located on the side of the first metal layer away from the substrate, and the second metal layer comprises: The first source signal line is connected to the first active layer through the first via and is located at one end of the first channel; The first drain signal line is connected to the first active layer through the second via and is located at the other end of the first channel; The first gate signal line is connected to the first gate through the third via; The first light-shielding signal line is connected to the first light-shielding structure through the fourth via.

[0011] In some optional embodiments, the display panel further includes: The second insulating layer is located between the first metal layer and the first active layer; A third insulating layer is located between the first metal layer and the second metal layer; Preferably, the first via and the second via are located in the third insulating layer and the second insulating layer; Preferably, the third via is located in the third insulating layer; Preferably, the fourth via is located in the first insulating layer, the second insulating layer, and the third insulating layer; Preferably, the depth of the fourth via is greater than the depths of the first via, the second via, and the third via; Preferably, the depths of the first via and the second via are greater than the depth of the third via.

[0012] In some optional embodiments, the display panel further includes: The third transistor is located in the display area, and the third transistor includes, The third channel is located in the first active layer and is spaced apart from the first channel; The third gate is located in the first metal layer and is spaced apart from the first gate; Preferably, the display panel further includes a third light-shielding structure located in the first light-shielding layer; the third transistor is a driving transistor.

[0013] In some alternative embodiments, the third transistor further includes: The third source signal line is connected to the first active layer through the fifth via and is located at one end of the third channel; The third drain signal line is connected to the first active layer through the sixth via and is located at the other end of the third channel; The third gate signal line is connected to the third gate through the seventh via; The third light-shielding signal line is connected to the third light-shielding structure through the eighth via.

[0014] In some alternative embodiments, the distance between the third light-shielding structure and the third channel in a direction perpendicular to the substrate is less than 5000 angstroms; The display panel further includes a first insulating layer located between the third light-shielding structure and the third channel, the thickness of the first insulating layer being less than 5000 angstroms; Preferably, the distance between the surface of the third light-shielding structure away from the substrate and the surface of the third channel near the substrate is less than 5000 angstroms; Preferably, the third channel is located on the surface of the first insulating layer away from the substrate; Preferably, the first insulating layer covers the upper surface and sidewalls of the third light-shielding structure away from the substrate.

[0015] In some optional embodiments, the distance between the projection boundary of the third light-shielding structure on the substrate and the projection boundary of the third channel on the substrate is greater than 0.5 μm; Preferably, in the first direction, the distance between the projection boundary of the third light-shielding structure on the substrate and the projection boundary of the first active layer on the substrate is greater than 0.5 μm, and the first direction is the width direction of the first active layer; Preferably, in the second direction, the distance between the projection boundary of the third light-shielding structure on the substrate and the projection boundary of the third gate on the substrate is greater than 0.5 μm, and the second direction is the width direction of the third gate; Preferably, the first active layer extends along the second direction, the third gate extends along the first direction, the projection of the first active layer on the substrate and the projection of the third gate on the substrate have an overlapping portion, the overlapping portion is the projection of the third channel on the substrate, and the first direction and the second direction intersect on a plane parallel to the substrate. In some optional embodiments, the display panel further includes: The third metal layer is located on the side of the third light-shielding structure closer to the substrate, and the third metal layer is provided with a first electrode plate; The third light-shielding structure is reused as the second electrode plate, and the first electrode plate and the second electrode plate form a capacitor. The projections of the first electrode plate onto the substrate and the projections of the second electrode plate onto the substrate partially overlap; Preferably, the projection of the first electrode plate onto the substrate overlaps the projection of the second electrode plate onto the substrate.

[0016] Another object of this application is to provide a display panel, comprising: Substrate; A first light-shielding layer is located on one side of the substrate, and the first light-shielding layer includes a first light-shielding structure; A first active layer is located on the side of the first light-shielding layer away from the substrate, and the first active layer is provided with a first channel; A first metal layer is located on the side of the first active layer away from the substrate, and a first gate is disposed on the first metal layer. Wherein, the distance between the projection boundary of the first light-shielding structure on the substrate and the projection boundary of the first channel on the substrate is greater than 0.5 μm.

[0017] In some optional embodiments, in a first direction, the distance between the projection boundary of the first light-shielding structure on the substrate and the projection boundary of the first active layer on the substrate is greater than 0.5 μm, and the first direction is the width direction of the first active layer. Preferably, in the second direction, the distance between the projection boundary of the first light-shielding structure on the substrate and the projection boundary of the first gate on the substrate is greater than 0.5 μm, and the second direction is the width direction of the first gate; Preferably, the first active layer extends along the second direction, the first gate extends along the first direction, the projection of the first active layer on the substrate and the projection of the first gate on the substrate have an overlapping portion, the overlapping portion is the projection of the first channel on the substrate, and the first direction and the second direction intersect on a plane parallel to the substrate. Preferably, the first gate and the first channel constitute a first transistor, the first transistor is located in the display area, and the first transistor is at least one of a switching transistor or a driving transistor.

[0018] In some optional embodiments, the display panel further includes a second transistor located in the non-display area. The second transistor includes a second channel and a second gate, both of which are located on the side of the first light-shielding layer closest to the substrate; Preferably, the display panel further includes a second light-shielding structure located on the side of the second channel near the substrate; Preferably, the material of the second channel is different from the material of the first channel; Preferably, the material of the second channel includes polycrystalline silicon, and the material of the first channel includes semiconductor oxide.

[0019] Another objective of this application is to provide a method for manufacturing a display panel, comprising: Forming a substrate; A first light-shielding layer is formed in the display area, and the first light-shielding layer is patterned to form a first light-shielding structure and a second light-shielding structure. A first active layer is formed in the display area, and a first channel and a third channel are formed by patterning and ion implantation of the first active layer. A first metal layer is formed, and a first gate and a third gate are formed by patterning the first metal layer; Wherein, in the direction perpendicular to the substrate, the distance between the first light-shielding structure and the first channel is less than 5000 angstroms.

[0020] In some optional embodiments, it also includes: After the substrate is formed and before the first light-shielding layer is formed, the second active layer and the third metal layer are sequentially formed in the non-display area, and the second channel and the second gate are respectively patterned to form them. A dielectric layer is formed between the third metal layer and the first light-shielding layer; A first insulating layer is formed between the first light-shielding layer and the first active layer; A second insulating layer is formed between the first active layer and the first metal layer; A third insulating layer is formed on the first metal layer; The above-mentioned film layer is subjected to a first hole etching to the first gate of the first metal layer, the third gate, both sides of the first channel of the first active layer, and both sides of the third channel of the first active layer; A second hole etching is performed on the above-mentioned film layer to the second gate of the third metal layer and both sides of the second channel of the second active layer; The first active layer and the second active layer are made of different materials.

[0021] Another object of this application is to provide a display device, including the display panel as described above.

[0022] Compared with the prior art, this application has the following beneficial effects: This application provides a display panel, a method for manufacturing the display panel, and the display panel itself. By adjusting the stacked structure of the film layers, the distance between the active layer and the light-shielding layer in the display panel is brought closer, reducing the influence of distance on the light-shielding effect of the light-shielding layer. This can improve the light-shielding effect of the light-shielding layer on the active layer and reduce the adverse effects of light on the active layer. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 One of the schematic diagrams of the display panel provided in this application; Figure 2 One of the partial cross-sectional views of the display panel provided in this application; Figure 3 One of the partial top views of the display panel provided in this application; Figure 4 A second partial cross-sectional view of the display panel provided in this application; Figure 5 The third partial cross-sectional view of the display panel provided in this application; Figure 6 Fourth partial cross-sectional view of the display panel provided for this application; Figure 7 A second partial top view of the display panel provided in this application; Figure 8 A schematic diagram of the equivalent circuit of the pixel driving circuit provided in this application; Figure 9 A schematic diagram of the light-emitting functional layer provided in this application; Figures 10a-10c Flowchart of the method for manufacturing the display panel provided in this application Figure 1 ; Figures 11a-11b Flowchart of the method for manufacturing the display panel provided in this application Figure 2 ; icon: 1-Substrate; 2-Buffer layer; 20-Second light-shielding structure; 3-Gate insulating layer; 30-Second active layer; 31-Second channel; 4-Dielectric layer; 40-Third metal layer; 41-Second gate; 5-First insulating layer; 50-First light-shielding layer; 51-First light-shielding structure; 52-Third light-shielding structure; 6-Second insulating layer; 60-First active layer; 61-First channel; 62-Third channel; 7-Third insulating layer; 70-First metal layer; 71-First gate; 72-Third gate; 8-First planarization layer; 80-Second metal layer; 81-First source signal line; 82-First drain signal line; 83-First gate signal line; 84-First light-shielding signal line; 811-First via; 821-Second via; 831-Third via; 841-Fourth via; 85-Third source signal line; 86-Third drain signal line; 87-Third gate signal line; 88-Third light-shielding signal line; 851-Fifth via; 861-Sixth via; 871-Seventh via; 881-Eighth via; 9-Second planarization layer; 90-Fourth metal layer; 10-pixel definition layer; 11-Anode; T1 - First transistor; T2 - Second transistor; T3 - Third transistor; AA - Display area; NA - Non-display area; Y - First direction; X - Second direction; Detailed Implementation To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0025] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0026] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0027] For ease of understanding, the accompanying diagram shows the mutually orthogonal X-axis, Y-axis, and Z-axis. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction relative to the plane containing the X and Y directions. Furthermore, a view where various elements are observed parallel to the plane containing the X and Y directions is called a top view. Alternatively, the planes in the X and Y directions can be planes parallel to the display surface of the display panel, and the Z-direction can be a direction parallel to the thickness direction of the display panel.

[0028] For certain elements, terms like "above" or "overhead" are sometimes used when describing the position of an element in the Z direction, and "below" or "under" are used when describing the position of an element in the opposite direction. Furthermore, when using terms like "above," "overhead," "below," "under," or "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly adjacent, but also the state where the two elements are separated by gaps or other elements. Additionally, terms like "first," "second," and "third" are used only for distinguishing descriptions and should not be interpreted as indicating or implying relative importance.

[0029] The inventors discovered that the electrical properties of oxide semiconductor TFTs in display panels change when exposed to light. This is mainly because the energy level defects in oxide semiconductors cause changes in the number of charge carriers after exposure to light. In particular, short-wavelength light can cause the threshold voltage of transistors to shift or the leakage current to increase, which in turn leads to display defects in the display panel.

[0030] In view of this, this embodiment provides a solution for displaying a faulty display panel. The solution provided in this embodiment will be described in detail below.

[0031] Please see Figure 1 , Figure 1 This is a schematic diagram of a display panel provided in this embodiment. The display panel can be an organic light-emitting diode (OLED) display panel or a quantum dot light-emitting diode (QLED) display panel. The display panel includes a display area AA with display function and a non-display area NA.

[0032] The shape of the display area AA of the display panel can be rectangular, square, circular, or elliptical, or other shapes, and is not specifically limited in this embodiment.

[0033] The display area AA includes a plurality of pixels PX arranged in the X and Y directions. Each pixel PX includes a plurality of sub-pixels SPX displaying different colors. In some embodiments, a pixel PX includes a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. For example, the first sub-pixel SPX1 is a blue sub-pixel, the second sub-pixel SPX2 is a green sub-pixel SPX2, and the third sub-pixel SPX3 is a red sub-pixel SPX3. In some embodiments, in addition to sub-pixels SPX1, SPX2, and SPX3, a pixel PX also includes sub-pixels SPX that emit white or other colors of light.

[0034] Sub-pixels (SPX) include pixel driving circuits and light-emitting devices driven by the pixel driving circuits to emit light of the corresponding color. First sub-pixel SPX1 includes a first light-emitting device, second sub-pixel SPX2 includes a second light-emitting device, and third sub-pixel SPX3 includes a third light-emitting device. One pixel driving circuit drives at least one light-emitting device to emit light. For example, display area AA includes a normal display area and a light-transmitting display area. The light-transmitting display area is a display area set according to a corresponding sensor and has light-transmitting properties, while the normal display area is a display area not set according to a corresponding sensor. In the normal display area, one pixel driving circuit drives one light-emitting device to emit light, and in the light-transmitting display area, one pixel driving circuit drives one or more light-emitting devices to emit light.

[0035] The display panel also includes non-display areas, such as the bezel area, which is equipped with scanning drive circuits and light-emitting drive circuits to transmit signals to the pixel drive circuits and control each light-emitting device to light up row by row or column by column.

[0036] Please refer to Figures 2-7 , Figures 2-7 The present invention provides a cross-sectional schematic diagram and a top view of a display panel provided in an embodiment of the present application. The display panel provided in this embodiment may include a substrate 1, a first light-shielding layer 50, a first active layer 60, and a first metal layer 70.

[0037] like Figure 2 As shown, in one embodiment of this application, the display panel includes a substrate 1; a first light-shielding layer 50 located on one side of the substrate 1, the first light-shielding layer 50 including a first light-shielding structure 51; a first active layer 60 located on the side of the first light-shielding layer 50 away from the substrate 1, the first active layer 60 having a first channel 61; and a first metal layer 70 located on the side of the first active layer 60 away from the substrate 1, the first metal layer 70 having a first gate 71, wherein, in a direction perpendicular to the substrate 1, the distance between the first light-shielding structure 51 and the first channel 61 is less than 5000 angstroms.

[0038] By providing a first light-shielding structure 51 below the first channel 61, the first channel 61 can be shielded from light, preventing electrical malfunctions caused by illumination. In the prior art, the first light-shielding structure 51 and the first channel 61 are separated by multiple insulating film layers, resulting in a large distance and inadequate shielding of the first channel 61, leading to poor light-shielding effect. In this embodiment, the first light-shielding layer 50 and the first light-shielding structure 51 are positioned at a distance of less than 5000 angstroms from the first channel 61, achieving a better light-shielding effect.

[0039] In some possible embodiments, a first insulating layer 5 is provided between the first light-shielding structure 51 and the first channel 61, the thickness of the first insulating layer 5 being less than 5000 angstroms.

[0040] In the preparation method, a first light-shielding layer 50 can be formed first and patterned to form a first light-shielding structure 51. The material of the first light-shielding structure 51 is metal. Then, a first insulating layer 5 is formed to cover the sidewalls of the first light-shielding structure 51 and the surface away from the substrate 1. Then, a first channel 61 is formed on the first insulating layer 5.

[0041] In some possible embodiments, the first insulating layer 5 is in surface contact with the first light-shielding structure 51 and the first channel 61, respectively, which can further reduce the thickness of the first light-shielding structure 51 and the first channel 61 in the direction perpendicular to the substrate 1. The distance between the surface of the first light-shielding structure 51 away from the substrate 1 and the surface of the first channel 61 near the substrate 1 is less than 5000 angstroms.

[0042] In some possible embodiments, after the formation of the first active layer 60, ion implantation is performed on different portions of the first active layer 60 to form a first channel 61 and source and drain regions located on both sides of the first channel 61, respectively. Please refer to [the relevant documentation] for details. Figure 2 and Figure 3 A first active layer 60 extends along the second direction X and forms a first channel 61 at its intermediate position. A second insulating layer 6 is formed on the first channel 61, and a first metal layer 70 is formed on the second insulating layer 6. A first gate 71 is patterned on the first metal layer 70 and extends along the first direction Y. Figure 3 As shown, Figure 3 This is a top view of the first active layer 60 and the first metal layer 70. The projections of the first active layer 60 and the first metal layer 70 onto the substrate 1 overlap, and this overlapping portion coincides with the projection of the first channel 61 onto the substrate 1. Therefore, the boundary of the first channel 61 in the first direction Y is the boundary of the first active layer 60, and the boundary of the first channel 61 in the second direction X coincides with the projection of the boundary of the first gate 71 in the second direction X onto the substrate 1.

[0043] In some possible embodiments, the distance between the projection boundary of the first light-shielding structure 51 on the substrate 1 and the projection boundary of the first channel 61 on the substrate 1 is greater than 0.5 μm.

[0044] In the first direction Y, the distance between the projection boundary of the first light-shielding structure 51 on the substrate 1 and the projection boundary of the first active layer 60 on the substrate 1 is greater than 0.5 μm, and the first direction is the width direction of the first active layer 60. In the second direction X, the distance between the projection boundary of the first light-shielding structure 51 on the substrate 1 and the projection boundary of the first gate 71 on the substrate 1 is greater than 0.5 μm, and the second direction is the width direction of the first gate 71. The first active layer 60 extends along the second direction X, and the first gate 71 extends along the first direction Y. The projection of the first active layer 60 on the substrate 1 and the projection of the first gate 71 on the substrate 1 have an overlapping portion. The overlapping portion is the projection of the first channel 61 on the substrate 1. The first direction and the second direction intersect on a plane parallel to the substrate 1. The first gate 71 and the first channel 61 constitute part of the first transistor T1, which is located in the display area and is a switching transistor.

[0045] By setting the projection of the first light-shielding structure 51 onto the substrate 1 to exceed the projection boundary of the first channel 61 onto the substrate 1 by 0.5 μm, the first light-shielding structure 51 can prevent electrical defects caused by light exposure in both the first and second directions. It should be noted that in this embodiment, by reducing the distance between the first light-shielding structure 51 and the first channel 61, and further setting the distance by which the first light-shielding structure 51 extends beyond the boundary of the first channel 61, and by comprehensively configuring the stacked structure and specific parameters on both the horizontal and vertical planes, the first light-shielding structure 51 can better achieve the light-shielding effect, thus stabilizing the electrical performance of the first channel 61.

[0046] In some possible embodiments, the first active layer 60 is made of an oxide semiconductor; the first active layer 60 is an oxide of at least one of indium, gallium, and zinc. The channel formed by the oxide semiconductor is more sensitive to light than other types of channels, and by providing a light-shielding structure below the semiconductor oxide channel, its electrical properties are made more stable.

[0047] In one embodiment of this application, a second transistor T2 located in the display area is also included. Please refer to... Figure 4 The second transistor T2 includes a second channel 31 and a second gate 41, both of which are located on the side of the first light-shielding layer 50 close to the substrate 1. In some possible embodiments, the display panel further includes a second light-shielding structure 20 located on the side of the second channel 31 near the substrate 1; the material of the second channel 31 is different from the material of the first channel 61; the material of the second channel 31 includes polycrystalline silicon, and the material of the second light-shielding structure 20 includes metal.

[0048] In the preparation process, substrate 1 is formed first; A second light-shielding structure 20 is formed on the non-display area; A buffer layer 2 is formed on the second light-shielding structure 20. The buffer layer 2 is formed directly on the sidewall of the second light-shielding structure 20 and the upper surface away from the substrate 1. A second active layer 30 is formed on the buffer layer 2, and the second active layer 30 is patterned to form a second channel 31; The distance between the second light-shielding structure 20 and the second channel 31 in the direction perpendicular to the substrate 1 is less than 5000 angstroms.

[0049] A gate insulating layer 3 is formed on the second channel 31, and the gate insulating layer 3 covers the sidewalls of the second channel 31 and the surface away from the substrate 1; A third metal layer 40 is formed on the gate insulating layer 3 and the second metal layer 80 is patterned to form a second gate 41; A dielectric layer 4 is formed on the second gate 41, and the dielectric layer 4 covers the sidewalls of the second gate 41 and the surface away from the substrate 1; A first light-shielding layer 50, a first active layer 60, and a first metal layer 70 are sequentially formed on the dielectric layer 4 in a direction away from the substrate 1, wherein the first channel 61 of the first active layer 60 and the first gate 71 of the first metal layer 70 constitute a part of the first transistor T1.

[0050] The display panel in this embodiment includes transistors made of two different materials. A first light-shielding structure 51 and a second light-shielding structure 20 are respectively formed on the side of the transistors closest to the substrate 1, providing light-shielding protection for all types of transistors in the display panel. Simultaneously, the first light-shielding structure 51 of the first transistor T1 is located on the side of the second gate 41 furthest from the substrate 1. That is, the first light-shielding structure 51 is closer to the first channel 61, making the distance more convenient. Compared to the prior art, the first light-shielding structure 51 being located on the side of the second transistor T2 closest to the substrate 1 provides better light-shielding protection for the first channel 61.

[0051] In another possible embodiment, the display panel includes a second transistor T2 located in the display area. Please refer to... Figure 5 The second transistor T2 includes a second channel 31 and a second gate 41. The second channel 31 is disposed in the same layer and with the same material as the first channel 61, and the second gate 41 is disposed in the same layer and with the same material as the first gate 71. The display panel also includes a second light-shielding structure 20, which is made of the same layer and material as the first light-shielding structure 51.

[0052] In the preparation process, substrate 1 is formed first; A first light-shielding layer 50 is formed on the substrate 1, and the first light-shielding layer 50 is patterned. At the same time, a first light-shielding structure 51 located in the display area and a second light-shielding structure 20 located in the non-display area are formed. A first insulating layer 5 is formed on the first light-shielding layer 50, and the first insulating layer 5 covers the sidewalls of the first light-shielding structure 51 and the second light-shielding structure 20 and the upper surface away from the substrate 1. A first active layer 60 and a second active layer 30 are formed on the first insulating layer 5, and a first channel 61 and a second channel 31 are respectively patterned to form the first channel 61 and the second channel 31, both of which are located on the upper surface of the first insulating layer 5. A second insulating layer 6 is formed, which covers the sidewalls of the first channel 61 and the second channel 31 and the upper surface away from the substrate 1; A first metal layer 70 is formed on the second insulating layer 6, and a first gate 71 and a second gate 41 are patterned to form them respectively.

[0053] In one embodiment of this application, a third transistor T3 located in the display area is also included. Please refer to... Figure 6 and Figure 7 The third transistor T3 includes a third channel located in the first active layer 60 and spaced apart from the first channel 61; a third gate 72 located in the first metal layer 70 and spaced apart from the first gate 71; the display panel also includes a third light-shielding structure 52 located in the first light-shielding layer 50, the material of the third light-shielding structure 52 including metal. The third transistor T3 is a driving transistor. In this embodiment, by setting the first light-shielding structure 51 and the third light-shielding structure 52 for the switching transistor and the driving transistor in the display area respectively, light-shielding structures are set for all transistors in the pixel driving circuit, making the electrical performance of the entire driving circuit more stable. At the same time, the third channel of the third transistor T3 is set in the same layer as the first communication layer, the third gate 72 is set in the same layer as the first gate 71, and the third light-shielding structure 52 is set in the same layer as the first light-shielding structure 51, simplifying the fabrication process. The distance between the third light-shielding structure 52 and the third channel in the direction perpendicular to the substrate 1 is less than 5000 angstroms, and the distance between the projection boundary of the third light-shielding structure 52 on the substrate 1 and the projection boundary of the third channel on the substrate 1 is greater than 0.5 μm. In the first direction Y, the distance between the projection boundary of the third light-shielding structure 52 on the substrate 1 and the projection boundary of the first active layer 60 on the substrate 1 is greater than 0.5 μm, and the first direction is the width direction of the first active layer 60; in the second direction X, the distance between the projection boundary of the third light-shielding structure 52 on the substrate 1 and the projection boundary of the third gate 72 on the substrate 1 is greater than 0.5 μm, and the second direction is the width direction of the third gate 72.

[0054] In some possible embodiments, the display panel further includes a capacitor comprising a first electrode plate and a second electrode plate, wherein the first electrode plate is located on a third metal layer 40, which is located on the side of the first light-shielding layer 50 closest to the substrate 1. The third light-shielding structure 52 of the first light-shielding layer 50 is reused as the second electrode plate of the capacitor, and the projections of the first electrode plate on the substrate 1 and the second electrode plate on the substrate 1 partially overlap, or the projection of the first electrode plate on the substrate 1 covers the projection of the second electrode plate on the substrate 1.

[0055] In some possible embodiments, the third metal layer 40 is located on the side of the first light-shielding layer 50 close to the substrate 1. The display panel includes a first transistor T1, a second transistor T2 and a third transistor T3. The third metal layer 40 forms the second gate 41 of the second transistor T2 and the first electrode plate of the capacitor, which can simplify the process flow.

[0056] In one embodiment of this application, the display panel further includes a second metal layer 80, such as... Figure 6 As shown, the second metal layer 80 is located on the side of the first metal layer 70 away from the substrate 1. A third insulating layer 7 is disposed between the first metal layer 70 and the second metal layer 80. The second metal layer 80 includes: a first source signal line 81, which is connected to the first active layer 60 through a first via 811 and is located at one end of the first channel 61; a first drain signal line 82, which is connected to the first active layer 60 through a second via 821 and is located at the other end of the first channel 61; a first gate signal line 83, which is connected to the first gate 71 through a third via 831; and a first light-shielding signal line 84, which is connected to the first light-shielding structure 51 through a fourth via 841.

[0057] In some possible embodiments, the second metal layer 80 further includes: a third source signal line 85, connected to the first active layer 60 through a fifth via 851 and located at one end of the first channel 61; a third drain signal line 86, connected to the first active layer 60 through a sixth via 861 and located at the other end of the third channel; a third gate signal line 87, connected to the third gate 72 through a seventh via 871; and a third light-shielding signal line 88, connected to the third light-shielding structure 52 through an eighth via 881. By placing the signal line layers of the first transistor T1 and the third transistor T3 on the same layer, the process flow can be simplified.

[0058] In some possible embodiments, the display panel further includes a second insulating layer 6 located between the first metal layer 70 and the first active layer 60; a third insulating layer 7 located between the first metal layer 70 and the second metal layer 80; a first via 811, a second via 821, a fifth via 851, and a sixth via 861 located in the third insulating layer 7 and the second insulating layer 6; a third via 831 and a seventh via 871 located in the third insulating layer 7; and a fourth via 841 and an eighth via 871 located in the first insulating layer 5, the second insulating layer 6, and the third insulating layer 7; the depth of the fourth via 841 is greater than the depth of the first via 811, the second via 821, and the third via 831; and the depth of the first via 811 and the second via 821 is greater than the depth of the third via 831.

[0059] The first via 811, the second via 821, the third via 831, the fifth via 851, the sixth via 861, and the seventh via 871 can be formed in the same etching process. The third via 831 and the seventh via 871 are etched to the first gate 71 and the third gate 72 respectively to cut off. Then the first via 811, the second via 821, the fifth via 851, and the sixth via 861 are further etched to the first active layer 60 to cut off. By using the first gate 71 and the third gate 72 of the first metal layer 70 as a cutoff layer, the third via 831 and the seventh via 871 are cut off, and the first via 811, the second via 821, the third via 831, the fifth via 851, the sixth via 861, and the seventh via 871 are further formed. This allows the first via 811, the second via 821, the third via 831, the fifth via 851, the sixth via 861, and the seventh via 871 to be formed simultaneously in a single etching process, which simplifies the process flow.

[0060] In some possible embodiments, after forming various signal lines of the second metal layer, a first planarization layer 8 is formed on the second metal layer. The first planarization layer 8 covers the first source signal line 81, the first drain signal line 82, the first gate signal line 83, the first light-shielding signal line 84, the third source signal line 85, the third drain signal line 86, the third gate signal line 87, the third light-shielding signal line 88, and the second capacitor signal line 89. The first planarization layer 8 has good fluidity, providing a flat upper surface and reducing the height difference caused by the height of the second metal layer. A fourth metal layer 90 is also disposed on the second metal layer 80. The fourth metal layer is electrically connected to the second metal layer 80 through vias in the first planarization layer 8 to realize signal transmission. A second planarization layer 9 is also disposed above the fourth metal layer 90. The second planarization layer 9 can further reduce the height difference existing between the second metal layer 80 and the fourth metal layer 90. A pixel defining layer 10 is also provided on the side of the fourth metal layer 90 away from the substrate. The pixel defining layer 10 is provided with a pixel opening. At least a portion of the anode 11 is exposed through the pixel opening. The anode 11 is electrically connected to the fourth metal layer 90 through a via in the second planarization layer 9 to realize signal transmission.

[0061] In one embodiment of this application, please refer to Figure 2 The display panel includes: Substrate 1; The first light-shielding layer 50 is located on one side of the substrate 1, and the first light-shielding layer 50 includes a first light-shielding structure 51. The first active layer 60 is located on the side of the first light-shielding layer 50 away from the substrate 1, and the first active layer 60 is provided with a first channel 61; A first metal layer 70 is located on the side of the first active layer 60 away from the substrate 1, and a first gate 71 is disposed on the first metal layer 70. The distance between the projection boundary of the first light-shielding structure 51 on the substrate 1 and the projection boundary of the first channel 61 on the substrate 1 is greater than 0.5 μm.

[0062] By setting the projection relationship and distance between the first light-shielding structure 51 and the first channel 61 on the substrate 1, it is ensured that the first light-shielding structure 51 can complete the light-shielding protection of the first channel 61.

[0063] Specifically, in the first direction, the distance between the projection boundary of the first light-shielding structure 51 on the substrate 1 and the projection boundary of the first active layer 60 on the substrate 1 is greater than 0.5 μm, and the first direction is the width direction of the first active layer 60. In the second direction, the distance between the projection boundary of the first light-shielding structure 51 on the substrate 1 and the projection boundary of the first gate 71 on the substrate 1 is greater than 0.5 μm, and the second direction is the width direction of the first gate 71. The first active layer 60 extends along the second direction, and the first gate 71 extends along the first direction. The projection of the first active layer 60 on the substrate 1 and the projection of the first gate 71 on the substrate 1 have an overlapping portion. The overlapping portion is the projection of the first channel 61 on the substrate 1. The first direction and the second direction intersect on a plane parallel to the substrate 1. The first gate 71 and the first channel 61 constitute the first transistor T1, which is located in the display area. The first transistor T1 is at least one of a switching transistor or a driving transistor.

[0064] In some possible embodiments, the display panel further includes a second transistor T2 located in the non-display area. The second transistor T2 includes a second channel 31 and a second gate 41, both of which are located on the side of the first light-shielding layer 50 near the substrate 1. The display panel also includes a second light-shielding structure 20, located on the side of the second channel 31 near the substrate 1. The material of the second channel 31 is different from that of the first channel 61. The material of the second channel 31 includes polysilicon, while the material of the first channel 61 includes semiconductor oxide. The display panel in this embodiment includes transistors made of two different materials. The first light-shielding structure 51 and the second light-shielding structure 20 are respectively formed on the side of the two transistors near the substrate 1, providing light-shielding protection for all types of transistors in the display panel. Simultaneously, the first light-shielding structure 51 of the first transistor T1 is located on the side of the second gate 41 away from the substrate 1. That is, the first light-shielding structure 51 is closer to the first channel 61, making the distance more convenient. Compared to the prior art, the first light-shielding structure 51 being located on the side of the second transistor T2 near the substrate 1 provides better light-shielding protection for the first channel 61.

[0065] In this embodiment, the material of substrate 1 may include a rigid material, such as glass; or the material of substrate 1 may include a flexible material, such as polyimide (Pi).

[0066] Optionally, an array of functional layers may also be disposed on one side of the substrate 1. The array of functional layers may include multiple film structures, such as a buffer layer 2, multiple conductive layers, multiple insulating layers, and a planarization layer. See also... Figure 2 Multiple film layers in the array functional layer can form multiple thin film transistors (TFTs) and wiring structures at different locations. The thin film transistors can cooperate with each other to form multiple pixel driving units or driving circuits.

[0067] In addition, the array functional layer also includes at least one of the following traces: a trace for transmitting the data signal Data, a trace for transmitting the scan number Scan, a trace for transmitting the drive voltage VDD, and a trace for transmitting the common voltage VSS.

[0068] Please see Figure 8 The pixel driving circuit 110D includes a driving transistor T2 and a switching transistor T1. The source of the switching transistor T1 can be connected to a data line that provides a data signal Data, the gate of the switching transistor T1 can be connected to a scan line that provides a scan signal Scan, and the drain of the switching transistor T1 can be connected to the gate of the driving transistor T2. The two ends of the storage capacitor Cst are respectively connected to the gate and the source of the driving transistor T2, and the drain of the driving transistor T2 is connected to the light-emitting device. Figure 7 This is one implementation of the pixel driving circuit, but the pixel driving circuit of this application is not limited to... Figure 7 The pixel driving circuit shown in the 2T1C diagram can also be other pixel driving circuits, such as 7T1C, 8T1C, etc.

[0069] In some possible implementations, the light-emitting device includes a first electrode, a light-emitting functional layer, and a second electrode stacked in a direction away from the substrate 1.

[0070] Optionally, the first electrode can be connected to the pixel driving circuit in the array functional layer. When there is a potential difference between the first electrode and the second electrode, the light-emitting functional layer located between the first electrode and the second electrode is driven to emit light.

[0071] The first electrode may include a multilayer structure, such as a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. The reflective layer can be formed, for example, using silver, a metallic material with excellent light reflectivity. The conductive oxide layers can be formed, for example, using transparent conductive oxides such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide). The second electrode 160 is formed, for example, using a metallic material such as an alloy of magnesium and silver (MgAg).

[0072] Please see Figure 9 , Figure 9 This is a schematic diagram of a light-emitting functional layer according to one embodiment of this application. The light-emitting functional layer of at least one of the first, second, and third light-emitting devices includes a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light-emitting material layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL, stacked along a direction away from the substrate 1 (i.e., the Z direction). The light-emitting functional layer may include a single light-emitting material layer EML, or a stacked light-emitting functional layer including multiple light-emitting material layers EML.

[0073] In order for the light-emitting functional layer to emit light, a pixel voltage is provided to the first electrode and a common voltage is provided to the second electrode, forming a potential difference between the first and second electrodes, causing the light-emitting functional layer disposed between the first and second electrodes to emit light. In one embodiment, if a potential difference is formed between the first and second electrodes of the first light-emitting device, the light-emitting material layer EML of the light-emitting functional layer emits blue light; if a potential difference is formed between the first and second electrodes of the second light-emitting device, the light-emitting material layer EML of the light-emitting functional layer emits green light; and if a potential difference is formed between the first and second electrodes of the third light-emitting device, the light-emitting material layer EML of the light-emitting functional layer emits red light.

[0074] Another embodiment of this application also includes a method for manufacturing a display panel, such as... Figures 10a-10c As shown, it includes: Forming substrate 1; A first light-shielding layer 50 is formed in the display area, and the first light-shielding layer 50 is patterned to form a first light-shielding structure 51 and a second light-shielding structure 20. A first active layer 60 is formed in the display area, and the first active layer 60 is patterned and ion implanted to form a first channel 61 and a third channel; A first metal layer 70 is formed, and a first gate 71 and a third gate 72 are patterned on the first metal layer 70. Wherein, in the direction perpendicular to the substrate 1, the distance between the first light-shielding structure 51 and the first channel 61 is less than 5000 angstroms.

[0075] In some possible embodiments, after the substrate 1 is formed and before the first light-shielding layer 50 is formed, a second active layer 30 and a third metal layer 40 are sequentially formed in the non-display area, and a second channel 31 and a second gate 41 are respectively patterned to form them. A dielectric layer 4 is formed between the third metal layer 40 and the first light-shielding layer 50; A first insulating layer 5 is formed between the first light-shielding layer 50 and the first active layer 60; A second insulating layer 6 is formed between the first active layer 60 and the first metal layer 70; A third insulating layer 7 is formed on the first metal layer 70; like Figure 11a As shown, the above-mentioned film layer is subjected to a first hole etching to the first gate 71 and the third gate 72 of the first metal layer 70, the two sides of the first channel 61 of the first active layer 60 and the two sides of the third channel 62 of the first active layer 60, and respectively forming a third via 831, a seventh via 871, a first via 811, a second via 821, a fifth via 851 and a sixth via 861; like Figure 11b As shown, a second hole etching is performed on the film layer to the first light-shielding structure 51, the third light-shielding structure 52, the first electrode plate cst1, and both sides of the second gate 41 and the second channel 31.

[0076] The first active layer 60 and the second active layer 30 are made of different materials.

[0077] Another embodiment of this application also includes a display device, comprising the display panel and light-emitting device described in the above embodiments.

[0078] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A display panel, comprising a pixel circuit, the pixel circuit including a first transistor, the first transistor including a first gate and a first channel, the display panel comprising: Substrate; A first light-shielding layer is located on one side of the substrate, and the first light-shielding layer includes a first light-shielding structure; A first insulating layer is located on the side of the first light-shielding layer away from the substrate; A first active layer is located on the side of the first insulating layer away from the substrate, and the first active layer includes the first channel; The second insulating layer is located on the side of the first active layer away from the substrate; A first metal layer is located on the side of the second insulating layer away from the substrate, and the first metal layer has the first gate disposed thereon. Wherein, in the direction perpendicular to the substrate, the distance between the first light-shielding structure and the first channel is less than 5000 angstroms.

2. The display panel according to claim 1, The distance between the surface of the first light-shielding structure away from the substrate and the surface of the first channel near the substrate is less than 5000 angstroms; Preferably, the first channel is located on the surface of the first insulating layer away from the substrate; Preferably, the first insulating layer covers the sidewalls of the first light-shielding structure and the surface away from the substrate.

3. The display panel according to claim 1, wherein the first active layer material is an oxide; Preferably, the first active layer material is an oxide of at least one of indium, gallium, and zinc.

4. The display panel according to claim 1, wherein the projection of the first light-shielding structure on the substrate covers the projection of the first channel on the substrate; The distance between the projection boundary of the first light-shielding structure on the substrate and the projection boundary of the first channel on the substrate is greater than 0.5 μm; Preferably, in the first direction, the distance between the projection boundary of the first light-shielding structure on the substrate and the projection boundary of the first active layer on the substrate is greater than 0.5 μm, and the first direction is the width direction of the first active layer; Preferably, in the second direction, the distance between the projection boundary of the first light-shielding structure on the substrate and the projection boundary of the first gate on the substrate is greater than 0.5 μm, and the second direction is the width direction of the first gate; Preferably, the first active layer extends along the second direction, the first gate extends along the first direction, the projection of the first active layer on the substrate and the projection of the first gate on the substrate have an overlapping portion, the overlapping portion is the projection of the first channel on the substrate, and the first direction and the second direction intersect on a plane parallel to the substrate. The first transistor is located in the display area and is a switching transistor.

5. The display panel according to claim 1, further comprising: The second transistor is located in the non-display area. The second transistor includes a second channel and a second gate, both of which are located on the side of the first light-shielding layer closest to the substrate; Preferably, the display panel further includes a second light-shielding structure located on the side of the second channel near the substrate; Preferably, the material of the second channel is different from the material of the first channel; Preferably, the material of the second channel includes polycrystalline silicon.

6. The display panel according to claim 5, wherein the second gate is located in a third metal layer, and the third metal layer is located on the side of the first light-shielding layer near the substrate; A dielectric layer is disposed between the third metal layer and the first light-shielding layer.

7. The display panel according to claim 1, further comprising: The second transistor is located in the non-display area. The second transistor includes a second channel and a second gate, wherein the second channel is disposed in the same layer and with the same material as the first channel, and the second gate is disposed in the same layer and with the same material as the first gate; Preferably, the display panel further includes a second light-shielding structure, wherein the second light-shielding structure and the first light-shielding structure are disposed in the same layer and made of the same material.

8. The display panel according to claim 1, further comprising: A second metal layer is located on the side of the first metal layer away from the substrate, and the second metal layer comprises: The first source signal line is connected to the first active layer through the first via and is located at one end of the first channel; The first drain signal line is connected to the first active layer through the second via and is located at the other end of the first channel; The first gate signal line is connected to the first gate through the third via; The first light-shielding signal line is connected to the first light-shielding structure through the fourth via.

9. The display panel according to claim 8, further comprising: A third insulating layer is located between the first metal layer and the second metal layer; Preferably, the first via and the second via are located in the third insulating layer and the second insulating layer; Preferably, the third via is located in the third insulating layer; Preferably, the fourth via is located in the first insulating layer, the second insulating layer, and the third insulating layer; Preferably, the depth of the fourth via is greater than the depths of the first via, the second via, and the third via; Preferably, the depths of the first via and the second via are greater than the depth of the third via.

10. The display panel according to claim 1, further comprising: The third transistor is located in the display area, and the third transistor includes, The third channel is located in the first active layer and is spaced apart from the first channel; The third gate is located in the first metal layer and is spaced apart from the first gate; Preferably, the display panel further includes a third light-shielding structure located in the first light-shielding layer; the third transistor is a driving transistor.

11. The display panel according to claim 10, wherein the third transistor further comprises: The third source signal line is connected to the first active layer through the fifth via and is located at one end of the third channel; The third drain signal line is connected to the first active layer through the sixth via and is located at the other end of the third channel; The third gate signal line is connected to the third gate through the seventh via; The third light-shielding signal line is connected to the third light-shielding structure through the eighth via.

12. The display panel according to claim 10, wherein the distance between the projection boundary of the third light-shielding structure on the substrate and the projection boundary of the third channel on the substrate is greater than 0.5 μm; Preferably, in the first direction, the distance between the projection boundary of the third light-shielding structure on the substrate and the projection boundary of the first active layer on the substrate is greater than 0.5 μm, and the first direction is the width direction of the first active layer; Preferably, in the second direction, the distance between the projection boundary of the third light-shielding structure on the substrate and the projection boundary of the third gate on the substrate is greater than 0.5 μm, and the second direction is the width direction of the third gate; Preferably, the first active layer extends along the second direction, the third gate extends along the first direction, the projection of the first active layer on the substrate and the projection of the third gate on the substrate have an overlapping portion, the overlapping portion is the projection of the third channel on the substrate, and the first direction and the second direction intersect on a plane parallel to the substrate.

13. The display panel according to claim 10, further comprising: The third metal layer is located on the side of the third light-shielding structure closer to the substrate, and the third metal layer is provided with a first electrode plate; The third light-shielding structure is reused as the second electrode plate, and the first electrode plate and the second electrode plate form a capacitor. The projections of the first electrode plate onto the substrate and the projections of the second electrode plate onto the substrate partially overlap; Preferably, the projection of the first electrode plate onto the substrate overlaps the projection of the second electrode plate onto the substrate.

14. A display panel, comprising: Substrate; A first light-shielding layer is located on one side of the substrate, and the first light-shielding layer includes a first light-shielding structure; A first active layer is located on the side of the first light-shielding layer away from the substrate, and the first active layer is provided with a first channel; A first metal layer is located on the side of the first active layer away from the substrate, and a first gate is disposed on the first metal layer. Wherein, the projection of the first light-shielding structure onto the substrate covers the projection of the first channel onto the substrate. The distance between the projection boundary of the first light-shielding structure on the substrate and the projection boundary of the first channel on the substrate is greater than 0.5 μm.

15. The display panel according to claim 15, wherein in a first direction, the distance between the projection boundary of the first light-shielding structure on the substrate and the projection boundary of the first active layer on the substrate is greater than 0.5 μm, and the first direction is the width direction of the first active layer. Preferably, in the second direction, the distance between the projection boundary of the first light-shielding structure on the substrate and the projection boundary of the first gate on the substrate is greater than 0.5 μm, and the second direction is the width direction of the first gate; Preferably, the first active layer extends along the second direction, the first gate extends along the first direction, the projection of the first active layer on the substrate and the projection of the first gate on the substrate have an overlapping portion, the overlapping portion is the projection of the first channel on the substrate, and the first direction and the second direction intersect on a plane parallel to the substrate. Preferably, the first gate and the first channel constitute a first transistor, the first transistor is located in the display area, and the first transistor is at least one of a switching transistor or a driving transistor.

16. The display panel according to claim 15, further comprising: The second transistor is located in the non-display area. The second transistor includes a second channel and a second gate, both of which are located on the side of the first light-shielding layer closest to the substrate; Preferably, the display panel further includes a second light-shielding structure located on the side of the second channel near the substrate; Preferably, the material of the second channel is different from the material of the first channel; Preferably, the material of the second channel includes polycrystalline silicon, and the material of the first channel includes semiconductor oxide.

17. A method for manufacturing a display panel, comprising: Forming a substrate; In the non-display area, a second active layer and a third metal layer are sequentially formed, and a second channel and a second gate are respectively patterned to form them. A dielectric layer is formed on the second gate; A first light-shielding layer is formed on the dielectric layer, and the first light-shielding layer is patterned to form a first light-shielding structure and a second light-shielding structure. A first insulating layer, a first active layer, a second insulating layer, a first metal layer, and a third insulating layer are sequentially formed on the first light-shielding layer, wherein the first active layer is patterned and ion implanted to form a first channel and a third channel, and the first metal layer is patterned to form a first gate and a third gate; The above-mentioned film layer is subjected to a first hole etching to the first gate of the first metal layer, the third gate, both sides of the first channel of the first active layer, and both sides of the third channel of the first active layer; A second hole etching is performed on the above-mentioned film layer to the second gate of the third metal layer and both sides of the second channel of the second active layer; The first active layer and the second active layer are made of different materials.

18. A display device comprising a display panel as described in any one of claims 1-17.

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