Custom layout recommendation using machine learning

Abstract

A processing device obtains an input (302), where the input specifies a set of devices to be placed and routed for a circuit design. In response to the input, the processing device executes a machine learning model (304) to calculate a probability distribution function on a historical device placement library, the probability distribution function estimates the suitability of each historical device placement in the library of historical device placement for placing and routing the set of devices specified in the input. The processing device presents (306) a graphical representation of a defined number of historical device placement from the library of historical device placement, the historical device placement being estimated to be suitable for placement and routing of the set of devices based on the probability distribution function.

Description

Technical Field

[0001] This disclosure generally relates to electronic design automation, and more specifically to machine learning-based techniques for recommending custom layouts for analog designs. Background Technology

[0002] The simulation design consists of well-defined building blocks representing devices such as differential pairs, current mirrors, custom digital cells, amplifiers, and the like. These devices are captured in the schematic design, from which a netlist is extracted and used for simulation to ensure the design conforms to specifications. Next, a layout of the schematic design is created, in which the devices are placed and routed, and simulation is performed from the post-layout netlist, which may exhibit parasitic effects. The placement and routing of devices in the layout can be refined until the post-layout simulation conforms to design specifications. Summary of the Invention

[0003] In one example, a processing device may acquire input specifying a set of devices to be placed and routed for a circuit design. In response to the input, the processing device may execute a machine learning model to compute a probability distribution function on a library of historical device placements, the probability distribution function estimating the suitability of each historical device placement in the library for placing and routing the set of devices specified in the input. The processing device may present a graphical representation of a defined number of historical device placements from the library, the historical device placements being estimated based on the probability distribution function to be suitable for placing and routing the set of devices.

[0004] In another example, a system may include a memory storing instructions and a processing means coupled to the memory and executing the instructions. When executed, the instructions cause the processing means to construct a library of historical device placements, wherein each data point in the library includes a set of devices for circuit design and historical device placements generated for said set of devices. The instructions may further cause the processing means to use the library of historical device placements to train a machine learning model to compute a probability distribution function on the library of historical device placements, the probability distribution function estimating the suitability of each historical device placement in the library for placing a set of devices for a new circuit design and for routing said set of devices.

[0005] In another example, a non-transitory computer-readable medium may contain stored instructions. When executed by a processing device, the stored instructions enable the processing device to receive input, wherein the input specifies a set of devices to be placed and routed for a circuit design. In response to the input, the processing device may execute a machine learning model to compute a probability distribution function on a library of historical device placements as output, the probability distribution function estimating the suitability of each historical device placement in the library for placing and routing the set of devices specified in the input. The processing system may then present, via a graphical user interface, a predefined number of historical device placements from the library, which are estimated based on the probability distribution function to be the most suitable for placing and routing the set of devices. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings illustrating embodiments of this disclosure. The drawings are provided to give an understanding of embodiments of this disclosure and are not intended to limit the scope of this disclosure to these specific embodiments. Furthermore, the drawings are not necessarily drawn to scale.

[0007] Figure 1 This describes an example method for training a machine learning model to recommend custom layouts for simulated designs, based on the present disclosure.

[0008] Figure 2 The example sequence neural network described in this disclosure has been trained to receive a set of devices to be placed and wired for a custom design as input and to compute a probability distribution function on a historical device placement library as output, the probability distribution function estimating the suitability of each historical device placement in the historical device placement library for placing the input set of devices and wiring the set of devices.

[0009] Figure 3 This describes an instance method for using machine learning to recommend the placement and wiring of a set of devices for a new custom design, based on historical device placement examples.

[0010] Figure 4 Flowcharts illustrating various processes used during the design and manufacture of integrated circuits according to some embodiments of this disclosure.

[0011] Figure 5 The diagram illustrates an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0012] This disclosure relates to machine learning-based techniques for recommending custom layouts for simulation designs. As discussed above, a simulation design consists of well-defined building blocks representing devices such as differential pairs, current mirrors, custom digital cells, amplifiers, and the like. These devices are captured in a schematic design, from which a netlist is extracted and used for simulation to ensure the design conforms to specifications. A layout of the schematic design is then created, in which the devices are placed and routed, and simulation is performed from the post-layout netlist, which has parasitic effects. The placement and routing of devices in the layout can be refined until the post-layout simulation conforms to design specifications. Although tools exist to assist engineers in creating layouts, the process still involves a significant amount of manual work and can therefore be very time-consuming.

[0013] This disclosure provides an example of training a machine learning model to recommend layouts from a historical (i.e., previously created) layout library (repository) when a set of devices is provided for a new custom design. In one example, training data in the form of historical layouts is automatically collected when a new placement is submitted to a master layout that is under development and from a completed placement project. A machine learning model (e.g., a sequence neural network (SNN)) can then be trained on the training data to learn the correspondence between devices in the schematic and the placement of those devices in the layout. Therefore, when an input consisting of a set of devices to be placed and wired is provided to the trained machine learning model, the model can identify from the library several historical layouts best suited for the input set of devices (e.g., layouts that will be reused for placing and wiring the input set of devices).

[0014] In one instance, historical layouts recommended by a machine learning model can be presented to the user as snapshots of the corresponding historical layouts in graphical representation. The user can load the recommended historical layouts into the main symbol canvas of the symbol editor tool by simply selecting (e.g., double-clicking) a snapshot of the recommended historical layout. Alternatively, the user can choose not to load any of the recommended historical layouts and can instead manually create new layouts (which can be collected as "new" historical layouts and used for further training of the machine learning model).

[0015] The technical advantages of this disclosure include, but are not limited to, the ability to quickly place and route devices in custom designs. Specifically, by training a machine learning model to capture collective knowledge and layout practices followed in previous custom layouts, the time, computational resources, and manual work required to build a layout according to the specifications of a new custom layout can be significantly reduced. Furthermore, experimental results have shown that in most test cases, the disclosed method can recommend device placement with 80% or better device-to-netlist matching.

[0016] As used in the context of this disclosure, the term "custom design" is understood to refer to a schematic diagram of an analog device (or a portion thereof) from which a netlist can be extracted. "Custom design" can be more broadly considered as an example of a circuit design historically developed at least in part by manual work rather than through fully automated electronic design automation tools. The term "custom layout" is understood to refer to the placement and routing of devices (e.g., differential pairs, current mirrors, custom digital cells, amplifiers, and the like) contained in a custom design.

[0017] Figure 1 This describes an example method 100 for training a machine learning model to recommend custom layouts for simulated designs, based on this disclosure. In one instance, method 100 may be implemented as an optional feature in a symbol editor or other simulated layout tool for creating custom layouts. In another instance, method 100 may be implemented as a separate or independent feature that can interact with a symbol editor or other simulated layout tool.

[0018] In one instance, method 100 may be provided by a computer system (e.g., Figure 5 The method 100 is executed by a computer system 500. In another example, the method 100 may be executed by a processing device, which may include a computer system (e.g., a computer system 500). Figure 5 The components of a computer system 500 (e.g., processing device 502). As an example, method 100 is described below as being executed by the processing device.

[0019] Method 100 begins at step 102. In step 102, the processing device may construct a historical device placement library, wherein each data point in the library includes a set of devices for a custom design and historical device placements generated for the set of devices.

[0020] In the context of this disclosure, "historical" placements are understood to refer to a set of placements that have been submitted, rather than, for example, placements that have not yet been generated. For instance, when a user submits a placement to the main layout of a custom design under development, historical placements can be automatically collected and written to a user-specified repository. In one instance, historical placements can be collected as a YAML (Yellow Markup Language) file. In another instance, the YAML file may contain ancillary data related to historical placements, such as symbol layout snapshots, library information, project information, user information, or similar. As discussed in further detail below, this ancillary data can be used to filter the output of machine learning models.

[0021] Historical device placements can also be collected from a design library, which may contain schematics and layout designs of different units from completed custom design projects. In one example, the design library may store schematics and layout designs as Graphical Design System (GDS) II files. By running the Layout & Schematic (LVS) tool on the GDSII file, a mapping can be established across devices in the schematic and their placements in the corresponding layout. This mapping can then be used to extract a set of devices and their historical placements from the GDSII file.

[0022] As discussed above, each data point in the library constructed in step 102 may include a set of devices for a custom design and historical device placements generated for said set of devices. In one instance, the set of devices may be obtained from a netlist of the custom design. Therefore, the set of devices may include multiple devices to be placed. In one instance, each device in the set of devices may be represented by a numeric tuple, where each number in the numeric tuple represents a value of an attribute of the device. Device attributes may include, for example, the type of device (e.g., p-type metal-oxide-semiconductor (PMOS) or n-type metal-oxide-semiconductor (NMOS)), the total channel width of the device, the channel length of the device, the number of fingers in the device, the multiplier of the device, the number of vector bits (when the device is a vector device), or the like. Each device may further be represented by a numeric identifier associated with a connection graph representing the connectivity of the device. For example, the numeric identifier may uniquely identify a particular unique (non-isomorphic) connection graph. In one instance, the set of devices may be represented by a single vector comprising a cascade of attribute tuples of all devices in the set of devices and numeric connection graph identifiers.

[0023] In one instance, the historical device placement corresponding to a set of devices in a custom layout can be represented by identifiers that uniquely identify the set of devices, arranged in rows from left to right. Therefore, each data point collected in step 102 may include: (1) a concatenated vector comprising attribute tuples and numerical connection diagram identifiers of a set of devices in a custom design; and (2) an identifier associated with the historical placement of the set of devices represented in the vector.

[0024] It should be noted that for several groups of devices in the collected data points, multiple historical device placements may be identified as suitable for placing and wiring the same group of devices, but it is impossible to determine which of the multiple historical device placements is the "best". For example, there may be multiple dissimilar placements for the same group of input devices, where this is due to the presence of different types and / or numbers of dummy devices (i.e., devices that are not part of the group of input devices) included in the placements for electrical protection purposes, and these multiple placements are different from each other. Depending on the required amount of electrical protection, different numbers of dummy devices may be included in different locations. In other cases, there may be multiple dissimilar placements for the same group of input devices because the multiple placements may have different aspect ratios. In the case of multiple dissimilar placements for a given group of devices, the processing device can create an equivalence class containing all historical device placements determined to be suitable for wiring and placement of the same group of devices. Identifiers may be assigned to equivalence classes and used in data points instead of identifiers associated with individual historical placements. In the case of historical device placements in equivalence classes having different aspect ratios, the processing device can help the user identify the aspect ratio most suitable for a given group of devices based on the context of the overall layout.

[0025] Building the library according to step 102 can be an ongoing process. That is, the library can be continuously enhanced with new data points as new design libraries gain access or as users submit new placements to the main layout of a custom design under development. In one instance, a user designing a layout can enable the automatic collection of their submitted new placements before submitting them. For example, a user can enable the feature that enables automatic collection of new placements when starting the layout design tool. In this way, any new placements submitted can be automatically collected without interrupting the user's workflow. Alternatively, users who do not want their placements to be collected as training data can disable the feature that enables the collection of new placements.

[0026] In step 104, the processing device may use a historical device placement library to train a machine learning model to compute a probability distribution function on the historical device placement library, the probability distribution function estimating the suitability of each historical device placement in the historical device placement library for placing a set of devices for a new custom design and for wiring the set of devices.

[0027] In one instance, the machine learning model may include a neural network model. For example, in one instance, the machine learning model may include a sequence neural network (SNN). The SNN may be trained as a classification model that returns the best-matching historical device placement (or a predefined number of best-matching historical device placements) from a historical device placement library of a set of new devices to be placed and wired, based on the results of a probability distribution function. In other instances, the machine learning model may include another type of machine learning model, such as a regression model, decision tree, support vector machine, random forest model, or a neural network model with an architecture different from that of an SNN (e.g., a convolutional neural network).

[0028] Figure 2 The example sequence neural network (SNN) 200 according to this disclosure has been trained to receive a set of devices to be placed and wired for a custom design as input and to compute a probability distribution function on a historical device placement library as output, the probability distribution function estimating the suitability of each historical device placement in the historical device placement library for placing the input set of devices and wiring the set of devices.

[0029] In one example, the SNN 200 includes multiple layers, including an input layer 204, an output layer 208, and multiple hidden layers 206 located between the input layer 204 and the output layer 208. Each of the input layer 204, the output layer 208, and the multiple hidden layers 206 includes multiple nodes.

[0030] In one instance, the number of nodes in the input layer 204 represents the maximum size of the input values ​​202 (i.e., device vectors x1 to x4) to be supported by the SNN 200. Although Figure 2 The input layer 204 is described as having four nodes, but it should be understood that the input layer 204 may have any number of nodes, depending on the size of the input vector to be supported.

[0031] In one example, the number of nodes in the output layer 208 represents the data used to train the SNN (i.e., Figure 1 The number of unique output values ​​210 (i.e., the number of historical device placements y1 to y3) contained in the historical device placement library constructed in step 102. Although Figure 2 The output layer 208 is described as containing three nodes, but it should be understood that the output layer 208 can contain any number of nodes depending on the number of data points in the training data. Furthermore, since the quality of the SNN's output is only as good as its training data, new data points can be continuously added to the historical device placement library to improve the quality of the SNN's output. Therefore, the number of nodes in the output layer 208 can increase as the number of data points in the historical device placement library increases.

[0032] In one instance, hidden layer 206 may include multiple layers, each containing multiple nodes. Although Figure 2 Hidden layer 206 is described as comprising five layers with varying numbers of nodes, but it should be understood that hidden layer 206 may comprise any number of layers with any number of nodes. In one instance, depending on the size of the input (device) vector and the size of the training data (i.e., the number of data points in the historical device placement library), SNN 200 contains three or four hidden layers.

[0033] In one instance, an open-source, general-purpose programming language application programming interface (API) can be used to train the SNN 200 and to generate the recommended device placement using the SNN 200.

[0034] The advantage of training a machine learning model using the method described above is that training allows the model to capture collective knowledge and layout practices followed in previous custom layouts. Furthermore, historical device placements recommended by the machine learning model are ready to be consumed in the placement and routing implementation. This reduces the time, resources, and manual effort required to build a layout according to the specifications of a new custom design.

[0035] Figure 3 This describes an example method 300 for recommending the placement and wiring of a set of devices for a new custom design using machine learning. In one example, method 300 may be implemented as an optional feature in a symbol editor or other simulation layout tool for creating custom layouts. In another example, method 300 may be implemented as a separate or independent feature that can interact with a symbol editor or other simulation layout tool. For example, method 300 may be loaded into a separate utility (or executable program) that can act as a placement recommendation service available to multiple users interacting with said utility.

[0036] In one instance, method 300 may be provided by a computer system (e.g., Figure 5 The method 300 is executed by a computer system 500. In another example, the method 300 may be executed by a processing device, which may include a computer system (e.g., a computer system 500). Figure 5 The components of a computer system 500 (e.g., processing device 502). As an example, method 300 is described below as being executed by the processing device.

[0037] In step 302, the processing device may acquire input, wherein the input specifies a set of means to be placed and wired for a circuit design (e.g., a new custom design).

[0038] As discussed above, in one instance, the input may include a vector. The vector may include a concatenation of attribute tuples and digital connectivity graph identifiers for all devices in the set of devices. Each number in the attribute tuple represents the value of an attribute of the device to which the attribute tuple corresponds. Device attributes may include, for example, the type of device (e.g., PMOS or NMOS), the total channel width of the device, the channel length of the device, the number of fingers in the device, the multiplier of the device, the number of vector bits (when the device is a vector device), or the like. Each digital connectivity graph identifier uniquely identifies a specific (non-isomorphic) connectivity graph representing the connectivity of the device to which the digital connectivity graph identifier corresponds.

[0039] In one instance, the set of devices can be obtained from a netlist of a new circuit design (e.g., a custom design whose device placement has not yet been submitted or finalized). The set of devices can be obtained from the netlist in response to a signal received from the user instructing that an input vector should be constructed from the set of devices. In another instance, the user can enable a feature that causes the processing device to automatically construct the input vector of a set of devices whenever the placement tool is initiated on a set of devices that does not have a current placement or routing.

[0040] In another instance, the input may additionally include one or more user-specified filters to be applied when recommending placements of the set of devices specified in the input and historical device placements for routing the set of devices. For example, a historical device placement library may contain historical device placements for multiple different process nodes (e.g., 10 nm, 5 nm, 3 nm, or similar), but a user may only want to see recommendations from one (or fewer than all) of these process nodes.

[0041] In step 304, the processing device may execute a machine learning model in response to the input to compute a probability distribution function on the historical device placement library (e.g., as the output of the machine learning model), the probability distribution function estimating the suitability of each historical device placement in the historical device placement library for the set of devices specified in the placement input and for wiring the set of devices.

[0042] In one instance, the machine learning model may include a neural network (e.g., a subnet mask neural network) trained to take a set of devices to be placed and routed for a new circuit design as input and compute a probability distribution function over a library of historical device placements as output to estimate the suitability of each historical device placement in the library for placing the input set of devices and routing the set of devices. In one instance, the machine learning model may include similar... Figure 2The machine learning model described above and the SNN are illustrated in the text. However, in other instances, the machine learning model may include another type of machine learning model, such as regression models, decision trees, support vector machines, random forest models, or neural network models with an architecture different from that of SNNs (e.g., convolutional neural networks).

[0043] As discussed above, historical device placements may include device placements corresponding to circuit designs (e.g., custom designs) whose device placements were previously submitted or finalized (e.g., before the input is acquired in step 302). These historical device placements may be stored in a historical device placement library, which may be accessed by a machine learning model. The historical device placement library may also be continuously enhanced as access to a new design library is gained or as users submit new placements to the main layout of circuit designs under development (e.g., custom designs).

[0044] In one instance, the processing device may calculate from the probability distribution function any historical device placements in the historical device placement library that the user has indicated (e.g., by selecting a filter with input) should not be applied, either omitting or removing them. For example, the user may have indicated that historical device placements for certain process nodes should not be considered. In another instance, the processing system may apply a filter after the machine learning model has calculated the probability distribution function, but before presenting any calculation results to the user (e.g., as discussed further in conjunction with step 306).

[0045] In step 306, the processing device may (e.g., via a graphical user interface) provide a defined number of historical device placements from a historical device placement library, the historical device placements being estimated based on a probability distribution function to be suitable for placing the set of devices and wiring the set of devices.

[0046] In one instance, a historical device placement corresponding to the index position with the highest probability distribution function value can be identified as the most suitable historical device placement for placing and routing the set of devices. In another instance, the processing device can identify a predefined number of historical device placements with the highest probability distribution function value. For example, if the predefined number is n, then in step 306, the processing device identifies the n historical device placements with the highest probability distribution function values ​​as a defined number of historical device placements from a historical device placement library, which are estimated to be suitable for placing and routing the set of devices. In one instance, the defined number can be configured by a user (e.g., an engineer designing a layout containing the set of devices).

[0047] In one instance, a graphical representation of a historical device placement may include an image "snapshot" of the historical device placement. However, a snapshot may not include an exact copy of the historical device placement. For example, certain information in a historical device placement (such as information designated as proprietary) may be omitted or replaced to prevent the unintentional disclosure of proprietary information.

[0048] In one instance, one or more suitability metrics may be displayed next to each graphical representation. In one instance, the one or more suitability metrics include at least one of the following: a device matching metric and a netlist matching metric. Each of the device matching metric and the netlist matching metric may be expressed as a percentage. For example, if the device matching metric for a historical device placement is 100%, this means that all devices in the set of devices specified in the input have matched devices in the historical device placement; if any device in the set of devices specified in the input has not yet matched a device in the historical device placement, or if the historical device placement contains devices that do not match any of the devices in the set of devices specified in the input, then the value of the device matching metric may be reduced proportionally.

[0049] If the netlist match metric for the historical device placement is 100%, this means that the graph corresponding to the netlist of the set of devices specified in the input completely matches the graph corresponding to the netlist of the historical device placement. In one instance, a graph edit distance can be calculated between the graph corresponding to the netlist of the set of devices specified in the input and the graph corresponding to the netlist of the historical device placement, and the graph edit distance can be expressed as a percentage.

[0050] It should be noted that in some cases, the processing device may fail to recognize any historical device placements recommended for the set of devices specified in the input. In such cases, a graphical representation may not be presented. Instead, the processing device may present a message indicating that historical device placements are not recommended.

[0051] In optional step 308 (illustrated by dashed lines), the processing device may receive a signal indicating a user selection of one of a defined number of historical device placements.

[0052] For example, in one instance, a user could double-click the graphical representation corresponding to one of a defined number of historical device placements to instruct the user to select it. However, in other instances, the user could be instructed to select in other ways, such as other gestures (e.g., clicking, dragging, tapping a touchscreen, or the like), verbal commands (e.g., saying the identifier associated with one of the defined number of historical device placements), typing commands (e.g., typing the identifier associated with one of the defined number of historical device placements into a field of a dialog box), or the like.

[0053] In optional step 310 (illustrated by dashed lines), the processing device may, in response to a signal, load one of a defined number of historical device placements into the symbol editor canvas of the circuit design (i.e., the new custom design).

[0054] Method 300 can be implemented to recommend and reuse historical device placements for both standard analog cells and custom analog structures, as well as for different types of circuits and across different process nodes. For example, machine models can be specifically trained to recommend device placements for differential pairs with different drive strengths and protection levels, for current mirrors with different numbers of legs and different ratios, or the like. Filters allow users to customize recommendations in a user-friendly manner.

[0055] Figure 4 This describes a set of example processes 400 used during the design, inspection, and fabrication of, for example, integrated circuits, to convert and inspect design data and instructions representing integrated circuits. Each of these processes can be structured and enabled as multiple modules or operations. The term 'EDA' stands for 'Electronic Design Automation'. These processes begin with the creation of a product concept 402 using information provided by the designer, which is then converted to create an article of art using a set of EDA processes 404. When the design is finalized, it is tape-out 426, where the layout (e.g., geometry) of the integrated circuit is sent to a fabrication facility to create a mask set, which is then used to manufacture the integrated circuit. After tape-out, semiconductor dies are fabricated 428 and packaging and assembly processes 430 are performed to produce a finished integrated circuit 432.

[0056] Specifications for circuits or electronic structures can range from low-level transistor material placement to high-level description languages. High-level representations can be used to design circuits and systems using hardware description languages ​​('HDLs') such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. HDL descriptions can be translated into logic-level register-transfer-level ('RTL') descriptions, gate-level descriptions, placement-level descriptions, or mask-level descriptions. Each lower-level representation, as a more detailed description, adds more useful details to the design description, such as more details about the modules contained in the description. Lower-level representations as more detailed descriptions can be computer-generated, exported from a design library, or created by another design automation process. An example of a specification language used to specify a lower-level representation language for more detailed descriptions is SPICE, used for detailed descriptions of circuits with many analog components. The description at each representation level is enabled for use by the corresponding system (e.g., a formal verification system) of that layer. The design process can use... Figure 4 The sequence described herein can be enabled through EDA products (or EDA systems).

[0057] During system design phase 406, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics (such as power consumption, performance, area (physical and / or lines of code), and cost reduction). The design can be partitioned into different types of modules or components at this stage.

[0058] During logic design and functional verification 408, modules or components in the circuit are specified in one or more description languages, and the functional accuracy of the specifications is checked. For example, components of the circuit can be tested to generate outputs that match the requirements of the specifications for the designed circuit or system. Functional verification can use simulators and other programs, such as test bench generators, static HDL checkers, and formal checkers. In some embodiments, a special component system called a 'simulator' or 'prototype system' is used to accelerate functional verification.

[0059] During the synthesis and testing of the design 410, the HDL code is converted into a netlist. In some embodiments, the netlist may be a graph structure, wherein the edges of the graph structure represent components of the circuit and the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are layered artifacts that can be used by EDA products to verify whether the integrated circuit behaves as specified in the design during manufacturing. The netlist can be optimized for a target semiconductor manufacturing technology. Additionally, the finished integrated circuit can be tested to verify that it meets specification requirements.

[0060] During netlist verification 412, the netlist is checked to ensure it meets timing constraints and corresponds to the HDL code. During design planning 414, the overall planar diagram of the integrated circuit is constructed, and timing analysis and top-level routing are performed on it.

[0061] During layout or physical implementation 416, physical placement (e.g., positioning of circuit components such as transistors or capacitors) and wiring (connecting circuit components via multiple conductors) occur, and cell selection from a library can be performed to enable specific logic functions. As used herein, the term 'cell' can specify a set of transistors, other components, and interconnections that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (e.g., flip-flops or latches). As used herein, a circuit 'block' can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and are used as physical structures and enabled during simulation. Parameters (e.g., size) are specified for selected cells (based on 'standard cells') and made accessible in a database for use in EDA products.

[0062] During analysis and extraction 418, circuit functionality is verified at the layout level, allowing for refined layout design. During physical inspection 420, the layout design is checked to ensure that manufacturing constraints are correct, such as DRC constraints, electrical constraints, and lithographic constraints, and that the circuit system functionality matches the HDL design specification. During resolution enhancement 422, the geometry of the layout is transformed to improve the fabrication method of the circuit design.

[0063] During the tape-out process, data is created for use (and, where appropriate, after the application of lithographic enhancement) in the production of a photomask. During mask data preparation 424, the 'tape-out' data is used to generate a photomask for the production of the finished integrated circuit.

[0064] Computer systems (e.g.) can be used Figure 5 The computer system 500) has a storage subsystem for storing some or all of the EDA products described herein, as well as units for developing libraries and programs and data structures used by products for physical and logical designs that use said libraries.

[0065] Figure 5 An example machine of computer system 500 is described, within which a set of instructions can be executed to cause the machine to perform any or more of the methodologies discussed herein. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0066] A machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network device, a server, a network router, a switch, or a bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, while describing a single machine, the term "machine" should also be considered as any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methodologies discussed herein.

[0067] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM), static memory 506 (e.g., flash memory, static random access memory (SRAM)) and the like) and a data storage device 518, which communicate with each other via a bus 530.

[0068] Processing device 502 represents one or more processors, such as microprocessors, central processing units, or the like. More specifically, processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 502 may be configured to execute instructions 526 for performing the operations and steps described herein.

[0069] The computer system 500 may further include a network interface device 508 for communication via a network 520. The computer system 500 may also include a video display unit 510 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 512 (e.g., a keyboard), a cursor control device 514 (e.g., a mouse), a graphics processing unit 522, a signal generation device 516 (e.g., a speaker), a graphics processing unit 522, a video processing unit 528, and an audio processing unit 532.

[0070] Data storage device 518 may include a machine-readable storage medium 524 (also referred to as a non-transitory computer-readable medium) thereon storing one or more sets of instructions 526 or software embodying any or more of the methodologies or functions described herein. Instructions 526 may also reside wholly or at least partially in main memory 504 and / or processing device 502 during execution by computer system 500, which also constitute machine-readable storage media.

[0071] In some embodiments, instruction 526 includes instructions that implement functionality corresponding to this disclosure. Although machine-readable storage medium 524 is shown as a single medium in example embodiments, the term "machine-readable storage medium" should be considered as including a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered as including any medium capable of storing or encoding a set of instructions for machine execution and causing the machine and processing device 502 to perform any or more of the methodologies of this disclosure. Therefore, the term "machine-readable storage medium" should be considered as including, but not limited to, solid-state memory, optical media, and magnetic media.

[0072] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are methods used by those skilled in the art of data processing to most effectively communicate the essence of their work to others skilled in the art. An algorithm can be a sequence of operations that leads to a desired result. An operation is an operation that requires physical manipulation of physical quantities. Such quantities can take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals can be referred to as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0073] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. Unless otherwise expressly stated as is evident from this disclosure, it should be understood that throughout the description, certain terms refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities in the registers and memories of the computer system into other data representing physical quantities similarly represented in the memory or registers or other such information storage devices of the computer system.

[0074] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0075] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various other systems may be used in conjunction with the programs taught herein, or it may be proven convenient to construct more specialized devices to execute the methods. Furthermore, this disclosure is not described with reference to any particular programming language. It should be understood that a variety of programming languages ​​can be used to implement the teachings of this disclosure as described herein.

[0076] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform processes according to this disclosure. A machine-readable medium includes any means for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0077] In the foregoing disclosure, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be understood that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Where elements are referred to in the singular in this disclosure, more than one element may be depicted in the figures and labeled with the same number for the same elements. Therefore, this disclosure and the figures should be viewed in an illustrative rather than restrictive sense.

Claims

1. A method comprising: Input is obtained from a processing device, wherein the input specifies a set of devices to be placed and wired for a circuit design; The processing device executes a machine learning model in response to the input to compute a probability distribution function on a historical device placement library, the probability distribution function estimating the suitability of each historical device placement in the historical device placement library for placing the set of devices specified in the input and for wiring the set of devices; and The processing device provides a graphical representation of a defined number of historical device placements from the historical device placement library, the historical device placements being estimated based on the probability distribution function to be suitable for placing the group of devices and wiring the group of devices.

2. The method of claim 1, wherein the input comprises a vector, and the vector cascades for each of the set of devices to be placed and wired with: a tuple of numeric values ​​representing the attributes of each device and a numeric identifier representing a unique connection graph of the connectivity of each device.

3. The method of claim 2, wherein the attribute includes at least one of the following: whether each device is an n-type metal-oxide-semiconductor device or a p-type metal-oxide-semiconductor device, the total channel width of each device, the channel length of each device, the number of fingers in each device, the multiplier of each device, or the number of vector bits in each device.

4. The method of claim 2, wherein the vector is automatically constructed by the processing device when the processing device detects that the layout tool has been activated on the set of devices and the set of devices has not yet been placed or wired.

5. The method of claim 1, wherein the machine learning model comprises a sequence neural network trained on a plurality of data points, and wherein each of the data points represents a historical device placement from the historical device placement library and a set of historical devices corresponding to the historical device placement from the historical device placement library.

6. The method of claim 1, wherein each historical device placement in the historical device placement library includes a device placement corresponding to a circuit design submitted at a time prior to the acquisition of its device placement.

7. The method of claim 1, wherein the providing further comprises providing for each of the defined number of historical device placements at least one of: a device matching metric or a netlist matching metric, wherein the device matching metric includes a percentage indicating the degree of matching between devices in the set of devices specified in the input and devices in each of the defined number of historical device placements, and wherein the netlist matching metric includes a percentage indicating the degree of matching between a graph of a netlist corresponding to the set of devices specified in the input and a graph of a netlist corresponding to each of the defined number of historical device placements.

8. The method of claim 1, further comprising: The processing device receives a signal instructing the user to select one of the defined number of historical device placements; and The processing device, in response to the signal, loads one of the defined number of historical device placements into the symbol editor canvas of the circuit design.

9. The method of claim 1, wherein the execution includes filtering the historical device placement library to remove any historical device placements in the historical device placement library that the user has indicated should not be considered so that they are not considered by the machine learning model.

10. A system comprising: Memory, which stores instructions; and A processing device coupled to the memory and executing the instructions, which, when executed, cause the processing device to: Construct a historical device placement library, wherein each data point in the library includes a set of devices for circuit design and historical device placements generated for said set of devices; and The historical device placement library is used to train a machine learning model to compute a probability distribution function on the historical device placement library, which estimates the suitability of each historical device placement in the historical device placement library for placing a set of devices for a new circuit design and for routing the set of devices.

11. The system of claim 10, wherein at least one data point in the library is automatically collected in response to the processing device detecting that a user of the simulation design tool has submitted a new placement to the master layout of the circuit design under development.

12. The system of claim 10, wherein the machine learning model comprises a sequence neural network model.

13. A non-transitory computer-readable medium including stored instructions, which, when executed by a processing means, cause the processing means to: Obtain input, wherein the input specifies a set of devices to be placed and wired for a circuit design; In response to the input, a machine learning model is executed to compute a probability distribution function on a historical device placement library, the probability distribution function estimating the suitability of each historical device placement in the historical device placement library for placing the set of devices specified in the input and for wiring the set of devices; and Provides a graphical representation of a defined number of historical device placements from the historical device placement library, the historical device placements being estimated based on the probability distribution function to be suitable for placing the set of devices and wiring the set of devices.

14. The non-transitory computer-readable medium of claim 13, wherein the instructions further cause the processing apparatus to filter the historical device placement library to remove any historical device placements that the user has indicated should not be considered so that they are not considered by the machine learning model.

15. The non-transitory computer-readable medium of claim 13, wherein the machine learning model comprises a sequence neural network trained on a plurality of data points, and wherein each of the plurality of data points represents a historical device placement from the historical device placement library and a set of historical devices corresponding to the historical device placement from the historical device placement library.

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