Semiconductor device

Abstract

The semiconductor device includes: a chip having a main surface; a drift region of a first conductivity type formed in a surface layer portion of the main surface; a trench electrode type gate structure formed on the main surface so as to be located within the drift region, and a second conductivity type well region formed along a bottom wall of the gate structure in a region below the gate structure within the drift region, the well region including a plurality of first well regions, the first well regions have a first bottom portion having a first depth, the plurality of first well regions are formed at a first interval in the depth direction of the gate structure, and adjacent first well regions face each other in the depth direction of the gate structure across a part of the drift region.

Description

[0001] Related applications

[0002] This application corresponds to Japanese Patent Application No. 2023-178289 filed with the Japan Patent Office on October 16, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor device. Background Technology

[0004] Patent Document 1 discloses a semiconductor device including a semiconductor substrate, a semiconductor region, a body region, a gate trench, a gate insulating film, a gate electrode, and a p-type diffusion region. The semiconductor region is formed on the upper surface side of the semiconductor substrate. The body region is formed on the upper surface side of the semiconductor substrate, adjacent to the semiconductor region.

[0005] A gate trench is formed on the upper surface of the semiconductor substrate and extends through the bulk region. A gate insulating film covers the walls of the gate trench. The gate electrode is embedded in the gate trench via the gate insulating film. A p-type diffusion region is formed within the semiconductor region along the bottom wall of the gate trench.

[0006] Existing technical documents

[0007] Patent documents

[0008] Patent Document 1: U.S. Patent Application Publication No. 2010 / 0224932 Summary of the Invention

[0009] One embodiment of this disclosure provides a semiconductor device capable of reducing resistance while suppressing a decrease in withstand voltage.

[0010] One embodiment of this disclosure provides a semiconductor device including: a chip having a main surface; a drift region of a first conductivity type formed on a surface portion of the main surface; a gate structure of a trench electrode type formed on the main surface located within the drift region; and a well region of a second conductivity type formed along the bottom wall of the gate structure in a region of the drift region below the gate structure. Furthermore, the well region includes a plurality of first well regions, each first well region having a first bottom having a first depth, the plurality of first well regions being formed at a first interval in the depth direction of the gate structure. Moreover, adjacent first well regions are opposed to each other in the depth direction of the gate structure, separated by a portion of the drift region. Attached Figure Description

[0011] Figure 1 This is a top view showing a semiconductor device according to the first embodiment of the present disclosure.

[0012] Figure 2 It is along Figure 1 The cross-sectional view along line II-II shown.

[0013] Figure 3 This is a top view showing an example of chip layout.

[0014] Figure 4 It is by Figure 3 Enlarged view of the area enclosed by the single-dash line IV.

[0015] Figure 5 It is along Figure 4 The cross-sectional view of the VV line shown.

[0016] Figure 6 It is along Figure 4 The sectional view of line VI-VI shown.

[0017] Figure 7 It is along Figure 4 The sectional view along line VII-VII shown.

[0018] Figure 8 It is by Figure 5 An enlarged view of the portion enclosed by the single-dotted line VIII.

[0019] Figure 9 It is by Figure 6 A magnified view of the area enclosed by the single-dotted dashed line IX.

[0020] Figure 10 This is a cross-sectional view of a semiconductor device in reference mode, and is related to... Figure 6 The corresponding diagram.

[0021] Figure 11 This is a cross-sectional view of a semiconductor device in reference mode, and is related to... Figure 7 The corresponding diagram.

[0022] Figure 12 This is a top view showing an example layout of the chip according to the second embodiment of this disclosure, and is related to... Figure 4 The corresponding diagram.

[0023] Figure 13 It is along Figure 12 The cross-sectional view of line XIII-XIII shown.

[0024] Figure 14 It is along Figure 12 The cross-sectional view of line XIV-XIV shown.

[0025] Figure 15 It is along Figure 12 The cross-sectional view of the XV-XV line shown.

[0026] Figure 16 It is along Figure 12 The cross-sectional view of the XVI-XVI line shown.

[0027] Figure 17 It is by Figure 15 An enlarged view of the portion enclosed by the dashed line XVII.

[0028] Figure 18 This is a cross-sectional view of the semiconductor device of the first modified example, which is... Figure 16 The corresponding diagram.

[0029] Figure 19 This is a cross-sectional view of the semiconductor device of the second variation, which is... Figure 9 The corresponding diagram.

[0030] Figure 20 This is a cross-sectional view of the semiconductor device of the third variation, which is... Figure 5 The corresponding diagram.

[0031] Figure 21 This is a cross-sectional view of the semiconductor device of the third variation, which is... Figure 6 The corresponding diagram.

[0032] Figure 22 This is a cross-sectional view of the semiconductor device in the fourth variation.

[0033] Figure 23 This is a cross-sectional view of the semiconductor device in the fourth variation.

[0034] Figure 24 This is a cross-sectional view of the semiconductor device in the fifth variation.

[0035] Figure 25 This is a cross-sectional view of the semiconductor device in the fifth variation.

[0036] Figure 26 This is a cross-sectional view of the semiconductor device of the sixth variation, which is related to... Figure 5 The corresponding diagram.

[0037] Figure 27 This is a cross-sectional view of the semiconductor device of the sixth variation, which is related to... Figure 6 The corresponding diagram. Detailed Implementation

[0038] The specific methods are explained in detail below with reference to the accompanying drawings. The drawings are schematic diagrams, not strict illustrations; the positions, scales, ratios, and angles of opposing elements may not be consistent. Corresponding structures in the drawings are labeled with the same reference symbols, and repeated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions preceding the omission or simplification shall apply.

[0039] When the term "substantially" is used in this specification, this term includes not only the numerical value (shape) that is equal to the numerical value (shape) of the comparison object, but also a numerical error (shape error) within a range of ±10% based on the numerical value (shape) of the comparison object. In the following description, terms such as "first," "second," and "third" are used, but these are notations assigned to the names of each structure to clarify the order of description, and are not intended to define the essence of the names of each structure.

[0040] In the following description, "p-type" or "n-type" is used to refer to the conductivity type of the semiconductor (impurity), but "n-type" can also be called the "first conductivity type" and "p-type" the "second conductivity type." Alternatively, "p-type" can be called the "first conductivity type" and "n-type" the "second conductivity type." "P-type" is a conductivity type derived from trivalent elements, and "n-type" is a conductivity type derived from pentavalent elements. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0041] Figure 1 This is a top view showing the semiconductor device 1 according to the first embodiment of the present disclosure. Figure 2 It is along Figure 1 The cross-sectional view along line II-II shown. Figure 3 This is a top view showing a layout example of chip 2.

[0042] Reference Figures 1 to 3 Semiconductor device 1 is a semiconductor switching device having an insulated-gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a vertical structure. Semiconductor device 1 is a SiC semiconductor device having a chip 2 including a SiC single crystal. Chip 2 can also be called a "SiC chip" or a "semiconductor chip".

[0043] In this embodiment, chip 2 is made of hexagonal SiC single crystal and formed into a cuboid shape. Hexagonal SiC single crystals have various polymorphs, including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, and 6H-SiC single crystal. In this embodiment, an example of chip 2 being made of 4H-SiC single crystal is shown, but chip 2 can also be made of other polymorphs.

[0044] Chip 2 has a first main surface (main surface) 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are quadrilaterals when viewed from the vertical direction Z (hereinafter referred to as "top view"). The vertical direction Z is also the thickness direction of chip 2 and the normal direction of the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 can also be squares or rectangles when viewed from the top.

[0045] The first main surface 3 and the second main surface 4 are preferably formed from the c-plane of a SiC single crystal. In this case, the first main surface 3 is preferably formed from the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed from the carbon surface ((000-1) surface) of the SiC single crystal.

[0046] The first side surface 5A and the second side surface 5B extend along the first main surface 3 in a first direction X and are opposite each other along the first main surface 3 in a second direction Y that intersects the first direction X. Specifically, the second direction Y is orthogonal to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and are opposite each other in the first direction X.

[0047] In this configuration, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X can be the a-axis direction of the SiC single crystal, and the second direction Y can be the m-axis direction of the SiC single crystal. Hereinafter, the direction extending along the first principal surface 3 is sometimes referred to as the "horizontal direction," and the surface along the first principal surface 3 is sometimes referred to as the "horizontal plane." The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, which is orthogonal to the vertical direction Z.

[0048] Chip 2 (first main surface 3 and second main surface 4) has a deviation angle that is tilted at a predetermined angle in a predetermined deviation direction relative to the c-plane of the SiC single crystal. The amount of the deviation angle by which the c-axis ((0001) axis) of the SiC single crystal is tilted from the vertical line toward the deviation direction. In addition, the amount of the deviation angle by which the c-plane of the SiC single crystal is tilted relative to the horizontal plane.

[0049] The deviation direction is preferably the a-axis direction (second direction Y) of the SiC single crystal. The deviation angle can be greater than 0° and less than 10°. The deviation angle can have a value belonging to at least one of the following ranges: greater than 0° and less than 1°, greater than 1° and less than 2.5°, greater than 2.5° and less than 5°, greater than 5° and less than 7.5°, and greater than 7.5° and less than 10°.

[0050] The deviation angle is preferably 5° or less. Particularly preferred is a deviation angle of 2° or more but less than 4.5°. The deviation angle is typically set in the range of 4° ± 0.1°. This specification does not exclude a deviation angle of 0° (where the first main surface 3 is the front face relative to surface c).

[0051] Semiconductor device 1 includes an n-type first semiconductor region 6 formed on the surface portion of the second main surface 4 of chip 2. A drain potential, serving as a first potential (high potential), is assigned to the first semiconductor region 6. The first semiconductor region 6 may also be referred to as a "semiconductor layer," "first semiconductor layer," "drain region," etc. The first semiconductor region 6 may also have a 1×10⁻⁶ ohm diameter. 14 cm -3 Above and 1×10 21 cm -3 The following are the concentrations of n-type impurities.

[0052] The first semiconductor region 6 is formed as a layer extending along the second main surface 4, exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D of the chip 2. In this embodiment, the first semiconductor region 6 is composed of an n-type semiconductor layer. Specifically, the first semiconductor region 6 is composed of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal), forming the second main surface 4 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2. The first semiconductor region 6 has the aforementioned offset direction and offset angle.

[0053] The first semiconductor region 6 may have a thickness of 10 μm or more and 500 μm or less. The thickness of the first semiconductor region 6 may have a value belonging to at least one of the following ranges: 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0054] Semiconductor device 1 includes an n-type second semiconductor region (drift region) 7 formed on the surface portion of the first main surface 3 of chip 2. The second semiconductor region 7 may also be referred to as a "semiconductor layer," "second semiconductor layer," or "drift region," etc. The second semiconductor region 7 has an n-type impurity concentration lower than that of the first semiconductor region 6. The n-type impurity concentration of the second semiconductor region 7 can be 1 × 10⁻⁶. 14 cm -3 Above and 1×10 18 cm -3 the following.

[0055] The second semiconductor region 7 is formed as a layer extending along the first main surface 3 and is electrically connected to the first semiconductor region 6. The second semiconductor region 7 is exposed from the second main surface 4 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2. In this embodiment, the second semiconductor region 7 is composed of an n-type semiconductor layer.

[0056] Specifically, the second semiconductor region 7 is composed of an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal), forming the first main surface 3 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2. The second semiconductor region 7 (epitaxy layer) has the aforementioned offset direction and offset angle. The second semiconductor region 7 preferably has a thickness less than that of the first semiconductor region 6. The thickness of the second semiconductor region 7 can be greater than that of the first semiconductor region 6. The thickness of the second semiconductor region 7 can be 5 μm or more and 50 μm or less.

[0057] Semiconductor device 1 includes a first facet 8, a second facet 9, and first to fourth connecting facest 10A to 10D formed on a first main surface 3. The first facet 8, the second facet 9, and the first to fourth connecting facest 10A to 10D are divided into mesa 11 on the first main surface 3. The first facet 8, the second facet 9, and the first to fourth connecting facest 10A to 10D (mesa 11) can also be regarded as constituent elements of chip 2 (first main surface 3).

[0058] The first face 8 can also be called the "active surface", the second face 9 can be called the "outer surface", the first to fourth connecting faces 10A to 10D can be called the "connecting surface", and the platform 11 can be called the "active mesa".

[0059] The first facet 8 is formed by spacing inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main facet 3. The first facet 8 has a flat surface extending in the horizontal direction, formed by the c-surface (Si-surface). In this embodiment, the first facet 8 is formed as a quadrilateral with four sides parallel to the first to fourth side surfaces 5A to 5D when viewed from above. The planar area of ​​the first facet 8 is preferably 50% or more and 90% or less of the planar area of ​​the first main facet 3.

[0060] The second facet 9 is located on the peripheral side of the first main surface 3 relative to the first facet 8, and is recessed from the height of the first facet 8 toward the thickness direction of the chip 2 (towards the second main surface 4). When viewed from above, the second facet 9 extends in a strip along the first facet 8, forming a ring (specifically a four-sided ring) surrounding the first facet 8. The second facet 9 is connected to the first to fourth side surfaces 5A to 5D.

[0061] The second facet 9 is formed substantially parallel to the first facet 8 and has a flat surface extending in the horizontal direction. In this embodiment, the second facet 9 is formed from a c-plane (Si plane). The second facet 9 is formed in the second semiconductor region 7 at a distance from the first semiconductor region 6. The second facet 9 is recessed to a depth less than the thickness of the second semiconductor region 7, thereby exposing the second semiconductor region 7.

[0062] The second face 9 has a depth of 0.1 μm or more and 3 μm or less. The depth of the second face 9 may have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the second face 9 is preferably 1.5 μm or more and 2.5 μm or less.

[0063] The first to fourth connecting faces 10A to 10D extend along the vertical direction Z and connect with the first face 8 and the second face 9. The first connecting face 10A is located on the first side 5A, the second connecting face 10B is located on the second side 5B, the third connecting face 10C is located on the third side 5C, and the fourth connecting face 10D is located on the fourth side 5D. The first connecting face 10A and the second connecting face 10B extend in the first direction X and are opposite each other in the second direction Y. The third connecting face 10C and the fourth connecting face 10D extend in the second direction Y and are opposite each other in the first direction X.

[0064] The first to fourth connecting faces 10A to 10D can also extend approximately perpendicularly between the first face 8 and the second face 9, dividing a prism-shaped platform 11. Alternatively, the first to fourth connecting faces 10A to 10D can slope downwards from the first face 8 toward the second face 9, dividing a frustum-shaped platform 11. The first to fourth connecting faces 10A to 10D can also be tilted relative to the first face 8 at an angle exceeding 90° and less than 135°.

[0065] Thus, the mesa 11 is divided into protrusions by the second semiconductor region 7 in the first main surface 3. The mesa 11 is formed only in the second semiconductor region 7, and not in the first semiconductor region 6.

[0066] Semiconductor device 1 includes an active region 12 disposed on chip 2. The active region 12 is a region that includes a device structure (transistor structure Tr) and generates output current (drain current). The active region 12 is disposed on the inner side of chip 2. Specifically, the active region 12 is disposed on the first surface 8.

[0067] Semiconductor device 1 includes an outer peripheral region 13 disposed in chip 2 outside the active region 12. The outer peripheral region 13 is a region excluding device structures (transistor structures Tr). The outer peripheral region 13 is disposed at the periphery of chip 2. Specifically, the outer peripheral region 13 is disposed on the second surface 9. The outer peripheral region 13, when viewed from above, is disposed in the region between the periphery of the first surface 8 and the periphery of the second surface 9.

[0068] The structure within the active region 12 is shown below. The semiconductor device 1 includes a plurality of trench-type (trench electrode type) gate structures 15 formed on the first main surface 3 (first surface 8). The gate structure 15 may also be referred to as a "trench gate structure", "trench configuration", etc. A gate potential, serving as a control potential, is assigned to the plurality of gate structures 15.

[0069] Reference Figure 2 and Figure 3 Multiple gate structures 15 are formed on the first facet 8 at intervals from the periphery (first to fourth connecting faces 10A to 10D) inwards. When viewed from above, the multiple gate structures 15 are arranged at intervals in the first direction X, each forming a strip extending in the second direction Y. When viewed from above, the multiple gate structures 15 are arranged as stripes extending along the second direction (depth direction) Y. The multiple gate structures 15 may also be arranged with intervals of 0.25 μm or more and 3 μm or less.

[0070] Multiple gate structures 15 are located within the second semiconductor region 7. The multiple gate structures 15 are formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3, and are opposed to the first semiconductor region 6 across a portion of the second semiconductor region 7. The multiple gate structures 15 are formed substantially perpendicular to the first main surface 3 (first surface 8).

[0071] Figure 4 It is by Figure 3 Enlarged view of the area enclosed by the single-dash line IV. Figure 5 It is along Figure 4 The cross-sectional view of the VV line shown. Figure 6 It is along Figure 4 The sectional view of line VI-VI shown. Figure 7 It is along Figure 4 The sectional view along line VII-VII shown. Figure 8 It is by Figure 5 An enlarged view of the portion enclosed by the single-dotted line VIII. Figure 9 It is by Figure 6 A magnified view of the area enclosed by the single-dotted line IX. Besides Figure 2 as well as Figure 3 In addition, refer to Figures 4 to 6 , Figure 8 as well as Figure 9The structure of the multiple gate structures 15 will be further described.

[0072] like Figure 8 as well as Figure 9 As shown, the plurality of gate structures 15, when viewed in cross section, each have a first sidewall 15a on one side of the first direction X (third sidewall 5C side), a second sidewall 15b on the other side of the first direction X (fourth sidewall 5D side), and a bottom wall 15c connecting the first sidewall 15a and the second sidewall 15b.

[0073] The first sidewall 15a and the second sidewall 15b are each formed from the a-plane ((11-20) plane) of a SiC single crystal. Alternatively, the first sidewall 15a and the second sidewall 15b can be formed from the m-plane ((1-100) plane) of a SiC single crystal, depending on the depth direction (second direction Y) of the gate structure 15. The first sidewall 15a and the second sidewall 15b are formed approximately perpendicular to the first main surface 3. The tilt angle (absolute value) of the first sidewall 15a (second sidewall 15b) relative to a vertical line can be 85° or more and 95° or less. The tilt angle of the first sidewall 15a (second sidewall 15b) is preferably 87° or more and 93° or less. The bottom wall 15c is formed from the c-plane (Si plane) of a SiC single crystal. The bottom wall 15c preferably extends approximately flat along the horizontal direction. Alternatively, the bottom wall 15c can be curved into an arc shape towards the second main surface 4.

[0074] The gate structure 15 may also have a width of 0.1 μm or more and 1.5 μm or less. The width of the gate structure 15 may have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, and 1.25 μm or more and 1.5 μm or less. Preferably, the width of the gate structure 15 is 0.25 μm or more and 0.75 μm or less.

[0075] The gate structure 15 may also have a depth of 0.1 μm or more and 3 μm or less. The depth of the gate structure 15 may have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the gate structure 15 is preferably 0.5 μm or more and 1.5 μm or less. The depth of the gate structure 15 is preferably approximately equal to the depth of the second facet 9.

[0076] Multiple gate structures 15 each include a trench 16, an insulating film 17, and a buried electrode 18. The trench 16 is formed on a first main surface 3 (first surface 8), dividing the walls of the gate structure 15 (first sidewall 15a, second sidewall 15b, and bottom wall 15c). The trench 16 extends along a second direction Y. The depth direction of the trench 16 is the second direction Y. The depth direction of the gate structure 15 is consistent with the depth direction of the trench 16, which is the second direction Y.

[0077] The insulating film 17 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 17 has a single-layer structure made of a silicon oxide film. The insulating film 17 is particularly preferably made of a silicon oxide film made of the oxide of the chip 2.

[0078] An insulating film 17 covers the walls of the trench 16 in a film-like manner. The insulating film 17 includes a first film portion, a second film portion, and a third film portion. The first film portion covers the first sidewall 15a in a film-like manner. The second film portion covers the second sidewall 15b in a film-like manner. The third film portion covers the bottom wall 15c in a film-like manner and is connected to the first and second film portions. The second film portion has a thickness approximately equal to that of the first film portion. The third film portion has a thickness greater than both the thickness of the first and second film portions. Alternatively, the thickness of the third film portion can also be approximately equal to the thickness of both the first and second film portions. The insulating film 17 can have a thickness of 10 nm or more and 150 nm or less.

[0079] The embedded electrode 18 may comprise one or both of p-type and n-type conductive polysilicon. The embedded electrode 18 is embedded in the trench 16 through an insulating film 17. The embedded electrode 18 has an electrode surface exposed from the trench 16. The height position of the electrode surface relative to the first main surface 3 is located on the bottom wall 15c side. The electrode surface has an internal groove that is tapered towards the bottom wall 15c side. Preferably, the bottom of the groove is located on the first main surface 3 side relative to the depth position of the middle portion of the trench 16.

[0080] Reference Figure 5 and Figure 6 The semiconductor device 1 includes a plurality of p-type main regions 20 formed on the surface portion of a first main surface 3 (first surface 8). A source potential, which is a second potential (low potential) different from a first potential (high potential), is assigned to the plurality of main regions 20. The main regions 20 may also be referred to as "channel regions," "base regions," etc. The plurality of main regions 20 may also have a 1×10⁻⁶ ohm² / 4 ... 17 cm -3 Above and 1×10 19 cm -3 The following are the concentrations of p-type impurities.

[0081] Multiple main regions 20 are formed along the regions of multiple gate structures 15. Specifically, the regions formed between the multiple gate structures 15 extend in a strip shape along the multiple gate structures 15.

[0082] The following is for reference Figure 6 as well as Figure 9 The structure of a main body region 20 will be described below. In this embodiment, the main body region 20 is formed in cross-section as a layer extending along the first direction X, and is connected to any one or both (both in this embodiment) of the plurality of adjacent gate structures 15. The main body region 20 is positioned opposite the buried electrodes 18 of the plurality of gate structures 15 through the insulating film 17 of the plurality of gate structures 15.

[0083] The main body region 20 is formed spaced apart from the depth position of the second face 9 toward the region of the first face 8. The main body region 20 is also formed spaced apart from the depth position of the bottom wall 15c of the gate structure 15 toward the first main face 3. The main body region 20 is located at a depth position relative to the middle portion of the gate structure 15, at the bottom wall 15c of the gate structure 15 (see reference). Figure 9 (The bottom of the side)

[0084] The bottom of the main body region 20 is located between the bottom wall 15c of the gate structure 15 and the middle portion of the gate structure 15. The distance between the bottom of the main body region 20 and the bottom wall 15c of the gate structure 15 is less than the thickness (depth) T of the main body region 20. B (Reference Figure 9 The bottom of the main body region 20 is located on the bottom wall 15c side of the gate structure 15 relative to the bottom of the groove where the buried electrode 18 is located. Of course, the bottom of the main body region 20 may also be located on the first main surface 3 relative to the depth of the middle part of the gate structure 15.

[0085] The main body region 20 can also have a thickness of 0.1 μm or more but less than 1 μm. The thickness T of the main body region 20... B (Reference Figure 9 The thickness T of the main body region 20 may also have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, and 0.8 μm or more and 1 μm or less. B (Reference Figure 9 The preferred size is 0.3μm or larger and 0.7μm or smaller.

[0086] Reference Figure 4 , Figure 6 as well as Figure 9The semiconductor device 1 includes multiple n-type source regions 21 formed on the side of the first main surface 3 relative to multiple main regions 20. The multiple source regions 21 have an n-type impurity concentration higher than that of the second semiconductor region 7. The n-type impurity concentration of the multiple source regions 21 can also be 1 × 10⁻⁶. 18 cm -3 Above and 1×10 21 cm -3 the following.

[0087] Multiple source regions 21 are formed on the surface of multiple body regions 20 in regions along multiple gate structures 15. Specifically, multiple source regions 21 are formed in regions between multiple gate structures 15 and extend in a strip shape along multiple gate structures 15.

[0088] The following is for reference Figure 6 as well as Figure 9 The structure of a source region 21 is described below. The source regions 21 are formed spaced apart from the bottom of the main body region 20 toward the first main surface 3. In this embodiment, the source regions 21 are formed in cross-section as a layer extending along the first direction X, and are connected to any one or both (both in this embodiment) of the adjacent plurality of gate structures 15. The source regions 21 are positioned opposite the buried electrodes 18 of the plurality of gate structures 15 across the insulating films 17 of the plurality of gate structures 15.

[0089] Source region 21 has a height position relative to the electrode surface of buried electrode 18 located at the bottom wall 15c of trench 16 (see reference). Figure 9 The bottom of the source electrode region 21 and the surface portion located at the height of the electrode surface relative to the embedded electrode 18 on the first main surface 3 side. The source electrode region 21 has a portion (bottom) that faces the embedded electrode 18 through the insulating film 17 and a portion (surface portion) that does not face the embedded electrode 18 through the insulating film 17.

[0090] The bottom of the source region 21 may be located on the side of the first main surface 3, relative to the depth of the bottom of the groove where the electrode 18 is embedded. Of course, the bottom of the source region 21 may also be located on the bottom side of the main body region 20, relative to the depth of the bottom of the groove.

[0091] Semiconductor device 1 includes a plurality of p-type well regions 22 formed within chip 2 (second semiconductor region 7). The plurality of well regions 22 have a higher p-type impurity concentration than the p-type impurity concentration of the main body region 20. Of course, the p-type impurity concentration of the plurality of well regions 22 can be the same as or lower than the p-type impurity concentration of the main body region 20. The p-type impurity concentration of the plurality of well regions 22 can be 1 × 10⁻⁶. 16 cm -3 Above and 1×1020 cm -3 The following. Multiple well regions 22 can also be referred to as "electric field mitigation layers".

[0092] Multiple well regions 22 are formed at intervals along the bottom wall 15c of multiple gate structures 15 in the chip 2 (second semiconductor region 7) in a first direction X. In this embodiment, the multiple well regions 22 are formed in a one-to-one correspondence with the multiple gate structures 15.

[0093] Multiple well regions 22 are each formed as strips extending along their respective gate structures 15 when viewed from above, and are positioned opposite their respective buried electrodes 18 separated by their respective insulating films 17. Alternatively, the multiple well regions 22 can be formed in a one-to-many correspondence with respect to a single gate structure 15. In this case, the multiple well regions 22 are formed spaced apart in the second direction Y.

[0094] The following is for reference Figure 5 , Figure 6 The structure of a well region 22 is described below. The well region 22 is formed to be wider than the gate structure 15 when viewed from above. The well region 22 is formed to be columnar in cross-section, extending along the thickness direction (vertical direction Z) of the second semiconductor region 7.

[0095] The well region 22 may also have a depth that extends through the middle portion between the bottom of the second semiconductor region 7 and the bottom wall 15c of the gate structure 15. The well region 22 may also be formed at intervals from the middle portion between the bottom of the second semiconductor region 7 and the bottom wall 15c of the gate structure 15 toward the first main surface 3.

[0096] The well region 22 is formed spaced apart from the bottom of the second semiconductor region 7 toward the first surface region 8, and is opposed to the first semiconductor region 6 across a portion of the second semiconductor region 7. Alternatively, the well region 22 may have a bottom that extends across the bottom of the second semiconductor region 7 and is located within the first semiconductor region 6. The well region 22 and the second semiconductor region 7 form a pn junction.

[0097] In this embodiment, the trap region 22 has a thickness (depth) T greater than that of the main body region 20. B (Reference Figure 9 The thickness (depth) of the well region 22 is the thickness in the vertical direction Z of the well region 22, with reference to the bottom wall 15c of the gate structure 15. In this embodiment, the thickness of the well region 22 is greater than the depth of the gate structure 15. Of course, the thickness of the well region 22 can also be less than the depth of the gate structure 15. In this case, the thickness of the well region 22 can also be less than the thickness T of the main body region 20. B (Reference Figure 9 ).

[0098] The well region 22 has an upper end portion along the corner of the bottom wall 15c of the gate structure 15. The well region 22 has a first extension 22a on the side of the first sidewall 15a and a second extension 22b on the side of the second sidewall 15b at the upper end portion (see reference). Figure 9 ).

[0099] The first extension 22a extends from the region directly below the gate structure 15 toward the lower end of the first sidewall 15a. The first extension 22a is formed at intervals from the bottom of the main body region 20 toward the bottom wall 15c of the gate structure 15. In this embodiment, the first extension 22a is positioned horizontally opposite the buried electrode 18 across the insulating film 17.

[0100] Of course, the first extension 22a may also be formed at a depth relative to the lower end of the buried electrode 18 on the bottom wall 15c side of the trench 16, and is only opposite to the insulating film 17 (third film portion) in the horizontal direction. The first extension 22a is formed into a pointed shape facing the first main surface 3 (bottom side of the main body region 20) when viewed in cross section.

[0101] The second extension 22b extends from the region directly below the gate structure 15 toward the lower end of the second sidewall 15b, and is opposed to the first extension 22a across the gate structure 15. The second extension 22b is formed at intervals from the bottom of the main body region 20 toward the bottom wall 15c of the gate structure 15. In this embodiment, the second extension 22b is opposed to the buried electrode 18 in the horizontal direction across the insulating film 17.

[0102] Of course, the second extension 22b may also be formed at a depth relative to the lower end of the buried electrode 18 on the bottom wall 15c side of the trench 16, and is only opposite to the insulating film 17 (third film portion) in the horizontal direction. The second extension 22b is formed into a pointed shape facing the first main surface 3 (bottom side of the main body region 20) in cross-section.

[0103] The trap region 22 has one or more (in this embodiment, multiple) first bulges 22c (refer to...) Figure 8 ).exist Figure 8 The diagram illustrates a well region 22 having four first protrusions 22c. The number of first protrusions 22c is appropriately adjusted by adjusting process conditions. Each of the multiple first protrusions 22c is formed from a portion of the well region 22 whose width in the horizontal direction (first direction X) gradually increases and decreases in the thickness direction, and is formed in multiple stages from the bottom wall 15c of the gate structure 15 toward the bottom of the second semiconductor region 7.

[0104] Multiple first bulges 22c extend in an arc shape (circular arc) from the region directly below the gate structure 15 toward both sides of the gate structure 15. In the case where the well region 22 has a single first bulge 22c, the single first bulge 22c may also be formed to extend in an arc shape (circular arc) toward both sides of the gate structure 15 from the middle of the well region 22.

[0105] Semiconductor device 1 includes a plurality of high-concentration p-type well regions 23 respectively formed within a plurality of well regions 22. The plurality of high-concentration well regions 23 are regions that increase the p-type impurity concentration of the well regions 22, and have a higher p-type impurity concentration than the p-type impurity concentration of the well regions 22. In this embodiment, the high-concentration well regions 23 are considered as part of the well regions 22. In this case, the high-concentration well regions 23 are considered as high-concentration portions of the well regions 22. The p-type impurity concentration of the plurality of high-concentration well regions 23 may also be 1 × 10⁻⁶. 18 cm -3 Above and 1×10 20 cm -3 The following. Multiple high-concentration trap regions 23 can also be referred to as "high-concentration electric field mitigation layers".

[0106] Multiple high-concentration trap regions 23 are formed in a one-to-one correspondence with multiple trap regions 22. The multiple high-concentration trap regions 23 are formed in regions along the bottom wall 15c of the corresponding gate structure 15. The multiple high-concentration trap regions 23 are formed as strips extending along the corresponding gate structure 15 (trap region 22) when viewed from above, and are opposed to the corresponding buried electrode 18 through the corresponding insulating film 17.

[0107] The following is for reference Figure 5 , Figure 6 The structure of a high-concentration trap region 23 is described below. The high-concentration trap region 23 is formed spaced apart from the bottom of the trap region 22 toward the bottom wall 15c side of the gate structure 15. Preferably, the high-concentration trap region 23 has a bottom 23a located at a depth relative to the middle portion of the trap region 22 on the bottom wall 15c side of the gate structure 15 (see reference). Figure 8 and Figure 9 ).

[0108] The bottom 23a of the high-concentration trap region 23 is a concentration transition section where the concentration of p-type impurities gradually decreases towards the bottom side of the trap region 22. Of course, the bottom 23a of the high-concentration trap region 23 can also be located at the bottom side of the trap region 22 at a depth relative to the middle part of the trap region 22.

[0109] The high-concentration trap region 23 is formed to be narrower than the trap region 22. In this embodiment, the high-concentration trap region 23 is formed to be narrower than the gate structure 15. Of course, the high-concentration trap region 23 may also be formed to be wider than the gate structure 15, extending laterally from both sides of the gate structure 15.

[0110] The high-concentration trap region 23 has a thickness (depth) T that is less than the depth of the gate structure 15. H (Reference Figure 8 and Figure 9 The thickness T of the high-concentration trap region 23 H The thickness of the high-concentration well region 23 in the vertical direction Z is based on the bottom wall 15c of the gate structure 15. The thickness of the high-concentration well region 23 is less than the thickness of the main body region 20. Of course, the thickness of the high-concentration well region 23 can be greater than the thickness of the main body region 20 or greater than the depth of the gate structure 15.

[0111] The semiconductor device 1 includes multiple high-concentration n-type regions 24 formed below multiple main regions 20 within the chip 2 (second semiconductor region 7). The multiple high-concentration regions 24 are regions that increase the n-type impurity concentration of the second semiconductor region 7, and have a higher n-type impurity concentration than the n-type impurity concentration of the second semiconductor region 7. The multiple high-concentration regions 24 can also be considered as high-concentration portions of the second semiconductor region 7.

[0112] The concentration of n-type impurities in multiple high-concentration regions 24 can also be 1×10. 16 cm -3 Above and 1×10 19 cm -3 For example, by comparing the n-type impurity concentration with that at the bottom side of the second semiconductor region 7, the n-type impurity concentration of multiple high-concentration regions 24 can be appropriately compared.

[0113] Multiple high-concentration regions 24 are formed below multiple main regions 20, respectively, along the regions of multiple gate structures 15. Specifically, the multiple high-concentration regions 24 are formed in the region between the multiple gate structures 15, respectively, within the thickness range between the bottom wall 15c of the multiple gate structures 15 and the bottom of the multiple main regions 20. The multiple high-concentration regions 24 extend in a strip shape along the multiple gate structures 15 when viewed from above.

[0114] The following is for reference Figure 5 as well as Figure 6The structure of a high-concentration region 24 will be described below. In this embodiment, the high-concentration region 24 is formed as a layer extending along the first direction X in cross-section, and is connected to any one or both (both in this embodiment) of the plurality of adjacent gate structures 15. The high-concentration region 24 is opposite to the buried electrodes 18 of the plurality of gate structures 15 through the insulating film 17 of the plurality of gate structures 15.

[0115] The high-concentration region 24 is positioned opposite the source region 21 in the thickness direction, separated by a portion of the main body region 20. In this embodiment, the high-concentration region 24 is positioned opposite the source region 21 in a one-to-one correspondence in the thickness direction. The high-concentration region 24 is formed spaced apart from the bottom of the second semiconductor region 7 toward the first main surface 3, and is positioned opposite the first semiconductor region 6 separated by a portion of the second semiconductor region 7.

[0116] Multiple high-concentration regions 24 may have approximately equal n-type impurity concentrations or different n-type impurity concentrations.

[0117] Semiconductor device 1 includes multiple medium-concentration n-type regions (drift regions) 25 formed within chip 2 (second semiconductor region 7) below multiple high-concentration regions 24. The multiple medium-concentration regions 25 are regions that increase the n-type impurity concentration of the second semiconductor region 7, having an n-type impurity concentration higher than that of the second semiconductor region 7 but lower than that of the high-concentration regions 24. The multiple medium-concentration regions 25 can also be considered as high-concentration portions of the second semiconductor region 7.

[0118] The concentration of n-type impurities in multiple medium-concentration regions 25 can also be 1×10. 15 cm -3 Above and 1×10 17 cm -3 For example, by comparing the n-type impurity concentration with that at the bottom side of the second semiconductor region 7, the n-type impurity concentration of multiple medium-concentration regions 25 can be appropriately compared. The medium-concentration regions 25 can also be referred to as "medium-concentration drift regions".

[0119] Multiple medium-concentration regions 25 are formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom of the multiple high-concentration regions 24 in the region between the multiple gate structures 15. Each of the multiple medium-concentration regions 25 has a portion of the region between the multiple well regions 22. In this embodiment, each of the multiple medium-concentration regions 25 has a portion of the region between the regions of the multiple gate structures 15.

[0120] Multiple medium-concentration regions 25 extend in a strip-like shape along multiple gate structures 15 when viewed from above. In this embodiment, with respect to two adjacent well regions 22, the multiple medium-concentration regions 25 are connected to one or both (both in this embodiment) of the well region 22.

[0121] The following is for reference Figure 5 as well as Figure 6 The structure of a medium concentration region 25 will be described. The medium concentration region 25 is formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3, and is opposite to the first semiconductor region 6 across a portion of the second semiconductor region 7.

[0122] The medium-concentration region 25 has an upper end located above the bottom wall 15c of the gate structure 15 at a depth position above it. The upper end of the medium-concentration region 25 is located in the region between the plurality of gate structures 15, and is opposite to the gate structure 15 across the upper end of the well region 22 (the first extension 22a and the second extension 22b). The upper end of the medium-concentration region 25 may also have a portion connected to the gate structure 15.

[0123] The medium concentration region 25 has a depth position located below the bottom of the bottom wall 15c of the gate structure 15. Specifically, the bottom of the medium concentration region 25 is formed at intervals from the bottom of the well region 22 toward the first main surface 3. Preferably, the bottom of the medium concentration region 25 is located closer to the bottom side of the well region 22 than the bottom of the high concentration well region 23.

[0124] Semiconductor device 1 includes multiple channel regions 26 (see reference) formed within multiple body regions 20 between multiple source regions 21 and multiple high-concentration regions 24. Figure 9 The inversion and non-inversion of the multiple channel regions 26 are controlled by the gate structure 15. The multiple channel regions 26 form current paths connecting the multiple source regions 21 and the multiple high-concentration regions 24 along the sidewalls (first sidewall 15a and second sidewall 15b) of the multiple gate structures 15 within the multiple main regions 20.

[0125] Reference Figure 4 , Figure 5 as well as Figure 8 The semiconductor device 1 includes a plurality of p-type first contact regions 27 formed in the surface portion of a first main surface 3 (first surface 8) along regions of a plurality of gate structures 15. The plurality of first contact regions 27 have a p-type impurity concentration higher than that of the plurality of main body regions 20. The p-type impurity concentration of the plurality of first contact regions 27 is higher than that of the plurality of well regions 22. The p-type impurity concentration of the plurality of first contact regions 27 can be 1 × 10⁻⁶. 17 cm -3 Above and 1×1019 cm -3 the following.

[0126] Multiple first contact regions 27 are formed in the regions between multiple gate structures 15. Multiple first contact regions 27 are formed on both sides of multiple gate structures 15. The multiple first contact regions 27 are arranged at intervals along the multiple gate structures 15 in the second direction Y, and are respectively formed as strips extending in the second direction Y. The multiple first contact regions 27 overlap with multiple main regions 20, thereby increasing the p-type impurity concentration of the multiple main regions 20.

[0127] Regarding the first contact regions 27 located on one side and the other side of a gate structure 15, the first contact region 27 of the other side is opposite to the first contact region 27 of the first side across the gate structure 15. The plurality of first contact regions 27 are arranged in a matrix as a whole when viewed from above.

[0128] In the second direction Y, the length and spacing of the plurality of first contact regions 27 are appropriately adjusted according to the desired channel area. The channel area is equivalent to the total area of ​​the plurality of source regions 21. The length of the first contact regions 27 in the second direction Y can also be larger than the width of the gate structure 15 in the first direction X. Of course, the length of the first contact regions 27 can also be smaller than the width of the gate structure 15. The length ratio of the first contact regions 27 to the width of the gate structure 15 can be 0.5 or more and 10 or less. The length ratio of the spacing of the first contact regions 27 to the length of the first contact regions 27 can be 1 or more and 50 or less.

[0129] The following is for reference Figure 5 and Figure 8 The structure of a first contact region 27 will be described below. The first contact region 27 is formed as a layer extending horizontally along the first main surface 3, and is connected to any one or both (both in this embodiment) of the plurality of adjacent gate structures 15. The first contact region 27 is opposite to the buried electrodes 18 of the plurality of gate structures 15 through the insulating film 17 of the plurality of gate structures 15.

[0130] The first contact region 27 has a thickness greater than that of the source region 21, and has a bottom located on the bottom side of the second semiconductor region 7, relative to the bottom of the source region 21. The bottom of the first contact region 27 is located on the bottom side of the main body region 20 at a depth relative to the bottom of the groove of the buried electrode 18.

[0131] In this embodiment, the first contact area 27 has a thickness T greater than that of the main body area 20. B (Reference Figure 9The thickness is large. It has a bottom that is located on the bottom side of the second semiconductor region 7, which is closer to the bottom of the main body region 20. The bottom of the first contact region 27 is a concentration transition section where the p-type impurity concentration gradually decreases towards the bottom side of the second semiconductor region 7.

[0132] The bottom of the first contact area 27 can also be located at the bottom wall 15c of the gate structure 15 (see reference). Figure 8 The depth of the first contact area 27 is located near the first main surface 3. In this case, the first contact area 27 may also have a thickness less than that of the main body area 20, and a bottom located near the first main surface 3 than the bottom of the main body area 20. The first contact area 27 may also be positioned opposite the high concentration area 24, separated by a portion of the main body area 20.

[0133] In this embodiment, the bottom of the first contact region 27 is located at the bottom wall 15c of the gate structure 15 (see reference). Figure 8 The depth of the first contact region 27 is located near the bottom side of the second semiconductor region 7. In this embodiment, the first contact region 27 overlaps with part or all of the high-concentration region 24 in cross-section. The first contact region 27 replaces part or all of the n-type impurity concentration of the high-concentration region 24 with a p-type impurity concentration. Therefore, the p-type impurity concentration at the bottom of the first contact region 27 reduces the amount of n-type impurity concentration in the high-concentration region 24.

[0134] In this embodiment, the first contact region 27 has a bottom that extends across the bottom of the high-concentration region 24 and is located within the medium-concentration region 25. Therefore, the first contact region 27 replaces a portion of the n-type impurity concentration in the medium-concentration region 25 with a p-type impurity concentration. Preferably, the bottom of the first contact region 27 is located at a depth position in the middle of the specific well region 22, near the first main surface 3.

[0135] The bottom of the first contact region 27, at a depth greater than the bottom wall 15c of the gate structure 15, overlaps with the upper end of the well region 22. Thus, the first contact region 27 electrically connects the well region 22 to the main body region 20.

[0136] Reference Figure 8 In this embodiment, the first contact region 27 has a high-concentration portion 27a on the side of the first main surface 3 and a low-concentration portion 27b on the bottom side of the second semiconductor region 7. The high-concentration portion 27a is formed at least at a depth greater than the bottom wall 15c of the gate structure 15 on the side of the first main surface 3, forming the body portion of the first contact region 27. The high-concentration portion 27a extends in layers along the first main surface 3 in the horizontal direction.

[0137] The low-concentration portion 27b is formed on the bottom side of the second semiconductor region 7 relative to the high-concentration portion 27a, forming the bottom of the first contact region 27. The low-concentration portion 27b is also the portion where the p-type impurity concentration is reduced due to the n-type impurity concentration of the high-concentration region 24. The low-concentration portion 27b has a thickness less than that of the high-concentration portion 27a and extends in a layered manner in the horizontal direction along the high-concentration portion 27a.

[0138] The low-concentration portion 27b extends transversely through the depth of the bottom wall 15c of the gate structure 15 in the thickness direction. The low-concentration portion 27b has a portion located closer to the first main surface 3 than the depth of the bottom wall 15c of the gate structure 15, and a portion located closer to the bottom of the second semiconductor region 7 than the depth of the bottom wall 15c of the gate structure 15. The low-concentration portion 27b overlaps with the upper ends of the plurality of well regions 22 and is electrically connected to the plurality of well regions 22.

[0139] Reference Figure 7 The gate structure 15 includes a first portion 15P sandwiched by a first contact region 27 in a first direction X when viewed from above, and a second portion 15Q sandwiched by a source region 21 in the first direction X when viewed from above. The first portion 15P and the second portion 15Q are alternately formed in the second direction Y. Adjacent first portions 15P and second portions 15Q are connected to each other.

[0140] In the first part 15P of the gate structure 15, as Figure 8 As shown, no channel region is formed on the sidewalls (first sidewall 15a and second sidewall 15b) of the gate structure 15. In contrast, in the second portion 15Q of the gate structure 15, as... Figure 9 As shown, a channel region 26 is formed on the sidewalls (first sidewall 15a and second sidewall 15b) of the gate structure 15. The first portion 15P of the gate structure 15 is the portion where the channel region 26 is not formed, and the second portion 15Q of the gate structure 15 is the portion where the channel region 26 is formed.

[0141] Reference Figure 7 and Figure 8 In the medium concentration region 25 and the second semiconductor region 7, a first lower region (non-channel lower region) 61 is formed below the first portion 15P of the gate structure 15 (the portion where the channel region 26 is not formed). In this embodiment, a second contact region 28 is formed in the first lower region 61. A well region 22 is formed in the first lower region 61.

[0142] Reference Figure 7 as well as Figure 9In the medium concentration region 25 and the second semiconductor region 7, a second lower region (under-channel region) 62 is formed below the second portion 15Q of the gate structure 15 (the portion forming the channel region 26). In this embodiment, the second contact region 28 is not formed in the second lower region 62. The depth of the well region 22 of the second lower region 62 is shallower than the depth of the well region 22 of the first lower region 61.

[0143] Reference Figures 7 to 9 The well region 22 includes a first well region 51 and a second well region 53 with different bottom depths. The first well region 51 and the second well region 53 are alternately formed in the second direction Y. The first well region 51 and the second well region 53 adjacent to each other in the second direction Y are connected to each other.

[0144] The first well region 51 has a first bottom 52. The first bottom 52 penetrates the medium concentration region 25 and is located in the second semiconductor region 7. The first bottom 52 is located below the bottom 23a of the high concentration well region 23. The first bottom 52 is located below the bottom 28d of the second contact region 28.

[0145] The first bottom 52 has a first depth D1 (refer to...) Figure 8 The first depth D1 is the depth of the first bottom 52 of the first well region 51, referenced to the bottom wall 15c of the gate structure 15. (Refer to...) Figure 8 The thickness T of the main area is 20. B (Reference Figure 9 (D1>T) B ).

[0146] Reference Figure 7 as well as Figure 8 The first well region 51 is formed in the first lower region 61 below the second portion 15Q of the gate structure 15. Specifically, the first well region 51 is formed in the entire region of the first lower region 61 in the second direction Y. In this embodiment, the second well region 53 is not formed in the first lower region 61.

[0147] Reference Figure 7 The first well region 51 is formed by spacing a first interval W1 between adjacent first well regions 51. The first interval W1 may also be the same length as the second direction Y of the first contact region 27. The first interval W1 may also be larger than the width of the gate structure 15 in the first direction X. Of course, the first interval W1 may also be such that the length of the first contact region 27 is smaller than the width of the gate structure 15. The length ratio of the first interval W1 of the gate structure 15 to the width in the first direction X may be greater than 0.5 and less than 10.

[0148] Reference Figure 8The first well region 51 has one or more (in this embodiment, multiple) first bulges 22c. Figure 8 In the example, the first well region 51 does not have the first extension 22a (see reference). Figure 9 ) and the second extension 22b (refer to Figure 9 Of course, the first well region 51 may also have a first extension 22a and a second extension 22b.

[0149] Reference Figure 7 and Figure 9 The second well region 53 has a second bottom 54. The second well region 53 has a second depth D2 (refer to...). Figure 9 The second bottom 54 is located in the medium concentration region 25. The second bottom 54 is located below the bottom 23a of the high concentration trap region 23. Second depth D2 (refer to...) Figure 9 Thickness T less than 20 mm in the main area B (Reference Figure 9 (D2<T) B Of course, the second depth D2 can also be the thickness T of the main region 20. B Above (D2≥T B ).

[0150] The second bottom 54 of the second well region 53 is located on the side of the first main surface 3 relative to the bottom 28d of the second contact region 28. The second bottom 54 of the second well region 53 is located on the side of the first main surface 3 relative to the depth of the middle part of the medium concentration region 25. Of course, the second bottom 54 of the second well region 53 may also be located on the side of the second main surface 4 relative to the depth of the middle part of the medium concentration region 25.

[0151] The second bottom 54 of the second well region 53 is located closer to the second main surface 4 than the bottom 23a of the high-concentration well region 23. The bottom 23a of the high-concentration well region 23 is located closer to the bottom wall 15c of the gate structure 15 than the second bottom 54 of the second well region 53. The second spacing W2 in the thickness direction between the second bottom 54 of the second well region 53 and the bottom 23a of the high-concentration well region 23 is greater than the thickness T of the high-concentration well region 23. H Small. Of course, the second interval W2 can also be the thickness T of the high-concentration trap region 23. H above.

[0152] Reference Figure 7 as well as Figure 9 The second well region 53 is formed in the second lower region 62 below the second portion 15Q of the gate structure 15. Specifically, the second well region 53 is formed in the entire region of the second direction Y in the second lower region 62. The first well region 51 is not formed in the second lower region 62.

[0153] Reference Figure 7 The medium-concentration region 25 and the second semiconductor region 7 include a clamped portion (a portion) 7a sandwiched between adjacent first well regions 51 in the second direction Y. The adjacent first well regions 51 in the second direction Y are opposed to each other across the clamped portion 7a in the second direction Y. Multiple clamped portions 7a are formed at intervals in the second direction Y. The length of the clamped portion 7a in the second direction Y coincides with the first interval W1 of the adjacent first well regions 51. The clamped portion 7a has a flat upper surface.

[0154] Semiconductor device 1 includes a plurality of p-type second contact regions 28 formed within chip 2 along regions of the bottom walls 15c of a plurality of gate structures 15. The plurality of second contact regions 28 have a p-type impurity concentration higher than that of the plurality of body regions 20. The p-type impurity concentration of the plurality of second contact regions 28 is higher than that of the plurality of well regions 22. In this embodiment, the second contact regions 28 are included in the first well region 51 but not in the second well region 53.

[0155] The concentration of p-type impurities in multiple second contact regions 28 can be 1×10⁻⁶. 18 cm -3 Above and 1×10 20 cm -3 Hereinafter, it is preferred that the p-type impurity concentration of the plurality of second contact regions 28 is approximately equal to the p-type impurity concentration of the plurality of first contact regions 27.

[0156] Multiple second contact regions 28 are formed in a one-to-many correspondence with respect to the bottom walls 15c of multiple gate structures 15. Each of the multiple second contact regions 28 is located between multiple adjacent first contact regions 27 in the first direction X when viewed from above. The multiple second contact regions 28 and the multiple first contact regions 27 are located on the same straight line in the first direction X.

[0157] Multiple second contact regions 28 are formed as strips extending along the corresponding gate structure 15 when viewed from above, and are opposed to the buried electrode 18 through an insulating film 17. In the second direction Y, the lengths of the multiple second contact regions 28 are approximately equal to the lengths of the multiple first contact regions 27. In the second direction Y, the spacing between the multiple second contact regions 28 is approximately equal to the spacing between the multiple first contact regions 27.

[0158] The following is for reference Figure 5 and Figure 8The structure of a second contact region 28 will be described below. The second contact region 28 is formed within a corresponding trap region 22 (first trap region 51). The second contact region 28 overlaps with the high-concentration trap region 23 and is electrically connected to the high-concentration trap region 23 within the trap region 22. The second contact regions 28 are formed at intervals from the periphery of the trap region 22 inwards. The second contact region 28 has a bottom 28d.

[0159] Reference Figure 8 The second contact region 28 is formed at intervals from the bottom of the well region 22 toward the bottom wall 15c of the gate structure 15, and is opposite to the bottom of the second semiconductor region 7 across a portion of the well region 22. In cross-section, the second contact regions 28 are formed as columnar shapes extending along the thickness direction (vertical direction Z) of the second semiconductor region 7.

[0160] In this embodiment, the second contact region 28 has a bottom located at the thickness position of the middle portion of the well region 22 near the bottom side of the well region 22. Of course, the bottom of the second contact region 28 may also be located at the thickness position of the middle portion of the well region 22 near the bottom wall 15c of the gate structure 15.

[0161] The second contact region 28 has an upper end portion along the corner of the bottom wall 15c of the gate structure 15. The second contact region 28 is electrically connected at its upper end to a plurality of first contact regions 27. The second contact region 28 electrically connects the trap region 22 and the high-concentration trap region 23 to the body region 20 via the plurality of first contact regions 27.

[0162] The second contact region 28 has a first extension 28a on the side of the first sidewall 15a and a second extension 28b on the side of the second sidewall 15b. The first extension 28a extends from the region directly below the gate structure 15 toward the lower end of the first sidewall 15a. The first extension 28a is horizontally opposed to the buried electrode 18 across the insulating film 17. The first extension 28a is connected to the first contact region 27 along the region of the first sidewall 15a. Specifically, the first extension 28a is connected to both the high-concentration portion 27a and the low-concentration portion 27b of the first contact region 27.

[0163] The second extension 28b extends from the region directly below the gate structure 15 toward the lower end of the second sidewall 15b, and is opposed to the first extension 28a across the gate structure 15. The second extension 28b is opposed to the buried electrode 18 in the horizontal direction across the insulating film 17. The second extension 28b is connected to the first contact region 27 along the region of the second sidewall 15b. Specifically, the second extension 28b is connected to both the high-concentration portion 27a and the low-concentration portion 27b of the first contact region 27.

[0164] The second contact area 28 has one or more (in this embodiment, multiple) second bulges 28c. Figure 8 The diagram illustrates a second contact region 28 having two second protrusions 28c. The number of second protrusions 28c is appropriately adjusted by adjusting process conditions. Multiple second protrusions 28c are formed from portions of the second contact region 28 whose width in the horizontal direction (first direction X) gradually increases and decreases in the thickness direction, and are formed in multiple stages from the bottom wall 15c of the gate structure 15 toward the bottom of the second semiconductor region 7.

[0165] Reference Figure 2 The semiconductor device 1 includes a main surface insulating film 30 covering a first main surface 3. The main surface insulating film 30 selectively covers a first facet 8, a second facet 9, and first to fourth connecting facets 10A to 10D. The main surface insulating film 30 is connected to the insulating film 17 of a plurality of gate structures 15 on the first facet 8, exposing the buried electrodes 18 of the plurality of gate structures 15.

[0166] The main insulating film 30 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the main insulating film 30 has a single-layer structure composed of a silicon oxide film. The main insulating film 30 is particularly preferably composed of a silicon oxide film composed of the oxide of the chip 2.

[0167] Reference Figure 2 The semiconductor device 1 includes an insulating interlayer film 31 covering the main insulating film 30. The interlayer film 31 may also be referred to as an "insulating film," "interlayer insulating film," or "intermediate insulating film," etc. The interlayer film 31 selectively covers the first facet 8, the second facet 9, and the first to fourth connecting facets 10A to 10D, sandwiching the main insulating film 30. The interlayer film 31 covers a plurality of gate structures 15 on the first facet 8.

[0168] In this embodiment, the interlayer film 31 is connected to the first to fourth side surfaces 5A to 5D at the peripheral portion of the second surface surface 9. Alternatively, the interlayer film 31 may be formed at intervals from the peripheral portion of the second surface surface 9 inwards, exposing the second semiconductor region 7 at the peripheral portion of the second surface surface 9. The interlayer film 31 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Preferably, the interlayer film 31 includes a silicon oxide film.

[0169] The interlayer membrane 31 may have a thickness of 0.5 μm or more and 3 μm or less. The thickness of the interlayer membrane 31 may have a value belonging to at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0170] Reference Figure 5The semiconductor device 1 includes a plurality of source openings 32 formed on an interlayer film 31. The plurality of source openings 32 are respectively formed in regions between a plurality of gate structures 15, exposing a plurality of source regions 21 and a plurality of first contact regions 27. The plurality of source openings 32 extend in a strip shape along the plurality of gate structures 15 in a second direction Y.

[0171] Preferably, the multiple source openings 32 each have an opening end that is bent into an arc shape. In the region between adjacent gate structures 15, the multiple source openings 32 may also be formed with a gap in the second direction Y. In this case, the multiple source openings 32 may also be formed as quadrilaterals, rectangles (strips), circles, etc. when viewed from above.

[0172] Reference Figure 3 The semiconductor device 1 includes a plurality of gate openings 33 formed on an interlayer film 31. In this embodiment, the plurality of gate openings 33 selectively expose both ends of a corresponding gate structure 15. Specifically, the plurality of gate openings 33 expose both ends of the buried electrode 18 of the corresponding gate structure 15. Similar to the source openings 32, the plurality of gate openings 33 preferably have opening ends that are bent into an arc shape. The plurality of gate openings 33 may also be formed as quadrilaterals, rectangles (strips), circles, etc. when viewed from above.

[0173] Reference Figure 1 , Figure 2 , Figure 5 The semiconductor device 1 includes a source electrode 35 disposed on a first main surface 3. The source electrode 35 is a terminal electrode to which a source potential is applied from the outside. The source electrode 35 is disposed on a portion of the interlayer film 31 covering the first surface 8.

[0174] In this embodiment, the source electrode 35 has a first pad portion 35a, a second pad portion 35b, and a third pad portion 35c. The first pad portion 35a has a relatively large planar area and forms the main body of the source electrode 35. In this embodiment, the first pad portion 35a is formed into a polygonal shape (quadrilateral in this embodiment) with four sides parallel to the periphery of the chip 2 when viewed from above, and is offset towards the fourth side surface 5D relative to the center of the first face portion 8.

[0175] The second pad portion 35b has a planar area smaller than that of the first pad portion 35a, and extends in a strip (quadrilateral) shape from one end of the first pad portion 35a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C. The third pad portion 35c has a planar area smaller than that of the first pad portion 35a, and extends in a strip (quadrilateral) shape from the other end of the first pad portion 35a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and is opposite to the second pad portion 35b in the second direction Y.

[0176] The planar area of ​​the third pad portion 35c can also be approximately equal to the planar area of ​​the second pad portion 35b. Of course, the planar area of ​​the third pad portion 35c can be larger or smaller than the planar area of ​​the second pad portion 35b. Either or both of the second pad portion 35b and the third pad portion 35c can be used as a terminal portion for current monitoring. The source electrode 35 can also have only either the second pad portion 35b or the third pad portion 35c. Alternatively, the source electrode 35 can be composed only of the first pad portion 35a, without both the second pad portion 35b and the third pad portion 35c.

[0177] The source electrode 35 enters multiple source openings 32 from the interlayer film 31 and is connected to the first main surface 3 (first surface 8) within the multiple source openings 32. The source electrode 35 is electrically connected to multiple source regions 21 and multiple first contact regions 27 within the multiple source openings 32.

[0178] Reference Figure 5 In this embodiment, the source electrode 35 has a stacked structure comprising a lower electrode film 36 and a main electrode film 37 stacked sequentially from the chip 2 side. In this embodiment, the lower electrode film 36 has a stacked structure comprising a first electrode film 38 and a second electrode film 39. In this embodiment, the first electrode film 38 comprises a Ti film, and the second electrode film 39 comprises a TiN film. The lower electrode film 36 does not necessarily need to have a stacked structure; it can also have a single-layer structure composed of either the first electrode film 38 (Ti film) or the second electrode film 39 (TiN film). The first electrode film 38 has a thickness less than the thickness of the interlayer film 31. The thickness of the first electrode film 38 can be 10 nm or more and 100 nm or less. The second electrode film 39 has a thickness less than the thickness of the interlayer film 31. Preferably, the thickness of the second electrode film 39 is greater than the thickness of the first electrode film 38. The thickness of the second electrode film 39 can also be 50 nm or more and 200 nm or less.

[0179] The first electrode film 38 covers the regions of the interlayer film 31 where multiple source openings 32 are formed in a film-like manner, and extends from the interlayer film 31 into the multiple source openings 32. The first electrode film 38 has a portion that covers the insulating main surface of the interlayer film 31 in a film-like manner, a portion that covers the wall surface of the multiple source openings 32 in a film-like manner, and a portion that covers the first main surface 3 in a film-like manner within the multiple source openings 32. The first electrode film 38 covers the first main surface 3 (first surface area 8) in a film-like manner within the source openings 32, and is mechanically and electrically connected to the multiple source regions 21 and the multiple first contact regions 27 on the first main surface 3.

[0180] The second electrode film 39 directly covers the first electrode film 38. The second electrode film 39, through the first electrode film 38, covers the region in the interlayer film 31 where multiple source openings 32 are formed, and extends from the interlayer film 31 into the multiple source openings 32. The second electrode film 39 has: a portion that covers the insulating main surface of the interlayer film 31 in a film-like manner through the first electrode film 38; a portion that covers the wall surface of the multiple source openings 32 in a film-like manner through the first electrode film 38; and a portion that covers the first main surface 3 in a film-like manner within the multiple source openings 32, through the first electrode film 38. The second electrode film 39 covers the first main surface 3 (first surface area 8) in a film-like manner within the source openings 32, through the first electrode film 38, and is electrically connected to the multiple source regions 21 and the multiple first contact regions 27 via the first electrode film 38.

[0181] The main electrode film 37 comprises a conductive material different from that of the lower electrode film 36 (the first electrode film 38 and the second electrode film 39). The main electrode film 37 may also comprise at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may also comprise at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The main electrode film 37 has a thickness greater than the thickness (total thickness) of the lower electrode film 36. Preferably, the thickness of the main electrode film 37 is greater than the thickness of the interlayer film 31. The thickness of the main electrode film 37 can be 0.5 μm or more and 5 μm or less.

[0182] The main electrode film 37 directly covers the lower electrode film 36 (second electrode film 39). The main electrode film 37 backfills the multiple source openings 32, covering the areas in the interlayer film 31 where the multiple source openings 32 are formed in a film-like manner. The main electrode film 37 has a portion that covers the insulating main surface of the interlayer film 31 through the lower electrode film 36, a portion that covers the wall surface of the multiple source openings 32 through the lower electrode film 36, and a portion that covers the first main surface 3 through the lower electrode film 36. The main electrode film 37 covers the first main surface 3 (first surface area 8) within the source openings 32 through the lower electrode film 36, and is electrically connected to the multiple source regions 21 and the multiple first contact regions 27 via the lower electrode film 36.

[0183] Reference Figure 1 as well as Figure 2 The semiconductor device 1 includes a gate electrode 40 disposed on a first main surface 3. The gate electrode 40 is a terminal electrode to which a gate potential is applied from the outside. Although not shown in the figure, the gate electrode 40, like the source electrode 35, includes a lower electrode film 36 and a main electrode film 37 stacked sequentially from the chip 2 side.

[0184] The gate electrode 40 and the source electrode 35 are disposed at a distance from each other on the portion of the interlayer film 31 covering the first surface area 8. In this embodiment, the gate electrode 40 is disposed in the region on the third side surface 5C relative to the first pad portion 35a, and is opposite to the first pad portion 35a in the first direction X. Furthermore, in the region between the second pad portion 35b and the third pad portion 35c, the gate electrode 40 is opposite to both the second pad portion 35b and the third pad portion 35c in the second direction Y.

[0185] Viewed from above, the gate electrode 40 is formed as a polygon (quadrilateral in this embodiment) with four sides parallel to the periphery of the chip 2. The gate electrode 40 has a planar area smaller than that of the source electrode 35. The gate electrode 40 has a planar area smaller than that of the first pad portion 35a. The gate electrode 40 may also have a planar area smaller than that of the second pad portion 35b (third pad portion 35c).

[0186] The gate electrode 40 is partially opposed to the plurality of gate structures 15 via the interlayer film 31. Specifically, the gate electrode 40 is arranged at intervals from both ends of the plurality of gate structures 15 inward, and is opposed to the interior (middle portion in this embodiment) of the plurality of gate structures 15 via the interlayer film 31. In this embodiment, the gate electrode 40 does not have a direct electrical connection portion relative to the plurality of gate structures 15. Of course, the gate electrode 40 may also be electrically connected to the plurality of gate structures 15 via a plurality of gate openings 33.

[0187] Reference Figure 1 The semiconductor device 1 includes a gate wiring 41 extending from the gate electrode 40 to the first main surface 3. The gate wiring 41 transmits the gate potential assigned to the gate electrode 40 to other areas. Although not shown in the figure, the gate wiring 41, like the source electrode 35 (gate electrode 40), includes a lower electrode film 36 and a main electrode film 37 stacked sequentially from the chip 2 side.

[0188] Reference Figure 1 Gate wiring 41 extends from gate electrode 40 to a portion of interlayer film 31 covering the first surface area 8. Gate wiring 41 is wound in a strip shape in the region between the periphery of the first surface area 8 and the source electrode 35. Gate wiring 41, when viewed from above, has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y. In this embodiment, gate wiring 41 is formed as an end strip with four sides parallel to the periphery of the first main surface 3, surrounding the source electrode 35. Gate wiring 41 enters a plurality of gate openings 33 from interlayer film 31, and is mechanically and electrically connected to the ends (both ends) of a plurality of gate structures 15 within the plurality of gate openings 33. Thus, the gate potential applied to gate electrode 40 is applied to the plurality of gate structures 15 via gate wiring 41.

[0189] Reference Figure 2 and Figure 5 The semiconductor device 1 includes a drain electrode 42 covering a second main surface 4. The drain electrode 42 is a terminal electrode to which a drain potential is applied from the outside. The drain electrode 42 is electrically connected to a first semiconductor region 6. The drain electrode 42 may also cover the entire area of ​​the second main surface 4 in a manner connected to the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. Alternatively, the drain electrode 42 may partially cover the second main surface 4, exposing the periphery of the second main surface 4.

[0190] The breakdown voltage that can be applied between the source electrode 35 and the drain electrode 42 (between the first main surface 3 and the second main surface 4) can be 500V or more and 3000V or less. The breakdown voltage can have a value belonging to at least one of the following ranges: 500V or more and 1000V or less, 1000V or more and 1500V or less, 1500V or more and 2000V or less, 2000V or more and 2500V or less, and 2500V or more and 3000V or less.

[0191] As described above, according to one embodiment of this disclosure, a semiconductor device 1 includes a chip 2, an n-type second semiconductor region 7, a trench-type gate structure 15, and a p-type well region 22. The chip 2 has a first main surface 3. The second semiconductor region 7 is formed on the surface portion of the first main surface 3. The gate structure 15 is formed on the first main surface 3 and located within the second semiconductor region 7. The well region 22 is formed within the second semiconductor region 7 in a region below the gate structure 15 (a first lower region 61 and a second lower region 62). The well region 22 is formed along a second direction Y.

[0192] Assuming Figure 10 as well as Figure 11 As with the semiconductor device 101 involved in the reference configuration shown, the entire region of the well region 22 has the same first depth D1 (refer to...). Figure 11 If this happens, it may compress the current path of the JFET, causing the resistance (on-resistance, JFET resistance) to increase.

[0193] In contrast, in this embodiment, the well region 22 includes a plurality of first well regions 51 having a first bottom 52 having a first depth D1. The plurality of first well regions 51 are formed by being spaced apart by a first interval W1 in the second direction Y. Figure 7 As shown, adjacent first trap regions 51 are opposite each other in the second direction Y, separated by the clamped portion 7a.

[0194] A first well region 51 is formed in the region below the gate structure 15 (first lower region 61). The first well region 51 suppresses the increase in current density near the bottom wall 15c of the gate structure 15. As a result, the electric field relative to the bottom wall 15c of the gate structure 15 is mitigated, and the decrease in breakdown voltage caused by electric field concentration is suppressed.

[0195] Furthermore, a medium-concentration region 25 and a portion of the second semiconductor region 7, namely the clamped portion 7a, are sandwiched between adjacent first well regions 51. This clamped portion 7a functions as a current path. Therefore, a sufficient current path can be ensured in the region below the gate structure 15 (first lower region 61). As a result, the on-resistance and JFET resistance can be reduced.

[0196] Therefore, it is possible to reduce resistance while suppressing the decrease in withstand voltage. That is, a semiconductor device 1 that can improve electrical characteristics is provided.

[0197] Chip 2 preferably comprises SiC. According to this structure, a semiconductor device 1, as a SiC semiconductor device, is provided that can improve electrical characteristics. The first spacing W1 between adjacent first well regions 51 can be greater than the first depth D1 of the first bottom 52 of the first well region 51. According to this structure, a wider current path can be ensured.

[0198] The well region 22 may include a first well region 51 and a second well region 53 with different bottom depths in the region below the gate structure 15 (first lower region 61 and second lower region 62). The first well region 51 and the second well region 53 may be connected to each other. According to this structure, the first well region 51 and the second well region 53 are formed in the region below the gate structure 15 (first lower region 61 and second lower region 62), respectively. Through both the first well region 51 and the second well region 53, the increase in current density near the bottom wall 15c of the gate structure 15 is suppressed. As a result, the electric field relative to the bottom wall 15c of the gate structure 15 is mitigated, and the decrease in breakdown voltage caused by electric field concentration is suppressed. Therefore, the decrease in breakdown voltage can be further suppressed and the resistance (on-resistance, JFET resistance) can be reduced.

[0199] The second well region 53 may also have a second depth D2 that is shallower than the first depth D1. According to this structure, the electric field relative to the bottom wall 15c of the gate structure 15 can be mitigated, and the reduction in breakdown voltage caused by electric field concentration can be further suppressed.

[0200] The ratio (D2 / D1) of the second depth D2 of the second bottom 54 of the second well region 53 to the first depth D1 of the first bottom 52 of the first well region 51 can also be less than 0.5. According to this structure, the second depth D2 of the second bottom 54 of the second well region 53 is sufficiently shallow, thus ensuring that the thickness T of the clamped portion 7a formed below the second well region 53 is [not specified]. U (Reference Figure 7 The current path is relatively large. Therefore, the current path can be more fully guaranteed.

[0201] The first bottom 52 of the first well region 51 can also have a thickness T greater than that of the main body region 20. B The first depth D1. The second well region 53 can also have a thickness T less than that of the main region 20. B The second depth D2. According to this structure, the second depth D2 of the second bottom 54 of the second well region 53 is shallow enough to ensure that the thickness T of the clamped portion 7a formed below the second well region 53 is sufficient. U (Reference Figure 7 The current path is relatively large. Therefore, the current path can be more fully guaranteed.

[0202] The first bottom 52 of the first well region 51 can also penetrate the medium concentration region 25 and be located in the second semiconductor region 7. The second well region 53 can also have a second bottom 54 located in the medium concentration region 25. According to this structure, the second depth D2 of the second bottom 54 of the second well region 53 is shallow enough to ensure that the thickness T of the clamped portion 7a formed below the second well region 53 is sufficient. U (Reference Figure 7 The current path is relatively large. Therefore, the current path can be more fully guaranteed.

[0203] Furthermore, in this embodiment, the clamped portion 7a, which is sandwiched between adjacent first well regions 51, is formed in the second lower region 62 below the second portion (the portion forming the channel region 26) 15Q in the gate structure 15. The presence of the clamped portion 7a, which is part of the drift region (medium concentration region 25, second semiconductor region 7), ensures a wider current path in the second lower region 62, which is the lower channel region.

[0204] Furthermore, in this embodiment, the clamped portion 7a is not formed in the first lower region 61 below the first portion (the region where the channel region 26 is not formed) 15P of the gate structure 15. The amount of current flowing in the first lower region 61, which is a non-channel lower region, is less than that in the second lower region 62, which is a channel lower region. Therefore, even though the width of the current path in the first lower region 61, which is a non-channel lower region, is narrower, a large resistance (on-resistance, JFET resistance) is not generated. By forming the first well region 51 in the first lower region 61, which is a non-channel lower region, the increase in current density near the bottom wall 15c of the gate structure 15 can be suppressed. As a result, the electric field at the bottom wall 15c of the gate structure 15 is mitigated, and the decrease in breakdown voltage caused by electric field concentration can be effectively suppressed.

[0205] Figure 12 This is a top view showing an example layout of chip 2 according to the second embodiment of this disclosure, and corresponds to... Figure 4 . Figure 13 It is along Figure 12 The cross-sectional view of line XIII-XIII shown. Figure 14 It is along Figure 12 The cross-sectional view of line XIV-XIV shown. Figure 15 It is along Figure 12 The cross-sectional view of the XV-XV line shown. Figure 16 It is along Figure 12 The cross-sectional view of the XVI-XVI line shown. Figure 17 It is by Figure 15 An enlarged view of the portion enclosed by the dashed line XVII. Figures 12 to 17 In this document, structures identical to those described so far are marked with the same reference symbols, and their descriptions are omitted.

[0206] The semiconductor device 201 of the second embodiment of this disclosure differs from semiconductor device 1 in that the first well region 51 and the first lower region 61 are formed together in the second lower region 62. In semiconductor device 201, the first well region 51 includes a region formed in the second lower region 62. Specifically, the first well region 51 has a first region 251 formed in the second lower region 62 (see reference). Figures 15 to 17 The first region 251 is connected to the clamped portion 7a from one side of the second direction Y.

[0207] Reference Figures 15 to 17 The first region 251 has a third bottom 252. The third bottom 252 has a third depth D3 (see reference). Figure 17 The third depth D3 is the depth of the third bottom 252 of the first region 251, which is based on the bottom wall 15c of the gate structure 15. The third depth D3 is greater than the thickness T of the main body region 20. B (Reference Figure 9(D3>T) B In this embodiment, the third depth D3 and the first depth D1 (refer to...) Figure 8 The same. Of course, the third depth D3 can also be a different depth than the first depth D1.

[0208] In other words, in the semiconductor device 201, the clamped portion 7a is not formed in the entire area of ​​the second lower region 62, but in a part of the second lower region 62.

[0209] Reference Figure 17 The first region 251 has one or more (in this embodiment, multiple) first bulges 22c. In this embodiment, the first region 251 does not have a first extension 22a (see reference). Figure 9 ) and the second extension 22b (see reference) Figure 9 Of course, the first region 251 may also have a first extension 22a and a second extension 22b.

[0210] The semiconductor device 201 according to the second embodiment of this disclosure has the same effects as those described in the first embodiment.

[0211] Furthermore, by forming the clamping portion 7a in a part of the second lower region 62 instead of the entire second lower region 62, the first interval W1 of the adjacent first well regions 51 can be adjusted (see reference). Figure 16 As described above, the length of the second direction Y of the clamped portion 7a is separated from the first interval W1 of the adjacent first well region 51 (see reference). Figure 16 Consistent. By adjusting the first interval W1 (refer to...) Figure 16 It can adjust the saturation current to the optimal value when the channel is formed.

[0212] The following is for reference Figures 18 to 27 This describes the semiconductor devices 301A, 301B, 301C, 301D, 301E, and 301F of the first to sixth modifications. Figures 18 to 27 In this document, structures identical to those described so far are marked with the same reference symbols, and their descriptions are omitted.

[0213] Figure 18 This is a cross-sectional view of the semiconductor device 301A of the first modified example, which is related to... Figure 16 The corresponding diagram. (Refer to...) Figure 18 The semiconductor device 301A of the first variant differs from the semiconductor device 201 in that the first well region 51, together with the first region 251, includes a second region 351 in the second lower region 62. The second region 351 is connected to the clamped portion 7a from the other side of the second direction Y. The second region 351 has the same structure as the first region 251.

[0214] By forming the clamping portion 7a in a portion of the second lower region 62, rather than the entire second lower region 62, similar to the semiconductor device 201 of the second embodiment, the first interval W1 of adjacent first well regions 51 can be adjusted. As described above, the length of the clamping portion 7a in the second direction Y and the first interval W1 of adjacent first well regions 51 (refer to...) Figure 18 Consistent. By adjusting the first interval W1 (refer to...) Figure 18 It can adjust the saturation current to the optimal value when the channel is formed.

[0215] Figure 19 This is a cross-sectional view of the semiconductor device 301B in the second modified example, which is related to... Figure 9 The corresponding diagram. (Refer to...) Figure 19 In the second modified semiconductor device 301B, the second bottom 54 of the second well region 53 is located at the same height as the bottom 23a of the high-concentration well region 23. The second depth D2 of the second bottom 54 of the second well region 53 is equal to the thickness T of the high-concentration well region 23. H They are of the same size. In other words, the high-concentration trap region 23 and the medium-concentration region 25 (semiconductor region) are connected in the vertical direction Z.

[0216] Figure 20 This is a cross-sectional view of the semiconductor device 301C of the third modified example, which is related to... Figure 5 The corresponding sectional view. Figure 21 This is a cross-sectional view of the semiconductor device 301C of the third modified example, which is related to... Figure 6 The corresponding cross-sectional view. The difference between the semiconductor device 301C in the third variation and the semiconductor device 1 is that the high-concentration region 24 is omitted. The region where the high-concentration region 24 is formed in the semiconductor device 1 is replaced by the medium-concentration region 25 in the semiconductor device 301C. In this case, multiple channel regions 26 (see reference) Figure 9 Multiple channel regions 26 are formed within multiple main regions 20, between multiple source regions 21 and multiple medium-concentration regions 25, respectively. Multiple channel regions 26 form current paths connecting multiple source regions 21 and multiple medium-concentration regions 25 along the sidewalls (first sidewall 15a and second sidewall 15b) of multiple gate structures 15 within multiple main regions 20.

[0217] Figure 22 This is a cross-sectional view of the semiconductor device 301D of the fourth variation. Figure 23 This is a cross-sectional view of the semiconductor device 301D of the fourth variation. Figure 22 as well as Figure 23 It is a cross-sectional view of the semiconductor device 301D cut at different positions in the second direction Y.

[0218] In the fourth variation, the source region 21 is selectively formed on the side of the first sidewall 15a, spaced apart from the second sidewall 15b of the gate structure 15 on the side of the first direction X, within the region (mesa) sandwiched by adjacent gate structures 15. On the other hand, the first contact region 27 is selectively formed on the side of the second sidewall 15b, adjacent to the source region 21 in the width direction (first direction X) of the region (mesa) sandwiched by adjacent gate structures 15. The source region 21 and the first contact region 27 are formed as stripes extending in the second direction Y.

[0219] A third contact region 71 is selectively formed on one side of the region (mesa) sandwiched by adjacent gate structures 15. The third contact region 71 extends along the first sidewall 15a in the vertical direction Z, connecting the first contact region 27 to the high concentration trap region 23.

[0220] The well region 22, which serves as an electric field mitigation layer, includes a first well region 51 formed below the high-concentration well region 23 (see reference). Figure 22 The trap region 22 has a second trap region 53 formed below the high-concentration trap region 23 (see reference). Figure 23 First pit region 51 (refer to) Figure 22 ) and second well region 53 (refer to Figure 23 It is formed alternately in the second direction Y.

[0221] Figure 24 This is a cross-sectional view of the semiconductor device 301E of the fifth modification. Figure 25 This is a cross-sectional view of the semiconductor device 301E of the fifth modification. Figure 24 as well as Figure 25 It is a cross-sectional view of the semiconductor device 301E cut at different positions in the second direction Y.

[0222] In a fifth variation, in the region (mesa) sandwiched by adjacent gate structures 15, source regions 21 are formed on both sides of the gate structure 15 on one side of the first direction X and on the gate structure 15 on the other side of the first direction X. In this variation, a pair of strip-shaped source regions 21 extend in a stripe-like pattern in the second direction Y in the region (mesa) sandwiched by adjacent gate structures 15.

[0223] Furthermore, the first contact region 27 is formed in the center of the region (mesa) sandwiched by adjacent gate structures 15 in the first direction X, between a pair of source regions 21. The first contact region 27 is sandwiched by a pair of source regions 21 in the first direction X. The first contact region 27 penetrates the source regions 21 in the vertical direction Z and is connected to the main body region 20. The first contact region 27 extends in a strip shape in the region (mesa) sandwiched by adjacent gate structures 15 in the second direction Y. The first contact region 27 and the pair of source regions 21 sandwiching the first contact region 27 from both sides are formed in a stripe shape extending in the second direction Y in the region (mesa) sandwiched by adjacent gate structures 15.

[0224] The well region 22, which serves as an electric field mitigation layer, includes a first well region 51 formed below the high-concentration well region 23 (see reference). Figure 24 The trap region 22 has a second trap region 53 formed below the high-concentration trap region 23 (see reference). Figure 25 First pit region 51 (refer to) Figure 24 ) and second well region 53 (refer to Figure 25 It is formed alternately in the second direction Y.

[0225] Figure 26 This is a cross-sectional view of the semiconductor device 301F of the sixth modified example, which is related to... Figure 5 The corresponding sectional view. Figure 27 This is a cross-sectional view of the semiconductor device 301F of the sixth modified example, which is related to... Figure 6 The corresponding sectional view.

[0226] In a sixth variation, the trap region 22 and the high-concentration trap region 23 are formed along the first direction X from one end of the gate structure 15 to the other. More specifically, the high-concentration trap region 23 is selectively formed on the other side of the first direction X relative to the gate structure 15. In this variation, the high-concentration trap region 23 extends downward in the vertical direction Z from a portion of the main body region 20 in the region (mesa) sandwiched by adjacent gate structures 15, and extends horizontally along the first main surface 3, overlapping the bottom wall 15c of the gate structure 15.

[0227] The high-concentration trap region 23 forms at least a portion of the second sidewall 15b and the bottom wall 15c of the gate structure 15, and is in contact with the insulating film 17. The high-concentration trap region 23 has a generally L-shaped exposed surface that serves as the lower portion of the second sidewall 15b and the bottom wall 15c.

[0228] The well region 22, which serves as an electric field mitigation layer, includes a first well region 51 formed below the high-concentration well region 23 (see reference). Figure 26The trap region 22 has a second trap region 53 formed below the high-concentration trap region 23 (see reference). Figure 27 First pit region 51 (refer to) Figure 26 ) and second well region 53 (refer to Figure 27 It is formed alternately in the second direction Y.

[0229] In the above embodiments (including variations), examples of the first conductivity type being n-type and the second conductivity type being p-type have been described, but it is also possible for the first conductivity type to be p-type and the second conductivity type to be n-type. In this case, the specific structure is obtained by replacing the n-type region with the p-type region and the p-type region with the n-type region in the foregoing description and drawings.

[0230] In the various embodiments described above (including variations), a chip 2 comprising a SiC single crystal is used. However, chip 2 may also comprise a wide-bandgap semiconductor single crystal other than SiC. A wide-bandgap semiconductor is a semiconductor having a bandgap larger than that of silicon. For example, chip 2 may comprise gallium nitride, gallium oxide, diamond, etc. Of course, chip 2 may also comprise single-crystal silicon.

[0231] Similarly, the first semiconductor region 6 may also include wide-bandgap semiconductor single crystals other than SiC single crystals. The first semiconductor region 6 may also include gallium nitride, gallium oxide, diamond, etc. Of course, the first semiconductor region 6 may also include single-crystal silicon.

[0232] Similarly, the second semiconductor region 7 may also include wide-bandgap semiconductor single crystals other than SiC single crystals. The second semiconductor region 7 may also include gallium nitride, gallium oxide, diamond, etc. Of course, the second semiconductor region 7 may also include single-crystal silicon.

[0233] In the various embodiments described above (including variations), a p-type collector region may also be formed on the surface layer of the second main surface 4 of the chip 2. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of a MISFET structure. The specific structure in this case is obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and replacing the "drain" of the MISFET structure with the "collector" of the IGBT structure, as described above.

[0234] The following are examples of features extracted from this specification and accompanying drawings. Hereinafter, the letters and numbers in parentheses indicate corresponding constituent elements in the above-described manner, but are not intended to limit the scope of each item (clause) to the manner. The term "semiconductor device" in the following item can be replaced as needed with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," etc.

[0235] [Postscript 1-1]

[0236] A semiconductor device 1, 201, 301A, 301B, 301C, 301D, 301E, 301F, comprising:

[0237] Chip 2, which has a main surface;

[0238] A first conductivity type drift region 7 is formed on the surface portion of the main surface 3;

[0239] A trench electrode type gate structure 15 is formed on the main surface 3 in a manner located within the drift region 7; and

[0240] A second conductivity type well region 22 is formed in the region below the gate structure 15 within the drift region 7 along the bottom wall 15c of the gate structure 15.

[0241] The well region 22 includes a plurality of first well regions 51, each first well region 51 having a first bottom 52 having a first depth D1, and the first well regions 51 being formed by being spaced apart by a first interval W1 in the depth direction Y of the gate structure 15.

[0242] The adjacent first well regions 51 are opposite each other in the depth direction Y of the gate structure 15, separated by a portion 7a of the drift regions 7, 25.

[0243] According to this structure, the well region 22 includes a plurality of first well regions 51 formed in the region below the gate structure 15, spaced apart by a first interval W1 in the depth direction Y of the gate structure 15. Moreover, adjacent first well regions 51 are opposed to each other in the depth direction Y of the gate structure 15, separated by a portion 7a of the drift regions 7, 25.

[0244] A first well region 51 is formed in the region below the gate structure 15. The first well region 51 suppresses the increase in current density near the bottom wall 15c of the gate structure 15. As a result, the electric field relative to the bottom wall 15c of the gate structure 15 is mitigated, and the decrease in breakdown voltage caused by electric field concentration is suppressed.

[0245] Furthermore, a portion 7a of the drift regions 7 and 25 is located between adjacent first well regions 51. This portion 7a functions as a current path. Therefore, a sufficient current path can be ensured in the region below the gate structure 15. As a result, a reduction in resistance (on-resistance, JFET resistance) can be achieved.

[0246] Therefore, it is possible to reduce resistance while suppressing the decrease in withstand voltage. That is, it is possible to provide a semiconductor device 1, 201, 301A, 301B, 301C, 301D, 301E, 301F that can improve electrical characteristics.

[0247] [Notes 1-2]

[0248] According to the semiconductor devices 1, 201, 301A, 301B, 301C, 301D, 301E, and 301F described in Appendix 1-1, wherein,

[0249] The chip 2 includes SiC.

[0250] [Notes 1-3]

[0251] Semiconductor devices 1, 201, 301A, 301B, 301C, 301D, 301E, and 301F as described in Appendix 1-1 or Appendix 1-2, wherein,

[0252] The first interval W1 is greater than the first depth D1 of the first well region 51.

[0253] [Notes 1-4]

[0254] According to any one of Annexes 1-1 to Annexes 1-3, the semiconductor devices 1, 201, 301A, 301B, 301C, 301D, 301E, and 301F, wherein,

[0255] The well region 22 further includes a second well region 53, which is formed between adjacent first well regions 51 in a manner connected to the first well regions 51, and has a second bottom 54 having a second depth D2 that is shallower than the first depth D1.

[0256] According to this structure, the well region 22 includes a first well region 51 and a second well region 53 with different bottom depths in the region below the gate structure 15. The first well region 51 and the second well region 53 are connected to each other.

[0257] A first well region 51 and a second well region 53 are formed in the region below the gate structure 15. Both the first well region 51 and the second well region 53 suppress the increase in current density near the bottom wall 15c of the gate structure 15. As a result, the electric field relative to the bottom wall 15c of the gate structure 15 is mitigated, and the decrease in breakdown voltage caused by electric field concentration is suppressed. Therefore, the decrease in breakdown voltage can be further suppressed, and the resistance (on-resistance, JFET resistance) can be reduced.

[0258] [Notes 1-5]

[0259] According to the semiconductor devices 1, 201, 301A, 301B, 301C, 301D, 301E, and 301F described in Appendices 1-4, wherein,

[0260] The ratio of the second depth D2 to the first depth D1, D2 / D1, is less than 0.5.

[0261] [Notes 1-6]

[0262] Semiconductor devices 1, 201, 301A, 301B, 301C, 301D, 301E, and 301F as described in Appendices 1-4 or 1-5, wherein,

[0263] It also includes a main body region 20 through which the gate structure 15 passes, which is formed on the surface portion of the main surface 3 relative to the drift regions 7 and 25 on the side of the main surface 3.

[0264] The first depth D1 is greater than the thickness T of the main body region 20. B big,

[0265] The second depth D2 is greater than the thickness T of the main body region 20. B Small.

[0266] [Notes 1-7]

[0267] According to the semiconductor devices 1, 201, 301A, 301B, 301C, 301D, 301E, and 301F described in Appendices 1-6, wherein,

[0268] The main body region 20 extends along the sidewalls 15a and 15b of the gate structure 15 in the depth direction Y of the gate structure 15.

[0269] The main body region 20 is connected to the trap region 22.

[0270] [Notes 1-8]

[0271] According to any one of the semiconductor devices 1, 201, 301A, 301C, 301D, 301E, 301F as described in Appendices 1-4 to 1-7, wherein,

[0272] It also includes a high-concentration well region 23 of a second conductivity type, which is formed at intervals within the well region 22 from the first bottom 52 of the first well region 51 toward the bottom wall 15c side of the gate structure 15, and has a higher impurity concentration than the well region 22.

[0273] The second bottom 54 of the second well region 53 is located in the drift regions 7 and 25.

[0274] The high-concentration trap region 23 has a bottom 23a, which is located on the side of the bottom wall 15c of the gate structure 15, which is closer to the second bottom 54 of the second trap region 53.

[0275] [Notes 1-9]

[0276] Semiconductor devices 201, 301A, 301B, 301C, 301D, 301E, and 301F according to any one of Appendices 1-4 to 1-8, wherein,

[0277] It also includes a high-concentration well region 23 of a second conductivity type, which is formed in the well region 22 at intervals from the first bottom 52 of the first well region 51 toward the bottom wall 15c side of the gate structure 15, and has an impurity concentration higher than that of the well region 22.

[0278] The high-concentration trap region 23 has a bottom 23a at the same height as the second bottom 54 of the second trap region 53.

[0279] [Notes 1-10]

[0280] Semiconductor devices 1, 201, 301A, 301B, and 301C according to any one of Appendices 1-1 to 1-9, wherein,

[0281] It also includes a channel region 26 of a second conductivity type, which is formed along the sidewalls 15a and 15b of the gate structure 15.

[0282] The clamped portion 7a, which is sandwiched between the adjacent first well region 51 in the drift regions 7 and 25, is formed in the lower channel region 62 below the portion 15Q that forms the channel region 26 in the gate structure 15.

[0283] According to this structure, the clamped portion 7a, which is clamped by the adjacent first well region 51, is formed in the lower channel region 62 below the portion 15Q that forms the channel region 26 in the gate structure 15. The presence of the clamped portion 7a, which is part of the drift region 7, ensures a wider current path in the lower channel region 62.

[0284] [Postscript 1-11]

[0285] According to the semiconductor devices 1, 301B, and 301C described in Appendices 1-10, wherein,

[0286] The first well region 51 is not formed in the lower region 62 of the channel.

[0287] [Postscript 1-12]

[0288] According to the semiconductor devices 201 and 301A described in Appendices 1-10, wherein,

[0289] The first trap region 51 includes the region formed in the lower region 62 of the channel.

[0290] [Postscript 1-13]

[0291] According to the semiconductor devices 201 and 301A described in Appendices 1-12, wherein,

[0292] The first well region 51 has a first region 251 in the lower channel region 62 that is connected to the clamped portion 7a from one of the depth directions Y of the gate structure 15.

[0293] [Postscript 1-14]

[0294] According to the semiconductor device 301A described in Appendix 1-13, wherein,

[0295] The first well region 51 also has a second region 351 in the first lower region 61 that is connected to the clamped portion 7a from the other side of the depth direction Y of the gate structure 15.

[0296] [Postscript 1-15]

[0297] Semiconductor devices 1, 201, 301A, 301B, and 301C according to any one of Appendices 1-10 to 1-14, wherein,

[0298] The first well region 51 is formed in the non-channel lower region 61 below the region 15P in the gate structure 15 where the channel region 26 is not formed.

[0299] The clamped portion 7a is not formed in the non-channel region 61.

[0300] According to this structure, the non-channel lower region 61 below the region 15P where the channel region 26 is not formed in the gate structure 15 does not have a clamped portion 7a. The amount of current flowing in the non-channel lower region 61 is less than that in the channel lower region 62. Therefore, even though the width of the current path in the non-channel lower region 61 is narrower, a large resistance (on-resistance, JFET resistance) is not generated. By forming the first well region 51 in the non-channel lower region 61, the increase in current density near the bottom wall 15c of the gate structure 15 can be suppressed. As a result, the electric field relative to the bottom wall 15c of the gate structure 15 is mitigated, and the decrease in breakdown voltage caused by electric field concentration can be effectively suppressed.

[0301] [Postscript 1-16]

[0302] According to the semiconductor devices 1, 201, 301A, 301B, and 301C described in Appendices 1-15, wherein,

[0303] In the non-channel region 61, the first well region 51 is formed over the entire region of the depth direction Y of the gate structure.

[0304] [Postscript 1-17]

[0305] The semiconductor device 301D according to any one of Appendices 1-1 to 1-9 includes:

[0306] Chip 2, which has a main surface;

[0307] A first conductivity type drift region 7 is formed on the surface portion of the main surface 3;

[0308] A trench electrode type gate structure 15 is formed on the main surface 3 in a manner located within the drift region 7; and

[0309] A second conductivity type well region 22 is formed in the region below the gate structure 15 within the drift region 7 along the bottom wall 15c of the gate structure 15.

[0310] The gate structure 15 is formed in a stripe pattern.

[0311] In the region sandwiched by adjacent gate structures 15, source regions 21 are selectively formed on the sidewall 15a of one side of the gate structure 15, spaced apart from the sidewall 15b of the other side of one side of the gate structure 15.

[0312] [Postscript 1-18]

[0313] The semiconductor device 301E according to any one of Appendices 1-1 to 1-9 includes:

[0314] Chip 2, which has a main surface;

[0315] A first conductivity type drift region 7 is formed on the surface portion of the main surface 3;

[0316] A trench electrode type gate structure 15 is formed on the main surface 3 in a manner located within the drift region 7; and

[0317] A second conductivity type well region 22 is formed in the region below the gate structure 15 within the drift region 7 along the bottom wall 15c of the gate structure 15.

[0318] The gate structure 15 is formed in a stripe pattern.

[0319] In the region sandwiched by the adjacent gate structures 15, the source region 21 is formed on both sides of the sidewall 15b on one side of the gate structure 15 and the sidewall 15a on one side of the gate structure 15 on the other side.

[0320] Symbol Explanation

[0321] 1—Semiconductor device; 2—Chip; 3—First main surface (main surface); 4—Second main surface; 5A—First side surface; 5B—Second side surface; 5C—Third side surface; 5D—Fourth side surface; 6—First semiconductor region; 7—Second semiconductor region (drift region); 7a—Clamped portion (partial); 8—First face surface; 9—Second face surface; 10A—First connection face surface; 10B—Second connection face surface; 10C—Third connection face surface; 10D—Fourth connection face surface; 11—Mesa; 12—Active region; 13—Outer peripheral region; 15—Gate structure; 15a—First sidewall (Sidewall); 15b—Second sidewall; 15c—Bottom wall; 15P—First part (part of the area where no channel is formed); 15Q—Second part (part of the area where the channel is formed); 16—Trench; 17—Insulating film; 18—Buried electrode; 20—Main body area; 21—Source area; 22—Trap area; 22a—First extension; 22b—Second extension; 22c—First bulge; 23—High concentration trap area; 23a—Bottom; 24—High concentration area; 25—Medium concentration area (drift area); 26—Channel area; 27—First contact area; 27a—High concentration region; 27b—Low concentration region; 28—Second contact area; 28a—First extension; 28b—Second extension; 28c—Second bulge; 28d—Bottom; 30—Main surface insulating film; 31—Interlayer film; 32—Source opening; 33—Gate opening; 35—Source electrode; 35a—First pad; 35b—Second pad; 35c—Third pad; 36—Lower electrode film; 37—Main electrode film; 38—First electrode film; 39—Second electrode film; 40—Gate electrode; 41—Gate wiring; 42—Drain electrode; 51—First well Region; 52—First bottom; 53—Second well region; 54—Second bottom; 61—First lower region (non-under-channel region); 62—Second lower region (under-channel region); 101—Semiconductor device; 201—Semiconductor device; 251—First region; 252—Third bottom; 301A—Semiconductor device; 301B—Semiconductor device; 301C—Semiconductor device; 301D—Semiconductor device; 301E—Semiconductor device; 301F—Semiconductor device; 351—Second region; D1—First depth; D2—Second depth; D3—Third depth; T B —Thickness; T H —Thickness; T U —Thickness; Tr—Transistor structure; W1—First gap; W2—Second gap; X—First direction; Y—Second direction; Z—Vertical direction.

Claims

1. A semiconductor device, characterized in that, include: A chip has a main surface; A drift region of the first conductivity type is formed on the surface portion of the main surface; A trench electrode type gate structure is formed on the main surface in such a way that it is located within the drift region. A second conductivity type well region is formed in the drift region below the gate structure along the bottom wall of the gate structure. The well region includes a plurality of first well regions, each first well region having a first bottom having a first depth, and the plurality of first well regions are formed at a first interval in the depth direction of the gate structure. The adjacent first well regions are opposed in the depth direction of the gate structure, separated by a portion of the drift region.

2. The semiconductor device according to claim 1, characterized in that, The chip includes SiC.

3. The semiconductor device according to claim 1 or 2, characterized in that, The first interval is greater than the first depth of the first well region.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The well region further includes a second well region formed between the plurality of first well regions in a manner connected to the plurality of first well regions, and having a second bottom with a second depth shallower than the first depth.

5. The semiconductor device according to claim 4, characterized in that, The ratio of the second depth to the first depth is less than 0.

5.

6. The semiconductor device according to claim 4 or 5, characterized in that, It also includes a main body region through which the gate structure passes, the main body region being formed on the main surface side relative to the drift region in the surface portion of the main surface. The first depth is greater than the thickness of the main body region. The second depth is less than the thickness of the main body region.

7. The semiconductor device according to claim 6, characterized in that, The main region extends along the sidewall of the gate structure in the depth direction of the gate structure. The main body region is connected to the trap region.

8. The semiconductor device according to any one of claims 4 to 7, characterized in that, It also includes a high-concentration well region of a second conductivity type, which is formed at intervals from the first bottom of the first well region toward the bottom wall side of the gate structure within the well region and has a higher impurity concentration than the well region. The second bottom of the second well region is located in the drift region. The high-concentration trap region has a bottom that is located on the bottom wall side of the gate structure, which is closer to the second bottom of the second trap region.

9. The semiconductor device according to any one of claims 4 to 8, characterized in that, It also includes a high-concentration well region of a second conductivity type, which is formed at intervals from the first bottom of the first well region toward the bottom wall side of the gate structure within the well region, and has an impurity concentration higher than that of the well region. The second bottom of the second trap region is located at the same height as the bottom of the high-concentration trap region.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that, It also includes a channel region of a second conductivity type, which is formed along the sidewall of the gate structure. The clamped portion in the drift region, which is sandwiched between adjacent first well regions, is formed in the under-channel region below the portion forming the channel region in the gate structure.

11. The semiconductor device according to claim 10, characterized in that, The first well region was not formed in the area below the channel.

12. The semiconductor device according to claim 10, characterized in that, The first trap region includes the region formed under the channel.

13. The semiconductor device according to claim 12, characterized in that, The first well region has a first region in the lower channel region that is connected to the clamped portion on one side of the gate structure in the depth direction.

14. The semiconductor device according to claim 13, characterized in that, The first well region also has a second region in the lower channel region that is connected to the clamped portion from the other side of the depth direction of the gate structure.

15. The semiconductor device according to any one of claims 10 to 14, characterized in that, The first well region is formed in the non-channel under-channel region below the region in the gate structure where the channel region is not formed. The clamped portion is not formed in the non-channel area.

16. The semiconductor device according to claim 15, characterized in that, In the non-channel region, the first well region is formed over the entire depth direction of the gate structure.

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