Voltage glitch detection

Abstract

The present disclosure relates to a supply voltage glitch detection circuit (300), comprising: a first flip-flop (301) having a data input (302), a clock input (303) and an output (304); a delay circuit (305) having an output (307) connected to the data input of the first flip-flop; a first clock signal divider (308) having a clock input (309) connected to receive an inverted clock signal and an output (312) connected to an input (306) of the delay circuit (305); a second clock signal divider (313) having a clock input (314) connected to receive the clock signal and an output (315) connected to the clock input (303) of the first flip-flop, wherein the circuit (300) is configured to cause a glitch detection signal output to change state upon deviation of a supply voltage of the circuit (300) to cause a change in delay provided by the delay circuit (305).

Description

Technical Field

[0001] This disclosure relates to circuits and methods for detecting voltage spikes. Background Technology

[0002] Voltage glitches in digital circuits—temporary increases or decreases in power supply voltage—can be used to extract information from otherwise secure circuits. Intentionally introducing voltage glitches can bring faults into the circuit, potentially causing it to output sensitive information, such as internally stored encryption or decryption keys. Therefore, detecting and / or mitigating the effects of such attacks is a crucial feature in designing more resilient and secure circuits. Summary of the Invention

[0003] According to a first aspect, a power supply voltage glitch detection circuit is provided, comprising: a first flip-flop having a data input, a clock input, and an output for providing a glitch detection signal; a delay circuit having an input and an output connected to the data input of the first flip-flop; a first clock signal divider having an output connected to receive a clock input via an inverted clock signal and an output connected to the input of the delay circuit; and a second clock signal divider having an output connected to receive a clock signal and an output connected to the clock input of the first flip-flop, wherein the voltage glitch detection circuit is configured to cause the glitch detection signal to change state immediately after a deviation of the power supply voltage of the circuit to cause a change in the delay provided by the delay circuit.

[0004] In some examples, the first clock signal divider includes a second flip-flop having a data input and an inverted output, the data input being connected to the inverted output; and the second clock signal divider includes a third flip-flop having a data input and an inverted output, the data input being connected to the inverted output.

[0005] In some examples, the power supply voltage glitch detection circuit includes an inverter connected between the clock input of a first clock signal divider and a clock signal line, wherein the clock input of a second clock signal divider is connected to the clock signal line. In an alternative example, the power supply voltage glitch detection circuit includes an inverter connected between the clock input of a second clock signal divider and a clock signal line, wherein the clock input of the first clock signal divider is connected to the clock signal line.

[0006] In some cases, the output of the first clock signal divider is directly connected to the input of the delay circuit.

[0007] In some examples, the power supply voltage glitches detection circuit also includes an AND gate having a first input connected to the output of a second flip-flop, a second input connected to the inverted output and data input of a third flip-flop, and an output connected to the input of a delay circuit.

[0008] In some examples, the clock signal is a frequency-divided clock signal, and the detector circuit further includes: a third clock signal divider having a clock input connected to receive an inverted clock signal and a clock input connected to a first clock signal divider for providing the inverted frequency-divided clock signal to the first clock signal divider; and a fourth clock signal divider having a clock input connected to receive a clock signal and a clock input connected to a second clock signal divider for providing the divided clock signal to the output of the second clock signal divider.

[0009] In some examples, the third clock signal divider includes a fourth flip-flop having a data input and an inverted output, the data input being connected to the inverted output, and the fourth clock signal divider includes a fifth flip-flop having a data input and an inverted output, the data input being connected to the inverted output.

[0010] In some examples, the power supply voltage glitch detection circuit includes an inverter connected between the clock input of the third clock signal divider and the clock signal line, wherein the clock input of the fourth clock signal divider is connected to the clock signal line. In some alternative examples, the power supply voltage glitch detection circuit includes an inverter connected between the clock input of the fourth clock signal divider and the clock signal line, wherein the clock input of the third clock signal divider is connected to the clock signal line.

[0011] The output of the first clock signal divider can be directly connected to the input of the delay circuit. Alternatively, the power supply voltage glitch detection circuit also includes an AND gate having a first input connected to the output of the second flip-flop, a second input connected to the inverted output and data input of the third flip-flop, and an output connected to the input of the delay circuit.

[0012] According to a second aspect, a method for detecting power supply voltage glitches using a detector circuit is provided, the detector circuit comprising: a first flip-flop having a data input, a clock input, and an output for providing a glitch detection signal; a delay circuit having an input and an output connected to the data input of the first flip-flop; a first clock signal divider having an output connected to receive a clock input via an inverted clock signal and an output connected to the input of the delay circuit; and a second clock signal divider having an output connected to receive a clock input via a clock signal and an output connected to the clock input of the first flip-flop, wherein the delay circuit provides a delay of at least half the clock period of the clock signal when the power supply voltage of the circuit is at a nominal level, and the glitch detection signal changes state when an increase in the power supply voltage causes the delay to drop below half the clock period.

[0013] The delay provided by the delay circuit can be at least half the period of the clock signal.

[0014] The first clock signal divider and the second clock signal divider can provide a divided clock signal at their respective outputs, the divided clock signal having twice the period of the clock signal provided at the respective clock input.

[0015] The delay provided by the delay circuit can be up to 1.5, 2, or 4 times the period of the clock signal.

[0016] In some examples, the first clock signal divider includes a second flip-flop having a data input and an inverted output connected to the inverted output, and the second clock signal divider includes a third flip-flop having a data input and an inverted output connected to the inverted output.

[0017] These and other aspects of the invention will be apparent from the embodiments described below, and will be illustrated with reference to those embodiments. Attached Figure Description

[0018] The embodiments are described using the reference drawings as examples only, wherein:

[0019] Figure 1a This is an example of a voltage glitch detection circuit;

[0020] Figure 1b yes Figure 1a Timing diagrams of example signals in a circuit;

[0021] Figure 2 yes Figure 1a Another time-limited diagram of example signals in a circuit, indicating the best and worst case scenarios of data signals in the circuit;

[0022] Figure 3a This is yet another example of a voltage glitch detection circuit;

[0023] Figure 3b yes Figure 3a Timing diagrams of example signals in a circuit;

[0024] Figure 4a This is yet another example of a voltage glitch detection circuit;

[0025] Figure 4b yes Figure 4a Timing diagrams of example signals in the circuit; and

[0026] Figure 5 This is yet another example of a voltage spike detection circuit.

[0027] It should be noted that the figures are illustrative and not drawn to scale. For clarity and convenience in the figures, the relative dimensions and scales of the parts have been shown as enlarged or reduced in size. The same reference numerals are generally used to refer to modified embodiments and corresponding or similar features in different embodiments. Detailed Implementation

[0028] US 11,321,457 B2 discloses a digital glitch detection system in which a detector with a combination of an initial delay and a capture segment provides a digital output value corresponding to a measured change from a nominal voltage. The initial delay is provided by a combination of delay circuits preset to provide delay according to any process changes in the circuit. The capture segment comprises a series of fixed delay and capture latches that together output a digital signal indicating a change from the initial nominal delay value, where a higher value indicates a voltage above normal and a lower value indicates a voltage below normal. This detector can be used to effectively detect voltage glitches, but for proper operation, the initial delay needs to be adjustable to cover all possible process and temperature changes, thus requiring trimming or fusing of the initial delay. Furthermore, the multi-bit output of the detector requires additional decoding capabilities, increasing the overall area requirement of the detector. This may limit the application of this detector to cases requiring only one or a small number of detectors. Detecting electromagnetic fault injection may require a wider coverage area across the circuit, making multiple such detectors less suitable due to the additional area required.

[0029] An alternative approach, as described in this paper, is to provide a simplified detector that uses only certain basic components to detect changes in the power supply voltage. Figure 1a An example burr detector 100 is shown, and Figure 1b An example timing diagram of the circuit is shown. Detector 100 includes a D-type flip-flop 101 having a clock input 102 connected to a clock signal CLK and a data input 103 connected to the output of a delay circuit 104. The input 105 of the delay circuit 104 is connected to the clock input 102 via an inverter 106. The output 107 of the flip-flop 101 provides an output signal OUT, which in this case indicates whether the power supply voltage VDD is within or above the normal range.

[0030] like Figure 1bAs shown, during normal operation when VDD is at its normal level, the clock signal CLK is followed by a delayed clock signal D input to data input 103, which has a constant delay 108 defined by the delay circuit 104. After a voltage spike occurs that increases VDD above its normal level, this immediately results in a reduced delay 109, as the increased voltage causes the delay circuit 104 to deliver the inverted clock signal to data input 103 more quickly. When this reduced delay 109 is less than half of the clock period 110, the output OUT changes state, in this case changing from low to high.

[0031] Under all process and temperature conditions, while keeping VDD within the normal range, the normal delay 10⁸ should be between 0.5 and 1 clock cycle. In this case, the operating delay range can be limited to half a clock cycle. This delay amount should be within this limit for all process and temperature variations; otherwise, it may lead to false positives at some process inflection points. Figure 2 The example shows a misconfiguration. Figure 1a The timing diagram of the circuit is shown. In the 'best case' scenario, the delay 201 of the data input signal D@BC is slightly longer than half a clock cycle, and therefore causes... Figure 1b The same behavior occurs in the circuit, where the output OUT@BC changes state after VDD rises from normal to high. However, in the 'worst-case' scenario, the data input signal D@WC is delayed by 202 times over a clock cycle and is inoperable because the output OUT@WC rises before VDD. Therefore, if the difference between the delays in the best-case and worst-case scenarios exceeds the operating delay range, which is half a clock cycle in this case, it is impossible to find a configuration point for all process inflection points.

[0032] Using a slower clock can increase the range of operating delays. However, this also increases the minimum required delay and causes the change between best-case and worst-case scenarios to increase by the same ratio.

[0033] Figure 3a An example power supply voltage glitch detection circuit 300 is shown, which provides a solution to the above problem by using a pair of clock dividers 308, 313 to extend the operating delay range with the same minimum required delay. Figure 3bA timing diagram is shown, illustrating the various signals in circuit 300. Circuit 300 includes a first flip-flop 301 having a data input 302, a clock input 303, and an output 304 for providing a glitch detection signal OUT. Delay circuit 305 has an input 306 and an output 307, with the output 307 connected to the data input 302 of the first flip-flop 301. A first clock signal divider 308 and a second clock signal divider 313 provide divided clock signals D / 2 and CLK / 2 to the clock inputs 303 of the delay circuit 305 and the first flip-flop 301, respectively. In this example, the first clock signal divider 308 and the second clock signal divider 313 include a second flip-flop 308 and a third flip-flop 313, but other arrangements are possible in alternative examples. In this example, each of the second flip-flop 308 and the third flip-flop 313 has data inputs 317 and 319, which are connected to inverted outputs 318 and 320 such that the flip-flops 308 and 313 operate as clock dividers.

[0034] A second clock signal divider 313 is connected to receive the clock signal CLK, and a first clock signal divider 308 is connected to receive an inverted version of the clock signal CLK. In this example, an inverter 311 is connected between the clock input 309 of the first clock signal divider 308 and the clock signal line 310, and the clock input 314 of the second clock signal divider 313 is directly connected to the clock signal line 310. In an alternative example, the same effect can be achieved using an inverter instead provided between the clock signal line 310 and the clock input 314 of the second clock signal divider 313, wherein the clock input 309 of the first clock signal divider 308 is directly connected to the clock signal line 310. In this example, the output 312 of the first clock signal divider 308 is connected to the input 306 of the delay circuit 305 by means of a direct connection between the output 312 of the first clock signal divider 308 and the input 306 of the delay circuit 305. The output 315 of the second clock signal divider 313 is connected to the clock input 303 of the first flip-flop 301.

[0035] Clock signal dividers 308 and 313 operate to slow down the clock input to the delay circuit 305 and the first flip-flop 301. Because clock signal dividers 308 and 313 use inverted edges, the outputs D / 2 and CLK / 2 have the same period, which is twice the period of the original clock signal CLK, and the phase difference is half the period of the original clock signal CLK. In this case, circuit 300 is therefore operable when the delay is between 0.5 and 1.5 clock cycles, making the operating delay range one clock cycle. Figure 1a It doubles the size of the circuitry, thus allowing for a wider range of process and temperature variations.

[0036] Figure 4a An alternative design for a burr detection circuit is shown, which is consistent with... Figure 3a Circuit 300 provides additional configuration margin compared to circuit 400. The components of circuit 400 are... Figure 3a The components of circuit 300 are the same, but an AND gate 401 is added between the first clock signal divider 308, the second clock signal divider 313, and the input 306 of the delay circuit 305. In this example, the first clock signal divider 308 and the second clock signal divider 313 need to be flip-flops using the inverted output 320 of the third flip-flop 313. The AND gate 401 has a first input connected to the output 312 of the second flip-flop 308 and a second input connected to the inverted output 320 and the data input 319 of the third flip-flop 313. The output of the AND gate 401 is connected to the input 306 of the delay circuit 305.

[0037] The AND gate 401 causes a half-clock cycle with a width of D / 2, such as Figure 4b As shown in the timing diagram, it provides an additional margin of half a clock cycle. In this case, the operating latency range is now from 0.5 to 2 clock cycles, covering 1.5 times the clock cycle. Because this design has Figure 1a The original simplified detector has three times the operating delay range, so circuit 400 is more configurable.

[0038] If additional delay margin is required, an additional clock signal divider can be added. Figure 5 Another alternative power supply voltage glitch detection circuit 500 is shown, which provides two additional clock signal dividers 501 and 502, extending the operating delay range from 0.5 to 4 clock cycles, resulting in an operating delay range of 3.5 clock signal cycles. Circuit 500 includes all the components of circuit 300 described above, but adds the optional AND gate 401 of circuit 400 and two additional clock signal dividers 501 and 502. In this example, the inverted clock signal received at the clock input of the first clock signal divider 308 is provided by the third clock signal divider 501, and the clock signal received at the clock input of the second clock signal divider 313 is provided by the fourth clock signal divider 502.

[0039] The third clock signal divider 501 has: a clock input 503 connected to receive an inverted clock signal; and an output 504 connected to the clock input 309 of the first clock signal divider 308 for providing the inverted clock signal to the first clock signal divider 308. The first clock signal divider 308 then further divides the divided inverted clock signal to obtain an output signal with a period four times that of the clock signal CLK at the output 312 of the first clock signal divider. The fourth clock signal divider 502 has: a clock input 505 connected to receive the clock signal CLK; and an output 506 connected to the clock input 314 of the second clock signal divider 313 for providing the divided clock signal to the second clock signal divider 313. The second clock signal divider 313 then further divides the divided clock signal to obtain an output signal also with a period four times that of the clock signal CLK at the output 315 of the second clock signal divider.

[0040] As described above in circuits 300 and 400, the third clock signal divider and the fourth clock signal divider may respectively include a fourth flip-flop 501 and a fifth flip-flop 502, wherein data inputs 507 and 509 are connected to the corresponding inverted outputs 508 and 510 in each of the fourth flip-flop 501 and the fifth flip-flop 502. Figure 5 The operation of circuit 500 is similar to that described above. Figure 4a The operation described by circuit 400, in which the divided clock signal is CLK / 4 and the inverted divided clock signal provided to delay circuit 305 is D / 4, further extends the operating delay range or margin width of circuit 500.

[0041] Table 1 below provides an overview of the detector design described above, indicating the minimum and maximum delays, margin width (i.e., the difference between the minimum and maximum delays), and sampling rate of operation, all in clock cycles.

[0042] The glitch detector circuit described in this paper has the advantage of not requiring the trimming of delay circuit 305 due to its wide operating delay margin. Another advantage is that the small area required for the circuit reduces the burden of using many such detectors throughout the safety circuit, making the detector more suitable for electromagnetic fault detection. Thus, data sampling integrity checks are achieved by using a trigger with a relative delay for sampling.

[0043] Table 1 – Overview of detector design and operating parameters.

[0044]

[0045] Unlike the circuit disclosed in US 11,321,457 B2, which also uses flip-flops and a delay with a common clock phase, the circuit disclosed herein uses opposite clock edges. Minimal operating delay can also be configured without slowing down the clock signal.

[0046] By reading this disclosure, those skilled in the art will understand other variations and modifications. Such variations and modifications may involve equivalents and other features known in the art of burr detectors and that can replace or supplement the features described herein.

[0047] Although the appended claims are directed to specific combinations of features, it should be understood that the scope of the disclosure of this invention also includes any novel feature or combination of novel features or any generalized form thereof explicitly or implicitly disclosed herein, regardless of whether it relates to the same invention as claimed in any of the present claims or whether it alleviates the same technical problem as any or all of the technical problems alleviated by this invention.

[0048] Features described in the context of multiple embodiments may also be provided in combination in a single embodiment. Conversely, for the sake of brevity, various features described in the context of a single embodiment may also be provided individually or in any suitable sub-combination. The applicant hereby reminds that new claims may be formulated based on such features and / or combinations of such features during the examination of this application or any other application derived therefrom.

[0049] For the sake of completeness, it is also stipulated that the term "comprising" does not exclude other elements or steps, the term "a" does not exclude a plurality, a single processor or other unit can perform the functions of several components recited in the claims, and the reference numerals in the claims should not be interpreted as limiting the scope of the claims.

Claims

1. A power supply voltage glitch detection circuit (300, 400, 500), characterized in that, The power supply voltage glitch detection circuit includes: The first flip-flop (301) has a data input (302), a clock input (303) and an output (304) for providing a glitch detection signal (OUT); The delay circuit (305) has an input (306) and an output (307) connected to the data input (302) of the first flip-flop (301). A first clock signal divider (308) has a clock input (309) connected to receive an inverted clock signal and an output (312) connected to the input (306) of the delay circuit (305). The second clock signal divider (313) has a clock input (314) connected to receive the clock signal (CLK) and an output (315) connected to the clock input (303) of the first flip-flop (301). The power supply voltage glitch detection circuits (300, 400, 500) are configured to cause the glitch detection signal (OUT) to change state immediately after the power supply voltage of the circuits (300, 400, 500) deviates, thereby causing a change in the delay provided by the delay circuit (305).

2. The power supply voltage glitch detection circuit (300, 400, 500) according to claim 1, characterized in that: The first clock signal divider includes a second flip-flop (308) having a data input (317) and an inverted output (318), the data input (317) being connected to the inverted output (318); and The second clock signal divider includes a third flip-flop (313) having a data input (319) and an inverted output (320), the data input (319) being connected to the inverted output (320).

3. The power supply voltage glitch detection circuit (300) according to claim 1 or claim 2, characterized in that, The power supply voltage glitch detection circuit includes an inverter (311) connected between the clock input (309) of the first clock signal divider (308) and the clock signal line (310), wherein the clock input (314) of the second clock signal divider (313) is connected to the clock signal line (310).

4. The power supply voltage glitch detection circuit according to any one of claims 1 to 3, characterized in that, The output (312) of the first clock signal divider (308) is directly connected to the input (306) of the delay circuit (305).

5. The power supply voltage glitch detection circuit (400, 500) according to claim 2 or claim 3, characterized in that, The power supply voltage glitch detection circuit further includes an AND gate (401) having a first input connected to the output (312) of the second flip-flop (308), a second input connected to the inverted output (320) and data input (319) of the third flip-flop (313), and an output connected to the input (306) of the delay circuit (305).

6. The power supply voltage glitch detector circuit (500) according to claim 1, characterized in that, The clock signal is a frequency-divided clock signal, and the detector circuit (500) further includes: A third clock signal divider (501) has a clock input (503) connected to receive an inverted clock signal and the clock input (309) connected to the first clock signal divider (308) for providing the inverted clock signal to the first clock signal divider (308); and an output (504) thereof. The fourth clock signal divider (502) has a clock input (505) connected to receive the clock signal and the clock input (309) connected to the second clock signal divider (313) for providing the divided clock signal to the second clock signal divider (313) for output (506).

7. The power supply voltage glitch detector circuit (500) according to claim 6, characterized in that: The third clock signal divider includes a fourth flip-flop (501) having a data input (507) and an inverted output (508), the data input (507) being connected to the inverted output (508); and The fourth clock signal divider includes a fifth flip-flop (502) having a data input (509) and an inverted output (510), the data input (509) being connected to the inverted output (510).

8. The power supply voltage glitch detection circuit (500) according to claim 6 or claim 7, characterized in that, The power supply voltage glitches detection circuit includes an inverter (311) connected between the clock input (503) of the third clock signal divider (501) and the clock signal line (310), wherein the clock input (505) of the fourth clock signal divider (502) is connected to the clock signal line (310).

9. The power supply voltage glitch detection circuit according to any one of claims 6 to 8, characterized in that, The output (312) of the first clock signal divider (308) is directly connected to the input (306) of the delay circuit (305).

10. A method for detecting power supply voltage glitches using a detector circuit (300, 400, 500), characterized in that, The detector circuit includes: The first flip-flop (301) has a data input (302), a clock input (303) and an output (304) for providing a glitch detection signal (OUT); The delay circuit (305) has an input (306) and an output (307) connected to the data input (302) of the first flip-flop (301). A first clock signal divider (308) has a clock input (309) connected to receive an inverted clock signal and an output (312) connected to the input (306) of the delay circuit (305). The second clock signal divider (313) has a clock input (314) connected to receive the clock signal and an output (315) connected to the clock input (303) of the first flip-flop (301). The delay circuit (305) provides a delay of at least half the clock period of the clock signal when the power supply voltage of the circuit is at the nominal level, and the glitch detection signal (OUT) changes state when the power supply voltage increases to cause the delay to drop below half the clock period.

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