Semiconductor waveguide device and forming method thereof

Abstract

The method includes: performing a first etch on a substrate, where the substrate includes six cross sections arranged in sequence to define five partitions along a first direction, where the first etch forms a first protruding region extending from first to fifth partitions and two first connection regions on both sides of the first protruding region; performing second etching on the two first connection areas to form a strip waveguide along the sixth cross section; performing third etching on the two first connection areas to form a rib waveguide along a third cross section; and performing fourth etching on the two first connection regions to form the deep-rib waveguide along the first cross section. The embodiment of the invention also relates to a semiconductor waveguide device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor waveguide devices and methods for forming the same. Background Technology

[0002] Modern technological advancements such as big data, cloud computing, cloud storage, and the Internet of Things (IoT) have driven the exponential growth of various applications in data processing and communication, including high-performance computing, data centers, and telecommunications. To address the emerging demand for high-data-rate transmission, modern semiconductor architectures can include optical elements to provide optical data links, which offer improvements in data transmission rates over existing electrical data links. When incorporating optical data links into semiconductor devices, various types of optical components can be integrated to perform different tasks. Such optical components may have different design and performance requirements. The performance of the optical device may depend on the robust integration of these optical components. Summary of the Invention

[0003] Some embodiments of this application provide a method for forming a semiconductor waveguide device, comprising: performing a first etching on a substrate, wherein the substrate includes a first cross-section, a second cross-section, a third cross-section, a fourth cross-section, a fifth cross-section, and a sixth cross-section arranged sequentially to define a first partition, a second partition, a third partition, a fourth partition, and a fifth partition along a first direction, wherein the first etching forms a first protruding region extending in the first partition to the fifth partition and two first connecting regions located on both sides of the first protruding region; performing a second etching on the two first connecting regions to form a strip waveguide along the sixth cross-section; performing a third etching on the two first connecting regions to form a rib waveguide along the third cross-section; and performing a fourth etching on the two first connecting regions to form a deep rib waveguide along the first cross-section.

[0004] Other embodiments of this application provide a method for forming a semiconductor waveguide device, comprising: performing a first etching on a substrate using a first mask layer, wherein the substrate includes a first cross-section, a second cross-section, a third cross-section, a fourth cross-section, a fifth cross-section, and a sixth cross-section arranged sequentially to define a first partition, a second partition, a third partition, a fourth partition, and a fifth partition along a first direction, wherein the first mask layer exposes a first region and a second region of the substrate extending in the first direction, and the first mask layer covers a central region of the substrate between the first region and the second region; performing a second etching on the substrate using a second mask layer, wherein the second mask layer exposes a first portion of the first region and the second region and the central region of the fifth partition, and exposes the first region and the second region... A second portion extending from the first portion and gradually tapering from the fifth partition to the third partition is performed on the substrate using a third mask layer, wherein the third mask layer exposes the third portion in the first and second regions, as well as the central region in the first, second, and third partitions, and exposes a fourth portion extending from the third portion and gradually tapering from the third partition to the fifth partition; and a fourth etching is performed on the substrate using a fourth mask layer, wherein the fourth mask layer exposes the fifth portion in the first and second regions, as well as the central region in the first partition, and exposes a sixth portion extending from the fifth portion in the first and second regions and gradually tapering from the first partition to the second partition.

[0005] Further embodiments of this application provide a semiconductor waveguide device, comprising: a substrate including a first partition, a second partition, a third partition, a fourth partition, and a fifth partition arranged sequentially in a first direction; the substrate including: a first protruding region extending from the first partition to the fifth partition in the first direction, the first protruding region having a first thickness; two first connecting regions extending in the first and second partitions in the first direction and connected from the bottom of the first protruding region to both sides of the first protruding region, wherein each of the first connecting regions includes a base portion having a second thickness less than the first thickness and a wing portion located above the base portion, the wing portion gradually tapering from the second partition to the first partition in a top view; and two second connecting regions extending in the first direction and connected from the bottom of the first protruding region to the first protruding region in the third and fourth partitions, wherein each of the second connecting regions gradually tapering from the third partition to the fourth partition in a top view. Attached Figure Description

[0006] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1A This is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure.

[0008] Figure 1B , Figure 1C and Figure 1D These are schematic cross-sectional views of deep-ribbed waveguides, ribbed waveguides, and strip waveguides according to some embodiments of this disclosure.

[0009] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E and Figure 2F This is a schematic cross-sectional view of an intermediate stage of a method for forming a semiconductor waveguide device according to some embodiments of the present disclosure.

[0010] Figure 3 This is a schematic plan view of a photomask according to some embodiments of the present disclosure.

[0011] Figure 4A This is a schematic top view of a semiconductor waveguide device according to some embodiments of the present disclosure.

[0012] Figure 4B and Figure 4C According to some embodiments of this disclosure Figure 4A The diagram shows a schematic three-dimensional view of the semiconductor waveguide device.

[0013] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E and Figure 5F According to some embodiments of this disclosure Figure 4A The diagram shows a schematic cross-sectional view of the semiconductor waveguide device.

[0014] Figure 6A This is a schematic plan view of a photomask according to some embodiments of the present disclosure.

[0015] Figure 6B This is a schematic plan view of a superimposed photomask according to some embodiments of the present disclosure.

[0016] Figure 7AThis is a schematic top view of a semiconductor waveguide device according to some embodiments of the present disclosure.

[0017] Figure 7B and Figure 7C According to some embodiments of this disclosure Figure 7A The diagram shows a schematic three-dimensional view of the semiconductor waveguide device.

[0018] Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E and Figure 8F According to some embodiments of this disclosure Figure 7A The diagram shows a schematic cross-sectional view of the semiconductor waveguide device.

[0019] Figure 9A This is a schematic plan view of a photomask according to some embodiments of the present disclosure.

[0020] Figure 9B This is a schematic plan view of a superimposed photomask according to some embodiments of the present disclosure.

[0021] Figure 10A This is a schematic top view of a semiconductor waveguide device according to some embodiments of the present disclosure.

[0022] Figure 10B and Figure 10C According to some embodiments of this disclosure Figure 7A The diagram shows a schematic three-dimensional view of the semiconductor waveguide device.

[0023] Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E and Figure 11F According to some embodiments of this disclosure Figure 10A The diagram shows a schematic cross-sectional view of the semiconductor waveguide device.

[0024] Figure 12A This is a schematic plan view of a photomask according to some embodiments of the present disclosure.

[0025] Figure 12B This is a schematic plan view of a superimposed photomask according to some embodiments of the present disclosure.

[0026] Figure 13A This is a schematic top view of a semiconductor waveguide device according to some embodiments of the present disclosure.

[0027] Figure 13B and Figure 13C According to some embodiments of this disclosure Figure 13AThe diagram shows a schematic three-dimensional view of the semiconductor waveguide device.

[0028] Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 14E and Figure 14F According to some embodiments of this disclosure Figure 13A The diagram shows a schematic cross-sectional view of the semiconductor waveguide device.

[0029] Figure 15A This is a schematic plan view of a photomask according to some embodiments of the present disclosure.

[0030] Figure 15B This is a schematic plan view of a superimposed photomask according to some embodiments of the present disclosure.

[0031] Figure 16A This is a schematic top view of a semiconductor waveguide device according to some embodiments of the present disclosure.

[0032] Figure 16B and Figure 16C According to some embodiments of this disclosure Figure 16A The diagram shows a schematic three-dimensional view of the semiconductor waveguide device.

[0033] Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 17E and Figure 17F According to some embodiments of this disclosure Figure 16A The diagram shows a schematic cross-sectional view of the semiconductor waveguide device.

[0034] Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 18E and Figure 18F This is a schematic cross-sectional view of a semiconductor waveguide device according to some embodiments of the present disclosure.

[0035] Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 19E and Figure 19F This is a schematic cross-sectional view of a semiconductor waveguide device according to some embodiments of the present disclosure.

[0036] Figure 20A , Figure 20B , Figure 20C , Figure 20D , Figure 20E and Figure 20FThis is a schematic cross-sectional view of a semiconductor waveguide device according to some embodiments of the present disclosure.

[0037] Figure 21 This is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0038] Figure 22A , Figure 22B , Figure 22C , Figure 22D , Figure 22E and Figure 22F This is a schematic cross-sectional view of a semiconductor waveguide device according to some embodiments of the present disclosure.

[0039] Figure 23 This is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0040] Figure 24A , Figure 24B , Figure 24C , Figure 24D , Figure 24E and Figure 24F This is a schematic cross-sectional view of a semiconductor waveguide device according to some embodiments of the present disclosure.

[0041] Figure 25 This is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0042] Figure 26 This is a schematic block diagram of a photomask according to some embodiments of the present disclosure.

[0043] Figure 27 A flowchart illustrating a method for manufacturing a semiconductor waveguide device according to some embodiments of the present disclosure is shown. Detailed Implementation

[0044] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0045] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0046] While the numerical ranges and parameters illustrating the broad scope of embodiments of this disclosure are approximate, the numerical values ​​described in specific embodiments are reported as precisely as possible. However, any numerical value inherently includes some error, which is necessarily caused by deviations typically found in the corresponding test measurements. Furthermore, as used herein, the terms “about,” “basically,” or “substantially” generally mean within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the terms “about,” “basically,” or “substantially” mean within an acceptable standard error of the average as considered by one of ordinary skill in the art. Except in operational / working instances, or unless explicitly stated otherwise, all numerical ranges, quantities, values, and percentages disclosed herein, such as the amount of material used for them, duration, temperature, operating conditions, ratios of quantities, etc., should be understood to be modified by the terms “about,” “basically,” or “substantially” in all instances. Therefore, unless indicated to the contrary, the numerical parameters set forth in embodiments of this disclosure and the appended claims are approximate values ​​that may vary as needed. At a minimum, each numerical parameter should be interpreted at least in light of the number of significant figures reported and by applying common rounding techniques. A range may be expressed in this document as a distance from one endpoint to another or between two endpoints. All ranges disclosed herein include endpoints unless otherwise stated.

[0047] Silicon photonics is an emerging and promising technology for advanced semiconductor manufacturing and applications such as high-performance computing, high-speed data transmission, microwave photonics, and optical sensing. Silicon photonics offers advantages such as high data transmission rates, low transmission loss, high production yield, low manufacturing costs, and high compatibility with mature complementary metal-oxide-semiconductor (CMOS) technology. In the development of silicon photonic devices, various types of photonic (optical) components are used to implement different functions and are integrated to accomplish signal transmission or processing tasks. Such photonic components can be formed with different types of waveguides. Examples of these waveguides include, for example, strip waveguides used in optical filters, ribbed waveguides used, for example, grating couplers, and deep-ribbed waveguides used, for example, microring modulators. When integrating photonic components with different types of waveguides, optical transition waveguides or similar structures may be needed to smoothly guide optical signals from one type of waveguide to another with minimal transmission loss.

[0048] In some cases, designing optical transition waveguides can be challenging when a new photonic component is incorporated into an existing photonic device. This is because when a new photonic component is introduced, it typically includes a different waveguide than the existing one on the existing photonic device, thus requiring a new transition structure (waveguide) to connect the new waveguide of the new photonic component to the existing waveguide of the existing photonic device. However, the fabrication of the new transition waveguide can affect the design parameters of the original photonic device, such as the configuration of the mask layer or the fabrication process. For example, the mask layer used to fabricate the existing photonic device may be over- or completely consumed by the additional etching process used to form the transition structure. Consequently, device reliability is significantly reduced. However, if the circuit redesign task is provided in other ways to address the parameter adjustments of the mask layer due to the impact of the transition structure on the original photonic device, the manufacturing cost and time inevitably increase.

[0049] To address the aforementioned issues, embodiments of this disclosure propose a structure and a method for forming waveguide devices that employ a transition structure to connect deep-rib waveguides and strip waveguides with minimal impact on the original design of existing photonic devices. The transition structure may include a rib waveguide located in the middle of the waveguide device between the deep-rib waveguide and the strip waveguide, wherein optical signals are guided to propagate between the deep-rib waveguide and the strip waveguide via the rib waveguide. A photomask with a suitable pattern is proposed to realize the rib waveguide and the transition waveguide between the rib waveguide and each of the deep-rib waveguide and the strip waveguide. Due to the design of the photomask used to form the deep-rib waveguide, the rib waveguide, the strip waveguide, and the transition waveguide, the impact on the original mask layer can be reduced. For example, in the region of the transition waveguide near the new photonic component including the strip waveguide, the amount of etching performed on the hard mask layer is substantially equal to the amount of etching performed on other regions of the transition waveguide near the existing photonic component including the deep-rib waveguide. This means that the design of the mask layer used to form the existing photonic component can remain unchanged without significant alteration. Furthermore, the transmission loss exhibited by the proposed transition waveguide device remains acceptable. Therefore, manufacturing costs and design cycles can be significantly reduced.

[0050] Figure 1A This is a schematic diagram of a semiconductor device 10 according to some embodiments of the present disclosure. The semiconductor device 10 may include a photonic device region 10A and an electronic device region 10B, wherein the photonic device region 10A includes a plurality of photonic devices, such as photonic devices 12 and 14, and the electronic device region 10B includes a plurality of electronic devices, such as electronic device 16. According to some embodiments, the photonic devices in the photonic device region 10A and the electronic devices in the electronic device region 10B are formed on the same substrate. According to some embodiments, photonic device 12 includes a first waveguide of a first waveguide type, such as a deep-rib waveguide. According to some embodiments, photonic device 14 includes a second waveguide of a second waveguide type, such as a strip waveguide.

[0051] According to some embodiments, the photonic device region 10A further includes a semiconductor waveguide device 100 located between and connecting photonic devices 12 and 14. The semiconductor waveguide device 100 may include three types of waveguides along different cross sections, such as deep-rib waveguides, rib waveguides, and strip waveguides, and may include transition waveguides located between the aforementioned waveguides.

[0052] Figure 1B , Figure 1C and Figure 1D These are schematic cross-sectional views of a deep-ribbed waveguide WG-dR, a ribbed waveguide WG-R, and a strip waveguide WG-S, respectively, according to some embodiments of the present disclosure. According to some embodiments, such as those derived from... Figures 1B to 1DEach of the deep-rib waveguide WG-dR, rib waveguide WG-R, and strip waveguide WG-S, defined by the dashed box, is formed in a silicon layer 24 above the dielectric layer 22. Light or optical signals are confined within the region of the silicon layer 24 within the dashed box. Each of the deep-rib waveguide WG-dR, rib waveguide WG-R, and strip waveguide WG-S includes a protruding region P1 located at its central region. According to some embodiments, each of the deep-rib waveguide WG-dR, rib waveguide WG-R, and strip waveguide WG-S includes a first support region U1 and a second support region U2 located on both sides of the protruding region P1. The protruding region P1 is separated from the first support region U1 and the second support region U2 by a first strip region S1 and a second strip region S2, respectively. Each of the deep-rib waveguide WG-dR and rib waveguide WG-R also includes a first connection region Q1 and a second connection region Q2 disposed on both sides of the bottom portion of the protruding region P1 and connected to the bottom portion of the protruding region P1. The strip waveguide WG-S consists only of an upright structure with a protruding structure P1, and there is no connecting region around the protruding region P1. According to some embodiments, the protruding region P1 of the strip waveguide WG-S has a substantially equal width W11 from the bottom to the top of the strip waveguide WG-S.

[0053] According to some embodiments, the protruding region P1 for the deep-ribbed waveguide WG-dR, ribbed waveguide WG-R, and strip waveguide WG-S has a thickness T21 between about 240 nanometers (nm) and 300 nm, for example, 270 nm, wherein the thickness T21 is substantially equal to the thickness of the silicon layer 24. The first support region U1 and the second support region U2 may have a thickness equal to the thickness T21 of the protruding region P1. According to some embodiments, the protruding region P1 has a width W11 between about 200 nm and about 500 nm, for example, 350 nm. The first strip region S1 or the second strip region S2 may have a width W13 between about 600 nm and about 3000 nm, for example, 1800 nm.

[0054] The deep-ribbed waveguide WG-dR and the ribbed waveguide WG-R have first connecting regions Q1 and second connecting regions Q2 with different thicknesses. According to some embodiments, the first connecting region Q1 or the second connecting region Q2 of the deep-ribbed waveguide WG-dR has a thickness T1 between about 50 nm and about 90 nm, for example, 70 nm. According to some embodiments, the first connecting region Q1 or the second connecting region Q2 of the ribbed waveguide WG-R has a thickness T2 between about 120 nm and about 180 nm, for example, 150 nm. According to some embodiments, the thickness T2 of the ribbed waveguide WG-R is greater than the thickness T1 of the deep-ribbed waveguide WG-dR. The ratio of the thickness T1 of the deep-ribbed waveguide WG-dR to the thickness T2 of the ribbed waveguide WG-R is between about 50% and about 80%.

[0055] Figure 2A , Figure 2B, Figure 2C , Figure 2D , Figure 2E and Figure 2F This is a schematic cross-sectional view of an intermediate stage in a method for forming a semiconductor waveguide device 100 according to some embodiments of the present disclosure. Reference Figure 2A The semiconductor waveguide device 100 includes a substrate 101 having a layer stack, the layer stack including a dielectric layer 102, a silicon layer 104, and a hard mask layer 106 (or hard mask layer) arranged from bottom to top. The semiconductor waveguide device 100 may also include a mask layer 108 above the hard mask layer 106. According to some embodiments, the dielectric layer 102 is a silicon oxide layer. According to some embodiments, the hard mask layer 106 is a silicon nitride layer. According to some embodiments, the mask layer 108 is a photosensitive layer, such as a photoresist layer.

[0056] refer to Figure 2B In the photolithography operation, a photomask PM1 is provided above the semiconductor waveguide device 100. Figure 3 This is a schematic plan view of a photomask PM1 according to some embodiments of the present disclosure. Figure 3 As shown, according to some embodiments, photomask PM1 includes an opening N1 comprising two strip regions arranged in parallel and extending in the X-axis direction. Other areas of photomask PM1 are opaque and do not have openings, including a central region C1 disposed between the two strip regions N1. According to some embodiments, the central region C1 has a width W11 measured in the Y-axis direction, while each of the strip regions N1 has a width W13 measured in the Y-axis direction. According to some embodiments, the width W15 is defined as a distance measured in the Y-axis direction between the two outer sides of the two strip regions N1.

[0057] refer to Figure 2C A radiation beam 122 is emitted from a radiation source (not shown separately) and illuminates a mask layer 108 through a photomask PM1. According to some embodiments, the radiation beam 122 includes wavelengths within a UV bandwidth. According to some embodiments where the mask layer 108 comprises a positive photoresist, a portion of the photosensitive material in region 108B of the mask layer 108 is exposed through a strip region N1 of the photomask PM1 and reacts to the radiation beam 122. The photosensitive material in region 108B is degraded by the energy of the radiation beam 122. According to some embodiments, a portion of the photosensitive material in region 108A of the mask layer 108 is covered by an opaque material of the photomask PM1, and thus such regions, for example, the central region C1, remain intact during the exposure of the mask layer 108 to the radiation beam 122. The radiation beam 122 forms patterned light on the mask layer 108 through the photomask PM1.

[0058] refer to Figure 2DA developer (not shown separately) is used to dissolve and remove the degradation regions 108B of the mask layer 108 during the development operation. An opening 108R is formed in the mask layer 108. After the development operation, the mask layer 108 is patterned to expose a portion of the upper surface of the hard mask layer 106, wherein the pattern of the photomask PM1 is transferred to the mask layer 108.

[0059] refer to Figure 2E A first etching operation is performed on the hard mask layer 106 using mask layer 108 as an etching mask. The first etching operation may include dry etching, wet etching, or combinations thereof, such as reactive ion etching (RIE). After the first etching operation, Figure 2E As shown, the pattern of photomask PM1 is further transferred to hard mask layer 106. A first etch operation extends opening 108R through hard mask layer 106 and forms grooves in the first region S1 and the second region S2 of hard mask layer 106.

[0060] According to some embodiments, the first etch operation causes the grooves of the hard mask layer 106 to extend further down into the silicon layer 104, and forms a groove 104R in the silicon layer 104. According to some embodiments, the first etch operation includes multiple etches, and the groove 104R is formed by another etch of the first etch operation using the hard mask layer 106 as an etch mask. After the first etch operation on the silicon layer 104, a pattern corresponding to the photomask PM1 is formed, comprising a protruding region P1, a first support region U1, a second support region U2, a first connection region Q1, and a second connection region Q2. According to some embodiments, the silicon layer 104 includes a thickness T21, measured in the Z-axis direction, between about 240 nanometers (nm) and about 300 nm, for example, 270 nm. According to some embodiments, the first connection region Q1 or the second connection region Q2 includes a thickness T22, measured in the Z-axis direction, between about 180 nanometers (nm) and about 240 nm, for example, 210 nm.

[0061] refer to Figure 2F After the first etching operation is completed, the mask layer 108 is removed or stripped. The mask layer 108 can be removed or stripped by plasma etching or plasma ashing.

[0062] The above reference Figures 2A to 2FThe discussed photolithography and etching operations illustrate the pattern transfer process from photomask PM1 to hard mask layer 106 and silicon layer 104. In the following paragraphs, additional iterations of the pattern transfer process are described, where the iterations utilize other photomasks, namely photomasks PM2, PM3, PM4, and PM5, to transfer more patterns onto silicon layer 104. For brevity, the deposition and removal of mask layer 108 and the exposure / development operations of photomasks PM2, PM3, PM4, and PM5 can be omitted, as the photolithography and etching operations implemented using photomasks PM2, PM3, PM4, and PM5 are similar to those described above. Figures 2A to 2F The descriptions are the same.

[0063] According to embodiments where the photosensitive material of the mask layer includes negative photoresist, the layout of the mask layer 108 can be maintained as a layout formed by the photomask PM1 and positive photoresist of the mask layer 108. The key to maintaining the same layout is to use a photomask PM11 with an inverted layout, wherein the opaque areas (openings) of the photomask PM11 correspond to the openings (opaque areas) of the photomask PM1. In this way, the photoresist material in region 108B of the mask layer 108 is not exposed to the radiation beam 122 and will be dissolved and removed during subsequent development operations. Therefore, the layout of the photomask PM1 can be successfully transferred to the mask layer 108, regardless of the type of photoresist.

[0064] Figure 4A This is a schematic top view of a semiconductor waveguide device 100 after a first etch operation using a photomask PM1, according to some embodiments of the present disclosure. Figure 4B and Figure 4C According to some embodiments of this disclosure Figure 4A The semiconductor waveguide device 100 shown is illustrated in schematic perspective views from different angles. According to some embodiments, Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E and Figure 5F They are along Figure 4A Schematic cross-sectional views of sections AA, BB, CC, DD, EE, and FF of the substrate 101 of the semiconductor waveguide device 100. Furthermore, the six sections AA, BB, CC, DD, EE, and FF define five partitions Z1, Z2, Z3, Z4, and Z5. (Reference) Figure 3 For ease of reference, photomask PM1 is also defined with six sections AA, BB, CC, DD, EE, and FF, and partitions Z1, Z2, Z3, Z4, and Z5. (Reference) Figure 1A as well as Figure 4A , Figure 4B and Figure 4CSections AA and FF can be located close to photonic devices 12 and 14, respectively. According to other embodiments, sections AA and FF can be located close to photonic devices 14 and 12, respectively.

[0065] refer to Figure 2F and Figure 4A , Figure 4B or Figure 4C It can be seen that the grooves 104R corresponding to the openings N1 of the two strip regions of the photomask PM1 are formed in the strip regions S1 and S2 of the hard mask layer 106 and the silicon layer 104, which extend across six cross-sections AA, BB, CC, DD, EE, and FF. Therefore, Figure 2F as well as Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E and Figure 5F The cross-sectional view has a profile that is substantially the same as the profiles of the protruding region P1, the first support region U1, the second support region U2, the first connecting region Q1, and the second connecting region Q2.

[0066] Figure 6A This is a schematic plan view of a photomask PM2 according to some embodiments of the present disclosure. According to some embodiments, the photomask PM2 includes an opening N2 having an inverted C-shape, having a width W21 measured in the Y-axis direction and a length L21 measured in the X-axis direction. The opening N2 includes a first portion PM21 and two second portions PM22 connected to the first portion PM21. According to some embodiments, the first portion PM21 has a substantially rectangular shape extending in partition Z5, wherein the first portion PM21 includes the width W21 and the length L22. According to some embodiments, the second portions PM22 have substantially equal shapes and areas. Each of the second portions PM22 includes a length L23 and extends from a location near section EE, through partition Z4, and to an end side A1 in partition Z3. The two second portions PM22 may be mirror images of each other with respect to an imaginary horizontal line between the two second portions PM22. Each of the two second portions PM22 gradually tapers from a first width W22 on one side of partition Z4 near cross section EE to a second width W23 on end side A1 of partition Z3 near cross section CC or the center line of substrate 101 of semiconductor waveguide device 100. The inverted C-shaped opening formed by the first portion PM21 and the two second portions PM22 includes a trapezoidal shape having two lateral sides that gradually taper from end side A1 of the second portion PM22 to the first portion PM21.

[0067] According to some embodiments, similar to the reference Figures 2A to 2FThe method described uses a photomask PM2 to perform a second etching operation on the semiconductor waveguide device 100. The second etching operation can be dry etching, wet etching, RIE, etc. Figure 7A This is a schematic top view of a semiconductor waveguide device 100 after a first etching operation and a second etching operation, according to some embodiments of the present disclosure. Figure 7B and Figure 7C According to some embodiments of this disclosure Figure 7A A schematic perspective view of the semiconductor waveguide device 100 shown. Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E and Figure 8F According to some embodiments of this disclosure Figure 7A The schematic cross-sectional view of the semiconductor waveguide device 100 shown is shown.

[0068] Figure 6B This is a schematic plan view of superimposed photomasks PM1 and PM2 according to some embodiments of the present disclosure. The plan view of superimposed photomasks PM1 and PM2 helps to show the overlapping area of ​​photomasks PM1 and PM2 more clearly. Figures 7A to 7C and Figures 8A to 8F The subtle contour variations in the thickness, height, width, or depth of the hard mask layer 106, silicon layer 104, and dielectric layer 102 shown in the cross-sectional view can correspond to such overlapping areas.

[0069] refer to Figure 6B , Figures 7A to 7C and Figures 8A to 8C Because the opening N2 of the photomask PM2 does not extend into partitions Z1 and Z2, the semiconductor waveguide device 100 extends along... Figure 8A , Figure 8B and Figure 8C The profiles of sections AA, BB, and CC shown remain consistent with... Figure 5A , Figure 5B and Figure 5C The outlines of the semiconductor waveguide devices 100 shown are substantially the same. According to some embodiments, the photomask PM2 is used to form a strip waveguide WG-S in the region around section Z5 or along section FF, and to form a transition waveguide between the strip waveguide WG-S and the rib waveguide WG-R to be formed in the region around section CC.

[0070] According to some embodiments, the opening N2 of the photomask PM2 causes the second etching operation to consume the thickness of the hard mask layer 106 in the protruding region P1, the first support region U1, and the second support region U2. (See reference...) Figure 6BOpening N2 overlaps with the first support region U1 and the second support region U2 in partitions Z3, Z4, and Z5, wherein the overlapping region has a length L21 and a width W24 measured in the Y-axis direction. Therefore, the second etching operation consumes a region of the hard mask layer 106 with a length L21 and a width W24 located on the side of the first support region U1 and the second support region U2 facing the protruding region P1. (Reference) Figure 8D , Figure 8E and Figure 8F The consumed area forms a step K1 at the upper corner of the hard mask layer 106 in each of the first support region U1 and the second support region U2. Therefore, the hard mask layer 106 includes a reduced thickness T12 at the step K1 at the corner of the first support region U1 or the second support region U2 after the second etching operation.

[0071] According to some embodiments, the first portion PM21 of the opening N2 overlaps with the entire protruding region P1 in the area surrounding partition Z5. Therefore, the second etching operation consumes the thickness of the hard mask layer 106 of the first protruding region P1 in partition Z5. (Reference) Figure 8E and Figure 8F Therefore, the hard mask layer 106 of the protruding region P1 includes a reduced thickness T12 after the second etching operation.

[0072] According to some embodiments, the first portion PM21 of the opening N2 allows for the removal of portions of the first connection region Q1 and the second connection region Q2 located within the silicon layer 104 during the second etching operation. Therefore, portions of the first connection region Q1 and the second connection region Q2 located within partition Z5 are completely removed from the silicon layer 104. The removed portion corresponds to the first portion PM21 of the opening N2. Furthermore, the semiconductor waveguide device 100 forms a strip waveguide WG-S in partition Z5 or along cross sections EE and FF. Additionally, refer to... Figure 8E and Figure 8F The hard mask layer 106 of the prominent region P1 includes a reduced thickness T12 along sections EE and FF and partition Z5, and maintains a thickness T11 outside partition Z5.

[0073] According to some embodiments, the two second portions PM22 of the opening N2 cause portions of the first connection region Q1 and the second connection region Q2 located in the silicon layer 104 to be partially removed during a second etching operation. The partially removed portions correspond to the taper shape of the second portions PM22 of the opening N2. Therefore, the remaining portions of the first connection region Q1 and the second connection region Q2, referred to herein as wing portions Q1 or Q2, are formed to include a taper shape when viewed from a top view. Reference Figure 6BWing portions Q1 and Q2 include a decreasing width W14 measured along the Y-axis from section GG in partition Z3 to a position along section EE, wherein section GG is cut at the intersection of the second portion PM22 of photomask PM2 and the strip region N1 of photomask PM1. (Reference) Figure 8D Wing portions Q1 and Q2, with a width of W14, are formed along section DD.

[0074] According to some embodiments, during the formation of wing portions Q1 and Q2, a second etching operation removes portions of the first connection region Q1 and the second connection region Q2 that lie outside the subsequently formed wing portions Q1 and Q2. A third etching operation may be performed further down to remove the thickness or depth D11 of the dielectric layer 102 during the formation of wing portions Q1 and Q2, ensuring complete removal of the silicon layer 104 in such regions. (Reference) Figure 6B The etched areas of the dielectric layer 102 correspond to the intersection points of each stripe region N1 of photomask PM2 and photomask PM1, wherein each etched area has a width W25. (Reference) Figure 8D , Figure 8E and Figure 8F The dielectric layer 102 exposed by the silicon layer 104 between the wing portion Q1 and the first support region U1 or between the wing portion Q2 and the second support region U2 has a groove with a width W25 and a depth D11, wherein the width W25 is substantially equal to the width W13 along the cross sections EE and FF.

[0075] Figure 9A This is a schematic plan view of a photomask PM3 according to some embodiments of the present disclosure. According to some embodiments, the photomask PM3 includes an opening N3 having a pencil-like shape, comprising a rectangular shape and a gradually tapering tip extending in the X-axis direction. The opening N3 includes a length L31 measured in the X-axis direction and a width W31 measured in the Y-axis direction. The opening N3 includes a first portion PM31 and a second portion PM32 connected to the first portion PM31. According to some embodiments, the first portion PM31 substantially has a rectangular shape extending in partitions Z1, Z2, and Z3, wherein the first portion PM31 includes a width W31 and a length L32. According to some embodiments, the second portion PM32 includes a length L33 and extends from a position in partition Z3, through partition Z4, and to an end side A2 in partition Z5. The second portion PM32 gradually tapers from a width W31 in the position in partition Z3 to a width W32 at the end side A2 in partition Z5.

[0076] According to some embodiments, similar to the reference Figures 2A to 2F The method described uses a photomask PM3 to perform a third etch operation on the semiconductor waveguide device 100. The third etch operation can be dry etching, wet etching, RIE, etc. Figure 10AThis is a schematic top view of a semiconductor waveguide device 100 after a first etching, a second etching, and a third etching operation according to some embodiments of the present disclosure. Figure 10B and Figure 10C According to some embodiments of this disclosure Figure 10A A schematic perspective view of the semiconductor waveguide device 100 shown. Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E and Figure 11F According to some embodiments of this disclosure Figure 10A The schematic cross-sectional view of the semiconductor waveguide device 100 shown is shown.

[0077] Figure 9B This is a schematic plan view of superimposed photomasks PM1, PM2, and PM3 according to some embodiments of the present disclosure. Reference Figure 9B , Figures 10A to 10C and Figure 11F Because the opening N3 of the photomask PM3 does not extend into the right half of section Z5 (including section FF), therefore along Figure 11F The profile of the semiconductor waveguide device 100, as shown in the cross section FF, remains consistent with... Figure 8F The semiconductor waveguide devices 100 shown have substantially the same outline. According to some embodiments, photomask PM3 is used to form a ribbed waveguide WG-R in the region surrounding section CC, and to form a transition waveguide between the ribbed waveguide WG-R and the deep ribbed waveguide WG-dR to be formed in the region surrounding section AA.

[0078] According to some embodiments, the opening N3 of the photomask PM3 causes the third etching operation to consume the thickness of the hard mask layer 106 in the protruding region P1, the first support region U1, and the second support region U2. (See reference...) Figure 9B The first portion PM31 overlaps with the first support region U1 and the second support region U2 in partitions Z1, Z2, and Z3, wherein the overlapping region has a length L31 and a width W33 measured in the Y-axis direction. Therefore, the third etching operation consumes the region of the hard mask layer 106 with a length L31 and a width W33 located on the side of the first support region U1 and the second support region U2 facing the protruding region P1. (Reference) Figure 11A , Figure 11B and Figure 11C The consumed area forms a step K2 at the upper corner of the hard mask layer 106 in each of the first support region U1 and the second support region U2. Therefore, the hard mask layer 106 includes a reduced thickness T13 at the step K1 at the upper corner of the first support region U1 or the second support region U2 after the third etching operation.

[0079] According to some embodiments, the first portion PM31 of the opening N3 overlaps with the entire protruding region P1 in the areas surrounding partitions Z1, Z2, Z3, and Z4. Therefore, the third etching operation consumes the thickness of the hard mask layer 106 of the first protruding region P1 in the entirety of partitions Z1, Z2, Z3, and Z4 and a portion of partition Z5. (Reference) Figure 11A , Figure 11B , Figure 11C and Figure 11D The hard mask layer 106 of the protruding region P1 includes a reduced thickness T13 along sections AA, BB, CC, and DD, and also includes a reduced thickness T14, wherein the thickness T14 is generated by a second etching operation and a third etching operation. Furthermore, the protruding region P1 maintains a thickness T12 in the region of partition Z5 offset from the opening N3, as can also be achieved in... Figure 11F As seen in the cross-sectional view.

[0080] According to some embodiments, the first portion PM31 of the opening N3 allows for the removal of portions of the first connection region Q1 and the second connection region Q2 located within the silicon layer 104 during the third etch operation. Therefore, the thickness of the first connection region Q1 and the second connection region Q2 in the entirety of partitions Z1 and Z2 and a portion of partition Z3 is removed from the silicon layer 104. The area of ​​thickness removed corresponds to the first portion PM31 of the opening N3. (See reference...) Figure 11A , Figure 11B and Figure 11C The first connection region Q1 and the second connection region Q2 include a reduced thickness T24 in the silicon layer 104. Therefore, the semiconductor waveguide device 100 forms a ribbed waveguide WG-R around the cross section CC.

[0081] According to some embodiments, the second portion PM32 of opening N1 further removes the thickness of the first connection region Q1 and the second connection region Q2 in the silicon layer 104 during the third etching operation. The area of ​​thickness removed corresponds to the taper shape of the second portion PM22 of opening N2, but not the taper shape of the second portion PM32 of opening N3, because the portion of the silicon layer 104 located between the taper shapes of the second portion PM22 and the second portion PM32 is removed during the second etching operation. Therefore, the wing portions Q1 and Q2 are formed to include a taper shape and thickness T24 when viewed from a top angle.

[0082] According to some embodiments, during the reduction of the thickness of the wing portions Q1 and Q2, a third etching operation can be performed further downwards such that the removal thickness or depth D12 of the dielectric layer 102 is greater than the depth D11, ensuring complete removal of the silicon layer 104 in such regions. (Reference) Figure 9BThe deeper etched area of ​​the etched dielectric layer 102 corresponds to the intersection of the tapering shape of the second portion PM22 of photomask PM2 and the tapering shape of the second portion PM32 of photomask PM3, and the deeply etched area has a width W34. (Reference) Figure 11D , Figure 11E and Figure 11F The dielectric layer 102 exposed through the silicon layer 104 has a groove with a width W34 and a depth D12, wherein the width W34 decreases to zero in the region of the partition Z5 offset from the opening N3 or along the cross section FF.

[0083] Figure 12A This is a schematic plan view of a photomask PM4 according to some embodiments of the present disclosure. According to some embodiments, the photomask PM4 includes an opening N4 having a C-shape, the opening N4 having a width W41 measured in the Y-axis direction and a length L41 measured in the X-axis direction. The opening N4 includes a first portion PM41 and two second portions PM42 connected to the first portion PM41. According to some embodiments, the first portion PM41 has a substantially rectangular shape extending into partitions Z1 and Z2, wherein the first portion PM41 includes a width W41 and a length L42. According to some embodiments, the second portions PM42 have substantially equal shapes and areas. Each of the second portions PM42 includes a length L43 and extends from a position in partition Z2 to an end side A3 in partition Z3. The two second portions PM42 may be mirror images of each other with respect to an imaginary horizontal line between the two second portions PM42. Each of the two second portions PM42 gradually tapers from a first width W42 in partition Z1 to a second width W43 on the end side A3 near the center line of the substrate 101 of the cross section CC or semiconductor waveguide device 100 in partition Z2. The C-shaped opening formed by the first portion PM41 and the two second portions PM42 includes a trapezoidal shape having two lateral sides that gradually taper from the end side A3 of the second portions PM42 to the first portion PM41.

[0084] According to some embodiments, similar to the reference Figures 2A to 2F The described method uses a photomask PM4 to perform a fourth etch operation on the semiconductor waveguide device 100. The fourth etch operation can be dry etching, wet etching, RIE, etc. Figure 13A This is a schematic top view of a semiconductor waveguide device 100 after a first etching operation, a second etching operation, a third etching operation, and a fourth etching operation, according to some embodiments of the present disclosure. Figure 13B and Figure 13C According to some embodiments of this disclosure Figure 13A A schematic perspective view of the semiconductor waveguide device 100 shown. Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 14E and Figure 14F According to some embodiments of this disclosure Figure 13A The schematic cross-sectional view of the semiconductor waveguide device 100 shown is shown.

[0085] Figure 12B This is a schematic plan view of superimposed photomasks PM1, PM2, PM3, and PM4 according to some embodiments of the present disclosure. Reference Figure 12B , Figures 13A to 13C and Figures 14C to 14F Because the opening N4 of the photomask PM4 does not extend into partitions Z3, Z4, and Z5, the semiconductor waveguide device 100 extends along... Figure 14C , Figure 14D , Figure 14E and Figure 14F The profiles of sections CC, DD, EE, and FF shown are maintained in accordance with... Figure 11C , Figure 11D , Figure 11E and Figure 11F The semiconductor waveguide devices 100 shown have substantially the same outline. According to some embodiments, photomask PM4 is used to form a deep-rib waveguide WG-dR in the region surrounding section AA, and a transition waveguide is formed between the deep-rib waveguide WG-dR and the rib waveguide WG-R formed around section CC.

[0086] According to some embodiments, the opening N4 of the photomask PM4 causes the fourth etch operation to consume the thickness of the hard mask layer 106 in the protruding region P1, the first support region U1, and the second support region U2. (See reference...) Figure 12B The opening N4 overlaps with the first support region U1 and the second support region U2 in partitions Z1 and Z2, wherein the overlapping region has a length L41 and a width W44 measured in the Y-axis direction. Therefore, the fourth etching operation further consumes the region of the hard mask layer 106 with a length L41 and a width W44 located on the side of the first support region U1 and the second support region U2 facing the protruding region P1. (Reference) Figure 14A and Figure 14B The consumed area forms a second step K3 on the top of the step K2 at the upper corner of the hard mask layer 106 in each of the first support region U1 and the second support region U2. Therefore, after the fourth etching operation, the hard mask layer 106 includes reduced thicknesses T15 and T16 at the corners of the first support region U1 or the second support region U2, respectively, at steps K2 and K3, wherein the thickness T15 is less than the thickness T16.

[0087] According to some embodiments, the first portion PM41 of the opening N4 overlaps with the entire protruding region P1 in the area surrounding section AA. Therefore, the fourth etching operation consumes the thickness of the hard mask layer 106 of the first protruding region P1 in a portion of partition Z1, including section AA. (Reference) Figure 14A Therefore, the hard mask layer 106 of the protruding region P1 includes a reduced thickness T15 after the fourth etching operation.

[0088] According to some embodiments, the first portion PM41 of the opening N4 causes the thickness of the first connection region Q1 and the second connection region Q2 in the silicon layer 104 to be removed during the fourth etching operation. Therefore, the thickness of the first connection region Q1 and the second connection region Q2 in the partition Z1 is removed from the silicon layer 104. The region with the removed thickness corresponds to the first portion PM41 of the opening N4. The remaining portion of the first connection region Q1 or the second connection region Q2 has a thickness T25. Furthermore, refer to... Figure 14A The semiconductor waveguide device 100 forms a deep-ribbed waveguide WG-dR with a thickness T25 in partition Z1 or along cross section AA, having a first connection region Q1 or a second connection region Q2.

[0089] According to some embodiments, the two second portions PM42 of the opening N4 cause the thickness of the first connection region Q1 and the second connection region Q2 in the silicon layer 104 to be removed during the fourth etching operation. The area of ​​removed thickness corresponds to the taper shape of the second portions PM42 of the opening N4. Therefore, the remaining portions of the first connection region Q1 and the second connection region Q2 include corresponding base portions Q11 and Q21 having a thickness T25 and corresponding wing portions Q21 or Q22 located above the base portions Q11 and Q21. From a top view, the wing portions Q21 and Q22 are formed to include a taper shape. Reference Figure 12B Wing portions Q21 and Q22 include a decreasing width W44 measured in the Y-axis direction from section HH in partition Z2 to section II, wherein section HH is cut at the intersection of the second portion PM42 of photomask PM4 and the strip region N1 of photomask PM1, and section II is cut at the interface between the first portion PM41 and the second portion PM42. (Reference) Figure 14B Wing portions Q21 and Q22, with a width of W44, are formed along section DD.

[0090] Figure 15A This is a schematic plan view of a photomask PM5 according to some embodiments of the present disclosure. Figure 15AAs shown, according to some embodiments, the photomask PM5 includes an opening N5 comprising two strip regions arranged in parallel and extending in the X-axis direction. Other areas of the photomask PM5 are opaque and do not have openings, including a central region C2 disposed between the two strip regions N5. According to some embodiments, each strip region N5 has a width W51 measured in the Y-axis direction, and the central region C2 has a width W52 measured in the Y-axis direction. According to some embodiments, the width W51 is defined as the distance measured in the Y-axis direction between the two outer sides of the first support region U1 and the second support region U2.

[0091] According to some embodiments, similar to the reference Figures 2A to 2F The method described uses photomask PM5 to perform a fifth etch operation on semiconductor waveguide device 100. The fifth etch operation can be dry etching, wet etching, RIE, etc. Figure 16A This is a schematic top view of a semiconductor waveguide device 100 after a first etching operation, a second etching operation, a third etching operation, a fourth etching operation, and a fifth etching operation, according to some embodiments of the present disclosure. Figure 16B and Figure 16C According to some embodiments of this disclosure Figure 16A A schematic perspective view of the semiconductor waveguide device 100 shown. Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 17E and Figure 17F According to some embodiments of this disclosure Figure 16A The schematic cross-sectional view of the semiconductor waveguide device 100 shown is shown.

[0092] Figure 15B This is a schematic plan view of superimposed photomasks PM1, PM2, PM3, PM4, and PM5 according to some embodiments of the present disclosure. Reference Figure 15B , Figures 16A to 16C and Figures 17A to 17F Because the opening N5 of the photomask PM5 penetrates through partitions Z1 to Z5 and does not extend into the main regions of the semiconductor waveguide device 100 corresponding to the photomasks PM1 to PM4 discussed above, the semiconductor waveguide device 100 extends along the main regions respectively. Figures 17A to 17F The profiles of sections AA, BB, CC, DD, EE, and FF shown are maintained in accordance with... Figures 14A to 14F The outlines shown are substantially the same. According to some embodiments, photomask PM5 is used to form an isolation region surrounding semiconductor waveguide device 100 across cross sections AA to FF.

[0093] According to some embodiments, the opening N5 of the photomask PM5 causes the fifth etch operation to consume the entire hard mask layer 106 and the entire silicon layer 104 in the outer regions of the first support region U1 and the second support region U2. A dielectric layer 102 with a width W41 is exposed through the first support region U1 and the second support region U2. Therefore, after the fifth etch operation, the first support region U1 and the second support region U2 comprise a width W53 measured in the Y-axis direction. One or more recesses 102R are formed during the fifth etch operation. (Reference) Figure 1A and Figure 16B According to some embodiments, the width W51 is determined to adapt to the layout of the photonic device region to remove excess areas of the first support region U1 and the second support region U2, so as to keep their width W53 within a predetermined range. In this way, the components of the semiconductor waveguide device 100 can be protected from external interference.

[0094] Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 18E and Figure 18F This is a schematic cross-sectional view of a semiconductor waveguide device 100 according to some embodiments of the present disclosure. A dielectric layer 112 is deposited over the semiconductor waveguide device 100. The dielectric layer 112 may include silicon oxide or other suitable dielectric materials. The dielectric layer 112 may include the same material as dielectric layer 102. According to some embodiments, the dielectric layer 112 fills the grooves 104R in the first region S1 and the second region S2. The dielectric layer 112 may be deposited over the protruding region P1, the first support region U1, and the second support region U2. The dielectric layer 112 may also fill the groove 102R. According to some embodiments, prior to the deposition of the dielectric layer 112, another dielectric layer (not shown separately) is deposited conformally on the upper surface and sidewalls of the components of the semiconductor waveguide device 100. Such additional dielectric layers may be used to improve the physical or optical properties of the dielectric layer 112.

[0095] Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 19E and Figure 19FThis is a schematic cross-sectional view of a semiconductor waveguide device 100 according to some embodiments of the present disclosure. A planarization operation is performed on the semiconductor waveguide device 100. The planarization operation may include mechanical polishing, chemical mechanical planarization (CMP), or another suitable planarization or polishing operation. During the planarization operation, the upper surface of the semiconductor waveguide device 100 is planarized. According to some embodiments, a hard mask layer 106 serves as an etch stop layer for the planarization operation. After the planarization operation is completed, the mask layer 106 on the protruding region P1 can protect the underlying silicon layer 104 from damage. According to some embodiments, the regions of the first support region U1 and the second support region U2 are made large enough to ensure that the total area of ​​the hard mask layer 106 of the semiconductor waveguide device 100 can be used as an etch stop layer. Otherwise, if the regions of the first support region U1 and the second support region U2 are not large enough, the hard mask layer 106 above the protruding region P1 may not be able to serve as an etch stop layer for the planarization operation.

[0096] Figure 20A , Figure 20B , Figure 20C , Figure 20D , Figure 20E and Figure 20F This is a schematic cross-sectional view of a semiconductor waveguide device 100 according to some embodiments of the present disclosure. An etching operation is performed to remove the remainder of the hard mask layer 106 above the silicon layer. The etching operation may include wet etching using hydrofluoric acid (HF). After the etching operation, the silicon layer 104 in the protruding region P1, the first support region U1, and the second support region U2 is exposed. According to some embodiments, another etching operation is performed to reduce the thickness of the dielectric layer 112. Such other etching operations may include wet etching.

[0097] Figure 21 This is a schematic cross-sectional view of a semiconductor device 10 according to some embodiments of the present disclosure. Reference Figure 1A and Figure 21 Semiconductor waveguide device 100 is formed together with other silicon photonic devices (such as photonic devices 12 and 14) in photonic device region 10A. According to some embodiments, multiple electronic devices, such as electronic device 16, are formed in electronic device region 10B. Photonic device region 10A and electronic device region 10B may share a common substrate 101, such as a common dielectric layer 102 and a common silicon layer 104. According to some embodiments, electronic device 16 includes at least one transistor, wherein the transistor includes a doped region 202 (e.g., a well region, source / drain region, etc.) formed in silicon layer 104 and a conductive region 204 disposed above the doped region 202. According to some embodiments, the upper surface of silicon layer 104 has a substantially uniform height across photonic device region 10A and electronic device region 10B.

[0098] Figure 22A , Figure 22B , Figure 22C , Figure 22D , Figure 22E and Figure 22F This is a schematic cross-sectional view of a semiconductor waveguide device 100 according to some embodiments of the present disclosure. An interlayer dielectric (ILD) layer 114 is formed over a silicon layer 104 in a photonic device region 10A. The ILD layer 114 may include a dielectric material, such as silicon oxide. The ILD layer 114 may be formed using a deposition operation followed by a planarization operation.

[0099] Figure 23 This is a schematic cross-sectional view of a semiconductor device 10 according to some embodiments of the present disclosure. According to some embodiments, an ILD layer 114 is formed over a silicon layer 104 in an electronics region 10B. The ILD layer 114 may laterally surround a conductive region 204 of the electronics 16. One or more conductive vias or pads may be formed in the ILD layer 114 to electrically interconnect components of the electronics 16 or to electrically connect components of the electronics 16 to an overlying layer. According to some embodiments, the ILD layer 114 spans the photonics device region 10A and the electronics region 10B and includes substantially equal height or thickness.

[0100] Figure 24A , Figure 24B , Figure 24C , Figure 24D , Figure 24E and Figure 24F This is a schematic cross-sectional view of a semiconductor waveguide device 100 according to some embodiments of the present disclosure. Figure 25 This is a schematic cross-sectional view of a semiconductor device 10 according to some embodiments of the present disclosure. According to some embodiments, an interconnect layer 116 is formed over an ILD layer 114 in a photonic device region 10A and an electronic device region 10B. The interconnect layer 116 may include a plurality of metal line layers and a plurality of metal via layers, wherein a metal line in one metal line layer is electrically connected to a metal line in an adjacent metal line layer through a metal via in a metal via layer between adjacent metal line layers. The metal lines and metal vias are interconnected to form wiring paths for electronic devices in the electronic device region 10B. Such metal lines may extend through the photonic device region 10A in the interconnect layer between different partitions of the electronic device region 10B. According to some embodiments, the interconnect layer 116 also includes an insulating material that electrically insulates the metal lines and metal vias. The insulating material may include silicon oxide, silicon nitride, or other suitable dielectric materials.

[0101] Figure 26This is a schematic block diagram of parallel-arranged photomasks PM1, PM2, PM3, and PM4 according to some embodiments of the present disclosure. As discussed above, according to some embodiments, a deep-ribbed waveguide WG-dR is formed around section AA, a strip waveguide WG-S is formed around section FF, and a ribbed waveguide WG-R is formed around section CC. Transition waveguides are formed in partitioned regions between the deep-ribbed waveguide WG-dR and the ribbed waveguide WG-R, and between the ribbed waveguide WG-R and the strip waveguide WG-S. Therefore, the proposed semiconductor waveguide device 100 includes a three-waveguide structure having a ribbed waveguide WG-R disposed between the deep-ribbed waveguide WG-dR and the strip waveguide WG-S. Furthermore, from Figure 26 It can be seen that the total amount of etching operations performed in each partition or each cross section is similar to each other. In other words, due to the careful design of the layout of photomasks PM1, PM2, PM3, and PM4, the exposed areas in each of the four etching operations are carefully calculated, and therefore, any area of ​​the semiconductor waveguide device 100 undergoes approximately three times the amount of etching performed during the first, second, third, and fourth etching operations. The area around the cross section FF used to form a new photonic assembly with strip waveguide WG-S can also be controlled to receive an etching amount substantially equal to that performed on the area around the cross section AA used to form an existing photonic assembly with deep rib waveguide WG-dR. Therefore, it is not necessary to redesign the manufacturing parameters of the hard mask layer 106, and thus manufacturing costs and time can be saved.

[0102] Figure 27 A flowchart of a method 2700 for manufacturing a semiconductor waveguide device according to some embodiments of the present disclosure is shown. It should be understood that additional steps may be provided before, during, and after the steps in method 2700, and some of the steps described below may be replaced or eliminated together with other embodiments. Figure 27 The order of the steps shown can be interchanged. Some of the steps can be performed simultaneously or independently.

[0103] In step 2702, a first etching is performed on the substrate using a first mask layer to form a first protruding region extending from a first partition to a fifth partition and two first connection regions located on either side of the first protruding region. According to some embodiments, the substrate includes a first cross-section, a second cross-section, a third cross-section, a fourth cross-section, a fifth cross-section, and a sixth cross-section arranged sequentially to define the first partition, the second partition, the third partition, the fourth partition, and the fifth partition along a first direction. According to some embodiments, the first mask layer exposes a first region and a second region of the substrate extending in the first direction, and the first mask layer covers a central region of the substrate between the first region and the second region.

[0104] In step 2704, a second etching is performed on the two first connection regions using a second mask layer to form a strip waveguide along the sixth cross section. According to some embodiments, the second mask layer exposes a first portion of the first strip region and the central region of the fifth partition in the second strip region, and exposes a second portion of the first strip region and the second strip region that extends from the first portion and gradually tapers from the fifth partition to the third partition.

[0105] In step 2706, a third etching is performed on the two first connection regions using a third mask layer to form a ribbed waveguide along a third cross section. According to some embodiments, the third mask layer exposes a third portion in the first and second regions, as well as the central region in the first, second, and third partitions, and exposes a fourth portion extending from the third portion and gradually tapering from the third partition to the fifth partition.

[0106] In step 2708, a fourth etch is performed on the two first connection regions using a fourth mask layer to form a deep-ribbed waveguide along the first cross-section. According to some embodiments, the fourth mask layer exposes a fifth portion in the first and second regions, as well as a central region in the first partition, and exposes a sixth portion in the first and second regions that extends from the fifth portion and gradually tapers from the first partition to the second partition.

[0107] In step 2710, an ILD layer is formed over the substrate.

[0108] In step 2712, an interconnect layer is formed above the ILD layer.

[0109] According to an embodiment, the method includes: performing a first etching on a substrate, wherein the substrate includes a first cross-section, a second cross-section, a third cross-section, a fourth cross-section, a fifth cross-section, and a sixth cross-section arranged sequentially to define a first partition, a second partition, a third partition, a fourth partition, and a fifth partition along a first direction, wherein the first etching forms a first protruding region extending from the first partition to the fifth partition and two first connecting regions located on both sides of the first protruding region; performing a second etching on the two first connecting regions to form a strip waveguide along the sixth cross-section; performing a third etching on the two first connecting regions to form a rib waveguide along the third cross-section; and performing a fourth etching on the two first connecting regions to form a deep rib waveguide along the first cross-section.

[0110] According to an embodiment, the method includes: performing a first etching on a substrate using a first mask layer, wherein the substrate includes a first cross-section, a second cross-section, a third cross-section, a fourth cross-section, a fifth cross-section, and a sixth cross-section arranged sequentially to define a first partition, a second partition, a third partition, a fourth partition, and a fifth partition along a first direction, wherein the first mask layer exposes a first region and a second region of the substrate extending in the first direction, and the first mask layer covers a central region of the substrate between the first region and the second region; performing a second etching on the substrate using a second mask layer, wherein the second mask layer exposes a first portion of the first region and the second region and a central region in the fifth partition, and exposes the first region and the second region... The second region extends from the first portion and gradually tapers from the fifth partition to the third partition; a third etching is performed on the substrate using a third mask layer, wherein the third mask layer exposes the third portion in the first and second regions and the central region in the first and second partitions, and exposes a fourth portion extending from the third portion and gradually tapers from the third partition to the fifth partition; and a fourth etching is performed on the substrate using a fourth mask layer, wherein the fourth mask layer exposes the fifth portion in the first and second regions and the central region in the first partition, and exposes a sixth portion extending from the fifth portion in the first and second regions and gradually tapers from the first partition to the second partition.

[0111] According to an embodiment, the semiconductor waveguide device includes: a substrate comprising a first partition, a second partition, a third partition, a fourth partition, and a fifth partition arranged sequentially in a first direction. The substrate includes: a first protruding region extending from the first partition to the fifth partition in the first direction, the first protruding region having a first thickness; two first connecting regions extending in the first and second partitions in the first direction and connected from the bottom of the first protruding region to both sides of the first protruding region, wherein each of the first connecting regions includes the base portion having a second thickness less than the first thickness and a wing portion located above the base portion, the wing portion gradually tapering from the second partition to the first partition in a top view; and two second connecting regions extending in the first direction and connected from the bottom of the first protruding region to the first protruding region in the third and fourth partitions, wherein each of the second connecting regions gradually tapers from the third partition to the fourth partition in a top view.

[0112] Some embodiments of this application provide a method for forming a semiconductor waveguide device, comprising: performing a first etching on a substrate, wherein the substrate includes a first cross-section, a second cross-section, a third cross-section, a fourth cross-section, a fifth cross-section, and a sixth cross-section arranged sequentially to define a first partition, a second partition, a third partition, a fourth partition, and a fifth partition along a first direction, wherein the first etching forms a first protruding region extending in the first partition to the fifth partition and two first connecting regions located on both sides of the first protruding region; performing a second etching on the two first connecting regions to form a strip waveguide along the sixth cross-section; performing a third etching on the two first connecting regions to form a rib waveguide along the third cross-section; and performing a fourth etching on the two first connecting regions to form a deep rib waveguide along the first cross-section.

[0113] In some embodiments, the substrate includes a dielectric layer, a silicon layer above the dielectric layer, and a hard mask layer above the silicon layer. In some embodiments, the ribbed waveguide includes a first protruding region and two second connection regions connected to the first protruding region, wherein the two second connection regions have a first thickness. In some embodiments, the deep ribbed waveguide includes the first protruding region and two third connection regions connected to the first protruding region, wherein the two third connection regions have a second thickness less than the first thickness. In some embodiments, after the first etching, the third etching, and the fourth etching, the silicon layer includes a first transition waveguide between the deep ribbed waveguide and the ribbed waveguide, wherein the first transition waveguide includes a first protruding region and two fourth connection regions connected to the first protruding region, wherein each of the fourth connection regions includes a base portion having the second thickness and a first wing portion above the base portion. In some embodiments, viewed from a top view, the first wing portion tapers gradually from the ribbed waveguide to the deep ribbed waveguide. In some embodiments, the strip waveguide includes the first protruding region and has a substantially equal width from the bottom to the top of the strip waveguide. In some embodiments, after the first etching, the second etching, and the third etching, the silicon layer includes a second transition waveguide located between the rib waveguide and the strip waveguide, wherein the second transition waveguide includes the first protruding region and two fifth connection regions connected to the first protruding region, wherein each of the fifth connection regions tapers from the rib waveguide to the strip waveguide. In some embodiments, the second etching creates a first groove of a first depth in the dielectric layer of the third, fourth, and fifth partitions. In some embodiments, the third etching causes a portion of the first groove to be etched to a second depth in the dielectric layer of the third and fourth partitions.

[0114] Other embodiments of this application provide a method for forming a semiconductor waveguide device, comprising: performing a first etching on a substrate using a first mask layer, wherein the substrate includes a first cross-section, a second cross-section, a third cross-section, a fourth cross-section, a fifth cross-section, and a sixth cross-section arranged sequentially to define a first partition, a second partition, a third partition, a fourth partition, and a fifth partition along a first direction, wherein the first mask layer exposes a first region and a second region of the substrate extending in the first direction, and the first mask layer covers a central region of the substrate between the first region and the second region; performing a second etching on the substrate using a second mask layer, wherein the second mask layer exposes a first portion of the first region and the second region and the central region of the fifth partition, and exposes the first region and the second region... A second portion extending from the first portion and gradually tapering from the fifth partition to the third partition is performed on the substrate using a third mask layer, wherein the third mask layer exposes the third portion in the first and second regions, as well as the central region in the first, second, and third partitions, and exposes a fourth portion extending from the third portion and gradually tapering from the third partition to the fifth partition; and a fourth etching is performed on the substrate using a fourth mask layer, wherein the fourth mask layer exposes the fifth portion in the first and second regions, as well as the central region in the first partition, and exposes a sixth portion extending from the fifth portion in the first and second regions and gradually tapering from the first partition to the second partition.

[0115] In some embodiments, the substrate includes a silicon layer, wherein the first etching forms a first protruding region, two first connection regions, a first support region, and a second support region in the silicon layer, wherein the first support region and the second support region are respectively connected to the first protruding region through the two first connection regions. In some embodiments, the substrate further includes a hard mask layer located above the silicon layer, wherein the second etching forms a first step at a first corner of the hard mask layer of the first support region or the second support region facing the first protruding region of the third, fourth, and fifth partitions. In some embodiments, the third etching forms a second step at a second corner of the hard mask layer of the first support region or the second support region facing the first protruding region of the first and second partitions. In some embodiments, the fourth etching forms a third step on the second step at the second corner. In some embodiments, the second mask layer covers the first and second regions of the substrate in the first and second partitions, as well as the central region. In some embodiments, the fourth mask layer covers the first and second regions of the third, fourth, and fifth partitions, as well as the central region.

[0116] Further embodiments of this application provide a semiconductor waveguide device, comprising: a substrate including a first partition, a second partition, a third partition, a fourth partition, and a fifth partition arranged sequentially in a first direction; the substrate including: a first protruding region extending from the first partition to the fifth partition in the first direction, the first protruding region having a first thickness; two first connecting regions extending in the first and second partitions in the first direction and connected from the bottom of the first protruding region to both sides of the first protruding region, wherein each of the first connecting regions includes a base portion having a second thickness less than the first thickness and a wing portion located above the base portion, the wing portion gradually tapering from the second partition to the first partition in a top view; and two second connecting regions extending in the first direction and connected from the bottom of the first protruding region to the first protruding region in the third and fourth partitions, wherein each of the second connecting regions gradually tapering from the third partition to the fourth partition in a top view.

[0117] In some embodiments, the semiconductor waveguide device is configured to form a ribbed waveguide in a first cross-section between the second and third partitions. In some embodiments, the semiconductor waveguide device is configured to form a deep ribbed waveguide in a second cross-section in the first partition and a strip waveguide in a third cross-section in the fifth partition.

[0118] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for forming a semiconductor waveguide device, comprising: A first etching is performed on a substrate, wherein the substrate includes a first cross section, a second cross section, a third cross section, a fourth cross section, a fifth cross section, and a sixth cross section arranged sequentially to define a first partition, a second partition, a third partition, a fourth partition, and a fifth partition along a first direction, wherein the first etching forms a first protruding region extending in the first partition to the fifth partition and two first connecting regions located on both sides of the first protruding region; A second etching is performed on the two first connection regions to form a strip waveguide along the sixth cross section; A third etching is performed on the two first connection regions to form a ribbed waveguide along the third cross-section; and A fourth etching is performed on the two first connection regions to form a deep-ribbed waveguide along the first cross section.

2. The method according to claim 1, wherein, The substrate includes a dielectric layer, a silicon layer above the dielectric layer, and a hard mask layer above the silicon layer.

3. The method according to claim 2, wherein, The ribbed waveguide includes a first protruding region and two second connecting regions connected to the first protruding region, wherein the two second connecting regions have a first thickness.

4. The method according to claim 3, wherein, The deep-ribbed waveguide includes a first protruding region and two third connecting regions connected to the first protruding region, wherein the two third connecting regions have a second thickness less than the first thickness.

5. The method according to claim 4, wherein, After the first etching, the third etching, and the fourth etching, the silicon layer includes a first transition waveguide located between the deep rib waveguide and the rib waveguide, wherein the first transition waveguide includes a first protruding region and two fourth connection regions connected to the first protruding region, wherein each of the fourth connection regions includes a substrate portion having the second thickness and a first wing portion located above the substrate portion.

6. The method according to claim 5, wherein, From a top view, the first wing portion gradually tapers from the rib waveguide to the deep rib waveguide.

7. The method according to claim 2, wherein, The strip waveguide includes the first protruding region and has a substantially equal width from the bottom to the top of the strip waveguide.

8. The method according to claim 7, wherein, After the first etching, the second etching, and the third etching, the silicon layer includes a second transition waveguide located between the rib waveguide and the strip waveguide, wherein the second transition waveguide includes the first protruding region and two fifth connection regions connected to the first protruding region, wherein each of the fifth connection regions gradually tapers from the rib waveguide to the strip waveguide.

9. A method for forming a semiconductor waveguide device, comprising: A first etching is performed on a substrate using a first mask layer, wherein the substrate includes a first cross section, a second cross section, a third cross section, a fourth cross section, a fifth cross section, and a sixth cross section arranged sequentially to define a first partition, a second partition, a third partition, a fourth partition, and a fifth partition along a first direction, wherein the first mask layer is exposed on a first region and a second region of the substrate extending in the first direction, and the first mask layer covers a central region of the substrate between the first region and the second region; A second etching is performed on the substrate using a second mask layer, wherein the second mask layer exposes a first portion of the first region and the second region and the central region of the fifth partition, and exposes a second portion of the first region and the second region that extends from the first portion and gradually tapers from the fifth partition to the third partition; A third etching is performed on the substrate using a third mask layer, wherein the third mask layer exposes a third portion of the first region and the second region, as well as the central region of the first partition, the second partition, and the third partition, and exposes a fourth portion extending from the third portion and gradually tapering from the third partition to the fifth partition; and A fourth etching is performed on the substrate using a fourth mask layer, wherein the fourth mask layer exposes a fifth portion in the first region and the second region, as well as the central region in the first partition, and exposes a sixth portion in the first region and the second region that extends from the fifth portion and gradually tapers from the first partition to the second partition.

10. A semiconductor waveguide device, comprising: A substrate comprising a first partition, a second partition, a third partition, a fourth partition, and a fifth partition arranged sequentially in a first direction, the substrate comprising: A first protruding region extends from the first partition to the fifth partition in the first direction, and the first protruding region has a first thickness; Two first connecting regions extend in the first direction in the first partition and the second partition, and connect from the bottom of the first protruding region to both sides of the first protruding region, wherein each of the first connecting regions includes a base portion having a second thickness less than the first thickness and a wing portion located above the base portion, the wing portion gradually tapering from the second partition to the first partition when viewed from a top angle; and Two second connecting regions extend in the first direction and connect from the bottom of the first protruding region to the first protruding region in the third and fourth partitions, wherein, viewed from a top view, each of the second connecting regions gradually tapers from the third partition to the fourth partition.

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