Low-temperature-drift segmented compensation band-gap reference circuit

Abstract

The invention relates to a low-temperature-drift segmented compensation band-gap reference circuit, and relates to the field of analog integrated circuit design. According to the technical scheme, by designing the linear segmentation compensation circuit, two segments of linear compensation currents matched with the temperature can be output, and the linear compensation currents are accurately overlaid on the parabola type temperature characteristic voltage with the downward opening output by the first-order compensation band-gap reference circuit. The two sections of compensation current respectively correspond to a low-temperature interval and a high-temperature interval to realize targeted compensation, an intermediate temperature area has no additional compensation interference, and the influence caused by high-order nonlinear temperature distortion is effectively counteracted through accurate adaptation and characteristic superposition of the temperature intervals. Compared with a traditional first-order compensation scheme, the temperature drift of the band-gap reference voltage can be remarkably restrained without a complex topological structure, the band-gap reference voltage source is suitable for wide-temperature-range application scenes, and a stable reference is provided for follow-up devices such as a low-dropout linear voltage stabilizer and a high-precision analog-digital converter.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit design technology, and in particular to a low-temperature drift segmented compensation bandgap reference circuit. Background Technology

[0002] In the fields of analog and mixed-signal integrated circuits, bandgap reference circuits are indispensable core modules. Their function is to provide the entire electronic system with a stable and accurate voltage or current reference signal that is minimally affected by environmental factors. Their performance directly determines the operating accuracy, stability, and long-term reliability of subsequent circuit stages. These circuits are widely used in core devices and modules such as low-dropout linear regulators, analog-to-digital converters, digital-to-analog converters, sensor interface circuits, RF transceivers, memory, and various high-precision measuring instruments, covering multiple strategically critical fields including consumer electronics, industrial control, automotive electronics, medical equipment, and aerospace.

[0003] Bandgap reference circuits have a variety of classic topologies. The core principle of traditional bandgap reference circuits is to use the negative temperature coefficient characteristic of the bipolar transistor itself and the positive temperature coefficient characteristic generated by the base-emitter voltage difference of the two bipolar transistors to perform weighted superposition, thereby canceling out the characteristics to achieve a stable reference voltage output that is not sensitive to temperature.

[0004] In practical circuit design, the negative temperature coefficient characteristic of bipolar transistors (BPTs) is difficult to achieve the ideal first-order linearity, and their temperature response curves exhibit significant high-order nonlinear curvature distortion. This non-ideal characteristic inevitably introduces second-order and higher-order temperature coefficients into the output voltage of bandgap reference circuits, severely limiting the improvement of bandgap reference accuracy.

[0005] Therefore, in order to further improve the temperature stability of the reference circuit, it is necessary to design a targeted temperature coefficient compensation scheme, and to suppress the influence of high-order temperature coefficients by introducing a segmented compensation circuit, so as to optimize and upgrade the accuracy of the bandgap reference. Summary of the Invention

[0007] The purpose of this invention is to provide a low-temperature drift segmented compensation bandgap reference circuit to solve the problems existing in the prior art.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows: In a first aspect, the present invention provides a low-temperature drift segmented compensation bandgap reference circuit, including a startup circuit, a first-order compensation bandgap reference circuit, a segmented compensation circuit, and a bias circuit. The startup circuit is electrically connected to the first-order compensated bandgap reference circuit. The startup circuit is used to inject current into the first-order compensated bandgap reference circuit when it is powered on so that it moves away from the degeneracy point. The first-order compensated bandgap reference circuit is electrically connected to the segmented compensation circuit. The first-order compensated bandgap reference circuit is used to provide a bandgap reference voltage to eliminate the first-order temperature coefficient and to provide a connection node for the segmented compensation circuit. The segmented compensation circuit is electrically connected to the bias circuit, and the segmented compensation circuit is used to provide a linear segmented compensation current for the bandgap reference voltage; The bias circuit is electrically connected to the first-order compensated bandgap reference circuit and the segmented compensation circuit, respectively, to provide stable bias voltage for both.

[0009] In some embodiments, the startup circuit includes a first PMOS transistor MP1, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a first resistor R1; One end of the first resistor R1 is connected to the power supply voltage Vref, and the other end is connected to the drain of the first NMOS transistor MN1; The gate of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2 are both connected to the drain of the first NMOS transistor MN1. The gate of the first PMOS transistor MP1 is connected to the control signal VOEN, the source of the first PMOS transistor MP1 is connected to the power supply voltage Vref, and the drain of the first PMOS transistor MP1 is connected to the drain of the second NMOS transistor MN2. The source of the first NMOS transistor MN1 is connected to the drain of the third NMOS transistor MN3 and the gate of the third NMOS transistor MN3. The source of the third NMOS transistor MN3 is connected to the drain and gate of the fourth NMOS transistor MN4. The source of the fourth NMOS transistor MN4 is connected to the drain and gate of the fifth NMOS transistor MN5. The source of the fifth NMOS transistor MN5 is connected to the drain of the sixth NMOS transistor MN6, and the gate of the sixth NMOS transistor MN6 is connected to the control signal VOE. The source of the second NMOS transistor MN2 is connected to the first-order compensated bandgap reference circuit.

[0010] In some embodiments, the first-order compensated bandgap reference circuit includes a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a first transistor QN1, a second transistor QN2, a third transistor QN3, a fourth transistor QN4, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9. One end of the second resistor R2 is connected to the power supply voltage Vref, and the other end is simultaneously connected to the source of the second PMOS transistor MP2, the source of the third PMOS transistor MP3, and the source of the fourth PMOS transistor MP4. The gate connection control signal OEN of the fourth PMOS transistor MP4; The gate of the second PMOS transistor MP2 and the gate of the third PMOS transistor MP3 are both connected to the drain of the second PMOS transistor MP2. The drain of the second PMOS transistor MP2 is connected to the drain of the seventh NMOS transistor MN7, and the drain of the third PMOS transistor MP3 is connected to the drain of the eighth NMOS transistor MN8, one end of the third resistor R3, and the gate of the tenth NMOS transistor MN10. The other end of the third resistor R3 is connected to the gate of the seventh NMOS transistor MN7 and the gate of the eighth NMOS transistor MN8. The source of the seventh NMOS transistor MN7 is connected to the collector of the first transistor QN1, the source of the eighth NMOS transistor MN8 is connected to the collector of the second transistor QN2, and the emitters of the first transistor QN1 and the second transistor QN2 are both grounded. The base of the first transistor QN1 and the base of the second transistor QN2 are both connected to the collector of the fourth transistor QN4; The drain of the tenth NMOS transistor MN10 is connected to the drain of the fourth PMOS transistor MP4, and the source of the tenth NMOS transistor MN10 is simultaneously connected to one end of the fifth resistor R5 and the source and drain of the eleventh NMOS transistor MN11. The gate of the eleventh NMOS transistor MN11 is simultaneously connected to the base of the third transistor QN3 and one end of the fourth resistor R4. The other end of the fourth resistor R4 is simultaneously connected to the collector of the third transistor QN3 and the base of the fourth transistor QN4; The fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 are connected in series. The two ends of the sixth resistor R6 are connected to the segmented compensation circuit, and the other end of the eighth resistor R8 is connected to the collector of the fourth transistor QN4. The emitter of the third transistor QN3 and the emitter of the fourth transistor QN4 are both connected to one end of the ninth resistor R9, and the other end of the ninth resistor R9 is grounded.

[0011] In some embodiments, the segmented compensation circuit includes a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a fifteenth NMOS transistor MN15, a sixteenth NMOS transistor MN16, a seventeenth NMOS transistor MN17, an eighteenth NMOS transistor MN18, a nineteenth NMOS transistor MN19, a twenty-first NMOS transistor MN21, a twenty-second NMOS transistor MN22, a twenty-third NMOS transistor MN23, a twenty-fourth NMOS transistor MN24, a twenty-fifth NMOS transistor MN25, a tenth resistor R10, and an eleventh resistor R11. The source of the fifth PMOS transistor MP5 is connected to the bias circuit, the gate of the fifth PMOS transistor MP5 is connected to the control signal OEN, and the drain of the fifth PMOS transistor MP5 is simultaneously connected to one end of the tenth resistor R10 and one end of the eleventh resistor R11. The other end of the tenth resistor R10 is connected to the source of the sixth PMOS transistor MP6. The gate of the sixth PMOS transistor MP6 is connected to the reference voltage Vref. The drain of the sixth PMOS transistor MP6 is simultaneously connected to the drain of the fourteenth NMOS transistor MN14 and the drain of the twenty-fourth NMOS transistor MN24. The gate of the fourteenth NMOS transistor MN14 and the gate of the thirteenth NMOS transistor MN13 are both connected to the drain of the fourteenth NMOS transistor MN14. The other end of the eleventh resistor R11 is connected to the source of the seventh PMOS transistor MP7. The gate of the seventh PMOS transistor MP7 is connected to the bias circuit. The drain of the seventh PMOS transistor MP7 is simultaneously connected to the drain of the fifteenth NMOS transistor MN15 and the drain of the sixteenth NMOS transistor MN16. The gate of the fifteenth NMOS transistor MN15 and the gate of the twelfth NMOS transistor MN12 are both connected to the drain of the fifteenth NMOS transistor MN15. The seventeenth NMOS transistor MN17, the eighteenth NMOS transistor MN18, and the nineteenth NMOS transistor MN19 are connected in series. The source of the nineteenth NMOS transistor MN19 is grounded, and the drain of the seventeenth NMOS transistor MN17 is connected to the drain of the sixteenth NMOS transistor MN16. The 21st NMOS transistor MN21, the 22nd NMOS transistor MN22, and the 23rd NMOS transistor MN23 are connected in series. The source of the 23rd NMOS transistor MN23 is grounded, and the drain of the 21st NMOS transistor MN21 is connected to the drain of the 24th NMOS transistor MN24. The gates of the sixteenth NMOS transistor MN16, the seventeenth NMOS transistor MN17, the eighteenth NMOS transistor MN18, the nineteenth NMOS transistor MN19, the twenty-first NMOS transistor MN21, the twenty-second NMOS transistor MN22, the twenty-third NMOS transistor MN23, the twenty-fourth NMOS transistor MN24, and the twenty-fifth NMOS transistor MN25 are all connected to the bias circuit.

[0012] In some embodiments, the bias circuit includes an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a twenty-sixth NMOS transistor MN26, a twenty-seventh NMOS transistor MN27, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifth transistor QN5, and a sixth transistor QN6. The sources of the eighth PMOS transistor MP8, the ninth PMOS transistor MP9, and the tenth PMOS transistor MP10 are all connected to the power supply VDD, and the gates of the eighth PMOS transistor MP8, the ninth PMOS transistor MP9, and the tenth PMOS transistor MP10 are all connected to the drain of the eighth PMOS transistor MP8. The drain of the eighth PMOS transistor MP8 is connected to the source of the eleventh PMOS transistor MP11. The gates of the eleventh PMOS transistor MP11, the twelfth PMOS transistor MP12, and the thirteenth PMOS transistor MP13 are all connected to the drain of the eleventh PMOS transistor MP11. The drain of the eleventh PMOS transistor MP11 is connected to the drain of the sixteenth NMOS transistor MN16. The source of the sixteenth NMOS transistor MN16 is simultaneously connected to one end of the twelfth resistor R12, one end of the thirteenth resistor R13, and one end of the fourteenth resistor R14. The other ends of the twelfth resistor R12, the thirteenth resistor R13, and the fourteenth resistor R14 are all grounded. The drain of the ninth PMOS transistor MP9 is connected to the source of the twelfth PMOS transistor MP12, and the drain of the twelfth PMOS transistor MP12 is connected to the collector of the fifth transistor QN5. The base of the fifth transistor QN5 is connected to its own collector, and the emitter of the fifth transistor QN5 is connected to the collector of the sixth transistor QN6. The base of the sixth transistor QN6 is connected to its own collector, and the emitter of the sixth transistor QN6 is grounded. The drain of the tenth PMOS transistor MP10 is connected to the source of the thirteenth PMOS transistor MP13, and the drain of the thirteenth PMOS transistor MP13 is connected to the segmented compensation circuit. The drain of the 26th NMOS transistor MN26 is connected to the source of the 27th NMOS transistor MN27, and the drain of the 27th NMOS transistor MN27 is connected to the segmented compensation circuit.

[0013] In some embodiments, the first NMOS transistor MN1, the third NMOS transistor MN3, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 in the startup circuit have the same size; The first NMOS transistor MN1 and the second NMOS transistor MN2 have the same width-to-length ratio, and together they form a current mirror structure.

[0014] In some embodiments, the ratio of the emitter area of ​​the third transistor QN3 to the fourth transistor QN4 in the first-order compensated bandgap reference circuit is 1:8. The second PMOS transistor MP2, the third PMOS transistor MP3, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, and the third resistor R3 constitute an operational amplifier; The ninth NMOS transistor MN9, together with the third resistor R3, achieves zero-pole compensation of the operational amplifier.

[0015] In some embodiments, the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 in the segmented compensation circuit both operate in the subthreshold region; The sixteenth NMOS transistor MN16, the seventeenth NMOS transistor MN17, the eighteenth NMOS transistor MN18, the nineteenth NMOS transistor MN19, the twenty-fourth NMOS transistor MN24, the twenty-first NMOS transistor MN21, the twenty-second NMOS transistor MN22, and the twenty-third NMOS transistor MN23, together with the twenty-fifth NMOS transistor MN25, form a current mirror structure.

[0016] In some embodiments, the dimensions of the 26th NMOS transistor MN26 and the 27th NMOS transistor MN27 in the bias circuit are the same as those of the 10th NMOS transistor MN10 and the 13th NMOS transistor MN13, respectively, so that the current flowing through the 26th NMOS transistor MN26 is equal to the current flowing through the 13th NMOS transistor MN13.

[0017] Secondly, the present invention provides an integrated circuit that integrates the above-mentioned low-temperature drift segmented compensation bandgap reference circuit.

[0018] The beneficial effects of the technical solution provided by this invention include at least the following: This technical solution designs a linear segmented compensation circuit that outputs two temperature-adaptive linear compensation currents, precisely superimposed on the downward-opening parabolic temperature characteristic voltage output by the first-order compensated bandgap reference circuit. The two compensation currents respectively provide targeted compensation for the low-temperature and high-temperature ranges, with no additional compensation interference in the intermediate temperature range. Through precise temperature range adaptation and characteristic superposition, the effects of high-order nonlinear temperature distortion are effectively offset. Compared to traditional first-order compensation schemes, this invention significantly suppresses the temperature drift of the bandgap reference voltage without requiring a complex topology, adapting to a wide temperature range of applications and providing a stable reference for subsequent low-dropout linear regulators, high-precision analog-to-digital converters, and other devices. Attached Figure Description

[0019] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof.

[0020] Figure 1 The diagram shows a schematic of a low-temperature drift segmented compensation bandgap reference circuit provided by an exemplary embodiment of the present invention.

[0021] Figure 2 A schematic diagram of the voltage characteristics of a low-temperature drift segmented compensation bandgap reference circuit provided by an exemplary embodiment of the present invention is shown. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0024] Figure 1 The diagram illustrates a structural schematic of a low-temperature drift segmented compensation bandgap reference circuit according to an exemplary embodiment of the present invention. This low-temperature drift segmented compensation bandgap reference circuit includes a startup circuit 1, a first-order compensation bandgap reference circuit 2, a segmented compensation circuit 3, and a bias circuit 4. The startup circuit 1 is electrically connected to the first-order compensation bandgap reference circuit 2 and is used to inject current into the first-order compensation bandgap reference circuit 2 upon power-up to remove it from its degeneracy point. The first-order compensation bandgap reference circuit 2 is electrically connected to the segmented compensation circuit 3 and is used to provide a bandgap reference voltage that eliminates the first-order temperature coefficient, and to provide a connection node for the segmented compensation circuit 3. The segmented compensation circuit 3 is electrically connected to the bias circuit 4 and is used to provide a linear segmented compensation current for the bandgap reference voltage. The bias circuit 4 is electrically connected to both the first-order compensation bandgap reference circuit 2 and the segmented compensation circuit 3, providing a stable bias voltage for both.

[0025] In this embodiment, the startup circuit 1 avoids the startup failure problem caused by the first-order compensated bandgap reference circuit 2 falling into the degeneracy point during the initial power-on period. It quickly activates the reference circuit through directional current injection, ensuring the system enters normal operating condition immediately upon power-on. The first-order compensated bandgap reference circuit 2 not only fundamentally eliminates the influence of the first-order temperature coefficient on the reference voltage, but its reserved connection nodes also provide a signal access basis for the segmented compensation circuit 3, achieving seamless connection between the compensation and reference signals. The configuration of the segmented compensation circuit 3 specifically addresses the high-order temperature distortion problem, adapting to different temperature scenarios through linear segmented compensation current, breaking through the accuracy bottleneck of traditional first-order compensation. The bias circuit 4 provides a stable operating bias for the first-order compensated bandgap reference circuit 2 and the segmented compensation circuit 3, isolating power fluctuations and external interference, ensuring the stability of parameters of each circuit module.

[0026] In some embodiments, see Figure 1The startup circuit 1 includes a first PMOS transistor MP1, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a first resistor R1. One end of the first resistor R1 is connected to the power supply voltage Vref, and the other end is connected to the drain of the first NMOS transistor MN1. The gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are both connected to the drain of the first NMOS transistor MN1. The gate of the first PMOS transistor MP1 is connected to the control signal VOEN, and the source of the first PMOS transistor MP1 is connected to the power supply voltage Vref. The drain of P1 is connected to the drain of the second NMOS transistor MN2; the source of the first NMOS transistor MN1 is connected to the drain and gate of the third NMOS transistor MN3; the source of the third NMOS transistor MN3 is connected to the drain and gate of the fourth NMOS transistor MN4; the source of the fourth NMOS transistor MN4 is connected to the drain and gate of the fifth NMOS transistor MN5; the source of the fifth NMOS transistor MN5 is connected to the drain of the sixth NMOS transistor MN6, and the gate of the sixth NMOS transistor MN6 is connected to the control signal VOE; the source of the second NMOS transistor MN2 is connected to the first-order compensated bandgap reference circuit 2.

[0027] In one example, the first NMOS transistor MN1, the third NMOS transistor MN3, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 in the startup circuit 1 have the same dimensions; the first NMOS transistor MN1 and the second NMOS transistor MN2 have the same width-to-length ratio, and the two form a current mirror structure.

[0028] In this embodiment, the first resistor R1 acts as a current limiter and voltage divider, suppressing the instantaneous current surge upon power-up and stabilizing the initial current flowing through the first NMOS transistor MN1, preventing damage to the device due to overcurrent. The first NMOS transistor MN1 and the second NMOS transistor MN1 form a simple current mirror, ensuring the current accuracy of the injection circuit and guaranteeing a stable startup signal. The third NMOS transistor MN3, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 are connected in series to form a multi-stage current path, enhancing the stability of current transmission and assisting the voltage divider adapter in setting the device's operating threshold. The first PMOS transistor MP1 and the sixth NMOS transistor MN6 are controlled by the control signals VOEN and VOE, respectively, enabling precise control of the startup circuit's on / off state and startup timing, avoiding unnecessary power consumption.

[0029] In some embodiments, see Figure 1The first-order compensated bandgap reference circuit 2 includes a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a first transistor QN1, a second transistor QN2, a third transistor QN3, a fourth transistor QN4, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9; one end of the second resistor R2 is connected to the power supply voltage Vref, and the other end is simultaneously connected to the second PMOS transistor MP4. The source of PMOS transistor MP2, the source of PMOS transistor MP3, and the source of PMOS transistor MP4 are all connected together; the gate of PMOS transistor MP4 is connected to the control signal OEN; the gates of PMOS transistor MP2 and MP3 are both connected to the drain of PMOS transistor MP2; the drain of PMOS transistor MP2 is connected to the drain of NMOS transistor MN7; the drain of PMOS transistor MP3 is connected to the drain of NMOS transistor MN8, one end of resistor R3, and the gate of NMOS transistor MN10; the other end of resistor R3 is connected to the gate of NMOS transistor MN7. The gate of the eighth NMOS transistor MN8 is connected to the same terminal; the source of the seventh NMOS transistor MN7 is connected to the collector of the first transistor QN1, and the source of the eighth NMOS transistor MN8 is connected to the collector of the second transistor QN2. The emitters of both the first and second transistors QN2 are grounded; the bases of both the first and second transistors QN1 and QN2 are connected to the collector of the fourth transistor QN4; the drain of the tenth NMOS transistor MN10 is connected to the drain of the fourth PMOS transistor MP4, and the source of the tenth NMOS transistor MN10 is simultaneously connected to one end of the fifth resistor R5 and the source of the eleventh NMOS transistor MN11. The drains are connected together; the gate of the eleventh NMOS transistor MN11 is connected to the base of the third transistor QN3 and one end of the fourth resistor R4; the other end of the fourth resistor R4 is connected to the collector of the third transistor QN3 and the base of the fourth transistor QN4; the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 are connected in series, the two ends of the sixth resistor R6 are connected to the segmented compensation circuit 3, and the other end of the eighth resistor R8 is connected to the collector of the fourth transistor QN4; the emitters of the third transistor QN3 and the fourth transistor QN4 are both connected to one end of the ninth resistor R9, and the other end of the ninth resistor R9 is grounded.

[0030] In this embodiment, the second resistor R2 provides a stable source bias for MP2, MP3, and MP4, suppressing power fluctuations from interfering with the operating state of the core components. MP2, MP3, MN7, MN8, and R3 form an operational amplifier, ensuring voltage balance at key nodes through negative potential feedback, providing a stable gain basis for reference voltage generation. QN1, QN2, QN3, and QN4 form a Banba structure, working with R4, R8, and R9 to regulate the current-voltage relationship and efficiently offset the first-order temperature coefficient. The R5-R8 series link not only constructs the reference voltage divider transmission path but also establishes a signal access port for the segmented compensation circuit 3 through the sixth resistor R6, achieving current coupling for compensation. MN10 and MN11 are responsible for current distribution and potential calibration, preventing branch current imbalance from affecting reference accuracy.

[0031] In some embodiments, see Figure 1The segmented compensation circuit 3 includes the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, the twelfth NMOS transistor MN12, the thirteenth NMOS transistor MN13, the fourteenth NMOS transistor MN14, the fifteenth NMOS transistor MN15, the sixteenth NMOS transistor MN16, the seventeenth NMOS transistor MN17, the eighteenth NMOS transistor MN18, the nineteenth NMOS transistor MN19, the twenty-first NMOS transistor MN21, the twenty-second NMOS transistor MN22, the twenty-third NMOS transistor MN23, the twenty-fourth NMOS transistor MN24, the twenty-fifth NMOS transistor MN25, the tenth resistor R10, and the eleventh resistor R11; the fifth PMOS transistor MP5... The source of S-MOSFET MP5 is connected to bias circuit 4. The gate of the fifth PMOS transistor MP5 is connected to the control signal OEN. The drain of the fifth PMOS transistor MP5 is connected to one end of the tenth resistor R10 and one end of the eleventh resistor R11. The other end of the tenth resistor R10 is connected to the source of the sixth PMOS transistor MP6. The gate of the sixth PMOS transistor MP6 is connected to the reference voltage Vref. The drain of the sixth PMOS transistor MP6 is connected to the drain of the fourteenth NMOS transistor MN14 and the drain of the twenty-fourth NMOS transistor MN24. The gates of the fourteenth NMOS transistor MN14 and the thirteenth NMOS transistor MN13 are both connected to the drain of the fourteenth NMOS transistor MN14. The eleventh resistor R11... The other end of resistor R11 is connected to the source of the seventh PMOS transistor MP7. The gate of the seventh PMOS transistor MP7 is connected to bias circuit 4. The drain of the seventh PMOS transistor MP7 is also connected to the drain of the fifteenth NMOS transistor MN15 and the drain of the sixteenth NMOS transistor MN16. The gates of the fifteenth NMOS transistor MN15 and the twelfth NMOS transistor MN12 are both connected to the drain of the fifteenth NMOS transistor MN15. The seventeenth NMOS transistor MN17, the eighteenth NMOS transistor MN18, and the nineteenth NMOS transistor MN19 are connected in series. The source of the nineteenth NMOS transistor MN19 is grounded, and the drain of the seventeenth NMOS transistor MN17 is connected to the drain of the sixteenth NMOS transistor MN16. The 21st NMOS transistor MN21, the 22nd NMOS transistor MN22, and the 23rd NMOS transistor MN23 are connected in series. The source of the 23rd NMOS transistor MN23 is grounded. The drain of the 21st NMOS transistor MN21 is connected to the drain of the 24th NMOS transistor MN24. The gates of the 16th NMOS transistor MN16, the 17th NMOS transistor MN17, the 18th NMOS transistor MN18, the 19th NMOS transistor MN19, the 21st NMOS transistor MN21, the 22nd NMOS transistor MN22, the 23rd NMOS transistor MN23, the 24th NMOS transistor MN24, and the 25th NMOS transistor MN25 are all connected to the bias circuit 4.

[0032] In this embodiment, the fifth PMOS transistor MP5 is controlled by the control signal OEN, and in conjunction with the bias circuit 4, it enables the start / stop of the compensation circuit and the control of the total current. The tenth resistor R10 and the eleventh resistor R11 provide stable source biases for the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7, respectively, suppressing current fluctuations and ensuring the stability of the two transistors in the subthreshold region. MP6 and MP7 are coupled to the reference voltage and the bias signal, respectively, to generate compensation currents specifically for high and low temperature ranges. MN12, MN13, MN14, and MN15 form two sets of current mirrors to achieve directional transmission and precise replication of the compensation current. MN17-MN19 and MN21-MN23 are connected in series to form a graded load, which, in conjunction with the unified bias of MN25, sets the compensation current threshold, enabling switching to zero compensation in the intermediate temperature range.

[0033] In some embodiments, see Figure 1The bias circuit 4 includes the eighth PMOS transistor MP8, the ninth PMOS transistor MP9, the tenth PMOS transistor MP10, the eleventh PMOS transistor MP11, the twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13, the twenty-sixth NMOS transistor MN26, the twenty-seventh NMOS transistor MN27, the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14, the fifth transistor QN5, and the sixth transistor QN6; the eighth PMOS transistor MP8, the ninth PMOS transistor MP9, and the tenth PMOS transistor MP10... The sources of all transistors are connected to the power supply VDD. The gates of the eighth PMOS transistor MP8, the ninth PMOS transistor MP9, and the tenth PMOS transistor MP10 are all connected to the drain of the eighth PMOS transistor MP8. The drain of the eighth PMOS transistor MP8 is connected to the source of the eleventh PMOS transistor MP11. The gates of the eleventh PMOS transistor MP11, the twelfth PMOS transistor MP12, and the thirteenth PMOS transistor MP13 are all connected to the drain of the eleventh PMOS transistor MP11. The drain of the eleventh PMOS transistor MP11 is connected to the source of the sixteenth NMOS transistor MP11. The drain of transistor MN16 is connected. The source of the sixteenth NMOS transistor MN16 is simultaneously connected to one end of the twelfth resistor R12, one end of the thirteenth resistor R13, and one end of the fourteenth resistor R14. The other ends of the twelfth resistor R12, the thirteenth resistor R13, and the fourteenth resistor R14 are all grounded. The drain of the ninth PMOS transistor MP9 is connected to the source of the twelfth PMOS transistor MP12. The drain of the twelfth PMOS transistor MP12 is connected to the collector of the fifth transistor QN5. The base of the fifth transistor QN5 is connected to its own collector. The emitter of the fifth transistor QN5 is connected to the collector of the sixth transistor QN6; the base of the sixth transistor QN6 is connected to its own collector, and the emitter of the sixth transistor QN6 is grounded; the drain of the tenth PMOS transistor MP10 is connected to the source of the thirteenth PMOS transistor MP13, and the drain of the thirteenth PMOS transistor MP13 is connected to the segmented compensation circuit 3; the drain of the twenty-sixth NMOS transistor MN26 is connected to the source of the twenty-seventh NMOS transistor MN27, and the drain of the twenty-seventh NMOS transistor MN27 is connected to the segmented compensation circuit 3.

[0034] In this embodiment, the eighth PMOS transistor MP8, the ninth PMOS transistor MP9, and the tenth PMOS transistor MP10 form a mirror current source, drawing power from the power supply VDD and stabilizing the current output. The eleventh PMOS transistor MP11, the twelfth PMOS transistor MP12, and the thirteenth PMOS transistor MP13 implement hierarchical distribution of the bias signal. The twelfth resistor R12, the thirteenth resistor R13, and the fourteenth resistor R14 are connected in parallel to divide the voltage, stabilizing the potential of critical nodes and suppressing power supply fluctuations and external interference. The fifth transistor QN5 and the sixth transistor QN6 are connected in a diode configuration to form a reference potential unit, improving the temperature stability of the bias signal. The twenty-sixth NMOS transistor MN26 and the twenty-seventh NMOS transistor MN27 directionally transmit the bias to the segmented compensation circuit 3, ensuring the accuracy of the compensation current generation.

[0035] In some embodiments, see Figure 1 In the first-order compensated bandgap reference circuit 2, the emitter area ratio of the third transistor QN3 to the fourth transistor QN4 is 1:8; the second PMOS transistor MP2, the third PMOS transistor MP3, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8 and the third resistor R3 constitute an operational amplifier; among them, the ninth NMOS transistor MN9 and the third resistor R3 work together to realize the zero-pole compensation of the operational amplifier.

[0036] In some embodiments, see Figure 1 In the segmented compensation circuit 3, the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 both operate in the subthreshold region; the sixteenth NMOS transistor MN16, the seventeenth NMOS transistor MN17, the eighteenth NMOS transistor MN18, the nineteenth NMOS transistor MN19, the twenty-fourth NMOS transistor MN24, the twenty-first NMOS transistor MN21, the twenty-second NMOS transistor MN22, and the twenty-third NMOS transistor MN23 respectively form a current mirror structure with the twenty-fifth NMOS transistor MN25.

[0037] In some embodiments, see Figure 1 The dimensions of the twenty-sixth NMOS transistor MN26 and the twenty-seventh NMOS transistor MN27 in the bias circuit 4 are the same as those of the tenth NMOS transistor MN10 and the thirteenth NMOS transistor MN13, respectively, so that the current flowing through the twenty-sixth NMOS transistor MN26 is equal to the current flowing through the thirteenth NMOS transistor MN13.

[0038] Next, combined Figure 1 and Figure 2 The working principle of a low-temperature drift segmented compensation bandgap reference circuit involved in the embodiments of the present invention will be explained.

[0039] In startup circuit 1, when the power supply voltage is applied, if the first-order temperature compensation voltage circuit 2 is at its degeneracy point, then Figure 1The potential of node V1 shown is the power supply ground potential; when the power supply is powered on and the control signals VOE=VDD and VOEN=0, since the dimensions of the first NMOS transistor MN1, the third NMOS transistor MN3, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 are the same, the current I1 flowing through the first resistor R1 is expressed as: ; In the formula, V GSN1 V is the gate-source voltage of the first NMOS transistor MN1. DSN6 This is the drain-source voltage of the sixth NMOS transistor MN6; Since node V1 is at the power supply ground potential, the first NMOS transistor MN1 and the second NMOS transistor MN2 can be approximately equivalent to a current mirror structure, and they have the same width-to-length ratio, therefore satisfying: ; The aforementioned current I1 is the target startup current injected into the first-order compensated bandgap reference circuit 2. When the injected target current I1 reaches the preset threshold, the first-order compensated bandgap reference circuit 2 can be removed from the degeneracy point. Subsequently, the potential of node V1 rises, causing the second NMOS transistor MN2 to turn off, and the target current I1 drops to zero, ensuring that the startup circuit 1 no longer causes additional interference to the normal operation of the first-order compensated bandgap reference circuit 2.

[0040] In the first-order bandgap reference circuit 2, NPN transistors QN3 and QN4, and resistors R4, R8, and R9 constitute a Banba-type bandgap reference structure. The emitter area ratio of the third transistor QN3 to the fourth transistor QN4 is 1:8. PMOS transistors MP2, MP3, and MP4, NMOS transistors MN7, MN8, and MN9, transistors QN1 and QN2, and resistor R3 together constitute an operational amplifier. NMOS transistor MN9, in conjunction with resistor R3, provides zero-pole compensation for this operational amplifier, ensuring that the potentials at points A and B in the circuit are equal.

[0041] Circuit analysis revealed that the output voltage of the first-order bandgap reference circuit 2... Satisfy the following expression: ; ; ; In the formula, The bandgap reference voltage; This represents the base-emitter voltage difference between the third transistor QN3 and the fourth transistor QN4. R1 is the base-emitter voltage of the third transistor QN3 (exhibiting a negative temperature coefficient characteristic); R5 is the resistance of the fifth resistor R5; R6 is the resistance of the sixth resistor R6; R7 is the resistance of the sixth resistor R7; R8 is the resistance of the sixth resistor R8; N2:N1 is the ratio of the emitter area of ​​the second transistor QN2 to that of the first transistor QN1; ln is the natural logarithm operation symbol.

[0042] The base-emitter voltage of the third transistor QN3 The expression is: ; In the formula, The silicon bandgap voltage at the reference temperature The value below; η is the thermal voltage; η is a process-related constant; ζ is the order of the transistor's collector current-temperature characteristic. When the current flowing through the transistor is PTAT (proportional to absolute temperature), ζ takes the value of 1; when the current flowing through the transistor is a negative temperature coefficient current, ζ takes the value of -1; when the current flowing through the transistor is a temperature-independent current, ζ takes the value of 0.

[0043] From the above expression, it can be seen that the bandgap reference voltage At reference temperature After Taylor expansion and elimination of the first-order temperature coefficient term, it can be transformed into Since α is a positive number, its temperature characteristic curve is a downward-opening parabola. Therefore, by simply superimposing the two linear compensation voltages with this first-order bandgap reference voltage, a bandgap reference voltage with smaller temperature drift can be obtained. The segmented temperature compensation circuit 3 in this invention can achieve this function.

[0044] In the segmented temperature compensation circuit 3, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, the tenth resistor R10, the eleventh resistor R11, the fourteenth NMOS transistor MN14, and the fifteenth NMOS transistor MN15 form a comparator structure. The source of the fifth PMOS transistor MP5 is connected to the drain of the thirteenth NMOS transistor MN13 in the bias circuit 4, therefore the current I flowing through the thirteenth NMOS transistor MN13... MN13 The current I flowing through the fifth PMOS transistor MP5 MP5 They are equal; at the same time, the dimensions of the twenty-sixth NMOS transistor MN26 and the twenty-seventh NMOS transistor MN27 are the same as those of the tenth NMOS transistor MN10 and the thirteenth NMOS transistor MN13, respectively, therefore I MN13 with I MN26 They are equal, and the currents satisfy the following relationship: ; The gate of the sixth PMOS transistor MP6 is connected to the reference voltage Vref, and the gate of the seventh PMOS transistor MP7 is connected to 2Vref. Both the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 operate in the subthreshold region. According to the formula for the subthreshold current characteristics of MOS transistors... We can obtain: ; ; And it satisfies the KCL current conservation relationship: ; In the formula, Characteristic current under specific processes and device dimensions. This is the subthreshold slope factor; Solving the above formulas simultaneously, we can obtain the solution. and The expression is: ; ; Because of the transistor's V BE It exhibits a linear negative correlation with temperature; substituting this into the equation, the above expression can be transformed into: ; ; As can be seen from the above expression, when the temperature rises, The value will continue to decrease, while It is a fixed value, therefore It will increase in size as the temperature rises. It decreases as temperature increases; exp is the exponential operator with the natural constant e (approximately 2.718) as the base.

[0045] The drain output current of the sixth PMOS transistor MP6 The current is divided into two branches, I2 and I3, and the drain output current of the seventh PMOS transistor MP7 is... I3 is divided into two branches with currents I4 and I5, I3 is divided into two branches with currents I6 and I7, and I5 is divided into two branches with currents I8 and I9. The branch currents satisfy the following relationship: ; ; ; ; Meanwhile, the sixteenth NMOS transistor MN16, the seventeenth NMOS transistor MN17, the eighteenth NMOS transistor MN18, the nineteenth NMOS transistor MN19, the twentieth NMOS transistor MN20, the twenty-first NMOS transistor MN21, the twenty-second NMOS transistor MN22, the twenty-third NMOS transistor MN23, and the twenty-fourth NMOS transistor MN24 all form a current mirror structure with the twenty-fifth NMOS transistor MN25, and the corresponding current relationships are as follows (where...). , >0.5): ; ; By combining these equations, we can obtain the expressions for the branch currents I2 and I4: ; ; When the temperature is low, the current supplied by the seventh PMOS transistor MP7 cannot exceed [a certain value]. At this point, I4 = 0; when the temperature is high, the current supplied by the sixth PMOS transistor MP6 cannot exceed [the specified value]. At this time, I2 = 0; because , All are greater than 0.5, but there is a temperature range in between where I2=I4=0, resulting in no compensation current output. This can be addressed by appropriately selecting... , The value can be precisely adjusted to control the operating temperature range of the compensation current.

[0046] The twelfth NMOS transistor MN12 and the fifteenth NMOS transistor MN15 form a current mirror, therefore the effective compensation current at low temperature is I2, corresponding to the compensation voltage V. 补偿 =I2*(R5+R6); The thirteenth NMOS transistor MN13 and the fourteenth NMOS transistor MN14 form a current mirror, therefore the effective compensation current at high temperature is I4, corresponding to the compensation voltage V. 补偿 =I4*R5. The corrected bandgap reference voltage is obtained by superimposing the compensation voltage with the first-order bandgap reference voltage. for: ; In the formula, T is the actual operating temperature of the circuit, in Kelvin (K); T1 and T2 are preset temperature thresholds, in Kelvin (K), which are the temperature boundary points for segmented compensation; T1 is the boundary temperature between the low temperature zone and the intermediate temperature zone. When the temperature is below this temperature, the circuit starts low temperature compensation; T2 is the boundary temperature between the intermediate temperature zone and the high temperature zone. When the temperature is above this temperature, the circuit starts high temperature compensation. T1 < T2. Both can be precisely set by adjusting the values ​​of k1 and k2.

[0047] It is understood that the present invention also provides an integrated circuit that integrates the above-mentioned low-temperature drift segmented compensation bandgap reference circuit.

[0048] In summary, this technical solution, through the design of a linear segmented compensation circuit, can output two temperature-adapted linear compensation currents, which are precisely superimposed on the downward-opening parabolic temperature characteristic voltage output by the first-order compensated bandgap reference circuit. The two compensation currents respectively provide targeted compensation for the low-temperature and high-temperature ranges, with no additional compensation interference in the intermediate temperature range. Through precise temperature range adaptation and characteristic superposition, the effects of high-order nonlinear temperature distortion are effectively offset. Compared to traditional first-order compensation schemes, this invention can significantly suppress the temperature drift of the bandgap reference voltage without a complex topology, adapting to a wide temperature range of applications and providing a stable reference for subsequent low-dropout linear regulators, high-precision analog-to-digital converters, and other devices.

[0049] It is understood that the specific examples in this document are only intended to help those skilled in the art better understand this disclosure, and are not intended to limit the scope of the invention.

[0050] It is understood that the various implementation methods described in this specification can be implemented individually or in combination, and this disclosure does not limit them.

[0051] Unless otherwise stated, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this specification. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0052] The above description is merely a specific embodiment of this specification, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this specification should be included within the scope of protection of this specification. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A low-temperature drift segmented compensation bandgap reference circuit, characterized in that, It includes a startup circuit (1), a first-order compensated bandgap reference circuit (2), a segmented compensation circuit (3), and a bias circuit (4); The startup circuit (1) is electrically connected to the first-order compensated bandgap reference circuit (2). The startup circuit (1) is used to inject current into the first-order compensated bandgap reference circuit (2) when it is powered on so that it is removed from the degeneracy point. The first-order compensated bandgap reference circuit (2) is electrically connected to the segmented compensation circuit (3). The first-order compensated bandgap reference circuit (2) is used to provide a bandgap reference voltage that eliminates the first-order temperature coefficient and to provide a connection node for the segmented compensation circuit (3). The segmented compensation circuit (3) is electrically connected to the bias circuit (4), and the segmented compensation circuit (3) is used to provide a linear segmented compensation current for the bandgap reference voltage; The bias circuit (4) is electrically connected to the first-order compensated bandgap reference circuit (2) and the segmented compensation circuit (3) respectively, providing stable bias voltage for both.

2. The low-temperature drift segmented compensation bandgap reference circuit according to claim 1, characterized in that, The startup circuit (1) includes a first PMOS transistor MP1, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a first resistor R1; One end of the first resistor R1 is connected to the power supply voltage Vref, and the other end is connected to the drain of the first NMOS transistor MN1; The gate of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2 are both connected to the drain of the first NMOS transistor MN1. The gate of the first PMOS transistor MP1 is connected to the control signal VOEN, the source of the first PMOS transistor MP1 is connected to the power supply voltage Vref, and the drain of the first PMOS transistor MP1 is connected to the drain of the second NMOS transistor MN2. The source of the first NMOS transistor MN1 is connected to the drain of the third NMOS transistor MN3 and the gate of the third NMOS transistor MN3. The source of the third NMOS transistor MN3 is connected to the drain and gate of the fourth NMOS transistor MN4. The source of the fourth NMOS transistor MN4 is connected to the drain and gate of the fifth NMOS transistor MN5. The source of the fifth NMOS transistor MN5 is connected to the drain of the sixth NMOS transistor MN6, and the gate of the sixth NMOS transistor MN6 is connected to the control signal VOE. The source of the second NMOS transistor MN2 is connected to the first-order compensated bandgap reference circuit (2).

3. The low-temperature drift segmented compensation bandgap reference circuit according to claim 1, characterized in that, The first-order compensated bandgap reference circuit (2) includes a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a first transistor QN1, a second transistor QN2, a third transistor QN3, a fourth transistor QN4, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9; One end of the second resistor R2 is connected to the power supply voltage Vref, and the other end is simultaneously connected to the source of the second PMOS transistor MP2, the source of the third PMOS transistor MP3, and the source of the fourth PMOS transistor MP4. The gate connection control signal OEN of the fourth PMOS transistor MP4; The gate of the second PMOS transistor MP2 and the gate of the third PMOS transistor MP3 are both connected to the drain of the second PMOS transistor MP2. The drain of the second PMOS transistor MP2 is connected to the drain of the seventh NMOS transistor MN7, and the drain of the third PMOS transistor MP3 is connected to the drain of the eighth NMOS transistor MN8, one end of the third resistor R3, and the gate of the tenth NMOS transistor MN10. The other end of the third resistor R3 is connected to the gate of the seventh NMOS transistor MN7 and the gate of the eighth NMOS transistor MN8. The source of the seventh NMOS transistor MN7 is connected to the collector of the first transistor QN1, the source of the eighth NMOS transistor MN8 is connected to the collector of the second transistor QN2, and the emitters of the first transistor QN1 and the second transistor QN2 are both grounded. The base of the first transistor QN1 and the base of the second transistor QN2 are both connected to the collector of the fourth transistor QN4; The drain of the tenth NMOS transistor MN10 is connected to the drain of the fourth PMOS transistor MP4, and the source of the tenth NMOS transistor MN10 is simultaneously connected to one end of the fifth resistor R5 and the source and drain of the eleventh NMOS transistor MN11. The gate of the eleventh NMOS transistor MN11 is simultaneously connected to the base of the third transistor QN3 and one end of the fourth resistor R4. The other end of the fourth resistor R4 is simultaneously connected to the collector of the third transistor QN3 and the base of the fourth transistor QN4; The fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 are connected in series. The two ends of the sixth resistor R6 are connected to the segmented compensation circuit (3), and the other end of the eighth resistor R8 is connected to the collector of the fourth transistor QN4. The emitter of the third transistor QN3 and the emitter of the fourth transistor QN4 are both connected to one end of the ninth resistor R9, and the other end of the ninth resistor R9 is grounded.

4. The low-temperature drift segmented compensation bandgap reference circuit according to claim 1, characterized in that, The segmented compensation circuit (3) includes the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, the twelfth NMOS transistor MN12, the thirteenth NMOS transistor MN13, the fourteenth NMOS transistor MN14, the fifteenth NMOS transistor MN15, the sixteenth NMOS transistor MN16, the seventeenth NMOS transistor MN17, the eighteenth NMOS transistor MN18, the nineteenth NMOS transistor MN19, the twenty-first NMOS transistor MN21, the twenty-second NMOS transistor MN22, the twenty-third NMOS transistor MN23, the twenty-fourth NMOS transistor MN24, the twenty-fifth NMOS transistor MN25, the tenth resistor R10, and the eleventh resistor R11; The source of the fifth PMOS transistor MP5 is connected to the bias circuit (4), the gate of the fifth PMOS transistor MP5 is connected to the control signal OEN, and the drain of the fifth PMOS transistor MP5 is connected to one end of the tenth resistor R10 and one end of the eleventh resistor R11. The other end of the tenth resistor R10 is connected to the source of the sixth PMOS transistor MP6. The gate of the sixth PMOS transistor MP6 is connected to the reference voltage Vref. The drain of the sixth PMOS transistor MP6 is simultaneously connected to the drain of the fourteenth NMOS transistor MN14 and the drain of the twenty-fourth NMOS transistor MN24. The gate of the fourteenth NMOS transistor MN14 and the gate of the thirteenth NMOS transistor MN13 are both connected to the drain of the fourteenth NMOS transistor MN14. The other end of the eleventh resistor R11 is connected to the source of the seventh PMOS transistor MP7. The gate of the seventh PMOS transistor MP7 is connected to the bias circuit (4). The drain of the seventh PMOS transistor MP7 is simultaneously connected to the drain of the fifteenth NMOS transistor MN15 and the drain of the sixteenth NMOS transistor MN16. The gate of the fifteenth NMOS transistor MN15 and the gate of the twelfth NMOS transistor MN12 are both connected to the drain of the fifteenth NMOS transistor MN15. The seventeenth NMOS transistor MN17, the eighteenth NMOS transistor MN18, and the nineteenth NMOS transistor MN19 are connected in series. The source of the nineteenth NMOS transistor MN19 is grounded, and the drain of the seventeenth NMOS transistor MN17 is connected to the drain of the sixteenth NMOS transistor MN16. The 21st NMOS transistor MN21, the 22nd NMOS transistor MN22, and the 23rd NMOS transistor MN23 are connected in series. The source of the 23rd NMOS transistor MN23 is grounded, and the drain of the 21st NMOS transistor MN21 is connected to the drain of the 24th NMOS transistor MN24. The gates of the sixteenth NMOS transistor MN16, the seventeenth NMOS transistor MN17, the eighteenth NMOS transistor MN18, the nineteenth NMOS transistor MN19, the twenty-first NMOS transistor MN21, the twenty-second NMOS transistor MN22, the twenty-third NMOS transistor MN23, the twenty-fourth NMOS transistor MN24, and the twenty-fifth NMOS transistor MN25 are all connected to the bias circuit (4).

5. The low-temperature drift segmented compensation bandgap reference circuit according to claim 1, characterized in that, The bias circuit (4) includes the eighth PMOS transistor MP8, the ninth PMOS transistor MP9, the tenth PMOS transistor MP10, the eleventh PMOS transistor MP11, the twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13, the twenty-sixth NMOS transistor MN26, the twenty-seventh NMOS transistor MN27, the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14, the fifth transistor QN5, and the sixth transistor QN6; The sources of the eighth PMOS transistor MP8, the ninth PMOS transistor MP9, and the tenth PMOS transistor MP10 are all connected to the power supply VDD, and the gates of the eighth PMOS transistor MP8, the ninth PMOS transistor MP9, and the tenth PMOS transistor MP10 are all connected to the drain of the eighth PMOS transistor MP8. The drain of the eighth PMOS transistor MP8 is connected to the source of the eleventh PMOS transistor MP11. The gates of the eleventh PMOS transistor MP11, the twelfth PMOS transistor MP12, and the thirteenth PMOS transistor MP13 are all connected to the drain of the eleventh PMOS transistor MP11. The drain of the eleventh PMOS transistor MP11 is connected to the drain of the sixteenth NMOS transistor MN16. The source of the sixteenth NMOS transistor MN16 is simultaneously connected to one end of the twelfth resistor R12, one end of the thirteenth resistor R13, and one end of the fourteenth resistor R14. The other ends of the twelfth resistor R12, the thirteenth resistor R13, and the fourteenth resistor R14 are all grounded. The drain of the ninth PMOS transistor MP9 is connected to the source of the twelfth PMOS transistor MP12, and the drain of the twelfth PMOS transistor MP12 is connected to the collector of the fifth transistor QN5. The base of the fifth transistor QN5 is connected to its own collector, and the emitter of the fifth transistor QN5 is connected to the collector of the sixth transistor QN6. The base of the sixth transistor QN6 is connected to its own collector, and the emitter of the sixth transistor QN6 is grounded. The drain of the tenth PMOS transistor MP10 is connected to the source of the thirteenth PMOS transistor MP13, and the drain of the thirteenth PMOS transistor MP13 is connected to the segmented compensation circuit (3). The drain of the 26th NMOS transistor MN26 is connected to the source of the 27th NMOS transistor MN27, and the drain of the 27th NMOS transistor MN27 is connected to the segmented compensation circuit (3).

6. The low-temperature drift segmented compensation bandgap reference circuit according to claim 2, characterized in that, The first NMOS transistor MN1, the third NMOS transistor MN3, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 in the startup circuit (1) have the same size; The first NMOS transistor MN1 and the second NMOS transistor MN2 have the same width-to-length ratio, and together they form a current mirror structure.

7. The low-temperature drift segmented compensation bandgap reference circuit according to claim 3, characterized in that, The ratio of the emitter area of ​​the third transistor QN3 to the fourth transistor QN4 in the first-order compensated bandgap reference circuit (2) is 1:8; The second PMOS transistor MP2, the third PMOS transistor MP3, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, and the third resistor R3 constitute an operational amplifier; The ninth NMOS transistor MN9, together with the third resistor R3, achieves zero-pole compensation of the operational amplifier.

8. The low-temperature drift segmented compensation bandgap reference circuit according to claim 4, characterized in that, The sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 in the segmented compensation circuit (3) both operate in the subthreshold region; The sixteenth NMOS transistor MN16, the seventeenth NMOS transistor MN17, the eighteenth NMOS transistor MN18, the nineteenth NMOS transistor MN19, the twenty-fourth NMOS transistor MN24, the twenty-first NMOS transistor MN21, the twenty-second NMOS transistor MN22, and the twenty-third NMOS transistor MN23, together with the twenty-fifth NMOS transistor MN25, form a current mirror structure.

9. The low-temperature drift segmented compensation bandgap reference circuit according to claim 5, characterized in that, The dimensions of the 26th NMOS transistor MN26 and the 27th NMOS transistor MN27 in the bias circuit (4) are the same as those of the 10th NMOS transistor MN10 and the 13th NMOS transistor MN13, respectively, so that the current flowing through the 26th NMOS transistor MN26 is equal to the current flowing through the 13th NMOS transistor MN13.

10. An integrated circuit, characterized in that, It integrates a low-temperature drift segmented compensation bandgap reference circuit as described in any one of claims 1 to 9.

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