Storage device and method of operating storage device

Abstract

A memory device and a method of operating the memory device are provided. The storage device includes: a memory device; and a memory controller for controlling the memory device by communicating with the memory device via the channel. A memory device includes a plurality of memory chips sharing a channel, and each of the plurality of memory chips includes a transfer driver and an adaptive body bias generator. A target memory chip selected by the memory controller among the plurality of memory chips includes a first adaptive body bias generator and a first transfer driver. The first adaptive body bias generator applies a first body bias to the first transfer driver in a write mode in which the target memory chip receives write data from the memory controller, and applies a second body bias in a read mode in which the target memory chip transmits read data to the memory controller.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0155842, filed on November 6, 2024, with the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a storage device and a method of operating the storage device. Background Technology

[0003] A storage device may include a memory device and a controller. The memory device includes multiple memory chips, and the controller controls the memory device. In the relevant memory system, signal communication between the memory device and the controller can be performed at a relatively low operating frequency compared to signal communication in a memory system that includes high-speed memory (such as dynamic random access memory (DRAM) or static random access memory (SRAM)). In the design and operation of one or more storage devices in computing systems and / or mobile communication systems, as the demand for high-speed storage devices continues to increase, the integrity (or robustness) of the signals communicating between the memory device and the controller, as well as the capacitance of the input / output pads for reducing channel power, become desirable. Summary of the Invention

[0004] Some example implementations provide storage devices capable of reducing the capacitance of the input / output pads.

[0005] Some example implementations provide methods for operating a storage device that can reduce the capacitance of the input / output pads.

[0006] According to some example embodiments, a storage device includes: a memory device; and a memory controller for controlling the memory device via a channel. The memory device includes a plurality of memory chips sharing the channel, and the memory device selects a target memory chip among the plurality of memory chips. The target memory chip includes a first adaptive volume bias generator and a first transfer driver. The first adaptive volume bias generator applies a first volume bias to the first transfer driver based on an operating mode, including a write mode and a read mode. In write mode, the target memory chip receives write data from the memory controller, and in read mode, the target memory chip sends read data to the memory controller.

[0007] According to some example embodiments, a storage device includes: a memory device; and a memory controller for controlling the memory device via a channel and selecting a target memory chip among a plurality of memory chips. The memory device includes the plurality of memory chips, which share a data bus for transmitting data and receive corresponding chip selection signals from the memory controller. Each of the plurality of memory chips includes a memory cell array, a transfer driver, and an adaptive body bias generator. The memory cell array includes a plurality of volatile memory cells coupled to a plurality of word lines and a plurality of bit lines, and stores the data in the memory cell array. The target memory chip includes a first adaptive body bias generator and a first transfer driver. The first adaptive body bias generator applies a first body bias to the first transfer driver based on an operating mode, including a write mode and a read mode. In write mode, the target memory chip receives write data from the memory controller, and in read mode, the target memory chip sends read data to the memory controller.

[0008] According to some example embodiments, a method of operating a storage device is provided. The storage device includes a memory device and a memory controller for controlling the memory device by communicating with the memory device via a channel, and the memory device includes a plurality of memory chips sharing the channel. According to the method, a memory chip selected as a target memory chip based on a chip address from the memory controller is determined in each of the plurality of memory chips; a first body bias is applied to a first transfer driver by a first adaptive body bias generator based on whether the operating mode is a write mode or a read mode, wherein the first adaptive body bias generator and the first transfer driver are included in the first memory chip selected as the target memory chip by the memory controller among the plurality of memory chips; and a second body bias is applied to a second transfer driver by a second adaptive body bias generator based on the activation of a corresponding on-chip termination function, wherein the second adaptive body bias generator and the second transfer driver are included in each of one or more non-target memory chips among the plurality of memory chips other than the first memory chip.

[0009] Therefore, in the storage device and the method of operating the storage device according to the example embodiment, the adaptive body bias generator in the selected chip can apply different body biases to the corresponding transfer driver based on the operating mode, and the adaptive body bias generator in the unselected chip can apply different body biases to the corresponding transfer driver based on whether the on-chip termination (ODT) function is enabled. Thus, the adaptive body bias generator can apply a reverse body bias to the corresponding transfer driver in write mode or when the ODT function is disabled, and power consumption can be reduced by decreasing parasitic capacitance. Attached Figure Description

[0010] The illustrative and non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figure 1 This is a block diagram illustrating a storage device according to an example embodiment.

[0012] Figure 2 This illustrates an example implementation. Figure 1 A block diagram of an example memory controller in a storage device.

[0013] Figure 3 Showing an example implementation Figure 1 Example of the connection between the memory controller and the memory device in a storage device.

[0014] Figure 4 This illustrates an example implementation. Figure 3 Timing diagram of chip selection operation for memory devices in the image.

[0015] Figure 5 This illustrates an example implementation. Figure 3 A block diagram of an example of one of a plurality of memory chips in a memory device.

[0016] Figure 6A Showing an example implementation Figure 5 An example of data I / O circuitry in a memory chip.

[0017] Figure 6B This illustrates an example implementation. Figure 6A The circuit diagram of the transfer driver in the data I / O circuit.

[0018] Figure 7 This illustrates an example implementation. Figure 5 A block diagram of an example adaptive volume bias generator in a memory chip.

[0019] Figure 8 This illustrates an example implementation. Figure 5 A block diagram illustrating an example of a memory plane in a memory chip.

[0020] Figure 9 It is shown Figure 8 A circuit diagram of one of the memory blocks.

[0021] Figure 10 This illustrates an example implementation. Figure 5 A block diagram of a portion of a memory chip.

[0022] Figure 11This illustrates an example implementation. Figure 10 A circuit diagram of an example of a transfer driver in a memory chip.

[0023] Figure 12 This illustrates the write mode according to an example implementation. Figure 3 Storage device.

[0024] Figure 13 This illustrates the reading mode according to an example implementation. Figure 3 Storage device.

[0025] Figure 14 It is shown Figure 12 and Figure 13 The table shows the body bias applied to the transfer driver in the memory chip.

[0026] Figure 15 This is a table showing the body bias of the transistors applied to the transfer driver according to an example embodiment.

[0027] Figure 16 and Figure 17 yes Figure 11 Cross-sectional views of the PMOS and NMOS transistors in the transmission driver.

[0028] Figure 18 This illustrates an example implementation. Figure 5 A block diagram of an example of the control circuitry in a memory chip.

[0029] Figure 19 This is a block diagram illustrating a storage device according to an example embodiment.

[0030] Figure 20 This illustrates an example implementation. Figure 19 Timing diagram of chip selection operation for memory devices in the image.

[0031] Figure 21 This illustrates an example implementation. Figure 19 Timing diagram of an example of ODT control operation of a memory device.

[0032] Figure 22 This is a block diagram illustrating a storage device according to an example embodiment.

[0033] Figure 23 This illustrates an example implementation. Figure 22 A block diagram of an example of one of a plurality of memory chips in a memory device.

[0034] Figure 24 Showing an example implementation Figure 23 An example of the first memory bank array in a memory chip.

[0035] Figure 25 This illustrates an example implementation. Figure 1 A block diagram of an example storage device.

[0036] Figure 26 This is a flowchart illustrating a method for operating a storage device according to an example embodiment.

[0037] Figure 27 This is a block diagram illustrating an electronic system including a semiconductor device according to some example embodiments. Detailed Implementation

[0038] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, in which some exemplary embodiments are shown.

[0039] Figure 1 This is a block diagram illustrating a storage device according to an example embodiment.

[0040] Reference Figure 1 The storage device 10 may include a memory controller 50 and a memory device 90. The memory device 90 may include multiple memory chips (or chips) (CHIP1, CHIP2, ..., CHIPk) 100a, 100b, ..., 100k, and the multiple memory chips 100a, 100b, ..., 100k may share a channel (e.g., a communication channel) CH. Here, k is an integer greater than two. The memory controller 50 can control the memory device 90 by communicating with it via the channel CH. The memory controller 50 can send commands / addresses (C / A) to the multiple memory chips 100a, 100b, ..., 100k, and can exchange data (DTA) with the multiple memory chips 100a, 100b, ..., 100k via the channel CH.

[0041] Each of the multiple memory chips 100a, 100b, ..., 100k may include a corresponding one of the adaptive volume bias generators ABBG1, ABBG2, ..., ABBGk and a corresponding one of the transfer drivers TDR1, TDR2, ..., TDRk.

[0042] The memory controller 50 can select one of a plurality of memory chips 100a, 100b, ..., 100k as the target memory chip, and can select the remaining memory chips of the plurality of memory chips 100a, 100b, ..., 100k other than the target memory chip as non-target memory chips.

[0043] The memory controller 50 can store data (e.g., write data) DTA in the target memory chip in write mode and can read data (e.g., read data) DTA from the target memory chip in read mode.

[0044] A first adaptive body bias generator ABBG1 in the target memory chip (e.g., memory chip 100a) can apply different body biases to the transfer driver TDR1 in write and read modes. For example, the first adaptive body bias generator ABBG1 can reduce the capacitance of the input / output pads in write mode by applying an inverse body bias to the transfer driver TDR1 in write mode and a normal body bias (e.g., a positive body bias) to the transfer driver TDR1 in read mode.

[0045] Each of the adaptive body bias generators ABBG2, ..., ABBGk for non-target memory chips (e.g., memory chips 100b, ..., 100k) can apply a different body bias to a corresponding one of the transfer drivers TDR2, ..., TDRk based on whether the corresponding on-chip termination (ODT, also known as on-chip terminal) function is enabled. For example, each of the adaptive body bias generators ABBG2, ..., ABBGk can apply a normal body bias to a corresponding one of the transfer drivers TDR2, ..., TDRk when the ODT function is enabled, and can apply an inverse body bias to a corresponding one of the transfer drivers TDR2, ..., TDRk when the ODT function is disabled, and thus reduce the capacitance of the input / output pads.

[0046] The memory controller 50 may include the processor 60 and may be referred to as the memory controller.

[0047] Figure 2 This illustrates an example implementation. Figure 1 A block diagram of an example memory controller in a storage device.

[0048] Reference Figure 2 The memory controller 50 may include a processor 60, an error correction code (ECC) engine 70, an on-chip memory 75, an advanced encryption standard (AES) engine 80, a host interface 82, a read-only memory (ROM) 84, and a memory interface 86 connected via a bus 55.

[0049] Processor 60 controls the overall operation of memory controller 50. Processor 60 controls ECC engine 70, on-chip memory 75, AES engine 80, host interface 82, ROM 84, and memory interface 86. Processor 60 may include one or more cores (e.g., homogeneous multi-core or heterogeneous multi-core). Processor 60 may be or include at least one of, for example, a central processing unit (CPU), image signal processor (ISP), digital signal processor (DSP), graphics processing unit (GPU), vision processor (VPU), and neural processor (NPU). Processor 60 can execute various applications loaded onto on-chip memory 75 (e.g., flash translation layer (FTL) 77 and firmware).

[0050] On-chip memory 75 can store various application programs that can be executed by processor 60. On-chip memory 75 can operate as a cache adjacent to processor 60. On-chip memory 75 can store commands, addresses, and data to be processed by processor 60, or it can store the processing results of processor 60. On-chip memory 75 can be, for example, a storage medium or working memory (including latches, registers, static random access memory (SRAM), dynamic random access memory (DRAM), thyristor random access memory (TRAM), tightly coupled memory (TCM), etc.).

[0051] Processor 60 can execute FTL 77 loaded onto on-chip memory 75. FTL 77 can be loaded onto on-chip memory 75 as firmware or a program stored in at least one of a plurality of memory chips 100a, 100b, ..., 100k. FTL 77 can manage the mapping between logical addresses provided from the host and the physical addresses of at least one of the plurality of memory chips 100a, 100b, ..., 100k, and may include an address mapping table manager that manages and updates the address mapping table. FTL 77 can also perform garbage collection operations, wear leveling operations, and the aforementioned address mapping. FTL 77 can be executed by processor 60 to address one or more of the following aspects of at least one of the plurality of memory chips 100a, 100b, ..., 100k: overwrite-infeasibility or in-situ write-infeasibility, memory cell lifetime, a limited number of program-erase (PE) cycles, and an erase speed slower than the write speed.

[0052] The memory cells of multiple memory chips 100a, 100b, ..., 100k may have physical characteristics where the threshold voltage distribution varies due to factors such as programming elapsed time, temperature, programming interference, and read interference. For example, the data stored in the multiple memory chips 100a, 100b, ..., 100k may become erroneous due to the above reasons.

[0053] The memory controller 50 can utilize various error correction techniques to correct such errors. For example, the memory controller 50 may include an ECC engine 70. The ECC engine 70 can correct errors occurring in data stored in a plurality of memory chips 100a, 100b, ..., 100k. The ECC engine 70 may include an ECC encoder 71 and an ECC decoder 73. The ECC encoder 71 can perform ECC encoding operations on data to be stored in at least one of the plurality of memory chips 100a, 100b, ..., 100k. The ECC decoder 73 can perform ECC decoding operations on data read from at least one of the plurality of memory chips 100a, 100b, ..., 100k. The ECC decoder 73 can correct errors in the hard decision data based on hard decision data and soft decision data read from at least one of the plurality of memory chips 100a, 100b, ..., 100k.

[0054] ROM 84 can store various information required for the operation of memory controller 50 in firmware.

[0055] The AES engine 80 can perform at least one of encryption and decryption operations on data input to the memory controller 50 using a symmetric key algorithm. Although not shown in detail, the AES engine 80 may include an encryption module and a decryption module. For example, the encryption and decryption modules may be implemented as separate modules. As another example, a module capable of performing both encryption and decryption operations may be implemented within the AES engine 80.

[0056] The memory controller 50 can communicate with the host via the host interface 82. For example, the host interface 82 may include Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC, Peripheral Component Interconnect (PCI), PCI Express, Advanced Technology Accessory (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Device (IDE), Mobile Industry Processor Interface (MIPI), Non-Volatile Memory Express (NVMe), Universal Flash Memory (UFS), etc. The memory controller 50 can communicate with the memory device 90 via the memory interface 86. The memory interface 86 may be referred to as a storage interface.

[0057] Figure 3 Showing an example implementation Figure 1 Example of the connection between the memory controller and the memory device in a storage device.

[0058] Reference Figure 3 The storage device 10a may include a memory device 90a and a memory controller 50. Figure 3The interface between memory device 90a and memory controller 50 is shown in detail.

[0059] Memory device 90a may include first to eighth pins P11, P12, P13, P14, P15, P16, P17, and P18, interface circuitry 95, and a plurality of memory chips (CHIP1, CHIP2, CHIP3, and CHIP4) 100a, 100b, 100c, and 100d. Interface circuitry 95 may be referred to as first interface circuitry. Each of the plurality of memory chips 100a, 100b, 100c, and 100d may include a corresponding one of ODT circuits (ODTC) 550a, 550b, 550c, and 550d.

[0060] Interface circuit 95 can receive the chip enable signal nCE from memory controller 50 via first pin P11. Interface circuit 95 can send signals to memory controller 50 and receive signals from memory controller 50 via second pin P12 to eighth pin P18 in response to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., low level), interface circuit 95 can send signals to memory controller 50 and receive signals from memory controller 50 via second pin P12 to eighth pin P18.

[0061] Interface circuit 95 can receive command latch enable signal CLE, address latch enable signal ALE, and write enable signal nWE from memory controller 50 via pins P12 to P14. Interface circuit 95 can receive data signal DQ from memory controller 50 via pin P17, or can send data signal DQ to memory controller 50. Command CMD, address ADDR, and data DTA can be sent via data signal DQ. For example, data signal DQ can be sent via multiple data signal lines. In this case, pin P17 may include multiple pins corresponding to multiple data signals DQ respectively.

[0062] Interface circuit 95 can obtain command CMD from data signal DQ received in the enable segment (e.g., high state) of command latch enable signal CLE based on the switching time of write enable signal nWE. Interface circuit 95 can obtain address ADDR from data signal DQ received in the enable segment (e.g., high state) of address latch enable signal ALE based on the switching time of write enable signal nWE.

[0063] In some example implementations, the write enable signal nWE may be held statically (e.g., high or low) and may toggle between high and low. For example, the write enable signal nWE may toggle during the segment in which command CMD or address ADDR is sent. Therefore, interface circuitry 95 may obtain command CMD or address ADDR based on the toggle timing of the write enable signal nWE.

[0064] Interface circuit 95 can receive the read enable signal nRE from memory controller 50 via pin 5 P15. Interface circuit 95 can receive the data strobe signal DQS from memory controller 50 via pin 6 P16, or can send the data strobe signal DQS to memory controller 50.

[0065] In the data output operation of memory device 90a, interface circuit 95 may receive a read enable signal nRE switched via pin 5 P15 before outputting data DTA. Interface circuit 95 may generate a data strobe signal DQS that switches based on the switching of the read enable signal nRE. For example, interface circuit 95 may generate a data strobe signal DQS that starts switching after a predetermined delay (e.g., tDQSRE) based on the switching start time of the read enable signal nRE. Interface circuit 95 may transmit a data signal DQ including data DTA based on the switching time of the data strobe signal DQS. Therefore, data DTA may be aligned with the switching time of data strobe signal DQS and may be sent to memory controller 50.

[0066] In the data input operation of memory device 90a, when a data signal DQ including data DTA is received from memory controller 50, interface circuit 95 can receive a switched data strobe signal DQS from memory controller 50 along with the data DTA. Interface circuit 95 can obtain data DTA from data signal DQ based on the switching time point of data strobe signal DQS. For example, interface circuit 95 can sample data signal DQ at the rising and falling edges of data strobe signal DQS and obtain data DTA.

[0067] Interface circuit 95 can receive the ODT signal ODTx from memory controller 50 via pin 8 P18. The ODT signal ODTx can indicate (e.g., specify) whether each of ODT circuits 550a, 550b, 550c and 550d is enabled.

[0068] Interface circuit 95 can provide commands / addresses (CMD / ADDR) to multiple memory chips 100a, 100b, 100c, and 100d, provide data DTA to a target memory chip among the multiple memory chips 100a, 100b, 100c, and 100d (e.g., memory chip 100a), and transmit data DTA received from the target memory chip to memory controller 50. In the following description, it is assumed that memory chip 100a is selected as the target memory chip by memory controller 50.

[0069] The memory controller 50 may include first to eighth pins P21, P22, P23, P24, P25, P26, P27, and P28, as well as interface circuitry 87. Interface circuitry 87 may be referred to as a second interface circuit. Interface circuitry 87 can be connected to... Figure 2 The memory interface 86 corresponds to this. The first pin P21 to the eighth pin P28 can correspond to the first pin P11 to the eighth pin P18 of the memory device 90a, respectively.

[0070] Interface circuit 87 can send the chip enable signal nCE to memory device 90a via the first pin P21. Interface circuit 87 can send signals to memory device 90a selected by chip enable signal nCE and receive signals from memory device 90a selected by chip enable signal nCE via the second pin P22 to the eighth pin P28.

[0071] Interface circuit 87 can send the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to memory device 90a via pins P22 to P24. Interface circuit 87 can send the data signal DQ to memory device 90a or receive the data signal DQ from memory device 90a via pin P27.

[0072] Interface circuit 87 can send a data signal DQ, including command CMD or address ADDR, to memory device 90a along with a switching write enable signal nWE. Interface circuit 87 can also send the data signal DQ, including command CMD, to memory device 90a by sending a command latch enable signal CLE with an enabled state. Furthermore, interface circuit 87 can send the data signal DQ, including address ADDR, to memory device 90a by sending an address latch enable signal ALE with an enabled state.

[0073] Interface circuit 87 can send the read enable signal nRE to memory device 90a via pin 5 P25. Interface circuit 87 can receive the data strobe signal DQS from memory device 90a or send the data strobe signal DQS to memory device 90a via pin 6 P26.

[0074] Interface circuit 87 can specify whether each of the ODT circuits 550a, 550b, 550c and 550d is enabled by sending the ODT signal ODTx to multiple memory chips 100a, 100b, 100c and 100d via pin 8 P28.

[0075] Figure 4 This illustrates an example implementation. Figure 3 Timing diagram of chip selection operation for memory devices in the image.

[0076] Reference Figure 3 and Figure 4 The chip selection operation can be an operation for selecting a target memory chip among multiple memory chips based on a chip enable signal nCE and a data signal DQ, and can be performed via a chip enable reduction (CER) mode (e.g., in CER mode, multiple memory chips jointly receive the chip enable signal nCE and the chip address CHIP_ADDR). During the interval when the chip enable signal nCE is in an enabled state (e.g., low level (“L”)) and each of the command latch enable signal CLE and the address latch enable signal ALE is in an enabled state (e.g., high level), the memory device 90a can receive the command CMD and the address ADDR via the data signal DQ received via a seventh pin P17, which includes multiple pins. For example, the command CMD can be “E1h”, and the command CMD and the address ADDR can be sent as a command set.

[0077] For example, a portion of the bits in address ADDR may include the chip address CHIP_ADDR, and memory device 90a can determine the target memory chip and non-target memory chip among a plurality of memory chips 100a, 100b, 100c, and 100d based on the chip address CHIP_ADDR. Each of the plurality of memory chips 100a, 100b, 100c, and 100d can receive the chip address CHIP_ADDR, and the chip address CHIP_ADDR can be compared with an identifier address that identifies a corresponding one of the plurality of memory chips 100a, 100b, 100c, and 100d, and the result of the comparison can be used to determine whether each of the plurality of memory chips 100a, 100b, 100c, and 100d is a target memory chip or a non-target memory chip. Figure 4 In this context, "R" indicates a reserved bit.

[0078] Figure 5 This illustrates an example implementation. Figure 3 A block diagram of an example of one of a plurality of memory chips in a memory device.

[0079] exist Figure 5In the figure, the configuration of memory chip 100a is shown, and the configuration of each of memory chips 100b, 100c and 100d may be substantially the same as that of memory chip 100a.

[0080] Reference Figure 5 The memory chip 100a may include a memory cell array 200a and peripheral circuitry 250a.

[0081] The memory cell array 200a may include memory planes PLN1 (210), PLN2 (220), PLN3 (230) and PLN4 (240) corresponding to different bit lines.

[0082] The peripheral circuitry 250a may include multiple page buffer circuits 410a, 410b, 410c and 410d, data input / output (I / O) circuitry 420a, adaptive volume bias generator 460a, control circuitry 480a, voltage generator 500a, ODT circuitry 550a and address decoder 300a.

[0083] Memory cell array 200a can be coupled to address decoder 300a via serial select line SSL, multiple word lines WL, and ground select line. Each of the multiple page buffer circuits 410a, 410b, 410c, and 410d can be connected to a corresponding one of the multiple memory planes 210, 220, 230, and 240 via a corresponding bit line BL. The multiple memory planes 210, 220, 230, and 240 may include multiple non-volatile memory cells coupled to multiple word lines WL and multiple bit lines BL. In some example embodiments, memory cell array 200a can store write data and provide read data.

[0084] Each of the multiple memory planes 210, 220, 230, and 240 may include multiple memory blocks, and each memory block may have a three-dimensional (3D) structure. Each memory block may include multiple (vertical) cell strings, and each cell string includes multiple memory cells stacked relative to each other.

[0085] Each of the multiple page buffer circuits 410a, 410b, 410c and 410d can be connected to the data I / O circuit 420a via the corresponding data line DL.

[0086] Control circuit 480a can receive commands CMD, address ADDR, control signal CTRL, and ODT signal ODTx from memory controller 50, and can control the erase cycle, programming cycle, and read operation of memory chip 100a based on commands CMD, address ADDR, and control signal CTRL. The programming cycle may include programming operations and programming verification operations, and the erase cycle may include erase operations and erase verification operations. Control circuit 480a can determine whether to enable ODT circuit 550a based on ODT signal ODTx. In addition, control circuit 480a can control adaptive volume bias generator 460a based on commands CMD and ODT signal ODTx.

[0087] In the example implementation, the control circuit 480a can generate a control signal CTL for controlling the voltage generator 500a based on the command CMD, and can provide the control signal CTL to the voltage generator 500a. It can also generate a page buffer control signal PCTL for controlling multiple page buffer circuits 410a, 410b, 410c and 410d, and can provide the page buffer control signal PCTL to the multiple page buffer circuits 410a, 410b, 410c and 410d.

[0088] Furthermore, control circuit 480a can generate a mode signal MS specifying a write or read mode based on command CMD, and can provide the mode signal MS to adaptive body bias generator 460a. Control circuit 480a can generate an ODT control signal OCTL based on ODT signal ODTx, and can provide the ODT control signal OCTL to adaptive body bias generator 460a and ODT circuit 550a. Additionally, control circuit 480a can selectively activate internal chip enable signal InCE1 by comparing the chip address included in address (signal) ADDR with the identifier address, and can indicate that memory chip 100a is the target memory chip.

[0089] Furthermore, the control circuit 480a can generate a row address R_ADDR and a column address C_ADDR based on the address (signal) ADDR. The control circuit 480a can provide the row address R_ADDR to the address decoder 300a, and can provide the column address C_ADDR to the data I / O circuit 420a.

[0090] Address decoder 300a can be integrated into memory cell array 200a via serial select line SSL, multiple word lines WL, and ground select line GSL. During programming or reading operations, address decoder 300a can determine one of the multiple word lines WL as the selected word line based on row address R_ADDR, and can determine the remaining word lines WL besides the selected word line as unselected word lines.

[0091] Voltage generator 500a can generate word line voltages VWL associated with the operation of memory chip 100a using power PWR supplied from memory controller 50, based on control signal CTL from control circuit 480a. Word line voltages VWL can include programming voltage, read voltage, pass voltage, erase verification voltage, or program verification voltage. Word line voltages VWL can be applied to multiple word lines WL via address decoder 300a.

[0092] For example, during an erase operation, voltage generator 500a can apply an erase voltage to the channels of the cell string of the selected memory block, and can apply a ground voltage to all word lines of the selected memory block. During an erase verification operation, voltage generator 500a can apply an erase verification voltage to all word lines of the selected memory block, or can apply an erase verification voltage to word lines of the selected memory block on a word line basis.

[0093] For example, during a programming operation, voltage generator 500a can apply a programming voltage to the selected word line and a programming pass voltage to the unselected word line. Furthermore, during a programming verification operation, voltage generator 500a can apply a programming verification voltage to the selected word line and a verification pass voltage to the unselected word line. Additionally, during a reading operation, voltage generator 500a can apply a reading voltage to the selected word line and a reading pass voltage to the unselected word line.

[0094] Each of the multiple page buffer circuits 410a, 410b, 410c, and 410d may include multiple page buffers PB. Each of the multiple page buffer circuits 410a, 410b, 410c, and 410d may temporarily store data to be programmed into or read from selected pages of the memory cell array 200a.

[0095] In the example implementation, the page buffer cells included in each of the multiple page buffers (PB) and the cache latches included in each of the multiple page buffers (PB) can be separated from each other and have individual structures. Therefore, the degrees of freedom for the lines on the page buffer cells can be increased, and the complexity of the layout can be reduced. Furthermore, because the cache latches are adjacent to the data I / O lines, the distance between the cache latches and the data I / O lines can be reduced, thus increasing the data I / O speed.

[0096] The data I / O circuit 420a can be connected to the data I / O pin 101 to receive data DTA from the memory controller 50 or to send data DTA to the memory controller 50.

[0097] The adaptive volume bias generator 460a can apply different volume biases to the transfer driver in the data I / O circuit 420a in write and read modes based on the mode signal MS. For example, in write mode where the memory chip 100a receives data DTA from the memory controller 50, the adaptive volume bias generator 460a can apply an inverted volume bias RBB to the transfer driver in the data I / O circuit 420a, while in read mode where the memory chip 100a sends data DTA to the memory controller 50, the adaptive volume bias generator 460a can apply a normal volume bias NBB to the transfer driver in the data I / O circuit 420a.

[0098] The ODT circuit 550a can be coupled to the data I / O pin 101, can be selectively enabled based on the ODT control signal OCTL, and can provide a termination resistance to the data transmission line (or transmission line) coupled to the data I / O pin 101 when the data I / O circuit 420a transmits or receives data DTA.

[0099] Figure 6A Showing an example implementation Figure 5 An example of data I / O circuitry in a memory chip.

[0100] Reference Figure 6A The data I / O circuit 420a may include a data input circuit 430a and a data output circuit 435a. The data output circuit 435a may include a pre-driver 440a and a transfer driver 450a.

[0101] Data input circuit 430a may be based on data from memory controller 50 (see...) Figure 3 The data signal DQ receives data DTA, converts the data DTA into internal data IDTA, and provides the internal data IDTA to one of page buffer circuits 410a, 410b, 410d, and 410d. The data output circuit 435a converts the internal data IDTA from one of the page buffer circuits 410a, 410b, 410d, and 410d, and can output it via interface circuit 95 (see...). Figure 3 The data DTA is provided to the memory controller 50.

[0102] The pre-driver 440a can receive internal data ITA, generate pull-up drive signal PUDS and pull-down drive signal PDDS based on pull-up control code PUCD and pull-down control code PDCD, and provide the pull-up drive signal PUDS and pull-down drive signal PDDS to the transmission driver 450a.

[0103] For example, when the internal data IDTA is high, the pre-driver 440a can buffer the pull-up control code PUCD and generate a pull-up drive signal PUDS that is substantially the same as the pull-up control code PUCD, and can generate a pull-down driver (such as in the transmission driver 450a) for use with the pull-down driver included in the transmission driver 450a. Figure 6B The pull-down drive signal PDDS is a pull-down drive signal that turns off all transistors in the pull-down driver 453 shown in the diagram. Conversely, when the internal data IDTA is low, the pre-driver 440a buffers the pull-down control code PDCD and generates the pull-down drive signal PDDS to be substantially the same as the pull-down control code PDCD, and generates a signal to enable the pull-up driver (such as in the transmission driver 450a) included in the transmission driver 450a. Figure 6B The pull-up drive signal PUDS in the pull-up driver 451 (shown in the diagram) turns off all transistors. When the transfer driver 450a outputs data DTA, the pre-driver 440a can determine the current generated by the pull-up driver 451 and (in the diagram) the pull-up drive signal PUDS. Figure 6B (The resistor of the pull-down driver 453 is shown in the figure.)

[0104] The transmission driver 450a can receive normal body bias NBB or reverse body bias RBB based on the operating mode.

[0105] Figure 6B This illustrates an example implementation. Figure 6A The circuit diagram of the transfer driver in the data I / O circuit.

[0106] Reference Figure 6B The transfer driver 450a may include a pull-up driver 451 and a pull-down driver 453.

[0107] Pull-up driver 451 may include a first pull-up transistor NU1 to an r-th pull-up transistor NUr (r is a natural number greater than one) connected between the power supply voltage VCCQ and the output node ON1. Each of the first pull-up transistor NU1 to the r-th pull-up transistor NUr may be an n-type metal-oxide-semiconductor (NMOS) transistor.

[0108] The pull-down driver 453 may include a first pull-down transistor ND1 to an r-th pull-down transistor NDr connected between the output node ON1 and the ground voltage VSS. Each of the first pull-down transistors ND1 to the r-th pull-down transistor NDr may be an NMOS transistor.

[0109] When the internal data IDTA is high, the pull-up driver 451 can receive the pull-up drive signal PUDS (e.g., PUDS[1] to PUDS[r]) corresponding to the pull-up control code PUCD from the pre-driver 440a, and generate the current determined by the pull-up control code PUCD. The pull-down transistors ND1 to NDr included in the pull-down driver 453 can all be turned off according to the pull-down drive signal PDDS (e.g., PDDS[1] to PDDS[r]).

[0110] At this time, the current generated by the pull-up driver 451 can be sent to the on-chip termination (ODT) resistor RODT_MC in the memory controller 50 via the data I / O pin 101. The data signal DQ received by the ODT resistor RODT_MC is determined by the current generated by the pull-up driver 451 and the ODT resistor RODT_MC.

[0111] When the internal data IDTA is low, the pull-up transistors NU1 to NUR in the pull-up driver 451 can all be turned off according to the pull-up drive signal PUDS. The pull-down driver 453 can receive the pull-down drive signal PDDS corresponding to the pull-down control code PDCD from the pre-driver 440a, and can have a resistor determined by the pull-down control code PDCD.

[0112] At this time, no current is generated by the pull-up driver 451, and therefore, the data signal DQ received by the ODT resistor RODT_MC has an output low-level voltage that is essentially the same as the ground voltage VSS.

[0113] According to the example implementation, the total resistance (e.g., terminating resistance (RTT)) of the pull-up driver 451 or pull-down driver 453 may be changed in response to a specific pull-up drive signal PUDS or pull-down drive signal PDDS.

[0114] Figure 7 This illustrates an example implementation. Figure 5 A block diagram of an example adaptive volume bias generator in a memory chip.

[0115] Reference Figure 7 The adaptive body bias generator 460a may include a first bias voltage generator 465 and a second bias voltage generator 470.

[0116] When the memory chip 100a, including the adaptive volume bias generator 460a, is selected as the target memory chip, the first bias voltage generator 465 can generate bias voltages VB11 and VB12 based on the mode signal MS and the ground voltage VSS, and can apply the bias voltages VB11 and VB12 to... Figure 1The body of the NMOS transistor in the transfer driver TDR1. The second bias voltage generator 470 can generate bias voltages VB21 and VB22 based on the mode signal MS and the power supply voltage VDD, and can apply bias voltages VB21 and VB22 to... Figure 1 The main body of the PMOS transistor in the transmission driver TDR1.

[0117] The bias voltage VB11 can correspond to the ground voltage VSS, and the bias voltage VB12 can correspond to a negative voltage less than the ground voltage VSS. The bias voltage VB21 can correspond to the power supply voltage VDD, and the bias voltage VB22 can correspond to a voltage greater than the power supply voltage VDD.

[0118] When the memory chip 100a, including the adaptive volume bias generator 460a, is a non-target memory chip, the first bias voltage generator 465 can generate bias voltages VB11 and VB12 based on the ODT control signal OCTL and the ground voltage VSS, and can apply the bias voltages VB11 and VB12 to... Figure 1 The main body of the NMOS transistor in the transfer driver TDR1. The second bias voltage generator 470 can generate bias voltages VB21 and VB22 based on the ODT control signal OCTL and the power supply voltage VDD, and can apply the bias voltages VB21 and VB22 to... Figure 1 The main body of the PMOS transistor in the transmission driver TDR1.

[0119] Figure 8 This illustrates an example implementation. Figure 5 A block diagram illustrating an example of a memory plane in a memory chip.

[0120] Reference Figure 8 The memory plane 210 may include multiple memory blocks BLK1, BLK2, ..., BLKz extending along multiple directions HDR1, HDR2, and VDR. Here, z is an integer greater than two. In some embodiments, the memory blocks BLK1, BLK2, ..., BLKz are... Figure 5 The address decoder 300a is selected. For example, the address decoder 300a can select the memory block corresponding to the block address from memory blocks BLK1, BLK2, ..., BLKz.

[0121] Figure 9 It is shown Figure 8 A circuit diagram of one of the memory blocks.

[0122] Figure 9The memory block BLKi can be formed on the substrate SUB in a three-dimensional (or vertical) structure. For example, multiple (memory) cell strings included in the memory block BLKi can be formed on the vertical direction VDR perpendicular to the substrate SUB.

[0123] Reference Figure 9 The memory block BLKi may include multiple cell strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 (hereinafter referred to as NS11 to NS33) coupled between bit lines BL1, BL2, and BL3 and the common-source line CSL. Each of the cell strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8 (hereinafter referred to as MC1 to MC8), and a ground select transistor GST. Figure 9 In the illustration, each of the cell strings NS11 to NS33 is shown as comprising eight memory cells MC1 to MC8. However, this disclosure is not limited thereto. In some example embodiments, each of the cell strings NS11 to NS33 may include any number of memory cells.

[0124] The serial select transistor SST can be connected to the corresponding serial select lines SSL1, SSL2, and SSL3 (hereinafter referred to as SSL1 to SSL3). Multiple memory cells MC1 to MC8 can be connected to the corresponding word lines WL1 to WL8, respectively. The ground select transistor GST can be connected to the corresponding ground select lines GSL1, GSL2, and GSL3 (hereinafter referred to as GSL1 to GSL3). The serial select transistor SST can be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground select transistor GST can be connected to the common source line CSL.

[0125] Word lines with the same height (e.g., WL1) can be connected together, while ground select lines GSL1 to GSL3 and string select lines SSL1 to SSL3 can be separated.

[0126] Figure 10 This illustrates an example implementation. Figure 5 A block diagram of a portion of a memory chip.

[0127] exist Figure 10 The image shows an adaptive volume bias generator 460a, a receive buffer (RBF) 433a, a transfer driver 450a, and an ODT circuit 550a in a memory chip 100a.

[0128] Reference Figure 10The receive buffer 433a, the transfer driver 450a, and the ODT circuit 550a can be coupled to the data I / O pin 101 at the output node ON1. The transfer driver 450a can drive the data I / O pin 101 based on read data, and the receive buffer 433a can receive write data provided through the data I / O pin 101. For example, the transfer driver 450a can transmit read data through a data transmission line coupled to the data I / O pin 101, and the receive buffer 433a can receive write data through the data transmission line.

[0129] The ODT circuit 550a may include a terminating controller 560 and a terminating resistor unit 570.

[0130] The terminating resistor unit 570 can be coupled to the data I / O pin 101 and can provide terminating impedance to the transmission line coupled to the data I / O pin 101.

[0131] The method for controlling the ODT according to the example embodiment can be applied to the termination of I / O pins to enable bidirectional communication between the memory controller 50 and the memory chip. Therefore, in addition to the data I / O pin 101, the method according to the example embodiment can also be applied to data strobe pins, data mask pins, or termination data strobe pins. The term "pin" broadly refers to an electrical interconnect used in an integrated circuit (e.g., a pad or other electrical contact on an integrated circuit).

[0132] In some implementations, the terminating resistor unit 570 may perform a pull-up terminating operation to provide a terminating resistor between the power supply voltage node and the data I / O pin 101 and / or a pull-down terminating operation to provide a terminating resistor between the ground node and the data I / O pin 101.

[0133] even though Figure 10 Some example implementations are shown equipped with differentiated terminating resistor units 570, where the signal driver in the transfer driver 450a can also be used as a terminating resistor. For example, during a write operation, the transfer driver 450a does not send read data and acts as the terminating resistor unit 570, while the receive buffer 433a is enabled to receive write data.

[0134] When the terminating resistor unit 570 performs a pull-up termination operation, the voltage on the transmission line connected to the data I / O pin 101 can be maintained essentially at the supply voltage level. Therefore, current flows through the terminating resistor unit 570 and the transmission line only when logic low-level data is transmitted.

[0135] The termination controller 560 can receive a control code CCD and an output enable signal OEN. The termination controller 560 can generate a termination control signal TCS based on the control code CCD and the output enable signal OEN to control the termination resistor unit 570 to adjust the termination impedance. The control code CCD and the output enable signal OEN can be included in... Figure 5 In the ODT control signal OCTL.

[0136] In some implementations, the output enable signal OEN is activated during a read operation. When the output enable signal OEN is activated, the termination controller 560 can provide a termination control signal TCS of a predetermined logic level to control the termination resistor unit 570 not to provide termination impedance. In that case, the termination resistor unit 570 can be electrically decoupled from the data I / O pin 101 in response to the termination control signal TCS of the predetermined logic level. When the termination resistor unit 570 is decoupled from the data I / O pin 101, the ODT circuit 550a or the termination resistor unit 570 can be referred to as "disabled".

[0137] When the output enable signal OEN is deactivated during a write operation, the termination controller 560 can generate a termination control signal TCS to control the termination resistor unit 570 to provide termination impedance.

[0138] Based on the mode signal MS indicating the write mode or read mode, the adaptive volume bias generator 460a can apply an inverse volume bias RBB to the transfer driver 450a in write mode and a normal volume bias NBB to the transfer driver 450a in read mode.

[0139] Figure 11 This illustrates an example implementation. Figure 10 A circuit diagram of an example of a transfer driver in a memory chip.

[0140] Reference Figure 11 The transmission driver 450a may include a first NMOS transistor NM1, a second NMOS transistor NM2, and a PMOS transistor PM.

[0141] A first NMOS transistor NM1 can be coupled between the power supply voltage VCCQ and the data I / O pin 101, a second NMOS transistor NM2 can be coupled between the data I / O pin 101 and the ground voltage VSS, and a PMOS transistor PM can be coupled between the power supply voltage VCCQ and the data I / O pin 101. Therefore, each of the first NMOS transistor NM1, the second NMOS transistor NM2, and the PMOS transistor PM can be connected to a data transmission line coupled to the data I / O pin 101.

[0142] The first NMOS transistor NM1 and the PMOS transistor PM can form a pull-up driver, and the second NMOS transistor NM2 can form a pull-down driver. The pull-up control code PUCD11 can be applied to the gate of the first NMOS transistor NM1, the pull-up control code PUCD12 can be applied to the gate of the PMOS transistor PM, and the pull-down control code PDCD11 can be applied to the gate of the second NMOS transistor NM2.

[0143] Figure 10 The adaptive body bias generator 460a can apply a bias voltage VB1 to the body of each of the first NMOS transistor NM1 and the second NMOS transistor NM2, and can apply a bias voltage VB2 to the body of the PMOS transistor PM. The bias voltages VB1 and VB2 can be applied as normal body bias or reverse body bias based on the operating mode of the memory chip 100a.

[0144] Figure 12 This illustrates the write mode according to an example implementation. Figure 3 Storage device.

[0145] exist Figure 12 For ease of explanation, it is assumed that memory chip 100a is selected by memory controller 50 as the target memory chip among a plurality of memory chips 100a, 100b, 100c and 100d (e.g., in...). Figure 12 The memory chips 100b, 100c, and 100d were not selected as non-target memory chips (e.g., in [the context of the memory chips shown as "SEL"). Figure 12 (This is shown as "UNSEL"). Furthermore, it is assumed that ODT circuits 550b and 550c in memory chips 100b and 100c are enabled, and that ODT circuit 550d in memory chip 100d is disabled. Figure 12 In, enabled (e.g., Figure 12 The "ON" element in the text is shaded.

[0146] Reference Figure 12 The memory controller 50 can be connected to memory chips 100a, 100b, 100c, and 100d via data I / O pins PAD1, PAD2, PAD3, and PAD4, and transmission line TL. Transmission line TL can branch at a common node NC to the data I / O pins PAD1, PAD2, PAD3, and PAD4 of memory chips 100a, 100b, 100c, and 100d. Transmission line TL can be connected to the ODT circuitry in a corresponding one of the memory chips 100a, 100b, 100c, and 100d via each of the data I / O pins PAD1, PAD2, PAD3, and PAD4.

[0147] During a write operation (DTA) that transmits data from memory controller 50 to target memory chip 100a, the transfer driver TDR0 is enabled in memory controller 50, and the receive buffer RBF0 and ODT circuit ODTC0 are disabled. In memory chip 100a corresponding to the target memory chip, the receive buffer 433a, ODT circuit 550a, and adaptive volume bias generator 460a are enabled, and the transfer driver 450a is disabled. Furthermore, in memory chips 100b, 100c, and 100d corresponding to non-target memory chips, the receive buffers 433b, 433c, and 433d, as well as the transfer drivers 450b, 450c, and 450d, are disabled; the ODT circuits 550b and 550c in memory chips 100b and 100c are enabled, and the ODT circuit 550d in memory chip 100d is disabled.

[0148] An adaptive body bias generator 460a in memory chip 100a corresponding to the target memory chip applies an inverse body bias RBB to the transfer driver 450a; an adaptive body bias generator 460b in memory chip 100b including an enabled ODT circuit 550b applies a normal body bias NBB to the transfer driver 450b; an adaptive body bias generator 460c in memory chip 100c including an enabled ODT circuit 550c applies a normal body bias NBB to the transfer driver 450c; and an adaptive body bias generator 460d in memory chip 100d including a disabled ODT circuit 550d applies an inverse body bias RBB to the transfer driver 450d.

[0149] Therefore, the junction capacitance of each of the transmission drivers 450a and 450d with the reverse body bias RBB applied is reduced, and thus, the capacitance of I / O pins PAD1 and PAD4 can be reduced.

[0150] Figure 13 This illustrates the reading mode according to an example implementation. Figure 3 Storage device.

[0151] exist Figure 13 For ease of explanation, it is assumed that memory chip 100a is selected by memory controller 50 as the target memory chip among multiple memory chips 100a, 100b, 100c, and 100d, and memory chips 100b, 100c, and 100d are not selected as non-target memory chips. Furthermore, it is assumed that ODT circuits 550b and 550c in memory chips 100b and 100c are enabled, and ODT circuit 550d in memory chip 100d is disabled. Figure 13 In the image, enabled elements are highlighted with a shadow.

[0152] Reference Figure 13 The memory controller 50 can be connected to memory chips 100a, 100b, 100c, and 100d via data I / O pins PADC, PAD1, PAD2, PAD3, and PAD4, and transmission line TL. Transmission line TL can branch at the common node NC to the data I / O pins PAD1, PAD2, PAD3, and PAD4 of memory chips 100a, 100b, 100c, and 100d.

[0153] During the read mode (read operation) when data DTA is sent from memory chip 100a to memory controller 50, in memory controller 50, transfer driver TDR0 is disabled, and receive buffer RBF0 and ODT circuit ODTC0 are enabled. In memory chip 100a corresponding to the target memory chip, transfer driver 450a and adaptive volume bias generator 460a are enabled, and receive buffer 433a and ODT circuit 550a are disabled. Furthermore, in memory chips 100b, 100c, and 100d corresponding to non-target memory chips, receive buffers 433b, 433c, and 433d and transfer drivers 450b, 450c, and 450d are disabled, ODT circuits 550b and 550c in memory chips 100b and 100c are enabled, and ODT circuit 550d in memory chip 100d is disabled.

[0154] An adaptive volume bias generator 460a in memory chip 100a corresponding to the target memory chip applies a normal volume bias NBB to the transfer driver 450a; an adaptive volume bias generator 460b in memory chip 100b including an enabled ODT circuit 550b applies a normal volume bias NBB to the transfer driver 450b; an adaptive volume bias generator 460c in memory chip 100c including an enabled ODT circuit 550c applies a normal volume bias NBB to the transfer driver 450c; and an adaptive volume bias generator 460d in memory chip 100d including a disabled ODT circuit 550d applies a reverse volume bias RBB to the transfer driver 450d.

[0155] Therefore, the junction capacitance of the transfer driver 450d with the reverse body bias RBB applied can be reduced, and thus, the capacitance of the I / O pin PAD4 can be reduced.

[0156] exist Figure 12 and Figure 13In the memory chip 100a corresponding to the target memory chip, the adaptive body bias generator 460a can be a first adaptive body bias generator, the transfer driver 450a can be a first transfer driver, and the body bias applied by the adaptive body bias generator 460a can be a first body bias. Furthermore, in the memory chip 100b including the enabled ODT circuit 550b, the adaptive body bias generator 460b can be a second adaptive body bias generator, the transfer driver 450b can be a second transfer driver, and the body bias applied by the adaptive body bias generator 460b can be a second body bias. Furthermore, in the memory chip 100c including the enabled ODT circuit 550c, the adaptive body bias generator 460c can be a third adaptive body bias generator, the transfer driver 450c can be a third transfer driver, and the body bias applied by the adaptive body bias generator 460c can be a third body bias. Furthermore, the adaptive volume bias generator 460d in the memory chip 100d, including the disabled ODT circuit 550d, can be a fourth adaptive volume bias generator, the transfer driver 450d can be a fourth transfer driver, and the volume bias applied by the adaptive volume bias generator 460d can be a fourth volume bias.

[0157] exist Figure 12 and Figure 13 In the illustration, each of the ODT circuits 550a, 550b, 550c, and 550d is shown to be separate from a corresponding one of the transfer drivers 450a, 450b, 450c, and 450d in the memory chips 100a, 100b, 100c, and 100d. However, according to an example embodiment, each of the transfer drivers 450a, 450b, 450c, and 450d may include ODT functionality, and the ODT functionality of each of the transfer drivers 450a, 450b, 450c, and 450d may be selectively enabled. In other words, each of the adaptive volume bias generators 460a, 460b, 460c, and 460d may apply a normal volume bias NBB or a reverse volume bias RBB to a corresponding one of the transmission drivers 450a, 450b, 450c, and 450d based on whether the ODT function of the corresponding one of the transmission drivers 450a, 450b, 450c, and 450d is enabled. Each of the adaptive volume bias generators 460b and 460c may apply a normal volume bias NBB to a corresponding one of the transmission drivers 450b and 450c based on whether the ODT function of the corresponding one of the transmission drivers 450b and 450c is enabled, and the adaptive volume bias generator 460d may apply a reverse volume bias RBB to the transmission driver 450d based on whether the ODT function of the transmission driver 450d is disabled.

[0158] Furthermore, it is understood that each of the ODT circuits 550a, 550b, 550c and 550d may be included in a corresponding one of the transmission drivers 450a, 450b, 450c and 450d.

[0159] Figure 14 It shows that it is applied to Figure 12 and Figure 13 The table of body bias of the transfer driver in the memory chip.

[0160] Reference Figure 14 Table TB1 shows the body bias of the transfer driver TDR applied to the target memory chip (selected chip) based on the operating mode and the body bias of the transfer driver TDR applied to the non-target memory chip (unselected chip) based on whether the ODT circuit is enabled.

[0161] For reference Figure 12 and Figure 13 As described, in write mode, a reverse body bias (RBB) is applied to the transfer driver 450a in the target memory chip 100a, and in read mode, a normal body bias (NBB) is applied to the transfer driver 450a. Furthermore, a normal body bias (NBB) is applied to the transfer drivers 450b and 450c in memory chips 100b and 100c, which include enabled ODT circuits 550b and 550c, and a reverse body bias (RBB) is applied to the transfer driver 450d in memory chip 100d, which includes disabled ODT circuitry 550d.

[0162] Figure 15 This is a table showing the body bias of the transistors applied to the transfer driver according to an example embodiment.

[0163] Table TB2 shows the application to Figure 11 The transistors in the transmission driver 450a have normal body bias NBB and reverse body bias RBB.

[0164] Reference Figure 15 A bias voltage VB1 corresponding to ground voltage GND can be applied as a normal body bias NBB to at least one NMOS transistor NM in the transmission driver 450a, and a bias voltage VB2 corresponding to power supply voltage VDD can be applied as a normal body bias NBB to at least one PMOS transistor PM in the transmission driver 450a. Furthermore, a bias voltage VB1 less than ground voltage GND can be applied as a reverse body bias RBB to at least one NMOS transistor NM in the transmission driver 450a, and a bias voltage VB2 greater than power supply voltage VDD can be applied as a reverse body bias RBB to at least one PMOS transistor PM in the transmission driver 450a.

[0165] At least one NMOS transistor NM may include a first NMOS transistor NM1 and a second NMOS transistor NM2.

[0166] Figure 16 and Figure 17 yes Figure 11 Cross-sectional views of the PMOS and NMOS transistors in the transmission driver 450a.

[0167] Reference Figure 16 N+ doped regions 451b and 451c, serving as drain and source, can be formed at the P-Sub of the P-type substrate to form an NMOS transistor NM. Additionally, a P+ doped region 451d can be formed at the P-Sub of the P-type substrate to provide NMOS body bias. The gate insulating layer 451f and the gate electrode 451e can be stacked sequentially. A bias voltage VB1 is applied to the P+ doped region 451d.

[0168] When a bias voltage VB1 less than ground voltage is applied as a reverse body bias RBB to the P+ doped region 451d, the depletion region below the gate insulating layer 451f can be increased, and therefore, the junction capacitance of the NMOS transistor NM is reduced.

[0169] Reference Figure 17 An N-well 452a can be formed at the P-sub of a P-type substrate to form a PMOS transistor PM. The N-well 452a can be formed by implanting an N-type dopant into the P-sub of the P-type substrate. Then, P+ doped regions 452b and 452c for the source and drain of the PMOS transistor PM can be formed at the N-well 452a. An N+ doped region 452d for providing PMOS body bias can be formed at the N-well 452a. A gate insulating layer 452e and a gate electrode 452f can be sequentially stacked. The gate insulating layer 452e can be formed from an oxide film, a nitride film, or a film formed by stacking oxide and nitride films. Furthermore, the gate insulating layer 452e can be formed from a metal oxide film with a high dielectric constant, a stacked film formed by stacking metal oxide films in a laminated structure, or a hybrid film formed by mixing metal oxide films and stacked films. The gate electrode 452f can be formed from a polycrystalline silicon film or a metal layer doped with impurity ions. A bias voltage VB2 is applied to the N+ doped region 452d.

[0170] When a bias voltage VB2 greater than the power supply voltage is applied as a reverse body bias RBB to the N+ doped region 452d, the depletion region below the gate insulating layer 452e can be increased, and thus the junction capacitance of the PMOS transistor PM is reduced.

[0171] Figure 18 This illustrates an example implementation. Figure 5 A block diagram of an example of the control circuitry in a memory chip.

[0172] Reference Figure 18 The control circuit 480a may include a command decoder 485a, an address buffer 487a, a control signal generator 490a, a status signal generator 495a, and an address comparator 497a.

[0173] The command decoder 485a can decode the command CMD and provide the decoded command D_CMD to the control signal generator 490a and the status signal generator 495a.

[0174] Address buffer 487a can receive address signal ADDR, provide row address R_ADDR to address decoder 300a, and provide column address C_ADDR to data I / O circuit 420a.

[0175] Control signal generator 490a can receive decoding command D_CMD and ODT signal ODTx. Based on the operation indicated by decoding command D_CMD, it can generate control signal CTL and page buffer control signal PCTL. It can provide control signal CTL to voltage generator 500a and page buffer control signal PCTL to page buffer circuits 410a, 410b, 410c, and 410d. Control signal generator 490a can generate mode signal MS based on the operation pointed to by decoding command D_CMD, and can generate ODT control signal OCTL based on ODT signal ODTx. It can provide mode signal MS and ODT control signal OCTL to adaptive volume bias generator 460a and ODT control signal OCTL to ODT circuit 550a.

[0176] The status signal generator 495a can receive the decoding command D_CMD, monitor the operation pointed to by the decoding command D_CMD, and convert the status signal nR / B into one of the ready state and busy state based on whether the operation pointed to by the decoding command D_CMD has been completed.

[0177] Address comparator 497a compares the chip address CHIP_ADDR with the identifier address ID_ADDR of memory chip 100a, and selectively activates (or generates) the internal chip enable signal InCE1 based on the comparison result. The internal chip enable signal InCE1 specifies the target memory chip. When the chip address CHIP_ADDR matches the identifier address ID_ADDR, address comparator 497a activates the internal chip enable signal InCE1; when the chip address CHIP_ADDR differs from the identifier address ID_ADDR, address comparator 497a deactivates the internal chip enable signal InCE1.

[0178] Figure 19 This is a block diagram illustrating a storage device according to an example embodiment.

[0179] Reference Figure 19 The storage device 10b may include a memory device 90b and a memory controller 50b. The memory device 90b and the memory controller 50b may communicate with each other based on a separate command address (SCA) scheme in which command / address CA and data signals DQ are transmitted separately. Figure 19 The interface between memory device 90b and memory controller 50b is shown in detail.

[0180] Memory device 90b may include first to eighth pins P11', P12', P13', P14', P15', P16', P17', and P18', interface circuitry 95b, and a plurality of memory chips (CHIP1, CHIP2, CHIP3, and CHIP4) 100a, 100b, 100c, and 100d. Interface circuitry 95b may be referred to as first interface circuitry. Each of the plurality of memory chips 100a, 100b, 100c, and 100d may include a corresponding one of ODT circuits 550a, 550b, 550c, and 550d.

[0181] The interface circuit 95b can receive the command / address chip enable signal CA_nCE from the memory controller 50b through the first pin P11', the command / address CA from the memory controller 50b through the second pin P12', the command / address clock signal CA_CLK from the memory controller 50b through the third pin P13', and the SCA enable signal SCA_EN from the memory controller 50b through the fourth pin P14'.

[0182] Interface circuit 95b can receive the read enable signal nRE from memory controller 50b via pin 5 P15'. Interface circuit 95b can receive the data strobe signal DQS from memory controller 50b via pin 6 P16', or can send the data strobe signal DQS to memory controller 50b. Interface circuit 95b can receive the data signal DQ from memory controller 50b via pin 7 P17', or can send the data signal DQ to memory controller.

[0183] Interface circuit 95b can receive the ODT signal ODTx from memory controller 50b via pin 8 P18'. The ODT signal ODTx can indicate (e.g., specify) whether each of ODT circuits 550a, 550b, 550c, and 550d is enabled.

[0184] The memory controller 50b may include first pins to eighth pins P21', P22', P23', P24', P25', P26', P27', and P28', as well as interface circuitry 87b. Interface circuitry 87b may be referred to as a second interface circuit. First pins P21' to eighth pins P28' may correspond to first pins P11' to eighth pins P18' of the memory device 90b, respectively.

[0185] The interface circuit 87b can send the command / address chip enable signal CA_nCE to the memory device 90b through the first pin P21', the command / address CA to the memory device 90b through the second pin P22', the command / address clock signal CA_CLK to the memory device 90b through the third pin P23', and the SCA enable signal SCA_EN to the memory device 90b through the fourth pin P24'.

[0186] Figure 20 This illustrates an example implementation. Figure 19 Timing diagram of chip selection operation for memory devices in the image.

[0187] Reference Figure 19 and Figure 20 The chip selection operation can be an operation for selecting a target memory chip among multiple memory chips based on the command / address chip enable signal CA_nCE and the command / address CA, and can be performed via the SCA scheme. During the period when the command / address chip enable signal CA_nCE is in the enabled state (e.g., low level), the memory device 90b can receive the command / address CA[1:0] via the second pin P12'. The memory controller 50b can send the command / address CA[1:0] to the memory device 90b synchronously with the rising and falling edges of the command / address clock signal CA_CLK. For example, the command / address CA[1:0] can be sent as a select chip enable SCE data packet during the three cycles of the command / address clock signal CA_CLK. In some example embodiments, the memory device 90b (e.g., the control circuit in the memory device (e.g., Figure 18 The control circuit 480a) can selectively activate the internal chip enable signal of the specified target memory chip based on the command / address chip enable signal CA_nCE and the command / address CA[1:0], and generate an ODT control signal that selectively enables the ODT circuit based on the ODT signal.

[0188] For example, the command / address CA[1:0] may include a LUN address LUN_ADDR indicating a valid logical unit number (LUN). For example, the LUN address LUN_ADDR may be sent as part of an SCE packet. Here, a LUN is the smallest unit capable of independently executing a command, and a LUN may correspond to a memory chip. Memory device 90b may determine a target memory chip and a non-target memory chip among a plurality of memory chips 100a, 100b, 100c, and 100d based on the LUN address LUN_ADDR. Each of the plurality of memory chips 100a, 100b, 100c, and 100d may determine whether each of the plurality of memory chips 100a, 100b, 100c, and 100d is a target memory chip or a non-target memory chip based on the LUN address LUN_ADDR.

[0189] Control circuit (e.g., Figure 18 The control circuit 480a) can compare the LUN address LUN_ADDR with the identifier address of each of the memory chips 100a, 100b, 100c, and 100d, and can determine, based on the comparison result, whether each of the multiple memory chips 100a, 100b, 100c, and 100d is a target memory chip or a non-target memory chip. Figure 20 In this context, "R" indicates a reserved bit, and "DIR" indicates the data direction.

[0190] Figure 21 This illustrates an example implementation. Figure 19 Timing diagram of an example of ODT control operation of a memory device.

[0191] Reference Figure 21 The memory device 90b can sequentially receive a selection chip enable signal SCE0 to activate LUN0 and a selection chip termination signal SCT0 to terminate LUN0 via the memory controller 50b (e.g., from the memory controller 50b) through the second pin P12'. The selection chip enable signal SCE0 can be sent in the form of a data packet. The memory chip 100a corresponding to LUN0 is selected in response to the selection chip enable signal SCE0, while the memory chips 100b, 100c, and 100d corresponding to LUN1, LUN2, and LUN3, respectively, may not be selected. The ODT resistance values ​​LUN0_ODT, LUN1_ODT, LUN2_ODT, and LUN3_ODT of the memory chips 100a, 100b, 100c, and 100d can be determined as A1, B1, C1, and D1, respectively.

[0192] The memory device 90b can sequentially receive the selection chip enable signal SCE1 for activating LUN1 and the selection chip termination signal SCT1 for terminating LUN1 via the memory controller 50b through the second pin P12'. The memory chip 100b corresponding to LUN1 is selected in response to the selection chip enable signal SCE1, and the memory chips 100a, 100c, and 100d corresponding to LUN0, LUN2, and LUN3, respectively, may not be selected. The ODT resistance values ​​LUN0_ODT, LUN1_ODT, LUN2_ODT, and LUN3_ODT of the memory chips 100a, 100b, 100c, and 100d can be determined as A2, B2, C2, and D2, respectively.

[0193] The memory device 90b can sequentially receive the selection chip enable signal SCE3 for activating LUN3 and the selection chip termination signal SCT3 for terminating LUN3 via the memory controller 50b through the second pin P12'. The memory chip 100d corresponding to LUN3 is selected in response to the selection chip enable signal SCE3, and the memory chips 100a, 100b, and 100c corresponding to LUN0, LUN1, and LUN2, respectively, may not be selected. The ODT resistance values ​​LUN0_ODT, LUN1_ODT, LUN2_ODT, and LUN3_ODT of the memory chips 100a, 100b, 100c, and 100d can be determined as A4, B4, C4, and D4, respectively.

[0194] The memory device 90b can sequentially receive the selection chip enable signal SCE2 for activating LUN2 and the selection chip termination signal SCT2 for terminating LUN2 via the memory controller 50b through the second pin P12'. The memory chip 100c corresponding to LUN2 is selected in response to the selection chip enable signal SCE2, and the memory chips 100a, 100b, and 100d corresponding to LUN0, LUN1, and LUN3, respectively, may not be selected. The ODT resistance values ​​LUN0_ODT, LUN1_ODT, LUN2_ODT, and LUN3_ODT of the memory chips 100a, 100b, 100c, and 100d can be determined as A3, B3, C3, and D3, respectively.

[0195] Figure 19 Each of the memory chips 100a, 100b, 100c, and 100d in the memory device 90b may include an adaptive volume bias generator, a transfer driver, and ODT circuitry, and may perform reference... Figure 12 and Figure 13 The described operation.

[0196] Figure 22 This is a block diagram illustrating a storage device according to an example embodiment.

[0197] Reference Figure 22 The storage device 10c may include a memory controller 50c and a storage device 90c. The storage device 90c may include a plurality of memory chips (CHIP1, CHIP2, ..., CHIPk) 100aa, 100bb, ..., 100kk, and each of the plurality of memory chips 100aa, 100bb, ..., 100kk may be a volatile memory device (such as DRAM) that includes volatile memory cells coupled to word lines and bit lines.

[0198] Multiple memory chips 100aa, 100bb, ..., 100kk can share a data bus 55 for transmitting data (e.g., data signals) DQ and a command / address (C / A) bus 51 for transmitting commands and / or addresses CA, and can receive the corresponding chip select signals from chip select signals CS1, CS2, ..., CSK. The C / A bus 51 and the data bus 55 (e.g., data transmission lines) can form a channel 53.

[0199] The memory chip selected by the chip selection signals CS1, CS2, ..., CSk with a first logic level from among the multiple memory chips 100aa, 100bb, ..., 100kk is called the target memory chip, and at least one memory chip among the multiple memory chips 100aa, 100bb, ..., 100kk that is not selected by one of the chip selection signals CS1, CS2, ..., CSk with a second logic level is called the non-target memory chip.

[0200] Figure 23 This illustrates an example implementation. Figure 22 A block diagram of an example of one of a plurality of memory chips in a memory device.

[0201] exist Figure 23 In the diagram, the configuration of memory chip 100aa is shown, and the configuration of each of memory chips 100bb, ..., 100kk is substantially the same as that of memory chip 100aa.

[0202] Reference Figure 23 The memory chip 100aa may include control logic circuitry 610, address register 620, memory bank control logic 630, row address multiplexer (RA MUX) 640, column address latch 650, row decoder 660, column decoder 670, memory cell array 710, sense amplifier unit 685, I / O gate circuitry 690, refresh counter 645, data I / O circuitry 720, error correction code (ECC) engine 790, adaptive volume bias generator 730, and ODT circuitry 750.

[0203] The memory cell array 710 may include first memory arrays 710a to sixteenth memory arrays 710p. The row decoder 660 may include first row decoders 660a to sixteenth row decoders 660p respectively coupled to the first memory arrays 710a to sixteenth memory arrays 710p. The column decoder 670 may include first column decoders 670a to sixteenth column decoders 670p respectively coupled to the first memory arrays 710a to sixteenth memory arrays 710p. The sense amplifier unit 685 may include first sense amplifiers 685a to sixteenth sense amplifiers 685p respectively coupled to the first memory arrays 710a to sixteenth memory arrays 710p. The first memory arrays 710a to sixteenth memory arrays 710p, the first row decoders 660a to sixteenth row decoders 660p, the first column decoders 670a to sixteenth column decoders 670p, and the first sense amplifiers 685a to sixteenth sense amplifiers 685p may form the first to sixteenth memory cells.

[0204] Each of the first memory bank arrays 710a to the eighth memory bank arrays 710h may include a plurality of memory cells MC formed at the intersection of a plurality of word lines WL and a plurality of bit lines BTL.

[0205] Address register 620 can be accessed from memory controller 50 (or...) Figure 22 The memory controller 50c receives an address ADDR including the bank address BANK_ADDR, the row address ROW_ADDR, and the column address COL_ADDR. The address register 620 can provide the received bank address BANK_ADDR to the bank control logic 630, the received row address ROW_ADDR to the row address multiplexer 640, and the received column address COL_ADDR to the column address latch 650.

[0206] The memory bank control logic 630 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. One of the first row decoders 660a to the sixteenth row decoders 660p corresponding to the memory bank address BANK_ADDR can be activated in response to the memory bank control signal, and one of the first column decoders 670a to the sixteenth column decoders 670p corresponding to the memory bank address BANK_ADDR can be activated in response to the memory bank control signal.

[0207] The row address multiplexer 640 can receive the row address ROW_ADDR from the address register 620 and the refresh row address REF_ADDR from the refresh counter 645. The row address multiplexer 640 can selectively output one of the row address ROW_ADDR and the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 640 can be applied to the first row decoder 660a through the sixteenth row decoder 660p.

[0208] The refresh counter 645 can sequentially increase or decrease the refresh row address REF_ADDR under the control of the control logic circuit 610.

[0209] One of the first-line decoders 660a to the sixteenth-line decoders 660p, when activated, can decode the line address RA output from the line address multiplexer 640 and can activate the word line corresponding to the line address RA. For example, the activated bank line decoder can apply a word line drive voltage to the word line corresponding to the line address RA.

[0210] Column address latch 650 can receive column address COL_ADDR from address register 620 and can temporarily store the received column address COL_ADDR. In an example implementation, in burst mode, column address latch 650 can generate a column address COL_ADDR' incremented from the received column address COL_ADDR. Column address latch 650 can apply the temporarily stored or generated column address COL_ADDR' to the first column decoder 670a through the sixteenth column decoder 670p.

[0211] One of the first column decoders 670a to the sixteenth column decoder 670p, when activated, can decode the column address COL_ADDR' output from the column address latch 650 and control the I / O gate circuit 690 to output the data corresponding to the column address COL_ADDR.

[0212] I / O gate circuit 690 may include circuitry for gate input / output data. I / O gate circuit 690 may also include a read data latch for storing data output from the first memory array 710a to the sixteenth memory array 710p, and a write driver for writing data to the first memory array 710a to the sixteenth memory array 710p.

[0213] A codeword CW read from one of the memory arrays 710a to 710p can be sensed by a sense amplifier coupled to the memory array from which data will be read, and can be stored in a read data latch. The codeword CW stored in the read data latch can be provided to the ECC engine 790. The ECC engine 790 can perform ECC decoding on the codeword CW to provide data DTA to the data I / O circuit 720. The data I / O circuit 720 can convert the data DTA into a data signal DQ and send the data signal DQ to the memory controller 50c.

[0214] The data signal DQ to be written to one of the memory arrays 710a to 710p can be provided from the memory controller 50c to the data I / O circuit 720. The data I / O circuit 720 can convert the data signal DQ into a data DTA and provide the data DTA to the ECC engine 790. The ECC engine 790 can perform ECC encoding on the data DTA to generate a parity bit, and the ECC engine 790 can provide the data DTA and the parity bit to the I / O gating circuit 690. The I / O gating circuit 690 can write the data DTA and the parity bit into a subpage in a memory array via a write driver.

[0215] The data I / O circuit 720 can drive the bits of the data DTA to generate the data signal DQ, and provide the data signal DQ to the memory controller 50c through the data I / O pin 601.

[0216] The ECC engine 790 can perform ECC encoding and ECC decoding on the data DTA based on the second control signal CTL2 from the control logic circuit 610.

[0217] When memory chip 100aa is selected as the target memory chip, the adaptive body bias generator 730 can apply different body biases to the transfer driver in the data I / O circuit 720 based on the mode signal MS in write and read modes. For example, in write mode where memory chip 100aa receives data signal DQ from memory controller 50c, the adaptive body bias generator 730 can apply an inverted body bias RBB to the transfer driver in the data I / O circuit 720, while in read mode where memory chip 100aa sends data signal DQ to memory controller 50c, the adaptive body bias generator 730 can apply a normal body bias NBB to the transfer driver in the data I / O circuit 720.

[0218] The ODT circuit 750 can be coupled to the data I / O pin 601, can be selectively enabled based on the third control signal CTL3, and can provide a terminating resistor to the data transmission line coupled to the data I / O pin 601 when the data I / O circuit 720 transmits or receives the data signal DQ.

[0219] When memory chip 100aa is not selected as the target memory chip, the adaptive body bias generator 730 can apply different body biases to the transfer driver in the data I / O circuit 720 based on whether the ODT circuit 750 is enabled.

[0220] When the ODT circuit 750 is enabled, the adaptive body bias generator 730 can apply a normal body bias NBB to the transmission driver, and when the ODT circuit 750 is disabled, the adaptive body bias generator 730 can apply a reverse body bias RBB to the transmission driver.

[0221] The control logic circuit 610 can control the operation of the memory chip 100aa. For example, the control logic circuit 610 can generate control signals for the memory chip 100aa to perform write or read operations. The control logic circuit 610 may include a command decoder 611 for decoding commands CMD received from the memory controller 50c, and may include a mode register 612 for setting the operating mode of the memory chip 100aa.

[0222] The command decoder 611 can generate control signals corresponding to the command CMD by decoding the write enable signal, row address strobe signal, column address strobe signal, chip select signal, etc. The control logic circuit 610 can generate a first control signal CTL1 for controlling the I / O gate circuit 690, a second control signal CTL2 for controlling the ECC engine 790, a third control signal CTL3 for controlling the ODT circuit 750, and a mode signal MS for controlling the adaptive body bias generator 730.

[0223] Figure 24 Showing an example implementation Figure 23 An example of the first memory bank array in a memory chip.

[0224] Reference Figure 24The first memory bank array 710a may include multiple word lines WL0 to WLm-1 (m is a natural number greater than two), multiple bit lines BTL0 to BTLn-1 (n is a natural number greater than two), and multiple memory cells MC disposed at the intersections between the word lines WL0 to WLm-1 and the bit lines BTL0 to BTLn-1. Each memory cell MC may include a cell transistor coupled to each of the word lines WL0 to WLm-1 and each of the bit lines BTL0 to BTLn-1, and a cell capacitor coupled to the cell transistor. Each memory cell MC may have a DRAM cell structure. Each of the word lines WL0 to WLm-1 extends in a first horizontal direction HDR1, and each of the bit lines BTL1 to BTLn-1 extends in a second horizontal direction HDR2 that intersects the first horizontal direction HDR1. For example, the second horizontal direction HDR2 is perpendicular to the first horizontal direction HDR1.

[0225] Word lines WL0 to WLm-1, which are associated with multiple memory cells MC, may be referred to as rows of the first memory bank array 710a, and bit lines BTL0 to BTLn-1, which are associated with multiple memory cells MC, may be referred to as columns of the first memory bank array 710a.

[0226] Figure 25 This illustrates an example implementation. Figure 1 A block diagram of an example storage device.

[0227] Reference Figure 25 The storage device 800 may include a memory controller 820 and a package (PKG) 900, the package 900 including a plurality of memory chips 900a to 900k disposed on a printed circuit board (PCB) 810.

[0228] The memory controller 820 and multiple memory chips 900a to 900k can be electrically connected to each other via transmission line 850. The memory controller 820 can send command signals and address signals to the multiple memory chips 900a to 900k, and can exchange data with the multiple memory chips 900a to 900k via transmission line 850.

[0229] The memory controller 820 can be connected to the connector 815 via the transmission line 840, and the connector 815 can be connected to an external host.

[0230] Storage device 800 may include flash-based data storage media such as memory cards, smart cards, universal serial bus (USB) memory, and solid-state drives (SSDs).

[0231] Package 900 may include multiple memory chips 900a to 900k. When multiple memory chips 900a to 900k are included in package 900 in the form of multi-stacked chips, the stacked memory chips 900a to 900k are connected to memory controller 820 through the same channel. Multiple memory chips 900a to 900k may be sequentially stacked on PCB 810 in a direction perpendicular to the surface of PCB 810. When a command associated with a read operation or write operation is received from the host, a specific memory chip (e.g., memory chip 900a) from which data is to be read or to which data is to be written can be selected.

[0232] However, the unselected memory chips 900b to 900k are connected to the memory controller 820 via transmission line 850. Therefore, the channel capacitance may include parasitic capacitances of the unselected memory chips 900b to 900k that are not associated with read or write operations. That is, the capacitance CP1 of memory chip 900a and the capacitances CP2 to CPk of memory chips 900b to 900k can affect the channel capacitance.

[0233] In terms of signal integrity, parasitic capacitance affects data transmission through the channel, and power consumption can increase as parasitic capacitance increases.

[0234] To reduce power consumption, each of the memory chips 900a to 900k may include the aforementioned adaptive body bias generator. The adaptive body bias generator in the selected chip applies a body bias to the corresponding transfer driver, and the applied body bias may vary based on the operating mode. The adaptive body bias generator in the unselected chip applies a body bias to the corresponding transfer driver, and the applied body bias may vary based on whether the ODT function is enabled. Therefore, the adaptive body bias generator can apply a reverse body bias to the corresponding transfer driver in write mode or when the ODT function is disabled, and can reduce power consumption by reducing parasitic capacitance.

[0235] Figure 26 This is a flowchart illustrating a method for operating a storage device according to an example embodiment.

[0236] Reference Figures 1 to 21 and Figure 26 A method for operating a storage device 10a is provided, the storage device 10a including a memory device 90a and a memory controller 50 for controlling the memory device 90a by communicating with the memory device 90a via a channel, wherein the memory device 90a includes a plurality of memory chips 100a, 100b, 100c and 100d sharing a channel.

[0237] According to this method, based on the chip address CHIP_ADDR from the memory controller 50, it is determined whether each of a plurality of memory chips 100a, 100b, 100c and 100d is selected as the target memory chip (operation S110).

[0238] The first adaptive volume bias generator 460a in the first memory chip 100a, selected from multiple memory chips 100a, 100b, 100c and 100d as the target memory chip, applies a first volume bias to the first transfer driver 450a based on whether the operating mode is write mode or read mode (operation S120).

[0239] The second adaptive body bias generator in each of the non-target memory chips 100b, 100c, and 100d (excluding the first memory chip 100a selected as the target memory chip) applies a second body bias to the second transfer driver based on whether the corresponding on-chip termination function is enabled (operation S130).

[0240] Figure 27 This is a block diagram illustrating an electronic system including a semiconductor device according to some example embodiments.

[0241] Reference Figure 27 Electronic system 3000 may include semiconductor device 3100 and controller 3200 electrically connected to semiconductor device 3100. Electronic system 3000 may be a storage device including one or more semiconductor devices 3100 or an electronic device including a storage device. For example, electronic system 3000 may be a solid-state drive (SSD) device, universal serial bus (USB), computing system, medical device, or communication device that may include one or more semiconductor devices 3100.

[0242] Semiconductor device 3100 may be or may include a memory device (e.g., see reference 1). Figures 1 to 21 (The memory device shown). Semiconductor device 3100 may include a first structure 3100F and a second structure 3100S on the first structure 3100F. The first structure 3100F may be a peripheral circuit structure including a decoder circuit 3110, a page buffer circuit (PBC) 3120, and a logic circuit 3130. The second structure 3100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first upper gate line UL1, a second upper gate line UL2, a first lower gate line LL1, a second lower gate line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0243] In the second structure 3100S, each of the memory cell strings CSTRs may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCTs between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary according to the example implementation.

[0244] In some example implementations, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. Lower gate lines LL1 and LL2 may be the gate electrodes of lower transistors LT1 and LT2, respectively. Word lines WL may be the gate electrodes of memory cell transistors MCT, respectively, and upper gate lines UL1 and UL2 may be the gate electrodes of upper transistors UT1 and UT2, respectively.

[0245] In some example implementations, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 that can be connected in series with each other. The upper transistors UT1 and UT2 may include a series select transistor UT1 and an upper erase control transistor UT2. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation for erasing data stored in the memory cell transistor MCT via the gate-induced drain leakage (GIDL) phenomenon.

[0246] The common-source line CSL, the first lower gate line LL1, the second lower gate line LL2, the word line WL, the first upper gate line UL1, and the second upper gate line UL2 can be electrically connected to the decoder circuit 3110 via a first wiring line 3115 extending from the first structure 3100F to the second structure 3110S. The bit line BL can be electrically connected to the page buffer circuit 3120 via a second wiring line 3125 extending from the first structure 3100F to the second structure 3100S.

[0247] In the first structure 3100F, the decoder circuit 3110 and the page buffer circuit 3120 can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit 3110 and the page buffer circuit 3120 can be controlled by logic circuit 3130. The semiconductor device 3100 can communicate with the controller 3200 via an input / output pad 3101 electrically connected to the logic circuit 3130. The input / output pad 3101 can be electrically connected to the logic circuit 3130 via an input / output connection line 3135 extending from the first structure 3100F to the second structure 3100S.

[0248] The controller 3200 may include a processor 3210, a NAND controller 3220, and a host interface (I / F) 3230. The electronic system 3000 may include a plurality of semiconductor devices 3100, and in this case, the controller 3200 may control the plurality of semiconductor devices 3100.

[0249] Processor 3210 controls the operation of electronic system 3000, including controller 3200. Processor 3210 is operable via firmware and can control NAND controller 3220 to access semiconductor device 3100. NAND controller 3220 may include NAND interface 3221 for communicating with semiconductor device 3100. Through NAND interface 3221, control commands for controlling semiconductor device 3100, data to be written to memory cell transistors (MCTs) of semiconductor device 3100, and data to be read from memory cell transistors (MCTs) of semiconductor device 3100 can be transmitted. Host interface 3230 provides communication between electronic system 3000 and external host. When control commands are received from external host through host interface 3230, processor 3210 can control semiconductor device 3100 in response to the control commands.

[0250] The storage device according to the example implementation can be packaged using various package types or package configurations.

[0251] While this specification contains numerous details of specific implementations, these should not be construed as limiting the scope of any invention or the scope of the claims, but rather as descriptions of features specific to particular embodiments of a particular invention. Specific features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a particular combination, in some cases, one or more features from the combination may be removed from the combination, and the combination may refer to a sub-combination or a variation of a sub-combination.

[0252] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting them. Although several exemplary embodiments have been described, those skilled in the art will readily understand that many modifications are possible in the exemplary embodiments without substantially departing from the novel teachings and advantages of this disclosure. Therefore, all such modifications are intended to be included within the scope of this disclosure as defined in the claims.

Claims

1. A storage device, comprising: Memory devices; as well as The memory controller is configured to control the memory device via a channel. The memory device includes multiple memory chips sharing the channel, and the memory device is configured to select a target memory chip among the multiple memory chips. The target memory chip includes a first adaptive volume bias generator and a first transfer driver. The first adaptive volume bias generator is configured to apply a first volume bias to the first transfer driver based on an operating mode, including a write mode or a read mode. The target memory chip is configured to receive write data from the memory controller in write mode and send read data to the memory controller in read mode.

2. The storage device as claimed in claim 1, wherein, The first adaptive volume bias generator is configured as follows: In write mode, an inverted body bias is applied to the first transfer driver; and In read mode, apply a normal volume bias to the first transfer driver.

3. The storage device as claimed in claim 1, wherein, The first transmission driver includes a first n-type metal-oxide-semiconductor transistor and a first p-type metal-oxide-semiconductor transistor. The first n-type metal-oxide-semiconductor transistor and the first p-type metal-oxide-semiconductor transistor are connected to the data transmission line, which is included in the channel. The data transmission line is configured to transmit read data and receive write data.

4. The storage device as claimed in claim 3, wherein, The first adaptive volume bias generator is configured to apply an inverse volume bias to the first transfer driver in write mode through the following process: A first bias voltage less than ground voltage is applied to the body of the first n-type metal-oxide-semiconductor transistor; and A second bias voltage greater than the power supply voltage is applied to the body of the first p-type metal-oxide-semiconductor transistor.

5. The storage device as claimed in claim 3, wherein, The first adaptive volume bias generator is configured to apply a normal volume bias to the first transfer driver in read mode through the following process: A first bias voltage corresponding to the ground voltage is applied to the body of the first n-type metal-oxide-semiconductor transistor; and A second bias voltage corresponding to the power supply voltage is applied to the body of the first p-type metal-oxide-semiconductor transistor.

6. The storage device as claimed in claim 3, in, Each of one or more non-target memory chips that was not selected by the memory controller includes an on-chip termination circuit connected to a data transmission line. Each of the one or more non-target memory chips includes a corresponding adaptive volume bias generator and a corresponding transfer driver, and The corresponding adaptive body bias generator is configured to apply a second body bias to the corresponding transmission driver based on the activation of the corresponding on-chip termination circuit.

7. The storage device as claimed in claim 6, in, The one or more non-target memory chips include a first non-target memory chip and a second non-target memory chip, the first non-target memory chip including an enabled first on-chip termination circuit, and the second non-target memory chip including a disabled second on-chip termination circuit. The first non-target memory chip includes a second adaptive volume bias generator and a second transfer driver, and The second non-target memory chip includes a third adaptive volume bias generator and a third transfer driver.

8. The storage device as claimed in claim 7, wherein, The second adaptive volume bias generator is configured to apply a normal volume bias to the second transmission driver, and The third adaptive volume bias generator is configured to apply an inverse volume bias to the third transmission driver.

9. The storage device as claimed in claim 8, wherein, The third transmission driver includes a second n-type metal-oxide-semiconductor transistor and a second p-type metal-oxide-semiconductor transistor. Among them, the second n-type metal-oxide-semiconductor transistor and the second p-type metal-oxide-semiconductor transistor are connected to the data transmission line, and The third adaptive volume bias generator is configured to apply an inverse volume bias to the third transmission driver through the following process: A first bias voltage, less than ground voltage, is applied to the body of the second n-type metal-oxide-semiconductor transistor; and A second bias voltage greater than the power supply voltage is applied to the body of the second p-type metal-oxide-semiconductor transistor.

10. The storage device of claim 8, wherein, The second transmission driver includes a second n-type metal-oxide-semiconductor transistor and a second p-type metal-oxide-semiconductor transistor. Among them, the second n-type metal-oxide-semiconductor transistor and the second p-type metal-oxide-semiconductor transistor are connected to the data transmission line, and The second adaptive volume bias generator is configured to apply a normal volume bias to the second transmission driver through the following process: A first bias voltage corresponding to the ground voltage is applied to the body of the second n-type metal-oxide-semiconductor transistor; and A second bias voltage corresponding to the power supply voltage is applied to the body of the second p-type metal-oxide-semiconductor transistor.

11. The storage device as claimed in claim 6, in, Each of the one or more non-target memory chips determines whether its corresponding on-chip termination circuit is enabled based on an on-chip termination signal received from the memory controller, and The corresponding on-chip termination circuit is included in the corresponding transfer driver of each of the one or more non-target memory chips.

12. The storage device according to any one of claims 1 to 11, wherein, Each of the plurality of memory chips includes: A memory cell array comprising multiple non-volatile memory cells coupled to multiple word lines and multiple bit lines, the memory cell array being configured to store write data and provide read data; An on-chip termination circuit is connected to a data transmission line configured to transmit read data and receive write data, the data transmission line being included in the channel; and The control circuitry is configured to: control the corresponding adaptive volume bias generator based on commands and addresses received from the memory controller, and control the on-chip termination circuitry based on on-chip termination signals received from the memory controller. The plurality of memory chips are stacked sequentially on the printed circuit board in a direction perpendicular to the surface of the printed circuit board.

13. The storage device of claim 12, wherein, The control circuit includes: An address comparator is configured to generate an internal chip enable signal for a specified target memory chip by comparing a chip address included in the address with an identifier address identifying each of the plurality of memory chips; and The control signal generator is configured to generate an on-chip termination control signal that selectively enables the on-chip termination circuitry based on the on-chip termination signal.

14. The storage device of claim 13, wherein, The address comparator is configured as follows: The internal chip enable signal is activated based on the chip address matching identifier address; and The internal chip enable signal is activated based on the difference between the chip address and the identifier address.

15. The storage device of claim 12, wherein, The plurality of memory chips are configured to operate in a chip enable reduction mode in which the plurality of memory chips jointly receive a chip enable signal and a chip address.

16. The storage device of claim 12, wherein, The control circuit is configured as follows: Based on the command / address chip enable signal and command / address received from the memory controller, the internal chip enable signal of the specified target memory chip is selectively activated; and On-chip termination control signals are generated based on on-chip termination signals to selectively enable on-chip termination circuitry, and The command / address includes the logical cell number address that indicates a valid logical cell number.

17. A storage device, comprising: Memory devices; as well as The memory controller is configured to control the memory device via a channel and select a target memory chip from a plurality of memory chips. The memory device includes multiple memory chips that share a data bus for transmitting data and receive corresponding chip selection signals from a memory controller. Each of the plurality of memory chips includes a memory cell array, a transfer driver, and an adaptive volume bias generator. The memory cell array includes a plurality of volatile memory cells coupled to multiple word lines and multiple bit lines. The memory cell array is configured to store the data. The target memory chip includes a first adaptive volume bias generator and a first transfer driver. The first adaptive volume bias generator is configured to apply a first volume bias to the first transfer driver based on an operating mode, including a write mode or a read mode. The target memory chip is configured to receive write data from the memory controller in write mode and send read data to the memory controller in read mode.

18. The storage device of claim 17, wherein, The first adaptive volume bias generator is configured as follows: In write mode, an inverted body bias is applied to the first transfer driver; and In read mode, apply a normal volume bias to the first transfer driver. The first transmission driver includes a first n-type metal-oxide-semiconductor transistor and a first p-type metal-oxide-semiconductor transistor connected to the data bus. The first adaptive body bias generator is configured to apply an inverted body bias to the first transfer driver in write mode by: applying a first bias voltage less than ground to the body of the first n-type metal-oxide-semiconductor transistor; and applying a second bias voltage greater than the power supply voltage to the body of the first p-type metal-oxide-semiconductor transistor. The first adaptive body bias generator is configured to apply a normal body bias to the first transmission driver in read mode by the following process: applying a first bias voltage corresponding to the ground voltage to the body of the first n-type metal-oxide-semiconductor transistor; and applying a second bias voltage corresponding to the power supply voltage to the body of the first p-type metal-oxide-semiconductor transistor.

19. The storage device as claimed in claim 17 or 18, in, Each of one or more non-target memory chips that was not selected by the memory controller includes an on-chip termination circuit connected to a data transmission line. Each of the one or more non-target memory chips includes a corresponding adaptive volume bias generator and a corresponding transfer driver. The corresponding adaptive volume bias generator is configured to apply a second volume bias to the corresponding transmission driver based on the activation of the corresponding on-chip termination circuit. The one or more non-target memory chips include a first non-target memory chip and a second non-target memory chip. The first non-target memory chip includes an enabled first on-chip termination circuit, and the second non-target memory chip includes a disabled second on-chip termination circuit. The first non-target memory chip includes a second adaptive volume bias generator and a second transfer driver. The second non-target memory chip includes a third adaptive volume bias generator and a third transfer driver. The second adaptive volume bias generator is configured to apply a normal volume bias to the second transmission driver, and The third adaptive volume bias generator is configured to apply an inverse volume bias to the third transmission driver.

20. A method of operating a storage device, wherein, The storage device includes a memory device and a memory controller, the memory controller being configured to control the memory device by communicating with the memory device via a channel, and wherein the memory device includes a plurality of memory chips sharing the channel, the method comprising: The selection of each of a plurality of memory chips as the target memory chip is determined based on the chip address from the memory controller. A first adaptive volume bias generator applies a first volume bias to a first transfer driver based on whether the operating mode is write mode or read mode. The first adaptive volume bias generator and the first transfer driver are included in a first memory chip selected as the target memory chip by a memory controller among the plurality of memory chips. The second adaptive body bias generator is enabled based on the corresponding on-chip termination function to apply a second body bias to the second transfer driver. The second adaptive body bias generator and the second transfer driver are included in each of one or more non-target memory chips other than the first memory chip among the plurality of memory chips.

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