Floating-point number processing method and device, computing equipment and storage medium

Abstract

The invention discloses a floating-point number processing method and device, computing equipment and a storage medium, and relates to the technical field of computers. The computing device obtains a first floating-point number and decodes the first floating-point number to obtain a second floating-point number. The first floating-point number comprises a first symbol field, a bit width indication field, a first-order code field and a first mantissa field, and the second floating-point number comprises a second symbol field, a second-order code field and a second mantissa field. The absolute value of an order code represented by a first order code field of the first floating-point number is greater than or equal to a set value, the bit width of the first mantissa field is greater than the difference value between the total bit width of the first floating-point number and the first bit width, and the first bit width is the sum of the bit width of the first symbol field, the bit width of the bit width indication field and the value of the bit width indication field. When the absolute value of the order code of the floating-point number is large, the bit width of the first mantissa field can be properly increased, and the requirement for the numerical precision of the floating-point number is met.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a floating-point number processing method, apparatus, computing device, and storage medium. Background Technology

[0002] In computer systems, floating-point (FP) is an approximate numerical representation of real numbers, also known as floating-point data representation. For example, floating-point data representations can include FP8, FP16, and FP32, where FP8 represents an 8-bit floating-point number, FP16 represents a 16-bit floating-point number, and FP32 represents a 32-bit floating-point number. Typically, a floating-point number contains three fields: a sign field, an exponent field, and a mantissa field. The value of the exponent field represents the exponent of a base. For example, if the base is 2, the value of the exponent field (i.e., the exponent of 2) is usually an integer, representing an integer power of 2. The value of the mantissa field multiplied by the exponent of the base yields a data value, and the sign field indicates the sign of the data.

[0003] In each of the above floating-point data representations, the bit width of each field is fixed. For example, FP16 includes a 1-bit sign field, a 5-bit exponent field, and a 10-bit mantissa field; FP32 includes a 1-bit sign field, an 8-bit exponent field, and a 23-bit mantissa field; FP8 can include two types, one including a 1-bit sign field, a 5-bit exponent field, and a 2-bit mantissa field; the other including a 1-bit sign field, a 4-bit exponent field, and a 3-bit mantissa field. The bit width of the exponent field determines the range of values ​​that the floating-point number can represent, while the bit width of the mantissa field determines the precision of the values ​​that the floating-point number can represent.

[0004] With the rapid development of artificial intelligence (AI) applications and neural network model training and inference, the scale of data used in AI scenarios (such as network parameters) has increased dramatically. Using floating-point numbers with shorter bit widths for AI training and inference can save on data storage and transfer costs. However, in AI scenarios, data accuracy is also crucial for the performance of model training and inference.

[0005] Currently, how to ensure data accuracy to meet requirements using a limited floating-point bit width is an urgent problem to be solved. Summary of the Invention

[0006] This application provides a floating-point number processing method, apparatus, computing device, and storage medium that can ensure data accuracy meets requirements using a limited floating-point bit width.

[0007] In a first aspect, embodiments of this application provide a floating-point number processing method. This method can be executed by a computing device, or by a chip, chip system, or circuit within the computing device. The floating-point number processing method may include: the computing device acquiring a first floating-point number, wherein the first floating-point number uses a data format including a first sign field, a bit-width indicator field, a first exponent field, and a first mantissa field. The first sign field indicates the sign of the first floating-point number, the first exponent field represents the exponent of the first floating-point number, and the first mantissa field represents the mantissa of the first floating-point number; the bit-width indicator field indicates the bit width of the first exponent field; the absolute value of the exponent of the first floating-point number is greater than or equal to a set value, and the bit width of the first mantissa field is greater than the difference between the total bit width of the first floating-point number and the first bit width; wherein the first bit width is the sum of the bit width of the first sign field, the bit width of the bit-width indicator field, and the value of the bit-width indicator field. After acquiring the first floating-point number, the computing device may decode the first floating-point number to obtain a second floating-point number, the second floating-point number using a data format including a second sign field, a second exponent field, and a second mantissa field. The second floating-point number represents the same data as the first floating-point number.

[0008] In this embodiment, the first floating-point number includes a first sign field, a bit width indicator field, a first exponent field, and a first mantissa field. The bit width indicator field indicates the bit width of the first exponent field. With the same total bit width, the bit widths of the first exponent field and the first mantissa field can dynamically change with the value of the bit width indicator field, thereby meeting the requirements for different numerical ranges and precisions of floating-point numbers in different scenarios. Furthermore, the absolute value of the exponent of the first floating-point number is greater than or equal to a set value, and the bit width of the first mantissa field is greater than the difference between the total bit width of the first floating-point number and the first bit width. When the absolute value of the exponent of the floating-point number is large, the bit width of the first mantissa field can be appropriately increased to meet the precision requirements when the exponent of the data is large. Here, a large exponent refers to a large absolute value of the exponent of the data. Therefore, this embodiment can use a limited floating-point bit width to ensure that the precision of the data meets the requirements.

[0009] In one alternative implementation, the computing device can also obtain a third floating-point number, whose data format is the same as that of the first floating-point number. The absolute value of the exponent of the third floating-point number is less than a set value, and the bit width of the first mantissa field of the third floating-point number is equal to the difference between the total bit width and the bit width of the first digit. After obtaining the third floating-point number, the computing device can decode it to obtain a fourth floating-point number. The data format of the fourth floating-point number is the same as that of the second floating-point number, and the fourth floating-point number represents the same data as the third floating-point number.

[0010] In the above implementation, when the absolute value of the exponent of the floating-point number is small, the bit width of the first mantissa field can be equal to the difference between the total bit width of the third floating-point number and the bit width of the first mantissa field. The bit width of the first mantissa field does not need to be increased to meet the numerical precision requirements when the exponent of the data is small.

[0011] In one alternative implementation, the first exponent field of the third floating-point number contains a sign bit; the sign bit is used to characterize the sign of the exponent of the third floating-point number.

[0012] In one alternative implementation, the first exponent field of the first floating-point number does not contain a sign bit, and the exponent represented by the first exponent field of the first floating-point number is negative.

[0013] In the above implementation, when the absolute value of the exponent of the floating-point number is greater than or equal to a set value, the first exponent field does not contain a sign bit, the bit width of the first exponent field is less than the value of the bit width indicator field, and the bit width of the first mantissa field is greater than the difference between the total bit width of the first floating-point number and the bit width of the first digit. When the absolute value of the exponent of the floating-point number is large, the bit width of the first exponent field is appropriately reduced to be less than the value of the bit width indicator field, thereby allowing the bit width of the first mantissa field to be appropriately increased to meet the numerical precision requirements when the exponent of the data is large. Furthermore, when the first exponent field does not contain a sign bit, the exponent represented by the first exponent field is negative, and positive exponent values ​​can be ignored. This not only matches the negatively skewed probability distribution of the exponent in AI scenarios but also saves the bit width occupied by the sign bit.

[0014] In one alternative implementation, the value of the bit-width indicator field is positively correlated with the absolute value of the exponent represented by the first exponent field.

[0015] In one alternative implementation, the value of the bit-width indicator field is negatively correlated with its bit width. When the total bit width of the first floating-point number is fixed, this avoids a jump in the bit width of the first mantissa field caused by simultaneous increases in the bit widths of the bit-width indicator field and the first exponent field. Since the bit width of the mantissa field determines the precision of the floating-point data, this implementation allows for a smooth change in the precision of the value represented by the first floating-point number, preventing jumps in precision.

[0016] In one alternative implementation, the computing device may read the first floating-point number from memory or obtain the first floating-point number via a communication network.

[0017] In one alternative implementation, after decoding the first floating-point number to obtain the second floating-point number, the computing device can use the second floating-point number to participate in the computing task.

[0018] In this embodiment, the first floating-point number can be used for data storage or data transfer. Since the bit width of the first exponent field and the first mantissa field of the first floating-point number can dynamically change according to the value indicated by the bit width indicator field, the total bit width of the floating-point number can be saved, thus saving data storage or data transfer costs. Furthermore, the second floating-point number is a normalized floating-point number. Decoding the first floating-point number into a normalized second floating-point number for use in computation tasks does not require the computing device or software used for computation to be changed to support the data format of the first floating-point number. While ensuring the accuracy of the data meets the requirements using a limited floating-point bit width, it also reduces the workload of hardware and software adaptation changes to the first floating-point number.

[0019] Secondly, embodiments of this application provide a floating-point number processing method. This method can be executed by a computing device, or by a chip, chip system, or circuit within the computing device. The floating-point number processing method may include: the computing device acquiring a second floating-point number; the second floating-point number uses a data format including a second sign field, a second exponent field, and a second mantissa field; the second sign field is used to represent the sign of the second floating-point number, the second exponent field is used to represent the exponent of the second floating-point number, and the second mantissa field is used to represent the mantissa of the second floating-point number. The computing device obtains a first floating-point number based on the second sign field, the second exponent field, and the second mantissa field of the second floating-point number. The first floating-point number includes a first sign field, a bit width indicator field, a first exponent field, and a first mantissa field; the bit width indicator field is used to indicate the bit width of the first exponent field; the absolute value of the first exponent field of the first floating-point number is greater than or equal to a set value, and the bit width of the first mantissa field is greater than the difference between the total bit width of the first floating-point number and the first bit width; the first bit width is the sum of the bit width of the first sign field, the bit width of the bit width indicator field, and the value of the bit width indicator field; the data represented by the first floating-point number and the second floating-point number are the same.

[0020] In one alternative implementation, the computing device can obtain a fourth floating-point number, the data format of which is the same as that of the second floating-point number. The computing device can then derive a third floating-point number based on the second sign field, second exponent field, and second mantissa field of the fourth floating-point number. The data format of the third floating-point number is the same as that of the first floating-point number, the absolute value of the exponent of the third floating-point number is less than a set value, and the bit width of the first mantissa field of the third floating-point number is equal to the difference between the total bit width and the first bit width of the third floating-point number.

[0021] In one alternative implementation, the first exponent field of the third floating-point number contains a sign bit, which is used to characterize the sign of the exponent of the third floating-point number.

[0022] In one alternative implementation, the first exponent field of the first floating-point number does not contain a sign bit, and the exponent represented by the first exponent field of the first floating-point number is negative.

[0023] In one alternative implementation, the value of the bit-width indicator field is positively correlated with the absolute value of the exponent.

[0024] In one alternative implementation, the value of the bit-width indicator field is negatively correlated with the bit width of the bit-width indicator field.

[0025] Thirdly, embodiments of this application provide a floating-point processing apparatus that can be applied to a computing device. The floating-point processing apparatus may include:

[0026] A floating-point number acquisition module is used to acquire a first floating-point number. The data format of the first floating-point number includes a first sign field, a bit width indicator field, a first exponent field, and a first mantissa field. The first sign field is used to represent the sign of the first floating-point number, the first exponent field is used to represent the exponent of the first floating-point number, and the first mantissa field is used to represent the mantissa of the first floating-point number. The bit width indicator field is used to indicate the bit width of the first exponent field. The absolute value of the exponent of the first floating-point number is greater than or equal to a set value, and the bit width of the first mantissa field is greater than the difference between the total bit width of the first floating-point number and the first bit width. The first bit width is the sum of the bit width of the first sign field, the bit width of the bit width indicator field, and the value of the bit width indicator field.

[0027] The decoding module is used to decode the first floating-point number to obtain a second floating-point number. The second floating-point number uses a data format that includes a second sign field, a second exponent field, and a second mantissa field. The second floating-point number represents the same data as the first floating-point number.

[0028] In one optional implementation, the floating-point number acquisition module can also be used to acquire a third floating-point number, the data format of which is the same as that of the first floating-point number. The absolute value of the exponent of the third floating-point number is less than a set value, and the bit width of the first mantissa field of the third floating-point number is equal to the difference between the total bit width and the bit width of the first bit of the third floating-point number.

[0029] The decoding module can also be used to decode the third floating-point number to obtain the fourth floating-point number. The data format of the fourth floating-point number is the same as that of the second floating-point number, and the fourth floating-point number represents the same data as the third floating-point number.

[0030] In one alternative implementation, the first exponent field of the third floating-point number contains a sign bit; the sign bit is used to characterize the sign of the exponent of the third floating-point number.

[0031] In one alternative implementation, the first exponent field of the first floating-point number does not contain a sign bit, and the exponent represented by the first exponent field of the first floating-point number is negative.

[0032] In one alternative implementation, the value of the bit-width indicator field is positively correlated with the absolute value of the exponent.

[0033] In one alternative implementation, the value of the bit-width indicator field is negatively correlated with the bit width of the bit-width indicator field.

[0034] In one alternative implementation, the floating-point acquisition module can be used to: read a first floating-point number from memory, or acquire a first floating-point number via a communication network.

[0035] In one alternative implementation, the floating-point processing device may further include a computation module that can use a second floating-point number to participate in the computation task.

[0036] Fourthly, embodiments of this application provide a floating-point processing apparatus that can be applied to a computing device. The floating-point processing apparatus may include:

[0037] The data acquisition module is used to acquire a second floating-point number; the second floating-point number includes a second sign field, a second exponent field, and a second mantissa field; the second sign field is used to represent the sign of the second floating-point number, the second exponent field is used to represent the exponent of the second floating-point number, and the second mantissa field is used to represent the mantissa of the second floating-point number.

[0038] The encoding module is used to obtain a first floating-point number based on the second sign field, second exponent field, and second mantissa field of the second floating-point number. The first floating-point number includes a first sign field, a bit-width indicator field, a first exponent field, and a first mantissa field; the bit-width indicator field is used to indicate the bit width of the first exponent field; the absolute value of the first exponent field of the first floating-point number is greater than or equal to a set value, and the bit width of the first mantissa field is greater than the difference between the total bit width of the first floating-point number and the first bit width; the first bit width is the sum of the bit width of the first sign field, the bit width of the bit-width indicator field, and the value of the bit-width indicator field; the data represented by the first floating-point number and the second floating-point number is the same.

[0039] In one alternative implementation, the data acquisition module can also be used to: acquire a fourth floating-point number, the data format of which is the same as that of the second floating-point number;

[0040] The encoding module can also be used to obtain a third floating-point number based on the second sign field, second exponent field, and second mantissa field of the fourth floating-point number. The data format of the third floating-point number is the same as that of the first floating-point number. The absolute value of the exponent of the third floating-point number is less than a set value. The bit width of the first mantissa field of the third floating-point number is equal to the difference between the total bit width and the first bit width of the third floating-point number.

[0041] In one alternative implementation, the first exponent field of the third floating-point number contains a sign bit, which is used to characterize the sign of the exponent of the third floating-point number.

[0042] In one alternative implementation, the first exponent field of the first floating-point number does not contain a sign bit, and the exponent represented by the first exponent field of the first floating-point number is negative.

[0043] Fifthly, embodiments of this application provide a computing device, which includes a processor and a memory; the memory stores a computer program; the processor is used to read the computer program stored in the memory and execute any of the floating-point number processing methods provided in the first or second aspect above.

[0044] In a sixth aspect, embodiments of this application provide a chip, which includes a processor and a power supply circuit; the power supply circuit is used to supply power to the processor, and the processor is used to execute a computer program to implement any of the floating-point number processing methods provided in the first or second aspect above.

[0045] In a seventh aspect, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which are used to cause a computer to perform any of the floating-point number processing methods provided in the first or second aspect above.

[0046] Eighthly, embodiments of this application provide a computer program product comprising computer-executable instructions, the computer-executable instructions being used to cause a computer to perform any of the floating-point number processing methods provided in the first or second aspect above.

[0047] The technical effects that can be achieved by any of the second to eighth aspects mentioned above can be referred to the description of the beneficial effects in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0048] Figure 1 Feature maps of data used in AI scenarios;

[0049] Figure 2 This is a schematic diagram illustrating one application scenario of an embodiment of this application;

[0050] Figure 3 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application;

[0051] Figure 4 A schematic diagram illustrating a floating-point number data format provided in an embodiment of this application;

[0052] Figure 5 A schematic diagram of the mantissa precision-exponent distribution of a floating-point number is provided for an embodiment of this application;

[0053] Figure 6 Another schematic diagram of the mantissa precision-exponent distribution of a floating-point number provided in this application embodiment;

[0054] Figure 7 A flowchart illustrating a floating-point number processing method provided in this application embodiment;

[0055] Figure 8 This is a schematic diagram illustrating how a decoder decodes a first floating-point number, as provided in an embodiment of this application.

[0056] Figure 9 A flowchart illustrating another floating-point number processing method provided in this application embodiment;

[0057] Figure 10 This is a schematic diagram illustrating an encoder encoding a first floating-point number according to an embodiment of this application.

[0058] Figure 11 A flowchart illustrating another floating-point number processing method provided in this application embodiment;

[0059] Figure 12 This is a schematic diagram of the structure of a floating-point processing device provided in an embodiment of this application;

[0060] Figure 13 A schematic diagram of another floating-point processing device provided in the embodiments of this application;

[0061] Figure 14 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application;

[0062] Figure 15 This is a schematic diagram of the structure of a chip provided in an embodiment of this application. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. The terminology used in the implementation section of this application is only for explaining specific embodiments of this application and is not intended to limit this application.

[0064] In this application embodiment, "multiple" refers to two or more. Therefore, in this application embodiment, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, "including at least one" means including one, two, or more, and it does not limit which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.

[0065] Unless otherwise stated, the ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are used to distinguish multiple objects, and are not used to limit the order, sequence, priority or importance of multiple objects.

[0066] Floating-point data representation is a scientific computing method. In the IEEE 754 binary floating-point standard, a floating-point number can contain three fields: a sign field, an exponent field, and a mantissa field. The value of the exponent field represents the integer exponent of a given base. The value of the mantissa field multiplied by the integer exponent of the given base yields the data. The sign field indicates whether the data is positive or negative. The formula for representing data using floating-point numbers can be written as: (-1) s ×2 E -bias ×(1+M / 1024), where the exponent s of the base -1 is the value of the sign field in the floating-point number, used to indicate the positive or negative sign of the data; E is the value of the exponent field in the floating-point number; bias is the offset, which can be equal to 15 or 0; and M is the value of the mantissa field in the floating-point number. For example, taking the decimal data 4.625 as an example, this data is converted to binary data 100.101. Using binary floating-point representation, this data can be represented as (-1). 0 ×2 2 ×1.00101, where the exponent 0 of the base -1 is the value of the sign field in the floating-point number, used to indicate the positive or negative sign of the data. The exponent 2 of the base 2 is the value of the exponent field in the floating-point number, representing the number of decimal point shifts. For example, from 100.101 to 1.00101, the decimal point is shifted by 2. 1.00101 is the mantissa. Since the value before the decimal point must be 1, the actual value stored in the mantissa field of the floating-point number can only include the data after the decimal point, i.e., 00101.

[0067] In commonly used floating-point data representations, the bit width of each field is fixed. For example, as shown in Table 1, floating-point data representations can include the FP32 format, which represents 32-bit floating-point numbers. FP32 includes a 1-bit sign field, an 8-bit exponent field, and a 23-bit mantissa field. The bit width of the exponent field determines the range of values ​​that the floating-point number can represent, while the bit width of the mantissa field determines the precision of the values ​​that the floating-point number can represent.

[0068] Table 1

[0069] Floating-point number format bit width of the symbol field bit width of the exponent field Bit width of the mantissa field FP32 1 bit 8 bits 23 bits FP16 1 bit 5 bits 10 bits E5M2 1 bit 5 bits 2 bits E4M3 1 bit 4 bits 3 bits

[0070] With the rapid development of AI applications and neural network model training and inference, the scale of data used in AI scenarios has increased dramatically. Using floating-point numbers with shorter bit widths for AI training and inference can save on data storage and transfer costs. Furthermore, in the field of large-scale AI model training and inference, shorter-bit-width floating-point numbers can improve computing power, increase training and inference efficiency, and reduce costs. For example, as shown in Table 1, the FP16 format represents a 16-bit floating-point number, including a 1-bit sign field, a 5-bit exponent field, and a 10-bit mantissa field. It can be seen that from the FP32 format to the FP16 format, the total bit width of the floating-point number is reduced from 32 bits to 16 bits, which can double the computing power. To further improve computing power, the FP8 format of floating-point numbers has emerged. The FP8 format represents an 8-bit floating-point number. As shown in Table 1, the FP8 format can include two types: E5M2 and E4M3. The floating-point number of E5M2 includes a 1-bit sign field, a 5-bit exponent field, and a 2-bit mantissa field; the floating-point number of E4M3 includes a 1-bit sign field, a 4-bit exponent field, and a 3-bit mantissa field.

[0071] In AI scenarios, data precision is also crucial for the performance of model training and inference. As shown in Table 1, floating-point numbers with a smaller total bit width have smaller bit widths in both the exponent and mantissa fields. The precision of the data they can represent often cannot meet the needs of AI training and inference, thus affecting the performance of AI training and inference.

[0072] To ensure data precision requirements are met using a limited floating-point number bit width, this application provides a floating-point number processing method. The floating-point number provided in this application includes a first sign field, a bit width indicator field (i.e., a Dot field), a first exponent field, and a first mantissa field. The first sign field represents the sign of the first floating-point number, and the Dot field indicates the bit width occupied by the first exponent field in the total bit width N of the floating-point number, where N is an integer greater than 1. When the bit width occupied by the first exponent field is non-zero, the first exponent field represents the exponent of the floating-point number, and the first mantissa field represents the mantissa of the floating-point number. With the same total bit width, the bit widths of the first exponent field and the first mantissa field can dynamically change with the value of the Dot field, thereby meeting the requirements for different numerical ranges and precisions of floating-point numbers in different AI scenarios. When the numerical precision requirement of the floating-point number is high, the bit width of the first exponent field can be appropriately reduced, and the bit width of the first mantissa field can be appropriately increased to meet the numerical precision requirements of the floating-point number. Therefore, compared with related technologies, the embodiments of this application can use a limited floating-point bit width to ensure that the accuracy of the data meets the requirements.

[0073] On the one hand, the data used in AI scenarios has the following characteristics: the larger the exponent, the higher the requirement for numerical precision. If the exponent is large, i.e., the value represented by the exponent field is large, and the bit width of the mantissa field is small, the numerical precision of the data will be reduced, which will not meet the needs of AI scenarios. In order to meet the requirement for numerical precision when the exponent of the data is large, the floating-point number provided in this application embodiment, when the absolute value of the exponent of the floating-point number is less than a set value, the bit width of the first exponent field is equal to the value D of the Dot field, and the bit width of the first mantissa field is equal to the difference between the total bit width N of the first floating-point number and the first bit width, where the first bit width is the sum of the bit width of the first sign field, the bit width of the Dot field, and the value of the bit width indicator field; when the absolute value of the exponent of the floating-point number is greater than or equal to the set value, the bit width of the first exponent field is less than the value D of the Dot field, and the bit width of the first mantissa field is greater than the difference between the total bit width of the first floating-point number and the first bit width. When the absolute value of the exponent of a floating-point number is large, the bit width of the first exponent field is appropriately reduced to be smaller than the value D of the Dot field, so that the bit width of the first mantissa field can be appropriately increased to meet the numerical precision requirements when the exponent of the data is large. Here, a large exponent means that the absolute value of the exponent of the data is large.

[0074] On the other hand, the values ​​of the data used in AI scenarios follow a normal distribution centered at 0, such as... Figure 1 As shown in (a), a normal distribution means that, according to the probability of different data occurring during the training or inference process, the closer the value is to 0, the higher the probability of the data appearing, and the further the value is from 0, the lower the probability of the data appearing. However, when using floating-point numbers to represent data, the exponential distribution of the data used in AI scenarios is not a normal distribution, but a negatively skewed probability distribution, such as... Figure 1As shown in (b), a negatively skewed probability distribution means that, according to the probability of different data occurring during the training or inference process, the probability of data with an exponent less than 0 decreases slowly as the absolute value of the exponent increases, while the probability of data with an exponent greater than 0 decreases rapidly as the absolute value of the exponent increases. In other words, the number of data with an exponent greater than 0 and a large exponent is very small. To match the negatively skewed probability distribution of data in AI scenarios, the floating-point number provided in this application allows the first exponent field to include a sign bit when the absolute value of the exponent is less than a set value. The sign bit is used to represent the sign of the exponent. When the absolute value of the exponent is greater than or equal to the set value, the first exponent field may not include a sign bit, and the exponent represented by the first exponent field is negative. For example, the set value can be 8. When the absolute value of the exponent is greater than or equal to 8, the first exponent field may not include a sign bit, and the exponent represented by the first exponent field is negative, such as -8 or a value less than -8. Since the first exponent field does not contain a sign bit when the absolute value of the exponent is greater than or equal to a set value, the exponent represented by the first exponent field is negative, and the positive value of the exponent can be ignored. This not only matches the negative skewed probability distribution of the exponent in AI scenarios, but also saves the bit width occupied by the sign bit, allowing the bit width of the first mantissa field to be increased.

[0075] The floating-point number processing method provided in this application embodiment can decode the aforementioned floating-point numbers to obtain the corresponding sign, exponent, and mantissa. This floating-point number processing method can be applied to computing devices and is widely applicable to various industries such as scientific research, engineering, finance, aerospace, and medicine, where a large amount of data needs to be stored, processed, and transmitted daily. Figure 2 An exemplary schematic diagram of an application scenario provided by an embodiment of this application is shown, such as... Figure 2 As shown, in this application scenario, computing devices 100, 200, and 300 can establish a communication connection via a network. This network can be a wired network or a wireless network, such as Wireless Fidelity (WiFi), Bluetooth, or a mobile network. Computing devices 100, 200, and 300 can be any electronic device such as a computer, server, smart wearable device, smart home device, tablet computer, laptop computer, in-vehicle terminal, or smartphone. When the computing device is a server, it can be a single server, a server cluster consisting of multiple servers, or a cloud computing service center. The communication connection established between computing devices 100, 200, and 300 enables data storage, computation, and transmission based on floating-point numbers.

[0076] It should be noted that in actual application scenarios, the system may contain more than 3 computing devices or less than 3 computing devices, and this application does not limit this.

[0077] The internal structures of computing devices 100, 200, and 300 can be identical. Taking computing device 100 as an example, as follows... Figure 3 As shown. The computing device 100 may internally include a processor 110 and a memory 120. The processor 110 and the memory 120 can be interconnected via a bus, which can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into address bus, data bus, control bus, etc.

[0078] The memory 120 can be used to store software programs and modules. The processor 110 executes various functional applications and data processing of the computing device 100 by running the software programs and modules stored in the memory 120, such as the floating-point number processing method provided in the embodiments of this application.

[0079] The memory 120 may primarily include a program storage area and a data storage area. The program storage area may store the operating system, application programs of at least one application, etc.; the data storage area may be used to store data, etc. Furthermore, the memory 120 may include random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and may also include non-volatile memory, such as hard disks, disk storage devices, or other non-volatile solid-state storage devices.

[0080] Processor 110 may be, but is not limited to, a central processing unit (CPU), a high-performance computing (HPC) service acceleration chip, a graphics processing unit (GPU), or neural network processing units (NPUs) and tensor network processing units (TPUs) in the field of AI. Processor 110 may include a decoder 111, an encoder 112, and computing units 113. The number of computing units 113 may be one or more. For example, the computing units in processor 110 may include a matrix acceleration engine, which may also be called a matrix computing unit. A computing unit with corresponding parallelism specifically designed for matrix computation can be called a matrix acceleration engine, such as a systolic array processor. Matrix acceleration engines can be used for matrix computations in fields such as HPC high-performance computing and AI machine learning, including matrix multiplication, matrix inversion, and matrix factorization. In this embodiment of the application, the decoder 111 can decode the floating-point number to obtain the corresponding sign, exponent and mantissa, and transmit the sign, exponent and mantissa to the matrix acceleration engine. The matrix acceleration engine can use the received sign, exponent and mantissa to perform matrix calculations.

[0081] In other embodiments, the computing units in processor 110 may further include vector computing units or tensor computing units. Vector computing units are designed for vector computation and possess a certain degree of parallelism, such as in single-instruction multiple-data (SIMD) processors. Vector computing units are widely used in HPC (High-Performance Computing) and AI machine learning fields, encompassing tasks such as linear programming, Fourier transforms, filtering calculations, and solving mathematical problems in linear algebra, partial differential equations, and integrals. Tensor computing units are designed for tensor computation and possess a certain degree of parallelism. Tensor computing units are widely used in AI machine learning fields, such as convolution operations.

[0082] In some embodiments, when the computing device 100 performs general-purpose computing, high-performance computing, or AI computing, it needs to use a large amount of floating-point data. In this case, the computing device 100 can decode the acquired floating-point number using the decoder 111, based on the floating-point number processing method provided in this application embodiment, to obtain decoded data. The decoded data includes the sign, exponent, and mantissa. Exemplarily, the floating-point number can be read from the local memory 120 of the computing device 100, or obtained from the computing device 200 or 300 via a network, or from other devices in the network. After decoding the acquired floating-point number, the decoder 111 can transmit the decoded data to the computing unit 113, where the computing unit 113 performs the corresponding calculation. The computing unit 113 transmits the calculation result to the encoder 112, which re-encodes the calculation result into a floating-point number. This floating-point number can be used for data storage and data transfer. For example, the processor 110 can save the floating-point number encoded by the encoder 112 into the memory 120.

[0083] Optionally, Figure 2 For details on the structure and function of computing devices 200 and 300, please refer to [reference needed]. Figure 3 The computing device 100 shown, in some possible embodiments, may include computing device 100, computing device 200, and computing device 300, which may include a ratio Figure 3 The embodiments of this application do not specifically limit the number of more or fewer components shown.

[0084] To facilitate understanding, the data format of floating-point numbers provided in the embodiments of this application will be described below. For example... Figure 4 As shown in the embodiments of this application, the floating-point number data format includes a first sign field, a bit width indicator field, a first exponent field, and a first mantissa field. When the absolute value of the exponent of the floating-point number is less than a set value, the bit width of the first exponent field is equal to the value D of the bit width indicator field; when the absolute value of the exponent of the floating-point number is greater than or equal to the set value, the bit width of the first exponent field is less than the value D of the bit width indicator field. The following embodiments use binary as an example for explanation.

[0085] In some embodiments, the total bit width of the floating-point number can be 8 bits. When the total bit width of the floating-point number is 8 bits, the floating-point number represented using the data format of this application embodiment can be called a HiF8_DML floating-point number. The above-mentioned setting value can be 4. When the absolute value of the exponent of the floating-point number is less than 4, the bit width of the first exponent field is equal to the value D of the Dot field; when the absolute value of the exponent of the floating-point number is greater than or equal to 4, the bit width of the first exponent field is less than the value D of the Dot field, and can be D-1. Table 2 exemplarily shows the data format of the floating-point number provided in this embodiment.

[0086] Table 2

[0087] Bit width of the first symbol field The bit width of the Dot field, DW: value D Bit width of the first exponent field: exponent E Bit width of the first mantissa field 1 2：4 D-1：-[8,15] 5-D+1 1 2：3 D-1：-[4,7] 5-D+1 1 2：2 D：±[2,3] 5-D 1 3：1 D：±1 4-D 1 4：0 D：0 3-D

[0088] The following section, in conjunction with Table 2, provides a detailed description of each field of floating-point numbers.

[0089] I. First Symbol Field: The first symbol field, also known as the sign bit, is located before the Dot field and occupies 1 bit in the total bit width N of the floating-point number. It is used to represent the positive or negative sign of the data. By default, 0 represents positive and 1 represents negative. However, 0 can also be used to represent negative and 1 to represent positive according to actual needs. This application does not impose any restrictions on this.

[0090] II. Dot Field: Occupies DW bits in the total bit width N of the floating-point number, where DW ranges from 2 to 4. The value (or encoded value) of the Dot field indicates the bit width occupied by the first exponent field in the total bit width N of the floating-point number. Assume the value of the Dot field is D, where D is an integer greater than or equal to 0. When the value D of the Dot field is non-zero, the first exponent field is used to represent the exponent of the floating-point number; the first mantissa field is used to represent the mantissa of the floating-point number.

[0091] As shown in Table 2, when the value D of the Dot field is 4, the bit width of the first exponent field is D-1, which is 3. In this case, the absolute value of the exponent represented by the first exponent field is [8, 15]. When the value D of the Dot field is 3, the bit width of the first exponent field is D-1, which is 2. In this case, the absolute value of the exponent represented by the first exponent field is [4, 7]. In both of these cases, the bit width of the first exponent field is D-1, which is less than the value D of the Dot field, and the absolute value of the exponent of the floating-point number is greater than or equal to 4.

[0092] When the value D of the Dot field is 2, the bit width of the first exponent field is D, meaning the bit width of the first exponent field is 2. In this case, the absolute value of the exponent represented by the first exponent field is [2, 3]. When the value D of the Dot field is 1, the bit width of the first exponent field is D, meaning the bit width of the first exponent field is 1. In this case, the absolute value of the exponent represented by the first exponent field is 1. When the value D of the Dot field is 0, the bit width of the first exponent field is D, meaning the bit width of the first exponent field is 0. In this case, the first exponent field does not exist. When the value D of the Dot field is 2, 1, or 0, the bit width of the first exponent field is D, which is equal to the value D of the Dot field, and the absolute value of the exponent of the floating-point number is less than 4.

[0093] In some embodiments, the Dot field can be encoded using prefix code. Prefix code encoding is also called prefix coding. If, in an encoding scheme, no single code is a prefix (leftmost substring) of any other code, then that encoding scheme can be called prefix coding. For example, variable-length codes: 1, 01, 001, 0101; or 00, 01, 10, 1100, 1101; and fixed-length codes: 00, 01, 10, 11, etc., all belong to prefix code encoding. Prefix coding ensures that there is no ambiguity when decoding compressed files, guaranteeing correct decoding.

[0094] Prefix code encoding can include regular prefix code encoding and unconventional prefix code encoding. Regular prefix code encoding uses shorter bit widths to represent smaller values ​​and longer bit widths to represent larger values. Unconventional prefix code encoding does the opposite, using shorter bit widths to represent larger values ​​and longer bit widths to represent smaller values.

[0095] For example, the Dot field can be encoded using an unconventional prefix code encoding method, that is, using a longer bit width to represent a smaller value and a shorter bit width to represent a larger value. For example, as shown in Table 2, the Dot field occupies 2 to 4 bits in the total bit width N of the floating-point number, that is, the bit width of the Dot field is 2 to 4. A specific encoding method for the Dot field is shown in Table 3.

[0096] Table 3

[0097]

[0098] As shown in Table 3, when the width of the Dot field is 2 bits, any one of the three values ​​2, 3, and 4 can be encoded using a 2-bit width. For example, encoding "11" can represent the Dot field value D as "4", encoding "10" can represent the Dot field value D as "3", and encoding "01" can represent the Dot field value D as "2". When the width of the Dot field is 3 bits, the value 1 can be encoded using a 3-bit width. For example, encoding "001" can represent the Dot field value D as "1". When the width of the Dot field is 4 bits, the value 0 can be encoded using a 4-bit width. In this case, the first exponent field does not exist.

[0099] The bit width indicator field uses unconventional prefix encoding. The bit width DW of the bit width indicator field is negatively correlated with the value indicated by the bit width indicator field. That is, the bit width DW of the bit width indicator field is negatively correlated with the bit width D of the first exponent field. When the total bit width of the floating-point number is fixed, this can prevent the bit width of the first mantissa field from jumping due to the simultaneous increase of the bit width of the bit width indicator field and the first exponent field. The bit width of the mantissa field determines the data precision. Therefore, using unconventional prefix encoding in the bit width indicator field can smoothly change the numerical precision of the data represented by the first floating-point number, preventing jumps in the numerical precision of the data represented by the first floating-point number. Especially near the center of the exponent, it can smooth the jumps in the bit width of the mantissa field, that is, smooth the precision jumps of the values ​​near the center of the exponent.

[0100] When the width of the Dot field is 4 bits, the value of the Dot field is 0, and the first exponent field does not exist. In some embodiments, the Dot field can also use different values ​​to indicate whether the first mantissa field represents the mantissa of the floating-point number or the offset of the floating-point number's exponent. For example, in one embodiment, the code "0001" can represent the value "0". In this case, the width D of the first exponent field is 0 bits, and the first mantissa field represents the mantissa of the floating-point number. The code "0000" can indicate that the floating-point number is DML data, which refers to a subnormal or denormal value. In this case, the first mantissa field represents the offset of the floating-point number's exponent. That is, when the width of the Dot field is 4 bits, if the Dot field is the preset value "0000", the Dot field indicates that the floating-point number is DML data, or in other words, it indicates that the first mantissa field represents the offset of the floating-point number's exponent. In another embodiment, the code "0000" can represent the value "0". In this case, the bit width D of the first exponent field is 0 bits, and the first mantissa field represents the mantissa of the floating-point number. The code "0001" can indicate that the floating-point number is DML data, that is, the Dot field is the preset value "0001". The Dot field indicates that the floating-point number is DML data, or in other words, it indicates that the first mantissa field represents the offset of the exponent of the floating-point number. DML data will be described in detail below.

[0101] III. First exponent field: Used to represent the exponent of the floating-point number. It occupies a bit width of D or D-1 in the total bit width N of the floating-point number, and the value of D ranges from 0 to 4 bits.

[0102] The first-order code field can use integer encoding, that is, using a fixed-length binary code to encode integers. For example, 2 bits can be used to encode 0 to 3, 3 bits can be used to encode 0 to 7, 4 bits can be used to encode 0 to 15, and so on.

[0103] For example, the first exponent field Es is used to characterize the exponent of a floating-point number. Assuming the exponent range of a floating-point number is Ev, the value E represented by the first exponent field Es belongs to the exponent range Ev, which can be determined by the following formula 1:

[0104] E v =(-1) Se ×[2 D-1 ,(2 D -1)] Formula 1

[0105] Wherein, Se is the sign bit of the value E in the first exponent field, also known as the sign bit of the exponent of the floating-point number. As shown in Table 2, when the absolute value of the exponent of the floating-point number is less than 4, that is, when the value D of the Dot field is less than 3, the bit width of the first exponent field is equal to the value D of the Dot field. Se occupies 1 bit in the bit width of the first exponent field to represent the positive or negative value E. In one embodiment, Se = 0 indicates that the value E of the first exponent field is positive, and Se = 1 indicates that the value E of the first exponent field is negative. In other embodiments, Se = 0 can also be used to represent that the value E of the first exponent field is positive, and Se = 1 can represent that the value E of the first exponent field is negative. This application does not specifically limit this.

[0106] Combining Formula 1 and Table 2, when the value D of the Dot field is 0, the bit width of the first exponent field is equal to the value D of the Dot field, the bit width of the first exponent field is 0, and the value E of the first exponent field is 0, meaning the exponent range Ev of the floating-point number is 0. When the value D of the Dot field is 1, the bit width of the first exponent field is equal to the value D of the Dot field, the bit width of the first exponent field is 1, and the value E of the first exponent field can be 1 or -1, meaning the exponent range Ev of the floating-point number is ±1. When the value D of the Dot field is 2, the bit width of the first exponent field is equal to the value D of the Dot field, the bit width D of the first exponent field is 2, and the value E of the first exponent field can be 2, 3, or -2, -3, meaning the exponent range Ev of the floating-point number is ±[2,3].

[0107] As shown in Table 2, when the absolute value of the exponent of a floating-point number is greater than or equal to 4, that is, when the value D of the Dot field is greater than or equal to 3, the bit width of the first exponent field is D-1. The first exponent field may not contain the sign bit Se. In this case, the exponent represented by the first exponent field (the value E of the first exponent field) is negative. For example, when the value D of the Dot field is 3, the bit width of the first exponent field is D-1 = 2, the first exponent field does not contain the sign bit Se, and the value E of the first exponent field is negative, which can be -4, -5, -6, or -7, that is, the exponent range Ev of the floating-point number is -[4,7]. When the value D of the Dot field is 4, the bit width of the first exponent field is D-1 = 3, the first exponent field does not contain the sign bit Se, and the value E of the first exponent field is negative, which can be any value between -8 and -15, that is, the exponent range Ev of the floating-point number is -[8,15]. Therefore, it can be seen that the exponent range Ev of the floating-point numbers that can be represented by the first exponent field is [-15, 3].

[0108] IV. First Mantissa Field: When the first exponent field occupies a non-zero bit width in the total bit width N of the floating-point number, the first exponent field is used to represent the exponent of the floating-point number, and the first mantissa field is used to represent the mantissa of the floating-point number. When the absolute value of the exponent of the floating-point number is greater than or equal to 4, the bit width of the first exponent field is D-1, and the bit width of the first mantissa field in the floating-point number is [N-1-DW-(D-1)] bits. For example, when the exponent of the floating-point number is -[8,15], the bit width DW of the Dot field is 2, the bit width of the first exponent field is D-1, and the bit width of the first mantissa field in the floating-point number is [N-1-DW-(D-1)]=[8-1-2-(D-1)]=5-D+1. At this time, the value D of the Dot field is 4, 5-4+1=2, that is, the bit width of the first mantissa field in the floating-point number is 2. When the exponent of the floating-point number is -[4,7], the bit width DW of the Dot field is 2, the bit width of the first exponent field is D-1, and the bit width occupied by the first mantissa field in the floating-point number is [N-1-DW-(D-1)]=[8-1-2-(D-1)]=5-D+1. At this time, the value D of the Dot field is 3, 5-D+1=3, that is, the bit width occupied by the first mantissa field in the floating-point number is 3.

[0109] When the absolute value of the exponent of a floating-point number is less than 4, the bit width of the first exponent field is D, and the bit width of the first mantissa field in the floating-point number is (N-1-DW-D) bits. For example, when the exponent of the floating-point number is ±[2,3], the bit width of the Dot field DW is 2, the bit width of the first exponent field is D, and the bit width of the first mantissa field in the floating-point number is (N-1-DW-D) = (8-1-2-D) = 5-D. At this time, the value of the Dot field D is 2, 5-2 = 3, that is, the bit width of the first mantissa field in the floating-point number is 3. When the exponent of the floating-point number is ±1, the bit width of the Dot field (DW) is 3, the bit width of the first exponent field is D, and the bit width occupied by the first mantissa field in the floating-point number is (N-1-DW-D) = (8-1-3-D) = 4-D. At this time, the value of the Dot field (D) is 1, and 4-1 = 3, meaning the bit width occupied by the first mantissa field in the floating-point number is 3. When the exponent of the floating-point number is 0, the bit width of the Dot field (DW) is 4, the bit width of the first exponent field is D, and the bit width occupied by the first mantissa field in the floating-point number is (N-1-DW-D) = (8-1-4-D) = 3-D. At this time, the value of the Dot field (D) is 0, and 3-0 = 3, meaning the bit width occupied by the first mantissa field in the floating-point number is 3.

[0110] In some embodiments, when the bit width of the first exponent field is 0 and the encoding of the Dot field is "0000", i.e., the Dot field is a DML flag, it indicates that the floating-point number is DML data. In this case, the first mantissa field represents the offset of the exponent of the floating-point number, the first exponent field does not exist, and the exponent of the floating-point number is the value obtained by correcting the preset exponent using the exponent offset. When the bit width of the first exponent field is 0 and the encoding of the Dot field is "0001", i.e., the floating-point number is not DML, the exponent E of the floating-point number is 0.

[0111] When the bit width of the first-order code field is non-zero, i.e., the bit width of the first-order code field is any value from 1 to 4, the first-order code field can use signed magnitude encoding, also known as the encoding method where the sign bit Se follows the original code. This representation adds a sign bit before the numerical value; that is, the highest bit of the original code is the sign bit, used to indicate whether the value is positive or negative. A sign bit of 0 indicates a positive number, and a sign bit of 1 indicates a negative number. The remaining bits in the original code, excluding the sign bit, are used to represent the magnitude of the numerical value, i.e., the magnitude of the original code. For example, the original code 1001 represents -1, and 0011 represents +3.

[0112] When the bit width of the first exponent field is non-zero, the first exponent field in the floating-point number can be encoded using the exponent sign bit Se following the magnitude of the original code, which can be represented as Es: {Se+Mag[2:end]}, where the exponent sign bit Se is the sign bit extracted from the initial original code, used to indicate the sign of the value E of the first exponent field; Mag is used to represent the magnitude of the value E of the first exponent field, end = D-1, D is the value of the Dot field, and Mag[2:end] is used to represent the value of the 2nd to D-1th bits of the first exponent field. For different values ​​of D, the highest bit b1 of the magnitude Mag of the first exponent field value E is always 1 (i.e., 1'b1). Therefore, the highest bit 1'b1 does not occupy bit width during encoding, that is, the highest bit 1'b1 is hidden and not actually stored. During subsequent decoding, the highest bit 1'b1 can be directly added to obtain the encoded value Ei of the exponent field in the normalized floating-point number: {Se+1'b1+Mag[2:end]}. Normalized floating-point numbers refer to floating-point numbers that conform to the IEEE 754 binary floating-point standard, such as FP32, FP16, and FP8 formats. Normalized floating-point numbers can be used for floating-point calculations. Since the highest bit of the exponent field's encoded value Ei does not need to occupy a bit width in the first exponent field and is not actually stored, storage space can be greatly saved, reducing the cost of data storage and data transfer.

[0113] For example, as shown in Table 4, when the Dot field is a DML flag (i.e., the Dot field is encoded as "0000"), it indicates that the floating-point number is DML data. In this case, the bit width of the first mantissa field is 3, meaning that the first mantissa field uses 3 bits to represent the offset of the floating-point number's exponent. The exponent of the floating-point number is the value obtained by correcting the preset exponent using the exponent offset. When the Dot field indicates that the bit width of the first exponent field is 0 (i.e., the Dot field is encoded as "0001"), the encoding Es of the first exponent field in the floating-point number is None. The decoded value Ei of the normalized floating-point number's exponent field is 0, indicating that the value E of the floating-point number's exponent is 0. In this case, the bit width of the Dot field is 4, and the bit width of the first mantissa field is 3, meaning that the first mantissa field uses 3 bits to represent the mantissa of the floating-point number.

[0114] When the value D of the Dot field is 1, the bit width of the first exponent field is equal to D, that is, the bit width of the first exponent field is 1. The encoding of the first exponent field in the floating-point number is Es = {Se}, and the decoded value of this first exponent field, that is, the value of the exponent field of the normalized floating-point number is Ei = {Se, 1}, where 1 is the value of the highest bit in Mag. As mentioned above, the highest bit in Mag is always 1. When the bit width D = 1, the exponent E of the floating-point number represented by the first exponent field can be 1 or -1, that is, the numerical range of the exponent E of the floating-point number can be ±1. At this time, the bit width of the Dot field is 3, and the bit width of the first mantissa field is 3, that is, the first mantissa field uses 3 bits to represent the mantissa of the floating-point number.

[0115] When the value D of the Dot field is 2, the bit width of the first exponent field is equal to D, that is, the bit width of the first exponent field is 2. The encoding of the first exponent field in the floating-point number is Es = {Se, Mag[2]}, where Mag[2] represents the value of the second bit in Mag. The decoded value of the first exponent field, that is, the value of the exponent field of the normalized floating-point number is Ei = {Se, 1, Mag[2]}, where 1 is the value of the highest bit in Mag. When the bit width D = 2, the exponent E of the floating-point number represented by the first exponent field can be any value in [-2, -3] or [2, 3], that is, the numerical range of the exponent E of the floating-point number can be ±[2, 3]. At this time, the bit width of the Dot field is 2, and the bit width of the first mantissa field is 3, that is, the first mantissa field uses 3 bits to represent the mantissa of the floating-point number.

[0116] When the value of the Dot field D is 3, the bit width of the first exponent field is equal to D-1, that is, the bit width of the first exponent field is 2. The encoding of the first exponent field in the floating-point number is Es = {Mag[2:3]}, where Mag[2:3] represents the values ​​of the 2nd and 3rd bits in Mag. The first exponent field does not contain the exponent sign bit Se, and the value of Se is 1 by default, indicating that the exponent is negative. The decoded value of this first exponent field, that is, the value of the exponent field of the normalized floating-point number Ei = {1, 1, Mag[2:3]}, where the first 1 is the value of the exponent sign bit Se, and the second 1 is the value of the highest bit in Mag. When the value of the Dot field D = 3, the bit width of the first exponent field is 2. The exponent E of the floating-point number represented by the first exponent field can be any value in [-4, -7], that is, the numerical range of the exponent E of the floating-point number can be -[4, 7]. At this point, the bit width of the first sign field is 1, the bit width of the Dot field is 2, the bit width of the first exponent field is 2, and the bit width of the first mantissa field is 3. That is, the first mantissa field uses 3 bits to represent the mantissa of the floating-point number.

[0117] When the value of the Dot field D is 4, the bit width of the first exponent field is equal to D-1, that is, the bit width of the first exponent field is 3. The encoding of the first exponent field in the floating-point number is Es = {Mag[2:4]}, where Mag[2:4] represents the values ​​of the 2nd, 3rd, and 4th bits in Mag. The first exponent field does not contain the exponent sign bit Se, and the value of Se is 1 by default, indicating that the exponent is negative. The decoded value of this first exponent field, that is, the value of the exponent field of the normalized floating-point number Ei = {1, 1, Mag[2:4]}, where the first 1 is the value of the exponent sign bit Se, and the second 1 is the value of the highest bit in Mag. When the value of the Dot field D = 4, the bit width of the first exponent field is 3. The exponent E of the floating-point number represented by the first exponent field can be any value in [-8, -15], that is, the numerical range of the exponent E of the floating-point number can be -[8, 15]. At this point, the bit width of the first sign field is 1, the bit width of the Dot field is 2, the bit width of the first exponent field is 3, and the bit width of the first mantissa field is 2. That is, the first mantissa field uses 2 bits to represent the mantissa of the floating-point number.

[0118] Table 4

[0119] The value of the Dot field D DML 0 1 2 3 4 The encoding of the first-order code field, Es / None Se Se, Mag[2] Mag[2:3] Mag[2:4] The decoded value Ei of the first-order code field / 0 Se, 1 Se, 1, Mag[2] 1, 1, Mag[2:3] 1, 1, Mag[2:4] The exponent E of a floating-point number / 0 ±1 ±[2,3] -[4,7] -[8,15] Bit width of the first mantissa field 3 3 3 3 3 2

[0120] In some embodiments, when the bit width DW of the Dot field is 4, the Dot field can be used to indicate whether the first mantissa field represents the mantissa of a floating-point number or the offset of the floating-point exponent. In one embodiment, when the bit width DW of the Dot field is 4 and the value of the Dot field is "0001", it is used to indicate that the first mantissa field represents the mantissa of a floating-point number; when the bit width DW of the Dot field is 4 and the value of the Dot field is "0000", it is used to indicate that the first mantissa field represents the offset of the floating-point exponent. In another embodiment, the opposite setting can also be used: when the bit width DW of the Dot field is 4 and the value of the Dot field is "0000", it is used to indicate that the first mantissa field represents the mantissa of a floating-point number; when the bit width DW of the Dot field is 4 and the value of the Dot field is "0001", it is used to indicate that the first mantissa field represents the offset of the floating-point exponent.

[0121] When the first mantissa field represents the mantissa of a floating-point number, it is used to store the value after the decimal point. For example, if storing the decimal places of 1.xxx, assume the integer part 1'b1 is hidden. For instance, if the encoding stored in the first mantissa field is 10011, then the decoded value M of the first mantissa field is 0.10011, and the value represented by the first mantissa field is 1.M, which is 1.10011.

[0122] When the first mantissa field represents the offset of the exponent of a floating-point number, the floating-point number represented is DML data. In this case, the bit width of the first mantissa field is 3, that is, the first mantissa field uses 3 bits to encode the integer value M from 0 to 7 to represent the exponent value of M-23. Here, M can be called the exponent offset, and the default exponent is -23. It can be seen that the first mantissa field can supplement the exponent range of [-23, -16]. When all 3 bits of the first mantissa field are 0, that is, when M=0 and M-23=-23, the floating-point number is used to represent special values ​​(which will be described in detail below). Therefore, the exponent range that the first mantissa field can represent is [-22, -16]. As shown in Table 4, the exponent range that the first exponent field can represent is [-15, 3]. After combining with the first exponent field, the HiF8_DML_AI floating-point number provided in this embodiment can represent the exponent range of the floating-point number as [-22, 3].

[0123] When the first mantissa field represents the offset of the exponent of a floating-point number, the corresponding floating-point number is DML data, and the value X of this floating-point number can be represented as:

[0124] X = (-1) s ×2 M-23

[0125] Where S is the value of the sign field of the floating-point number, and M is the value represented by the first mantissa field of the floating-point number. In this case, the mantissa of the floating-point number adopts the default value of 1.

[0126] When the first mantissa field represents the mantissa of a floating-point number, the corresponding floating-point number is normal data, and the value X of this floating-point number can be represented as:

[0127] X = (-1) s ×2 E ×1.M

[0128] Where S is the value of the sign field of the floating-point number, E is the value represented by the first exponent field of the floating-point number, i.e., the exponent of the floating-point number, M is the value represented by the first mantissa field of the floating-point number, and 1.M is the mantissa of the floating-point number. The 1 in 1.M is also considered as a valid bit. It can be seen that the number of valid bits of the mantissa of the floating-point number is the bit width of the first mantissa field + 1.

[0129] In summary, the value X of a floating-point number can be represented as:

[0130]

[0131] As shown in Table 5, the HiF8_DML_AI floating-point number provided in this application embodiment has an exponent range of [-15, 3] represented by the first exponent field. Taking positive numbers as an example, the maximum positive number that the HiF8_DML_AI floating-point number provided in this application embodiment can represent for normal data is 001011102 = 2. 3 ×1.75, where 011111102 represents "00101110" as binary data. The minimum positive number that the HiF8_DML_AI floating-point number provided in this application can represent as normal data is 001011102 = 2. -15 The HiF8_DML_AI floating-point number provided in this application embodiment can represent a maximum positive value of 000001112 = 2 for DML data. -16 The HiF8_DML_AI floating-point number provided in this application embodiment can represent DML data with a minimum positive value of 000000012 = 2. -22 .

[0132] Table 5

[0133] Data types data Maximum positive value of normal data 001011102 = 2 3 x 1.75 Minimum positive value of normal data 011111102 = 2 -15 ]] Maximum positive value of DML data <![CDATA[000001112=2 -16 ]]> Minimum positive value in DML data <![CDATA[000000012=2 -22 ]]> Zero <![CDATA[000000002]]> NaN <![CDATA[100000002]]> The first-order code field represents the range of the exponent. [-15，3]

[0134] As shown in Table 5, the HiF8_DML_AI floating-point number provided in this application embodiment can also support special values: zero (neither positive nor negative) and NaN (not a number), wherein:

[0135] (1) Zero: When the sign field S of the floating-point number is 0 and the Dot field is 0000, that is, the Dot field indicates that the floating-point number is DML data. That is, the first mantissa field represents the offset of the exponent of the floating-point number, and when all 3 bits of the first mantissa field are 0, the corresponding floating-point number can be represented as ±0, i.e., Zero. The above description can be summarized as follows: when HiF8 = 8'b 0 0000 000, the represented value X = Zero.

[0136] (2) NaN: When the sign field S of the floating-point number is 1 and the Dot field is 0000, that is, the Dot field indicates that the floating-point number is DML data, that is, the first mantissa field represents the offset of the exponent of the floating-point number, and when all 3 bits of the first mantissa field are 0, the corresponding floating-point number can represent a non-numeric value, that is, NaN. The above description can be summarized as follows: when HiF8 = 8'b 1 0000 000, it means X = NaN.

[0137] Figure 5This illustration shows a schematic diagram of the mantissa precision-exponent distribution of a HiF8_DML_AI floating-point number according to an embodiment of this application. The mantissa precision of the floating-point number characterizes the numerical precision of the floating-point number and is related to the bit width of the first mantissa field. The bit width of the first mantissa field can represent the magnitude of the numerical precision of the floating-point number. For example... Figure 5 As shown, since the absolute value of the exponent is greater than or equal to 4, the first exponent field does not contain a sign bit, and the exponent represented by the first exponent field is negative. The floating-point number HiF8_DML_AI provided in this application embodiment can represent an exponent range of [-22, 3], which exhibits a negatively skewed distribution, matching the characteristic of the exponent of data in AI scenarios exhibiting a negatively skewed probability distribution. Specifically, when the value of the exponent is between [-22, -16], the floating-point number represented by HiF8_DML_AI is DML data, and the bit width of the first mantissa field is 0 bits. At this time, the mantissa has a default value of 1. When the exponent value is between -15 and -8, the floating-point number represented by HiF8_DML_AI is normal data, and the width of the first mantissa field is 2 bits. When the exponent value is between -7 and -4, the floating-point number represented by HiF8_DML_AI is normal data, and the width of the first mantissa field is 3 bits. When the exponent value is between -3 and 3, the floating-point number represented by HiF8_DML_AI is normal data, and the width of the first mantissa field is also 3 bits. Since the first exponent field does not contain a sign bit when the absolute value of the exponent is greater than or equal to 4, the width of the first mantissa field can be increased by 1 bit to increase numerical precision and meet the precision requirements when the exponent of the data is large.

[0138] In other embodiments, the total bit width of the floating-point number can be 8 bits, and the above-mentioned setting value can be 8. When the absolute value of the exponent of the floating-point number is less than 8, the bit width of the first exponent field is equal to the value D of the Dot field; when the absolute value of the exponent of the floating-point number is greater than or equal to 8, the bit width of the first exponent field is less than the value D of the Dot field, and can be D-1. Table 6 exemplarily shows the data format of the floating-point number provided in this embodiment.

[0139] Table 6

[0140] Bit width of the first symbol field The bit width of the Dot field, DW: value D Bit width of the first exponent field: exponent E Bit width of the first mantissa field 1 2：4 D-1：-[8,15] 5-D+1 1 2：3 D：±[4,7] 5-D 1 2：2 D：±[2,3] 5-D 1 3：1 D：±1 4-D 1 4：0 D：0 3-D

[0141] The following mainly introduces the differences between the floating-point data formats shown in Table 6 and those shown in Table 2. The similarities between the floating-point data formats shown in Table 6 and those shown in Table 2 can be found above and will not be repeated here.

[0142] For the floating-point numbers shown in Table 6, when the value of the Dot field D is 3, the bit width of the first exponent field is D, that is, the bit width of the first exponent field is 3. In this case, the exponent represented by the first exponent field is ±[4,7]. When the value of the Dot field D is 4, the bit width of the first exponent field is D-1, that is, the bit width of the first exponent field is 3. In this case, the exponent represented by the first exponent field is -[8,15]. As can be seen from Table 6, when the absolute value of the exponent of the floating-point number is greater than or equal to 8, that is, when the value of the Dot field D is greater than or equal to 4, the bit width of the first exponent field is D-1 = 3. The first exponent field does not include the sign bit Se, and the exponent represented by the first exponent field (the value of the first exponent field E) is negative, which can be any value between -8 and -15. That is, the exponent range Ev of the floating-point number is -[8,15].

[0143] When the value D of the Dot field is 0, the bit width of the first exponent field is equal to the value D of the Dot field, the bit width of the first exponent field is 0, and the value E of the first exponent field is 0, meaning the exponent range Ev of the floating-point number is 0. When the value D of the Dot field is 1, the bit width of the first exponent field is equal to the value D of the Dot field, the bit width of the first exponent field is 1, and the value E of the first exponent field can be 1 or -1, meaning the exponent range Ev of the floating-point number is ±1. When the value D of the Dot field is 2, the bit width of the first exponent field is equal to the value D of the Dot field, the bit width D of the first exponent field is 2, and the value E of the first exponent field can be 2, 3, or -2, -3, meaning the exponent range Ev of the floating-point number is ±[2,3]. When the value D of the Dot field is 3, the bit width of the first exponent field is equal to the value D of the Dot field. The bit width D of the first exponent field is 3, and the value E of the first exponent field can be any value between -4 and -7 or between 4 and 7. That is, the exponent range Ev of the floating-point number is ±[4,7]. Therefore, it can be seen that the exponent range Ev of the floating-point number that the first exponent field can represent is [-15,7].

[0144] When the first exponent field occupies a non-zero bit width in the total bit width N of the floating-point number, it is used to represent the exponent of the floating-point number, and the first mantissa field is used to represent the mantissa. When the absolute value of the exponent of the floating-point number is greater than or equal to 8, the bit width of the first exponent field is D-1, and the bit width of the first mantissa field in the floating-point number is [N-1-DW-(D-1)] bits. As shown in Table 6, when the exponent of the floating-point number is -[8,15], the bit width DW of the Dot field is 2, the bit width of the first exponent field is D-1, and the bit width of the first mantissa field in the floating-point number is [N-1-DW-(D-1)].

[0145] = [8-1-2-(D-1)] = 5-D+1. At this time, the value of the Dot field D is 4, and 5-4+1=2, that is, the first mantissa field occupies a bit width of 2 in the floating point number.

[0146] When the absolute value of the exponent of a floating-point number is less than 8, the bit width of the first exponent field is D, and the bit width of the first mantissa field in the floating-point number is (N-1-DW-D) bits. As shown in Table 6, when the exponent of the floating-point number is ±[4,7], the bit width of the Dot field DW is 2, the bit width of the first exponent field is D, and the bit width of the first mantissa field in the floating-point number is (N-1-DW-D)=(8-1-2-D)=5-D. At this time, the value of the Dot field D is 3, and 5-D=2, that is, the bit width of the first mantissa field in the floating-point number is 2.

[0147] In this embodiment, the encoding method of the Dot field can also use prefix code encoding. A specific encoding method can be referred to Table 3, which will not be repeated here. As shown in Table 7, when the Dot field is a DML flag (i.e., the encoding of the Dot field is "0000"), it indicates that the floating-point number is DML data. At this time, the bit width of the first mantissa field is 3, that is, the first mantissa field uses 3 bits to represent the offset of the exponent of the floating-point number. The exponent of the floating-point number is the value obtained by correcting the preset exponent using the exponent offset. When the bit width of the Dot field indicating the first exponent field is 0 (i.e., the encoding of the Dot field is "0001"), the encoding Es of the first exponent field in the floating-point number is None. The value Ei of the normalized exponent field of the floating-point number is 0 after decoding, indicating that the value E of the exponent of the floating-point number is 0. At this time, the bit width of the Dot field is 4, and the bit width of the first mantissa field is 3, that is, the first mantissa field uses 3 bits to represent the mantissa of the floating-point number.

[0148] When the value D of the Dot field is 1, the bit width of the first exponent field is equal to D, that is, the bit width of the first exponent field is 1. The encoding of the first exponent field in the floating-point number is Es = {Se}, and the decoded value of this first exponent field, that is, the value of the exponent field of the normalized floating-point number is Ei = {Se, 1}, where 1 is the value of the highest bit in Mag. As mentioned above, the highest bit in Mag is always 1. When the bit width D = 1, the exponent E of the floating-point number represented by the first exponent field can be 1 or -1, that is, the numerical range of the exponent E of the floating-point number can be ±1. At this time, the bit width of the Dot field is 3, and the bit width of the first mantissa field is 3, that is, the first mantissa field uses 3 bits to represent the mantissa of the floating-point number.

[0149] When the value D of the Dot field is 2, the bit width of the first exponent field is equal to D, that is, the bit width of the first exponent field is 2. The encoding of the first exponent field in the floating-point number is Es = {Se, Mag[2]}, where Mag[2] represents the value of the second bit in Mag. The decoded value of the first exponent field, that is, the value of the exponent field of the normalized floating-point number is Ei = {Se, 1, Mag[2]}, where 1 is the value of the highest bit in Mag. When the bit width D = 2, the exponent E of the floating-point number represented by the first exponent field can be any value in [-2, -3] or [2, 3], that is, the numerical range of the exponent E of the floating-point number can be ±[2, 3]. At this time, the bit width of the Dot field is 2, and the bit width of the first mantissa field is 3, that is, the first mantissa field uses 3 bits to represent the mantissa of the floating-point number.

[0150] When the value D of the Dot field is 3, the bit width of the first exponent field is equal to D, that is, the bit width of the first exponent field is 3. The encoding of the first exponent field in the floating-point number is Es = {Se, Mag[2:3]}, where Mag[2:3] represents the values ​​of the 2nd and 3rd bits in Mag. The decoded value of this first exponent field, that is, the value of the exponent field of the normalized floating-point number is Ei = {Se, 1, Mag[2:3]}, where the first 1 is the value of the exponent sign bit Se, and the second 1 is the value of the highest bit in Mag. When the value D of the Dot field is 3, the bit width of the first exponent field is 3. The exponent E of the floating-point number represented by the first exponent field can be any value in [-4,-7] or [4,7], that is, the numerical range of the exponent E of the floating-point number can be ±[4,7]. At this point, the bit width of the first sign field is 1, the bit width of the Dot field is 2, the bit width of the first exponent field is 3, and the bit width of the first mantissa field is 2. That is, the first mantissa field uses 2 bits to represent the mantissa of the floating-point number.

[0151] When the value of the Dot field D is 4, the bit width of the first exponent field is equal to D-1, that is, the bit width of the first exponent field is 3. The encoding of the first exponent field in the floating-point number is Es = {Mag[2:4]}, where Mag[2:4] represents the values ​​of the 2nd, 3rd, and 4th bits in Mag. The first exponent field does not contain the exponent sign bit Se, and the value of Se is 1 by default, indicating that the exponent is negative. The decoded value of this first exponent field, that is, the value of the exponent field of the normalized floating-point number Ei = {1, 1, Mag[2:4]}, where the first 1 is the value of the exponent sign bit Se, and the second 1 is the value of the highest bit in Mag. When the value of the Dot field D = 4, the bit width of the first exponent field is 3. The exponent E of the floating-point number represented by the first exponent field can be any value in [-8, -15], that is, the numerical range of the exponent E of the floating-point number can be -[8, 15]. At this point, the bit width of the first sign field is 1, the bit width of the Dot field is 2, the bit width of the first exponent field is 3, and the bit width of the first mantissa field is 2. That is, the first mantissa field uses 2 bits to represent the mantissa of the floating-point number.

[0152] Table 7

[0153] The value of the Dot field D DML 0 1 2 3 4 The encoding of the first-order code field, Es / None Se Se, Mag[2] Se, Mag[2:3] Mag[2:4] The decoded value Ei of the first-order code field / 0 Se, 1 Se, 1, Mag[2] Se, 1, Mag[2:3] 1, 1, Mag[2:4] The exponent E of a floating-point number / 0 ±1 ±[2,3] ±[4,7] -[8,15] Bit width of the first mantissa field 3 3 3 3 2 2

[0154] The floating-point number format provided in this embodiment can represent numerical values ​​as shown in Table 8. The difference between Table 8 and Table 5 is that the HiF8_DML_AI floating-point number provided in this embodiment has an exponent range of [-15, 7] represented by the first exponent field. The maximum positive number that the HiF8_DML_AI floating-point number provided in this embodiment can represent for normal data is 010011102 = 2. 7 ×1.75, where 010011102 represents "01001110" as binary data. The similarities between Table 8 and Table 5 can be found in the explanation of Table 5 above, and will not be repeated here.

[0155] Table 8

[0156] Data types data Maximum positive value of normal data <![CDATA[010011102=2 7 ×1.75]]> Minimum positive value of normal data <![CDATA[011111102=2 -15 ]]> Maximum positive value of DML data <![CDATA[000001112=2 -16 ]]> Minimum positive value in DML data <![CDATA[000000012=2 -22 ]]> Zero <![CDATA[000000002]]> NaN <![CDATA[100000002]]> The first-order code field represents the range of the exponent. [-15，7]

[0157] Figure 6 This embodiment illustrates a schematic diagram of the mantissa precision-exponent distribution of a HiF8_DML_AI floating-point number. For example... Figure 6 As shown, since the absolute value of the exponent is greater than or equal to 8, the first exponent field does not contain a sign bit, and the exponent represented by the first exponent field is negative. The floating-point number HiF8_DML_AI provided in this embodiment can represent an exponent range of [-22, 7], which exhibits a negative skewed distribution. This matches the characteristic of the exponent of data in AI scenarios exhibiting a negative skewed probability distribution. Furthermore, compared with the floating-point numbers shown in Table 2, the floating-point number provided in this embodiment can represent a wider range of exponents. Specifically, when the value of the exponent is between [-22, -16], the floating-point number represented by HiF8_DML_AI is DML data, and the bit width of the first mantissa field is 0 bits. At this time, the mantissa has a default value of 1. When the exponent value is between -15 and -8, the floating-point number represented by HiF8_DML_AI is normal data, and the first mantissa field has a width of 2 bits. When the exponent value is between -7 and -4 or between 4 and 7, the floating-point number represented by HiF8_DML_AI is normal data, and the first mantissa field has a width of 2 bits. When the exponent value is between -3 and 3, the floating-point number represented by HiF8_DML_AI is normal data, and the first mantissa field has a width of 3 bits. Since the first exponent field does not contain a sign bit when the absolute value of the exponent is greater than or equal to 8, the width of the first mantissa field can be increased by 1 bit to increase numerical precision, meet the precision requirements when the exponent of the data is large, and improve the performance of floating-point numbers.

[0158] The floating-point numbers provided in this application can be applied not only to AI scenarios but also to other scenarios such as high-performance computing, and can be used for data storage or data transfer. Correspondingly, this application also provides a floating-point number processing method, which can be... Figure 3 The processor 110 shown executes the commands. Figure 7 As shown, the method may include the following steps:

[0159] S701, Get the first floating-point number.

[0160] The processor can read the first floating-point number from the local memory of the computing device to which it belongs, or it can obtain the first floating-point number from another computing device via a network. The data format of the first floating-point number includes a first sign field, a bit width indicator field, a first exponent field, and a first mantissa field. The first sign field indicates the sign of the first floating-point number, i.e., whether it is positive or negative; the bit width indicator field indicates the bit width occupied by the first exponent field in the total bit width N of the first floating-point number; the first exponent field represents the exponent of the first floating-point number; and the first mantissa field represents the mantissa of the first floating-point number. The absolute value of the exponent of the first floating-point number is greater than or equal to a set value. The bit width of the first mantissa field is greater than the difference between the total bit width of the first floating-point number and the first bit width, where the first bit width is the sum of the bit width of the first sign field, the bit width of the bit width indicator field, and the value of the bit width indicator field.

[0161] S702 decodes the first floating-point number to obtain the second floating-point number.

[0162] The second floating-point number uses a data format that includes a second sign field, a second exponent field, and a second mantissa field. The second floating-point number represents the same data as the first floating-point number.

[0163] For example, the processor can use the value of the first sign field of the first floating-point number as the value of the second sign field of the second floating-point number, and determine the second exponent field and the second mantissa field of the second floating-point number based on the values ​​of the first exponent field and the first mantissa field of the first floating-point number.

[0164] In some embodiments, the first mantissa field can represent not only the mantissa of the first floating-point number but also the offset of the exponent of the first floating-point number. The bit-width indicator field can also be used to indicate whether the first mantissa field represents the mantissa of the first floating-point number or the offset of the exponent of the first floating-point number.

[0165] When the bit width D of the first exponent field is 0, if the first mantissa field represents the mantissa of the first floating-point number, the value indicated by the first mantissa field can be used as the value indicated by the second mantissa field of the second floating-point number, and the first preset exponent can be used as the value indicated by the second exponent field of the second floating-point number. The first preset exponent can be 0. If the first mantissa field represents the offset of the exponent of the first floating-point number, the preset mantissa can be used as the value indicated by the second mantissa field of the second floating-point number, and the value of the first mantissa field can be used to correct the second preset exponent to obtain the value of the exponent field of the second floating-point number. The preset mantissa can be 1, and the second preset exponent can be -23.

[0166] When the bit width D of the first exponent field is non-zero, the first exponent field is used to represent the exponent of the first floating-point number, and the first mantissa field is used to represent the mantissa of the first floating-point number. In this case, the first exponent field and the first mantissa field can be determined in the first floating-point number based on the bit width indicator field. Then, the value indicated by the first mantissa field is used as the value indicated by the second mantissa field of the second floating-point number, and the value indicated by the first exponent field is used as the value indicated by the second exponent field of the second floating-point number.

[0167] For example, in some embodiments, if the value D of the bit width indicator field of the first floating-point number is 4, and the bit width of the first exponent field is D-1=3, then the bit width of the first sign field is 1 bit, the bit width of the bit width indicator field is 2 bits, the bit width of the first exponent field is 3 bits, and the bit width of the first mantissa field is 2 bits. That is, the 4th to 6th bits of the first floating-point number are the first exponent field, and the 7th and 8th bits are the first mantissa field. The values ​​indicated by the 7th and 8th bits of the first floating-point number can be used as the values ​​indicated by the second mantissa field of the second floating-point number, and the values ​​indicated by the 4th to 6th bits of the first floating-point number can be used as the values ​​indicated by the second exponent field of the second floating-point number. If the value D of the bit width indicator field of the first floating-point number is 3, and the bit width of the first exponent field is D-1=2, then the bit width of the first sign field is 1 bit, the bit width of the bit width indicator field is 2 bits, the bit width of the first exponent field is 2 bits, and the bit width of the first mantissa field is 3 bits. That is, the 4th and 5th bits of the first floating-point number are the first exponent field, and the 6th to 8th bits are the first mantissa field. The values ​​indicated by the 6th to 8th bits of the first floating-point number can be used as the values ​​indicated by the second mantissa field of the second floating-point number, and the values ​​indicated by the 4th and 5th bits of the first floating-point number can be used as the values ​​indicated by the second exponent field of the second floating-point number.

[0168] In other embodiments, if the value D of the bit width indicator field of the first floating-point number is 4 and the bit width of the first exponent field is D-1=3, then the bit width of the first sign field is 1 bit, the bit width of the bit width indicator field is 2 bits, the bit width of the first exponent field is 3 bits, and the bit width of the first mantissa field is 2 bits. That is, the 4th to 6th bits of the first floating-point number are the first exponent field, and the 7th and 8th bits are the first mantissa field. The values ​​indicated by the 7th and 8th bits of the first floating-point number can be used as the values ​​indicated by the second mantissa field of the second floating-point number, and the values ​​indicated by the 4th to 6th bits of the first floating-point number can be used as the values ​​indicated by the second exponent field of the second floating-point number.

[0169] In some embodiments, the decoder in the processor can be used to convert a first floating-point number to a second floating-point number. For example, a schematic diagram illustrating the operation of the decoder can be shown as follows: Figure 8 As shown, this decoder can also be called the HiF8_DML_AI decoder. For example... Figure 8 As shown, the first floating-point number sequentially includes a sign field, a dot field, a first exponent field, and a first mantissa field, with a total bit width N of 8. The sign field occupies 1 bit and is the most significant bit of the first floating-point number. The dot field occupies 2-4 bits, the first exponent field occupies 0-3 bits, and the first mantissa field occupies 2-3 bits. First, for the sign field of the floating-point number, the decoder can directly read and output its value, S = 0 or 1. Second, the decoder can determine the bit width of the dot field based on the values ​​of the second, third, or fourth bits of the first floating-point number. For example, if the second bit of the first floating-point number is "1", the bit width of the Dot field is 2; if the second bit of the first floating-point number is "0" and the third bit is "1", the bit width of the Dot field is also 2; if the second and third bits of the first floating-point number are both "0" and the fourth bit is "1", the bit width of the Dot field is 3; if the second, third, and fourth bits of the first floating-point number are all "0", the bit width of the Dot field is 4.

[0170] If the width of the Dot field is 4 bits, then the value of the Dot field can be used to determine whether the first mantissa field represents the mantissa of the first floating-point number or the offset of the exponent of the first floating-point number.

[0171] If the first mantissa field represents the mantissa of the first floating-point number, it indicates that the first floating-point number is normal data. The decoder can read the value of the first mantissa field, use it as the value of the second mantissa field of the second floating-point number, and use the first preset exponent as the value of the second exponent field of the second floating-point number. The first preset exponent can be 0.

[0172] If the first mantissa field represents the offset of the exponent of the first floating-point number, it indicates that the first floating-point number is DML data. The decoder can read the value of the first mantissa field and use it to correct the second preset exponent to obtain the value of the exponent field of the second floating-point number. For example, the second preset exponent can be -23. When the value of the first mantissa field is M, the value of the second exponent field of the second floating-point number can be M-23. The decoder can use the preset mantissa 1 as the value represented by the second mantissa field of the second floating-point number.

[0173] If the bit width of the Dot field is 2 or 3, the decoder can extract the Dot field and, by multiplexing the Dot field (MUX) according to a preset encoding rule, decode the Dot field to obtain the value D. The preset encoding rule can be shown in Table 4 above: encoding "11" can represent the value "4", encoding "10" can represent the value "3", encoding "01" can represent the value "2", and encoding "001" can represent the value "1".

[0174] The decoder can extract the first exponent field and the first mantissa field after the Dot field based on the value D of the Dot field. The value indicated by the first exponent field is used as the value indicated by the second exponent field of the second floating-point number; the value indicated by the first mantissa field is used as the value indicated by the second mantissa field of the second floating-point number. Thus, the decoder can determine the values ​​of the second exponent field, the second mantissa field, and the second sign field of the second floating-point number based on the values ​​of the first exponent field, the first mantissa field, and the first sign field of the first floating-point number.

[0175] For example, the first floating-point number input to the decoder is "11010110", with a total bit width N of 8 bits. The first bit "1" is the sign field, and the second and third bits "10" are the Dot field. According to the preset encoding rules, the value D of the Dot field is decoded to be 3. In one embodiment, since the Dot field value D is 3, the bit width of the first exponent field is determined to be D-1 = 2 bits. The first exponent field does not contain the exponent sign bit. Therefore, the decoder can accurately extract the fourth and fifth bits "10" as the first exponent field, which is used to represent the exponent of the first floating-point number. The remaining sixth to eighth bits "110" are the first mantissa field, which is used to represent the mantissa of the first floating-point number. Based on this, the encoding of the exponent field of the second floating-point number is "1110", representing a value of -6, and the value of the mantissa field of the second floating-point number is 0.110.

[0176] In other embodiments, the first floating-point number can also be decoded to directly obtain the sign, exponent, and mantissa. For example, the sign can be determined based on the value of the first sign field of the first floating-point number. For instance, if the value of the first sign field is 0, the sign is positive; if the value of the first sign field is 1, the sign is negative.

[0177] When the bit width D of the first exponent field is 0, it indicates that the first exponent field does not exist. In this case, if the Dot field indicates that the first mantissa field represents the mantissa of the first floating-point number, the exponent can be the first preset exponent 0. If the Dot field indicates that the first mantissa field represents the offset of the exponent of the first floating-point number, the exponent can be the value obtained by correcting the second preset exponent -23 using this offset, and the mantissa can be the preset mantissa 1.

[0178] When the bit width D of the first exponent field is not 0, the mantissa is the value indicated by the first mantissa field of the first floating-point number, and the exponent is the value indicated by the first exponent field of the first floating-point number.

[0179] After obtaining the second floating-point number, it can be used in the calculation task.

[0180] In some embodiments, the processor can also obtain a third floating-point number. For example, the processor can read the third floating-point number from the local memory of the computing device to which the processor belongs, or it can obtain the third floating-point number from another computing device via a network. The data format of the third floating-point number is the same as that of the first floating-point number, including a first sign field, a bit width indicator field, a first exponent field, and a first mantissa field. The absolute value of the exponent of the third floating-point number is less than a set value. The bit width of the first mantissa field of the third floating-point number is equal to the difference between the total bit width of the third floating-point number and the first bit width, wherein the first bit width is the sum of the bit width of the first sign field, the bit width of the bit width indicator field, and the value of the bit width indicator field. The processor decodes the third floating-point number to obtain a fourth floating-point number. The data format of the fourth floating-point number is the same as that of the second floating-point number, including a second sign field, a second exponent field, and a second mantissa field. The fourth floating-point number and the third floating-point number represent the same data.

[0181] For example, the processor can use the value of the first sign field of the third floating-point number as the value of the second sign field of the fourth floating-point number, and determine the second exponent field and the second mantissa field of the fourth floating-point number based on the values ​​of the first exponent field and the first mantissa field of the third floating-point number.

[0182] The process of decoding the third floating-point number to obtain the fourth floating-point number can be performed in the same way as the process of decoding the first floating-point number to obtain the second floating-point number. Specifically, when the bit width D of the first exponent field of the third floating-point number is non-zero, the first exponent field and the first mantissa field can be determined in the third floating-point number based on the bit width indicator field. Then, the value indicated by the first mantissa field of the third floating-point number is used as the value indicated by the second mantissa field of the fourth floating-point number, and the value indicated by the first exponent field of the third floating-point number is used as the value indicated by the second exponent field of the fourth floating-point number. The difference lies in the following: In some embodiments, if the value D of the bit width indicator field of the third floating-point number is 3, and the bit width of the first exponent field is D = 3, then the bit width of the first sign field of the third floating-point number is 1 bit, the bit width of the bit width indicator field is 2 bits, the bit width of the first exponent field is 3 bits, and the bit width of the first mantissa field is 2 bits. That is, the 4th and 5th bits of the third floating-point number are the first exponent field, and the 6th to 8th bits are the first mantissa field. The values ​​indicated by the 6th to 8th bits of the third floating-point number can be used as the values ​​indicated by the second mantissa field of the fourth floating-point number, and the values ​​indicated by the 4th and 5th bits of the third floating-point number can be used as the values ​​indicated by the second exponent field of the fourth floating-point number.

[0183] In some embodiments, the decoder in the processor can be used to convert a third floating-point number into a fourth floating-point number. For example, suppose the third floating-point number input to the decoder is "11010110", with a total bit width N of 8 bits. The first bit "1" is the sign field, and the second and third bits "10" are the Dot field. According to a preset encoding rule, the value D of the Dot field is decoded to be 3. Since the Dot field value D is 3, the bit width of the first exponent field is determined to be 3 bits. The first exponent field includes the exponent sign bit. Therefore, the decoder can accurately extract the fourth to sixth bits "101" as the first exponent field from the third floating-point number. The first exponent field is used to represent the exponent of the first floating-point number. The remaining seventh and eighth bits "10" are the first mantissa field, used to represent the mantissa of the third floating-point number. Based on this, the encoding of the exponent field of the fourth floating-point number is "1101", representing a value of -5, and the value of the mantissa field of the fourth floating-point number is 0.10.

[0184] After obtaining the fourth floating-point number, it can be used to participate in the calculation task.

[0185] Exemplarily, in other embodiments, such as Figure 9 As shown, the floating-point number processing method executed by the processor may include the following steps:

[0186] S901, get the first floating-point number.

[0187] S902 decodes the first floating-point number to obtain the second floating-point number.

[0188] S903 uses a second floating-point number to participate in the calculation task and obtain the calculation result.

[0189] In some embodiments, the processor includes a decoder, which decodes the first floating-point number to obtain a second floating-point number. The second floating-point number uses a data format including a second sign field, a second exponent field, and a second mantissa field. The decoder can transmit the decoded second floating-point number to a computation unit in the processor. The computation unit receives the second floating-point number and performs corresponding calculations to obtain a calculation result. The data format of the calculation result is the same as that of the second floating-point number, and may include a second sign field, a second exponent field, and a second mantissa field. The second sign field indicates the sign of the calculation result, the second exponent field indicates the exponent of the calculation result, and the second mantissa field indicates the mantissa of the calculation result.

[0190] S904 converts the calculation result into a fifth floating-point number.

[0191] The fifth floating-point number is a floating-point number that uses the same encoding method as the first floating-point number mentioned above. The fifth floating-point number may include a first sign field, a Dot field, a first exponent field, and a first mantissa field.

[0192] The processor can use the value of the sign field of the calculation result as the value of the first sign field of the fifth floating-point number, and determine the numerical range to which the calculation result belongs based on the exponent and mantissa of the calculation result.

[0193] If the numerical range of the calculation result is within the first set range, the value of the first mantissa field of the fifth floating-point number can be determined based on the exponent and mantissa fields of the calculation result, and the Dot field can be set to the first value. The first value indicates that the first mantissa field represents the offset of the exponent of the first floating-point number. Taking the encoding rules shown in Table 4 as an example, the first value can be the encoding "0000". Here, the first set range refers to the range of DML data.

[0194] If the numerical range of the calculation result falls within the second preset range, the values ​​of the first exponent field, the first mantissa field, and the Dot field of the fifth floating-point number can be determined based on the exponent field and the mantissa field of the calculation result, respectively. The second preset range refers to the range of normal data.

[0195] If the value of the first exponent field is determined to be the first preset exponent 0 based on the exponent field and mantissa field of the calculation result, that is, the bit width of the first exponent field is 0, then the Dot field can be set to the second value. The second value is used to indicate that the first mantissa field represents the mantissa of the fifth floating-point number. Taking the encoding rules shown in Table 4 as an example, the second value can be the encoding "0001".

[0196] If the value of the first exponent field is determined to be -6 based on the exponent and mantissa fields of the calculation result, in one embodiment, assuming the set value is 8, the absolute value of -6 in the first exponent field is 6, which is less than the set value of 8. The bit width of the first exponent field can be equal to the value of the Dot field. In this case, both the bit width of the first exponent field and the value of the Dot field are 3. The encoding of the Dot field can be "10", and the encoding of the first exponent field can be "110". In another embodiment, assuming the set value is 4, the absolute value of -6 in the first exponent field is 6, which is greater than the set value of 4. The bit width of the first exponent field can be less than the value of the Dot field. In this case, the value of the Dot field is 3, the bit width of the first exponent field is 2, and the encoding of the Dot field can be "10". The encoding of the first exponent field can also be "10".

[0197] In some embodiments, the processor may further include an encoder. After obtaining the calculation result, the computing unit in the processor can transmit the calculation result to the encoder, which converts the calculation result into a fifth-order floating-point number. The encoder can also be called a HiF8_DML_AI encoder. For example, a schematic diagram of the encoder's working principle can be shown as follows. Figure 10 As shown. The calculation result can include a second sign field, a second exponent field, and a second mantissa field. The encoder can use the value of the second sign field of the calculation result as the value of the first sign field of the fifth floating-point number. The encoder can determine the numerical range to which the calculation result belongs based on the value of the second exponent field of the calculation result.

[0198] If the numerical range of the calculation result is within a first predetermined range, i.e., the calculation result is DML data, the encoder can determine the value of the first mantissa field of the fifth floating-point number based on the exponent and mantissa of the calculation result. For example, the encoder can process the mantissa of the calculation result and adjust the exponent of the calculation result based on the processed mantissa, obtaining the first mantissa field of the fifth floating-point number based on the adjusted exponent. For instance, assuming the mantissa of the calculation result is 1.XXXXXX, the encoder can perform mantissa shifting and rounding operations on the mantissa of the calculation result, rounding to one integer digit, resulting in a processed mantissa of 1.0. This will cause the exponent value to increase by 1. Therefore, the exponent of the calculation result can be adjusted by adding 23 to the adjusted exponent value to obtain the value of the first mantissa field of the fifth floating-point number. The first mantissa field of the fifth floating-point number is then encoded according to the value of the first mantissa field. The encoder can set the Dot field to a first value, which indicates that the first mantissa field represents the offset of the exponent of the fifth floating-point number. Taking the encoding rules shown in Table 4 as an example, the first value can be encoded as "0000".

[0199] If the numerical range of the calculation result is within the second preset range, i.e., the calculation result is normal data, the encoder can determine the first exponent field and the first mantissa field of the fifth floating-point number based on the exponent and mantissa of the calculation result, and determine the bit width indicator field of the fifth floating-point number based on the first exponent field. For example, the encoder can process the mantissa of the calculation result and adjust the exponent of the calculation result based on the processed mantissa. Based on the processed mantissa, the value of the first mantissa field of the fifth floating-point number is obtained, and based on the adjusted exponent, the value of the first exponent field of the fifth floating-point number is obtained. Based on the value of the first exponent field, the bit width D occupied by the first exponent field is determined, and based on the bit width D occupied by the first exponent field, the value of the bit width indicator field is determined. When the bit width occupied by the first exponent field is 0, the bit width indicator field is set to a second value; the second value is used to indicate that the first mantissa field represents the mantissa of the first floating-point number. Taking the encoding rules shown in Table 4 as an example, the second value can be the encoding "0001". For example, the encoder can encode the Dot field, the first exponent field, and the first mantissa field of the fifth floating-point number by performing a find-first operation on the absolute value of the exponent in the calculation result, and by performing operations such as shifting and rounding the mantissa in the calculation result.

[0200] For example, suppose the sign bit of the calculation result is 1, the exponent is "00011" (i.e., 3), and the mantissa is "1111". The encoder can determine that the sign bit of the fifth floating-point number is "1". By performing a lookup operation on the absolute value of the exponent "00011" until the first 1 is found, the encoder can determine that the bit width of the first exponent field of the fifth floating-point number is 2 bits, and the encoded value of the first exponent field is "01". Here, "0" is the exponent sign bit, indicating that the exponent is positive, and the highest bit "1" in the exponent magnitude "11" can be hidden and does not occupy bit width, as described above, and will not be repeated here. Based on the bit width of the first exponent field of 2 bits, the encoder can determine that the value of the Dot field of the fifth floating-point number is 2. Taking the encoding rule shown in Table 4 as an example, the value represented by the Dot field is 2, and the encoded value of the corresponding Dot field can be determined to be "01", occupying a bit width of 2 bits. Then the remaining coded bit width of the first mantissa field is 3 bits. The bit width of the mantissa "1111" in the input calculation result is greater than the bit width of the first mantissa field of the fifth floating-point number. Therefore, the mantissa "1111" can be rounded to obtain the mantissa "10.000" including the hidden bits to the left of the decimal point. At this time, the decimal point in the mantissa "10.000" needs to be shifted one bit to the left to obtain the mantissa "1.0000" including the hidden bits to the left of the decimal point. Since the decimal point is shifted one bit to the left, the exponent needs to be increased by 1 (i.e., 3 plus 1, which is 4). That is, the magnitude of the first exponent field is 4, and the corresponding encoded value is "100". In "100", the highest bit "1" is hidden, and the final encoded value of the first exponent field is "00", and the final encoded value of the first mantissa field is "000". Finally, the fifth floating-point number encoded by the encoder is "10100000".

[0201] In the example above, the exponent is 3, which determines that the bit width of the first exponent field of the fifth floating-point number is 2 bits, and the encoding value of the first exponent field is "01". In other embodiments, if the exponent indicated by the second exponent field is -5, in one embodiment, when the bit width of the first exponent field is equal to the value of the Dot field, the bit width of the first exponent field can be determined to be 3, and the encoding of the first exponent field can be "101", where the first "1" is the exponent sign bit, indicating that the exponent is negative, the value of the Dot field is 3, and the encoding of the Dot field can be "10". In another embodiment, when the bit width of the first exponent field is less than the value of the Dot field, the value of the Dot field is 3, the bit width of the first exponent field is 2, the encoding of the Dot field can be "10", and the encoding of the first exponent field can be "01", omitting the exponent sign bit "1".

[0202] The final fifth floating-point number is the HiF8_DML_AI data provided in this application embodiment. The fifth floating-point number can be used for data storage and data transfer to reduce the resources required for data storage or data transfer.

[0203] Based on the same inventive concept as the above embodiments, this application also provides a floating-point number processing method for obtaining the first floating-point number used in the above process. For example... Figure 11 As shown, the method may include the following steps:

[0204] S1101, Get the second floating-point number.

[0205] For example, the processor can obtain a second floating-point number, which can be the result of an operation output by the computing unit. The data format of the second floating-point number includes a second sign field, a second exponent field, and a second mantissa field. The second sign field is used to represent the sign of the second floating-point number, the second exponent field is used to represent the exponent of the second floating-point number, and the second mantissa field is used to represent the mantissa of the second floating-point number.

[0206] S1102, based on the second sign field, the second exponent field and the second mantissa field of the second floating-point number, the first floating-point number is obtained.

[0207] The processor can determine the sign, exponent, and mantissa of the second floating-point number based on the second sign field, second exponent field, and second mantissa field of the second floating-point number, and obtain the first floating-point number based on the sign, exponent, and mantissa. The data format adopted by the first floating-point number includes a first sign field, a bit-width indicator field, a first exponent field, and a first mantissa field. The first sign field is used to indicate the sign of the first floating-point number, the first exponent field is used to represent the exponent of the first floating-point number, and the first mantissa field is used to represent the mantissa of the first floating-point number. The bit-width indicator field is used to indicate the bit width of the first exponent field. The absolute value of the exponent of the first floating-point number is greater than or equal to a set value, and the bit width of the first mantissa field is greater than the difference between the total bit width of the first floating-point number and the first bit width. The first bit width is the sum of the bit width of the first sign field, the bit width of the bit-width indicator field, and the value of the bit-width indicator field. The first floating-point number and the second floating-point number represent the same data.

[0208] In some embodiments, the processor can also obtain a fourth floating-point number, which uses the same data format as the second floating-point number and may include a second sign field, a second exponent field, and a second mantissa field. The processor can obtain a third floating-point number based on the second sign field, second exponent field, and second mantissa field of the fourth floating-point number. The third floating-point number uses the same data format as the first floating-point number, including a first sign field, a bit-width indicator field, a first exponent field, and a first mantissa field. The absolute value of the exponent of the third floating-point number is less than a set value, and the bit width of the first mantissa field of the third floating-point number is equal to the difference between the total bit width and the first bit width of the third floating-point number.

[0209] The process by which the processor obtains the first floating-point number based on the second floating-point number, and the process by which it obtains the third floating-point number based on the fourth floating-point number, can be executed with reference to the process of obtaining the fifth floating-point number based on the calculation result described above, and will not be repeated here.

[0210] The floating-point number representation method provided in this application can be applied to lossy compression of high-precision data and the early approximate solution calculation of mixed-precision matrix solvers. For general-purpose and high-performance computing, this application can achieve higher convergence speed and accuracy of computational tasks with the same total bit width, i.e., the same data storage or data transfer overhead. For AI neural network training and inference, this application can meet the functional and accuracy requirements of neural network training and inference with the same total bit width. When the absolute value of the exponent is large, the first exponent field may not include a sign bit. Therefore, the bit width of the first mantissa field can be increased by one bit to increase numerical precision, meeting the precision requirements when the exponent of the data is large. This also matches the negatively skewed probability distribution of the exponent in AI scenarios, thereby meeting the needs of AI neural network training and inference and improving the effectiveness of floating-point numbers.

[0211] Based on the same design concept as the above-described method embodiments, this application also provides a floating-point processing device. This floating-point processing device can be applied to... Figure 1 or Figure 2 In the computing device shown, or, applied to Figure 2 In the decoder 111 shown, the floating-point processing device can be used to implement the functions of the above-described method embodiments, thus achieving the beneficial effects of the above-described method embodiments. For example... Figure 12 As shown, the floating-point processing device 1200 may include a floating-point acquisition module 1201 and a decoding module 1202.

[0212] The floating-point number acquisition module 1201 can be used to acquire a first floating-point number. The data format of the first floating-point number includes a first sign field, a bit width indicator field, a first exponent field, and a first mantissa field. The first sign field is used to represent the sign of the first floating-point number, the first exponent field is used to represent the exponent of the first floating-point number, and the first mantissa field is used to represent the mantissa of the first floating-point number. The bit width indicator field is used to indicate the bit width of the first exponent field. The absolute value of the exponent of the first floating-point number is greater than or equal to a set value, and the bit width of the first mantissa field is greater than the difference between the total bit width of the first floating-point number and the first bit width. The first bit width is the sum of the bit width of the first sign field, the bit width of the bit width indicator field, and the value of the bit width indicator field.

[0213] The decoding module 1202 can be used to decode the first floating-point number to obtain a second floating-point number. The data format of the second floating-point number includes a second sign field, a second exponent field, and a second mantissa field. The second floating-point number represents the same data as the first floating-point number.

[0214] In some embodiments, the floating-point number acquisition module 1201 can also be used to acquire a third floating-point number, the data format of which is the same as that of the first floating-point number. The absolute value of the exponent of the third floating-point number is less than a set value, and the bit width of the first mantissa field of the third floating-point number is equal to the difference between the total bit width and the bit width of the third floating-point number.

[0215] The decoding module 1202 can also be used to decode the third floating-point number to obtain the fourth floating-point number. The data format of the fourth floating-point number is the same as that of the second floating-point number, and the fourth floating-point number and the third floating-point number represent the same data.

[0216] In some embodiments, the floating-point processing device 1200 may further include a calculation module, which can be used to participate in a calculation task using a second floating-point number. In other embodiments, the calculation module may also be located in a calculation unit outside the decoder, and the floating-point processing device 1200 may transmit the second floating-point number to the calculation unit, which then uses the second floating-point number to participate in the calculation task.

[0217] It should be noted that, in some embodiments, the floating-point number acquisition module 1201 can be used to execute any step in the floating-point data processing method, and the decoding module 1202 can be used to execute any step in the floating-point data processing method. The steps implemented by the floating-point number acquisition module 1201 and the decoding module 1202 can be specified as needed. The floating-point number acquisition module 1201 and the decoding module 1202 respectively implement different steps in the floating-point data processing method to achieve all the functions of the floating-point number processing device.

[0218] In the embodiments of this application, the functional modules can be integrated into a single processor, or each module can exist physically separately, or two or more modules can be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional units.

[0219] Based on the same design concept as the above-described method embodiments, this application also provides a floating-point processing device. This floating-point processing device can be applied to... Figure 1 or Figure 2 In the computing device shown, or, applied to Figure 2 In the encoder 112 shown, the floating-point processing device can be used to implement the functions of the above-described method embodiments, thus achieving the beneficial effects of the above-described method embodiments. For example... Figure 13 As shown, the floating-point processing device 1300 may include a data acquisition module 1301 and an encoding module 1302.

[0220] The data acquisition module 1301 can be used to acquire a second floating-point number. The second floating-point number includes a second sign field, a second exponent field, and a second mantissa field. The second sign field represents the sign of the second floating-point number, the second exponent field represents the exponent of the second floating-point number, and the second mantissa field represents the mantissa of the second floating-point number. The encoding module 1302 can be used to obtain a first floating-point number based on the second sign field, the second exponent field, and the second mantissa field of the second floating-point number. The first floating-point number includes a first sign field, a bit-width indicator field, a first exponent field, and a first mantissa field. The bit-width indicator field indicates the bit width of the first exponent field. The absolute value of the first exponent field of the first floating-point number is greater than or equal to a set value, and the bit width of the first mantissa field is greater than the difference between the total bit width of the first floating-point number and the first bit width. The first bit width is the sum of the bit width of the first sign field, the bit width of the bit-width indicator field, and the value of the bit-width indicator field. The first floating-point number and the second floating-point number represent the same data.

[0221] In some embodiments, the data acquisition module 1301 can also be used to: acquire a fourth floating-point number, wherein the data format of the fourth floating-point number is the same as the data format of the second floating-point number;

[0222] The encoding module 1302 can also be used to obtain a third floating-point number based on the second sign field, second exponent field, and second mantissa field of the fourth floating-point number. The third floating-point number and the fourth floating-point number represent the same data. The data format of the third floating-point number is the same as that of the first floating-point number. The absolute value of the exponent of the third floating-point number is less than a set value. The bit width of the first mantissa field of the third floating-point number is equal to the difference between the total bit width and the bit width of the third floating-point number.

[0223] It should be noted that, in some embodiments, the data acquisition module 1301 can be used to execute any step in the floating-point data processing method, and the encoding module 1302 can be used to execute any step in the floating-point data processing method. The steps implemented by the data acquisition module 1301 and the encoding module 1302 can be specified as needed. The data acquisition module 1301 and the encoding module 1302 respectively implement different steps in the floating-point data processing method to realize all the functions of the floating-point number processing device.

[0224] In the embodiments of this application, the functional modules can be integrated into a single processor, or each module can exist physically separately, or two or more modules can be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional units.

[0225] Based on the same technical concept as the above-described method embodiments, this application also provides a computing device. This computing device may be... Figure 2 or Figure 3 Any of the computing devices shown. This computing device can be used to implement the above. Figure 7 , Figure 9 or Figure 11 The method embodiments shown can achieve the beneficial effects of the above-described method embodiments by providing the functionality of the methods described above.

[0226] In some embodiments, the structure of the computing device 1400 may be as follows: Figure 14 As shown, the system includes a processor 1401 and a memory 1402 connected to the processor 1401. The processor 1401 and the memory 1402 can be interconnected via a bus. The processor 1401 can be a general-purpose processor, such as a microprocessor, or other conventional processor. The bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc.

[0227] The memory 1402 can be used to store software programs and modules. The processor 1401 executes various functional applications and data processing of the terminal device 1400 by running the software programs and modules stored in the memory 1402, such as any floating-point number processing method provided in the embodiments of this application.

[0228] The memory 1402 may primarily include a program storage area and a data storage area. The program storage area may store the operating system, application programs of at least one application, etc.; the data storage area may be used to store user data, etc. In addition, the memory 1402 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0229] The processor 1401 in the computing device 1400 is used to run computer instructions or programs stored in the memory 1402 to perform the functions in any of the above method embodiments. In some embodiments, the processor 1401 may include one or more processing units, which may be independent devices or integrated into one or more processors. The processor 1401 may also include a controller, which can generate operation control signals according to the instruction opcode and timing signals to control the fetching and execution of instructions.

[0230] In some embodiments, the processor 1401 of the computing device 1400 may include a decoder, and the processor 1401 may be used to implement... Figure 7The floating-point number processing method shown; in other embodiments, the processor 1401 of the computing device 1400 may include an encoder, and the processor 1401 may be used to implement Figure 11 The floating-point number processing method shown; or, in other embodiments, the processor 1401 of the computing device 1400 may include a decoder and an encoder, and the processor 1401 may be used to implement Figure 9 The floating-point number processing method shown.

[0231] In one embodiment, the computing device 1400 may further include a communication module that can be used to communicate with a network device.

[0232] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the terminal device. In other embodiments of this application, the terminal device may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0233] This application also provides a chip, which can be a memory controller, such as a storage-class memory controller, and can be applied to any computing device. This chip can be used to implement the functions of the above method embodiments, and therefore can achieve the beneficial effects of the above method embodiments.

[0234] In some embodiments, the structure of the chip 1500 can be as follows: Figure 15 As shown, the system includes a processor 1501 and a power supply circuit 1502 connected to the processor 1501. The processor 1501 and the power supply circuit 1502 can be interconnected via a bus. The processor 1501 can be a digital signal processor (DSP), ASIC, field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or other specific integrated circuits. The bus can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus can be divided into address bus, data bus, control bus, etc. The power supply circuit 1502 is used to supply power to the processor 1501 via the bus.

[0235] The processor 1501 can be connected to a memory located outside the chip or to a memory located inside the chip, and run software programs and modules stored in the memory to perform various functional applications and data processing of the chip 1500, such as the floating-point number processing method provided in the embodiments of this application.

[0236] In some embodiments, the processor 1501 may include one or more processing units, which may be independent devices or integrated into one or more processors. The processor 1501 may also include a controller, which can generate operation control signals according to the instruction opcode and timing signals to control the instruction fetching and execution.

[0237] This application also provides a computer program product comprising computer-executable instructions. In one embodiment, the computer-executable instructions are used to cause a computer to perform the functions described in the method embodiments above.

[0238] Computer-executable instructions can be stored in a computer-readable storage medium. This application also provides a computer-readable storage medium storing executable instructions. In one embodiment, the computer-executable instructions are used to cause a computer to perform the functions described in the method embodiments above.

[0239] The computer-readable storage medium provided in the embodiments of this application may be random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), register, hard disk, portable hard disk, CD-ROM, or any other form of computer-readable storage medium known in the art.

[0240] Computer-executable instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video disc (DVD); or it can be a semiconductor medium, such as a solid-state drive.

[0241] In the various embodiments of this application, unless otherwise specified or logically conflicting, the terminology and / or descriptions between different embodiments are consistent and can be referenced mutually. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or device is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0242] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely illustrative examples of the solutions defined by the appended claims and are to be considered as covering any and all modifications, variations, combinations, or equivalents within the scope of this application.

[0243] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application. Therefore, if these modifications and variations of the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A floating-point number processing method, characterized in that, The method includes: Obtain a first floating-point number; the data format of the first floating-point number includes a first sign field, a bit width indicator field, a first exponent field, and a first mantissa field; the first sign field is used to represent the sign of the first floating-point number, the first exponent field is used to represent the exponent of the first floating-point number, and the first mantissa field is used to represent the mantissa of the first floating-point number; the bit width indicator field is used to indicate the bit width of the first exponent field; when the absolute value of the exponent of the first floating-point number is greater than or equal to a set value, the bit width of the first mantissa field is greater than the difference between the total bit width of the first floating-point number and the first bit width; the first bit width is the sum of the bit width of the first sign field, the bit width of the bit width indicator field, and the value of the bit width indicator field. The first floating-point number is decoded to obtain the second floating-point number; the data format of the second floating-point number includes a second sign field, a second exponent field, and a second mantissa field, and the data represented by the second floating-point number and the first floating-point number are the same.

2. The method according to claim 1, characterized in that, The method further includes: Obtain a third floating-point number; the data format of the third floating-point number is the same as that of the first floating-point number, the absolute value of the exponent of the third floating-point number is less than the set value, and the bit width of the first mantissa field of the third floating-point number is equal to the difference between the total bit width of the third floating-point number and the first bit width. The third floating-point number is decoded to obtain a fourth floating-point number; the data format of the fourth floating-point number is the same as that of the second floating-point number, and the data represented by the fourth floating-point number and the third floating-point number are the same.

3. The method according to claim 2, characterized in that, The first exponent field of the third floating-point number includes a sign bit; the sign bit is used to characterize the sign of the exponent of the third floating-point number.

4. The method according to any one of claims 1 to 3, characterized in that, The first exponent field of the first floating-point number does not contain a sign bit, and the exponent represented by the first exponent field of the first floating-point number is negative.

5. The method according to any one of claims 1 to 4, characterized in that, The value of the bit width indicator field is positively correlated with the absolute value of the exponent represented by the first exponent field.

6. The method according to any one of claims 1 to 5, characterized in that, The value of the bit width indicator field is negatively correlated with the bit width of the bit width indicator field.

7. The method according to any one of claims 1 to 6, characterized in that, The process of obtaining the first floating-point number includes: The first floating-point number can be read from memory or obtained through a communication network.

8. The method according to any one of claims 1 to 7, characterized in that, The second floating-point number is a normalized floating-point number, and the method further includes: The second floating-point number is used in the calculation task.

9. A floating-point number processing method, characterized in that, The method includes: Obtain the second floating-point number; the second floating-point number is a normalized floating-point number, and the data format adopted by the second floating-point number includes a second sign field, a second exponent field, and a second mantissa field; the second sign field is used to represent the sign of the second floating-point number, the second exponent field is used to represent the exponent of the second floating-point number, and the second mantissa field is used to represent the mantissa of the second floating-point number; A first floating-point number is obtained based on the second sign field, the second exponent field, and the second mantissa field. The data format of the first floating-point number includes a first sign field, a bit width indicator field, a first exponent field, and a first mantissa field. The bit width indicator field is used to indicate the bit width of the first exponent field. The absolute value of the first exponent field of the first floating-point number is greater than or equal to a set value, and the bit width of the first mantissa field is greater than the difference between the total bit width and the first bit width of the first floating-point number. The first bit width is the sum of the bit width of the first sign field, the bit width of the bit width indicator field, and the value of the bit width indicator field. The first floating-point number and the second floating-point number represent the same data.

10. The method according to claim 9, characterized in that, The method further includes: Obtain the fourth floating-point number; the data format of the fourth floating-point number is the same as the data format of the second floating-point number; A third floating-point number is obtained based on the second sign field, the second exponent field, and the second mantissa field of the fourth floating-point number; the third floating-point number and the fourth floating-point number represent the same data; the data format of the third floating-point number is the same as that of the first floating-point number; the absolute value of the exponent of the third floating-point number is less than the set value; and the bit width of the first mantissa field of the third floating-point number is equal to the difference between the total bit width of the third floating-point number and the first bit width.

11. The method according to claim 10, characterized in that, The first exponent field of the third floating-point number includes a sign bit; the sign bit is used to characterize the sign of the exponent of the third floating-point number.

12. The method according to any one of claims 9 to 11, characterized in that, The first exponent field of the first floating-point number does not contain a sign bit, and the exponent represented by the first exponent field of the first floating-point number is negative.

13. A floating-point processing device, characterized in that, The device includes: A floating-point number acquisition module is used to acquire a first floating-point number. The data format of the first floating-point number includes a first sign field, a bit width indicator field, a first exponent field, and a first mantissa field. The first sign field is used to represent the sign of the first floating-point number, the first exponent field is used to represent the exponent of the first floating-point number, and the first mantissa field is used to represent the mantissa of the first floating-point number. The bit width indicator field is used to indicate the bit width of the first exponent field. When the absolute value of the exponent of the first floating-point number is greater than or equal to a set value, the bit width of the first mantissa field is greater than the difference between the total bit width of the first floating-point number and the first bit width. The first bit width is the sum of the bit width of the first sign field, the bit width of the bit width indicator field, and the value of the bit width indicator field. The decoding module is used to decode the first floating-point number to obtain a second floating-point number. The data format of the second floating-point number includes a second sign field, a second exponent field, and a second mantissa field. The data represented by the second floating-point number and the first floating-point number are the same.

14. The apparatus according to claim 13, characterized in that, The second floating-point number is a normalized floating-point number, and the device further includes a calculation module, which is used to: use the second floating-point number to participate in the calculation task.

15. A floating-point processing device, characterized in that, The device includes: The data acquisition module is used to acquire a second floating-point number; the second floating-point number is a normalized floating-point number, and the data format adopted by the second floating-point number includes a second sign field, a second exponent field, and a second mantissa field; the second sign field is used to represent the sign of the second floating-point number, the second exponent field is used to represent the exponent of the second floating-point number, and the second mantissa field is used to represent the mantissa of the second floating-point number. An encoding module is used to obtain a first floating-point number based on the second sign field, the second exponent field, and the second mantissa field. The data format of the first floating-point number includes a first sign field, a bit width indicator field, a first exponent field, and a first mantissa field. The bit width indicator field is used to indicate the bit width of the first exponent field. When the absolute value of the first exponent field of the first floating-point number is greater than or equal to a set value, the bit width of the first mantissa field is greater than the difference between the total bit width and the first bit width of the first floating-point number. The first bit width is the sum of the bit width of the first sign field, the bit width of the bit width indicator field, and the value of the bit width indicator field. The first floating-point number and the second floating-point number represent the same data.

16. The apparatus according to claim 15, characterized in that, The first exponent field of the first floating-point number does not contain a sign bit, and the exponent represented by the first exponent field of the first floating-point number is negative.

17. A computing device, characterized in that, It includes a processor and a memory; the memory stores computer programs. The processor is configured to read the computer program stored in the memory and execute the method of any one of claims 1 to 8, or execute the method of any one of claims 9 to 12.

18. A chip, characterized in that, It includes a processor and a power supply circuit; the power supply circuit is used to supply power to the processor, and the processor is used to execute a computer program to implement the method as described in any one of claims 1 to 8; or, the method as described in any one of claims 9 to 12.

19. A computer-readable storage medium, characterized in that, The device stores computer-executable instructions for causing a computer to perform the method as described in any one of claims 1 to 8; or the method as described in any one of claims 9 to 12.

20. A computer program product, characterized in that, It includes computer-executable instructions for causing a computer to perform the method as described in any one of claims 1 to 8; or, the method as described in any one of claims 9 to 12.

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