A pointer allocation device for a linked list, a linked list structure product and a chip
By constructing a three-level pointer management architecture, the problem of high hardware resource consumption and difficult timing convergence caused by the complexity of logic in traditional linked lists is solved, achieving efficient pointer allocation and resource optimization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN JAGUAR MICROSYSTEMS CO LTD
- Filing Date
- 2026-04-08
- Publication Date
- 2026-06-26
AI Technical Summary
Traditional linked lists based on large-capacity FIFOs have excessive hardware resource consumption, and linked lists based on bitmaps have complex logic that makes timing convergence difficult.
A three-level pointer management architecture is adopted, including a first-level FIFO module, a second-level cache module, and a third-level storage module. The pointer usage status information is automatically transferred between the modules through the pointer control logic module, so as to achieve efficient scheduling and resource optimization.
It effectively reduces hardware resource consumption, simplifies hardware logic, ensures high throughput and timing convergence of linked list operations, and solves the problem of excessive resource consumption in traditional solutions.
Smart Images
Figure CN121996429B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of linked list technology, specifically to a pointer allocation device for a linked list, a linked list structure product, and a chip. Background Technology
[0002] Linked lists use pointers to connect scattered memory nodes. They achieve ordered storage and non-contiguous access to data through head and tail pointers and successor pointers between nodes. The use of pointers includes allocating a null pointer to attach a new node when writing data, and removing the head node pointer and releasing resources when reading data.
[0003] The linked lists currently used in hardware design mainly fall into the following two categories:
[0004] Linked lists are implemented using large-capacity FIFOs. FIFOs (First In First Out) are typically composed of registers or RAM. Specifically, linked lists based on large-capacity FIFOs use a FIFO queue to store all available pointers. All child linked lists share this FIFO queue. The depth of the FIFO is proportional to the number of pointers (or nodes) supported by the linked list. For example, to support 4k nodes, a FIFO with a depth of 4k is required. The advantages of large-capacity FIFO-based schemes are simple logic and easy timing convergence. However, due to the large depth of the FIFO queue, it will occupy a large amount of register or RAM resources (hence the name "large-capacity FIFO"), resulting in large chip area overhead and being detrimental to chip design.
[0005] Linked lists implemented using bitmaps consist of multiple bits. Specifically, a bitmap-based linked list uses a bitmap to record the usage status of each pointer, with each bit corresponding to a pointer. 0 indicates that the pointer is available, and 1 indicates that the pointer is occupied. The advantage of the bitmap-based approach is relatively low resource consumption, but the logic for finding and releasing pointers is complex, requiring traversal of the bitmap to find null pointers. This results in a long timing path after synthesis and difficulty in timing convergence. Furthermore, its performance is poor, making it unable to achieve high-throughput pat-a-pat processing (i.e., processing one request per clock cycle), and it is not suitable for high-concurrency scenarios.
[0006] Therefore, how to solve the technical problems of excessive hardware resource consumption in traditional linked list implementations based on large-capacity FIFOs and the difficulty in timing convergence due to the logical complexity of linked lists based on bitmaps has become an urgent need in the current hardware design field. Summary of the Invention
[0007] The purpose of this application is to propose a pointer allocation device, a linked list structure, and a chip for linked lists, so as to reduce the hardware resources of linked lists and simplify the hardware logic of linked lists, and solve the technical problems of excessive hardware resource consumption of traditional linked lists based on large-capacity FIFO and the difficulty in timing convergence due to the complex logic of linked lists based on bitmap.
[0008] To achieve the above objectives, according to the first aspect of this application, a pointer allocation device for a linked list is proposed, comprising a first-level FIFO module, a second-level cache module, a third-level storage module, and a pointer control logic module;
[0009] The first-level FIFO module is used to store null pointers; wherein, the null pointer is the address of a free storage unit in the storage entity storing linked list data; the storage entity includes multiple storage units;
[0010] The second-level cache module is used to store the first usage status information of pointers corresponding to some storage units of the storage entity; wherein, the first usage status information includes unused and used;
[0011] The third-level storage module is used to store the second usage status information of the pointers corresponding to all storage units of the storage entity; wherein, the second usage status information includes unused and used, the storage capacity of the third-level storage module is greater than the storage capacity of the second-level cache module, and the storage capacity of the second-level cache module is greater than the storage capacity of the first-level FIFO module.
[0012] The pointer control logic module is used to obtain a target null pointer based on the first usage status information stored in the second-level cache module when the number of null pointers in the first-level FIFO module is less than a preset threshold, write the target null pointer into the first-level FIFO module, and update the corresponding first usage status information in the second-level cache module.
[0013] The pointer control logic module is further configured to, when detecting that the first usage status information in the second-level cache module meets the preset conditions, obtain a set of second usage status information based on the second usage status information stored in the third-level storage module, and write the set of second usage status information as a new set of first usage status information into the second-level cache module; wherein, the preset conditions indicate that a set of first usage status information needs to be added to the second-level cache module.
[0014] In one possible implementation, in the second-level cache module, when the storage unit corresponding to any pointer is free and the pointer has been written to the first-level FIFO module, or when the storage unit corresponding to any pointer is not free, the first usage status information of the pointer is set to used; otherwise, the first usage status information of the pointer is set to unused.
[0015] The pointer control logic module is specifically used to obtain a target null pointer based on the first usage status information of the pointers in the second-level cache module when the number of null pointers in the first-level FIFO module is less than a preset threshold, write the target null pointer into the first-level FIFO module, and update the first usage status information of the target null pointer in the second-level cache module to "used".
[0016] In one possible implementation, the second-level cache module includes multiple cache lines, each cache line including multiple first usage status information, and the third-level storage module includes multiple groups, each group including multiple second usage status information.
[0017] In the third-level storage module, when the storage unit corresponding to any pointer is idle and the group to which any pointer belongs has not been prefetched to the second-level cache module, or when any pointer has been released and its status has been flushed, the second usage status information of any pointer is set to unused; when the group to which any pointer belongs has been prefetched to the second-level cache module and the first usage status information in the cache line corresponding to that group is all used, the second usage status information of any pointer is set to used.
[0018] The pointer control logic module is specifically used to obtain a set of second usage status information based on the second usage status information in the third-level storage module when it is detected that the first usage status information of any cache line in the second-level cache module is used, and to flush the set of second usage status information as a new set of first usage status information to any cache line, wherein at least one of the second usage status information in the set of second usage status information is unused.
[0019] In one possible implementation, the second-level cache module includes a plurality of first status bits, each first status bit being used to store a first usage status information;
[0020] The pointer control logic module is specifically used to update the first mapping relationship between each first status bit and the pointer in any cache line after the set of second usage status information is written to any cache line as a new set of first usage status information.
[0021] The pointer control logic module is specifically used to obtain the target null pointer based on the first usage status information of the pointer in the second-level cache module and the first mapping relationship.
[0022] In one possible implementation, the pointer control logic module is further configured to update the second mapping relationship between the line number of any cache line and the group number corresponding to the set of second usage status information after the set of second usage status information is flushed to any cache line as a new set of first usage status information;
[0023] The pointer control logic module is further configured to, when it is detected that all first usage status information of any cache line in the second-level cache module is used, obtain the corresponding target group number according to the line number of any cache line and the second mapping relationship, and update all second usage status information of a group corresponding to the target group number in the third-level storage module to be used.
[0024] In one possible implementation, the first-level FIFO module includes multiple queue units, each queue unit being used to store a null pointer; each group of the third-level storage module includes multiple second status bits, each second status bit being used to store a second usage status information.
[0025] The number of second status bits in each group of the third-level storage module is the same as the number of queue units in the first-level FIFO module and the number of first status bits in each cache line of the second-level cache module.
[0026] In one possible implementation, the pointer control logic module is specifically used to determine whether the number of null pointers in the first-level FIFO module is less than the preset threshold when the data of the storage unit corresponding to the head pointer of the linked list is read out. If so, the head pointer is written into the first-level FIFO module; if not, a second usage status information corresponding to the head pointer in the third-level storage module is updated to unused.
[0027] In one possible implementation, the pointer control logic module is specifically used to, when the number of null pointers in the first-level FIFO module is less than a preset threshold, preferentially write the currently released head pointer of the linked list as the target null pointer into the first-level FIFO module. If, after writing the currently released head pointer of the linked list into the first-level FIFO module, the number of null pointers in the first-level FIFO module is still less than the preset threshold, then the target null pointer is further obtained according to the pointer usage status information stored in the second-level cache module, and the target null pointer is written into the first-level FIFO module until the number of null pointers in the first-level FIFO module is equal to the preset threshold.
[0028] In one possible implementation, the pointer control logic module is specifically configured to, upon receiving a write request, if the first-level FIFO module is empty and all first usage status information in the second-level cache module is used, then pause the response to the write request; otherwise, respond to the write request, obtain a null pointer from the first-level FIFO module, and output it.
[0029] According to a second aspect of this application, a linked list structure product is proposed, the linked list structure including a head pointer entity, a tail pointer entity, a storage entity, a pointer entity, a read control logic module, and a pointer allocation device as described in the first aspect of this application;
[0030] The head pointer entity is used to store the head pointer of the linked list;
[0031] The tail pointer entity is used to store the tail pointer of the linked list;
[0032] The storage entity is used to store the linked list data;
[0033] The pointer entity is used to store the pointing relationship between pointers;
[0034] The read control logic module is used to receive write requests, write the data carried by the write request into the storage unit corresponding to the null pointer according to the null pointer output by the pointer allocation device in response to the write request, and update the pointing relationship between corresponding pointers in the pointer entity and the tail pointer of the linked list.
[0035] In one possible implementation, the read control logic module is further configured to receive a read request, locate the head pointer entity to obtain a head pointer based on the read request, read data from the corresponding storage unit in the storage entity based on the head pointer, and update the head pointer of the linked list.
[0036] According to a third aspect of this application, a chip is provided, including a pointer allocation device as described in the first aspect of this application, or a linked list structure product as described in the second aspect of this application.
[0037] The pointer allocation device, linked list structure product, and chip proposed in this application have at least the following beneficial effects:
[0038] This application constructs a three-level pointer management architecture comprising a first-level FIFO module, a second-level cache module, and a third-level storage module. This architecture achieves efficient scheduling of pointer usage status information. Specifically, on one hand, the first-level FIFO module stores a small number of null pointers, enabling it to respond to write requests with extremely low logical latency, ensuring high throughput for linked list operations and overcoming the timing convergence problem of traditional bitmap schemes. On the other hand, the second-level cache module acts as an intermediate buffer, storing the first usage status information of pointers corresponding to some storage units of the storage entity. The third-level storage module centrally manages the second usage status information of pointers corresponding to all storage units of the storage entity. When resources in the second-level cache module are insufficient, the pointer control logic module can batch-obtain pointer resources from the third-level storage module and write them into the second-level cache module. When the number of null pointers in the first-level FIFO module is insufficient, the first usage status information of the second-level cache module can be used to supplement null pointers in the first-level FIFO module, avoiding accessing the underlying storage every time. This effectively balances access speed and resource overhead, solving the problem of excessive hardware resource consumption in traditional large-capacity FIFO schemes. In addition, the pointer control logic module automatically transfers pointer usage status information between storage modules at all levels through a threshold detection mechanism and a preset condition triggering mechanism, which ensures the real-time allocation of pointers while optimizing the configuration of hardware resources and simplifying logic.
[0039] Other features and advantages of this application will be set forth in the following description. Attached Figure Description
[0040] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings required in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0041] Figure 1 This is a schematic diagram of a pointer allocation device for a linked list in one embodiment of this application.
[0042] Figure 2 This is a schematic diagram of a linked list structure in one embodiment of this application.
[0043] Marked in the image:
[0044] 1-Linked list pointer allocation device; 11-First-level FIFO module; 12-Second-level cache module; 13-Third-level storage module; 14-Pointer control logic module; 2-Head pointer entity; 3-Tail pointer entity; 4-Storage entity; 5-Pointer entity; 6-Read control logic module. Detailed Implementation
[0045] The detailed description of the accompanying drawings is intended to illustrate the present preferred embodiments of this application and is not intended to represent only the forms in which this application can be implemented. It should be understood that the same or equivalent functions can be achieved by different embodiments intended to be included within the spirit and scope of this application.
[0046] Please see Figure 1 One embodiment of this application proposes a pointer allocation device for a linked list, including a first-level FIFO module, a second-level cache module, a third-level storage module, and a pointer control logic module;
[0047] The first-level FIFO module is used to store null pointers; wherein, the null pointer is the address of a free storage unit in the storage entity storing linked list data; the storage entity includes multiple storage units;
[0048] Specifically, the first-level FIFO module is a first-in-first-out hardware queue structure, and its depth (i.e., storage capacity) is much smaller than the total number of pointers supported by the system. For example, if the system supports 4096 nodes, the traditional solution needs to build a FIFO with a depth of 4096, while in this embodiment, the depth of the first-level FIFO module can be configured to 64 or 128. The null pointers stored in the first-level FIFO module directly point to free storage units in the storage entity (such as RAM or register array); the storage entity is divided into multiple independent storage units, each with a unique physical address, i.e., a pointer value; the first-level FIFO module responds to the dequeue operation when writing a request and the enqueue operation when releasing a pointer through its read port and write port, respectively, to realize the acquisition and recycling of null pointers, thereby avoiding the timing delay caused by traversal search.
[0049] The second-level cache module is used to store the first usage status information of pointers corresponding to some storage units of the storage entity; wherein, the first usage status information includes unused and used;
[0050] Specifically, the second-level cache module acts as a fast buffer for pointer resources. Its storage access speed falls between that of the first-level FIFO module (e.g., registers or SRAM) and the third-level storage module (e.g., high-capacity DRAM or low-speed RAM). The second-level cache module does not directly store the physical address values of the pointers; instead, it stores the pointer's initial usage status information. The storage capacity of the third-level storage module is greater than that of the second-level cache module, and the storage capacity of the second-level cache module is greater than that of the first-level FIFO module. In one example, the second-level cache module can be implemented using SRAM, organized into several cache lines. Each cache line records the status information of a set of pointers. When the resources of the first-level FIFO module are insufficient, the pointer control logic module can quickly retrieve available pointer addresses from the second-level cache module and fill them into the first-level FIFO module in a batch processing manner. This process does not require access to the low-speed third-level storage module, thus ensuring the system's real-time response capability.
[0051] The third-level storage module is used to store the second usage status information of the pointers corresponding to all storage units of the storage entity; wherein, the second usage status information includes unused and used; the storage capacity of the third-level storage module is greater than the storage capacity of the second-level cache module, and the storage capacity of the second-level cache module is greater than the storage capacity of the first-level FIFO module.
[0052] Specifically, the third-level storage module is the global management unit for system pointer resources. Its capacity covers the total number of pointers N supported by the system (e.g., N=4096). The third-level storage module stores the status information of all pointers, for example, in the form of a bitmap or a status bit array. In a specific example, the third-level storage module is divided into multiple groups, each containing a preset number of pointer status information. Because the third-level storage module stores a large amount of data, it usually uses highly integrated but high-latency storage media, such as external DRAM or on-chip high-capacity Block RAM. The main function of the third-level storage module is to provide batch backups of pointer resources to the second-level cache module during system initialization or when the resources of the second-level cache module are exhausted.
[0053] The pointer control logic module is used to obtain a target null pointer based on the first usage status information stored in the second-level cache module when the number of null pointers in the first-level FIFO module is less than a preset threshold, write the target null pointer into the first-level FIFO module, and update the corresponding first usage status information in the second-level cache module.
[0054] Specifically, the pointer control logic module internally maintains the read and write pointers of the first-level FIFO module. When external logic (such as the read control logic module) initiates a write request, the pointer control logic module checks the empty / full status of the first-level FIFO module. If the first-level FIFO module is not empty, the pointer control logic module immediately triggers a read operation, reads a null pointer from the head of the queue of the first-level FIFO module and outputs it to the external logic, enabling the external logic to write data into the memory unit corresponding to the null pointer. This process is a pure combinational logic or single-cycle register operation, without complex traversal or arbitration logic, which can meet the high-throughput pat-to-pat processing requirements.
[0055] The pointer control logic module monitors the fill counter value of the first-level FIFO module in real time. The preset threshold is a value pre-configured based on the depth of the first-level FIFO module and the system bandwidth requirements, for example, set to 1 / 4 or 1 / 2 of the FIFO depth. When the count value falls below the preset threshold, a pointer replenishment mechanism is triggered. The pointer control logic module analyzes the first usage status information stored in the second-level cache module, identifies target null pointers that can be written to the first-level FIFO module, calculates their physical addresses based on the first usage status information of the target null pointers, and pushes the physical address to the tail of the queue in the first-level FIFO module. At the same time, the pointer control logic module modifies the first usage status information of the corresponding target null pointers in the second-level cache module, for example, marking them as used to prevent duplicate allocation, thereby realizing on-demand scheduling of pointer resources, ensuring that the first-level FIFO module always maintains a certain level, and avoiding blocking write requests due to an empty FIFO.
[0056] The pointer control logic module is further configured to, when detecting that the first usage status information in the second-level cache module meets the preset conditions, obtain a set of second usage status information based on the second usage status information stored in the third-level storage module, and write the set of second usage status information as a new set of first usage status information into the second-level cache module; wherein, the preset conditions indicate that a set of first usage status information needs to be added to the second-level cache module.
[0057] Specifically, the preset conditions include, for example, the number of pointers in the second-level cache module that are not written to the first-level FIFO module being lower than a preset threshold; or, for example, all first usage status information of at least one cache line in the second-level cache module being marked as used. When the preset conditions are met, the pointer control logic module initiates access to the third-level storage module. Due to the large access latency of the third-level storage module, a batch read strategy is adopted. The pointer control logic module reads a set of second usage status information of pointers from the third-level storage module, and this set of second usage status information contains at least one unused pointer. Subsequently, the pointer control logic module overwrites the corresponding position in the second-level cache module with this set of second usage status information as a new set of first usage status information. The hierarchical loading mechanism of this embodiment effectively hides the latency of accessing slow-speed memory and balances resource overhead and access speed.
[0058] In some embodiments, in the second-level cache module, when the storage unit corresponding to any pointer is idle and the pointer has been written to the first-level FIFO module, or when the storage unit corresponding to any pointer is not idle, the first usage status information of the pointer is set to used; otherwise, the first usage status information of the pointer is set to unused.
[0059] Specifically, the first usage status information can be implemented using a register with a one-bit width, where a logical "1" indicates that it is used and a logical "0" indicates that it is not used. The "used" status includes two situations: one is that the physical resource is occupied, that is, the memory unit corresponding to the pointer has been written with valid data, and the pointer is obviously not allocable; the other is that the logical resource is occupied, that is, although the physical memory unit is free, the pointer has been extracted and written to the first-level FIFO module to wait for allocation. In order to avoid duplicate allocation, it needs to be marked as used. Correspondingly, the "unused" state indicates that the storage unit corresponding to the pointer is idle and has not yet been prefetched into the first-level FIFO module, and is a currently available candidate null pointer. For example, suppose a cache line manages the states P0 to P7 of 8 pointers. In the initial state, if the storage units pointed to by these 8 pointers are all idle, the first usage state information is "0". When the pointer control logic extracts pointer P0 into the first-level FIFO module, the first usage state information of P0 is flipped to "1". If the external logic subsequently writes data to the storage unit pointed to by P0, P0 still remains in the "1" state. The definition of the first usage state information in this embodiment allows the pointer control logic to quickly lock the null pointer by only reading the state bit of the second-level cache module, without having to query the state of the underlying storage entity, which greatly simplifies the logic hierarchy.
[0060] The pointer control logic module is specifically used to obtain a target null pointer based on the first usage status information of the pointers in the second-level cache module when the number of null pointers in the first-level FIFO module is less than a preset threshold, write the target null pointer into the first-level FIFO module, and update the first usage status information of the target null pointer in the second-level cache module to "used".
[0061] Specifically, the pointer control logic module compares the fill counter value of the first-level FIFO module with the value of the preset threshold register in real time. When the fill counter of the first-level FIFO module falls below the preset threshold (e.g., half the FIFO depth), pointer replenishment is triggered. First, the first usage status information of each cache line in the second-level cache module is read, and the bits with the first usage status information of "unused" are retrieved from the currently valid cache lines. Once the target null pointer is located, a double write operation is performed: on the one hand, based on the cache line number and the offset of the target null pointer's status bit within the cache line, the physical address value corresponding to the target null pointer is obtained, and this physical address value is pushed to the tail of the queue of the first-level FIFO module; on the other hand, a write operation is initiated to the second-level cache module to update the first usage status information corresponding to the target null pointer to "used," thereby locking the resource and preventing it from being allocated repeatedly.
[0062] For example, assuming a preset threshold of 64, the number of null pointers currently stored in the first-level FIFO module drops to 32, and the pointer control logic module detects that the preset condition is met. If at this time there is a cache line in the second-level cache module, and the first usage status information of the 8 pointers recorded inside is [1, 0, 1, 1, 0, 0, 1, 0] (where 1 represents used and 0 represents unused), the pointer control logic module selects the first 0 status bit as the target through logical judgment, and parses the specific physical pointer value (such as Addr_X) according to the position index of the status bit in the cache line and the pointer base address corresponding to the cache line. Addr_X is written into the first-level FIFO module, and the status of the cache line is updated to [1, 1, 1, 1, 0, 0, 1, 0], thereby ensuring that the water level of the first-level FIFO module is quickly restored. Moreover, the logic path only involves the query of status bits and simple address calculation, without complex traversal logic, ensuring timing convergence.
[0063] In some embodiments, the second-level cache module includes multiple cache lines, each cache line including multiple first usage status information, and the third-level storage module includes multiple groups, each group including multiple second usage status information;
[0064] In the third-level storage module, when the storage unit corresponding to any pointer is idle and the group to which any pointer belongs has not been prefetched to the second-level cache module, or when any pointer has been released and its status has been flushed, the second usage status information of any pointer is set to unused; when the group to which any pointer belongs has been prefetched to the second-level cache module and the first usage status information in the cache line corresponding to that group is all used, the second usage status information of any pointer is set to used.
[0065] Specifically, the third-level storage module, acting as a global pointer resource pool, typically has a higher access latency than the second-level cache module, but its storage capacity covers all N nodes supported by the system. The second usage status information is used to identify pointer occupancy globally, and its updates strictly follow the resource flow rules between the second-level cache module and the first-level FIFO module. In one example, to reduce the read / write power consumption of the third-level storage module, when a pointer is written from the second-level cache module to the first-level FIFO module, the status in the third-level storage module is not updated. Only when all the first usage status information of a cache line in the second-level cache module is marked as "used" and new pointer usage status information needs to be loaded from the third-level storage module is a flush operation of a set of second usage status information in the third-level storage module triggered, effectively reducing the access frequency to the large-capacity third-level storage module.
[0066] The pointer control logic module is specifically used to obtain a set of second usage status information based on the second usage status information in the third-level storage module when it is detected that the first usage status information of any cache line in the second-level cache module is used, and to flush the set of second usage status information as a new set of first usage status information to any cache line, wherein at least one of the second usage status information in the set of second usage status information is unused.
[0067] Specifically, when a cache line triggers a resource shortage condition (e.g., all lines are in use), the pointer control logic module determines a set of second usage status information that can be written to any cache line based on the second usage status information in the third-level storage module. Since pointers are released and reclaimed during use, the corresponding second usage status information in the third cache module is updated to "unused." Therefore, in any group within the third cache module, some second usage status information may be "unused." The pointer control logic module obtains this set of statuses and flushes it to the cache line, completing resource replenishment. For example, if the third-level storage module is divided into 512 groups, each containing 8 pointer states, when the Kth row of the second-level cache module is exhausted, the pointer control logic module determines that the group number to be loaded is M based on the polling algorithm and the second usage status information in the third storage module. Subsequently, the pointer control logic module obtains the 8 pointer states contained in group M. Assuming the group state is [0, 0, 1, 0, 1, 1, 0, 1], where 5 bits are "unused" (0), the pointer control logic module directly writes this state vector to the Kth row. After that, the Kth row can again provide null pointers to the first-level FIFO module.
[0068] In some embodiments, the second-level cache module includes a plurality of first status bits, each first status bit being used to store a first usage status information;
[0069] The pointer control logic module is specifically used to update the first mapping relationship between each first status bit and the pointer in any cache line after the set of second usage status information is written to any cache line as a new set of first usage status information.
[0070] Specifically, the first mapping relationship defines the correspondence between each status bit in each cache line of the second-level cache module and the physical pointer address. Since a set of second usage status information in the third-level storage module corresponds to a continuous or fixed pointer address space, when a set of second usage status information is flushed to the cache line of the second-level cache module, a mapping between each first usage status information in the cache line and the physical address can be established. This first mapping relationship can be recorded in a table, and the index of each status bit in each cache line can be determined by adding the base address corresponding to the line number of the cache line to the offset of the status bit in the cache line.
[0071] The pointer control logic module is specifically used to obtain the target null pointer based on the first usage status information of the pointer in the second-level cache module and the first mapping relationship.
[0072] Specifically, in one embodiment, assume the pointer control logic module detects that the first usage status information stored in the i-th status bit of cache line K is "unused" (e.g., logic 0), and the pointer base address currently mapped to this cache line is Base_Addr. The address generation unit inside the pointer control logic module obtains the physical address Target_Addr of the target null pointer based on the first mapping relationship. Subsequently, the pointer control logic module pushes this Target_Addr into the write port of the first-level FIFO module. Simultaneously, the value of the i-th status bit in cache line K is updated to "used," significantly shortening the timing delay of the critical path.
[0073] In some embodiments, the pointer control logic module is further configured to update the second mapping relationship between the line number of any cache line and the group number corresponding to the set of second usage status information after the set of second usage status information is flushed to any cache line as a new set of first usage status information;
[0074] Specifically, the second mapping relationship is used to maintain the address mapping consistency between the second-level cache module and the third-level storage module. This second mapping relationship can be implemented by maintaining a mapping table stored in the register array within the pointer control logic module, recording the group number of the third-level storage module corresponding to each cache line. This mechanism ensures that when the status bit of cache line K is subsequently read, the physical pointer corresponding to that status bit can be deduced based on this second mapping relationship, thus guaranteeing the correctness of pointer addressing in a multi-level storage architecture.
[0075] The pointer control logic module is further configured to, when it is detected that all first usage status information of any cache line in the second-level cache module is used, obtain the corresponding target group number according to the line number of any cache line and the second mapping relationship, and update all second usage status information of a group corresponding to the target group number in the third-level storage module to be used.
[0076] Specifically, when the pointer control logic module detects that all first usage status information of cache line K is "used," it indicates that all pointer resources previously mapped to this cache line have been allocated to the first-level FIFO module. At this time, the pointer control logic module performs a write-back operation. The pointer control logic module looks up the mapping table to determine the target group number currently mapped to cache line K, assuming it is M_old. Since all first usage status information of cache line K is currently "used," meaning that the physical pointer resources corresponding to group M_old have also been allocated and occupied at the system level, the pointer control logic module initiates a write request to the third-level storage module to forcibly update each second usage status information corresponding to group M_old to "used." This completes the batch synchronization of resource status from the second-level cache to the third-level storage, and also helps to reduce the frequency of status update accesses to the third-level storage module.
[0077] In some embodiments, the first-level FIFO module includes multiple queue units, each queue unit being used to store a null pointer; each group of the third-level storage module includes multiple second status bits, each second status bit being used to store a second usage status information.
[0078] The number of second status bits in each group of the third-level storage module is the same as the number of queue units in the first-level FIFO module and the number of first status bits in each cache line of the second-level cache module.
[0079] Specifically, setting the number of basic units in each level of storage module to be the same aims to achieve batch pipelined scheduling of pointer resources and simplify cross-level data interaction logic. For example, the depth of the first-level FIFO module is configured as W, the bit width of each cache line in the second-level cache module is W bits, and each group in the third-level storage module contains W status bits. When a cache line in the second-level cache module is exhausted, the pointer control logic module can read a set of status information with a width of W from the third-level storage module at once to fill the entire line. This width-aligned architecture eliminates the splicing logic of data bit width conversion between different levels, greatly improving the regularity of hardware implementation and the timing performance of logic synthesis.
[0080] In some embodiments, the pointer control logic module is specifically used to determine whether the number of null pointers in the first-level FIFO module is less than the preset threshold when the data of the storage unit corresponding to the head pointer of the linked list is read out. If so, the head pointer is written into the first-level FIFO module; if not, a second usage status information corresponding to the head pointer in the third-level storage module is updated to unused.
[0081] Specifically, when the read control logic module performs a linked list data read operation, the physical storage unit that originally stored the data is released. The pointer control logic module has two paths for reclaiming this resource: if the first-level FIFO module urgently needs resources (the amount is less than a preset threshold), then the head pointer is directly written to the first-level FIFO module; if the first-level FIFO module has sufficient resources, then the corresponding second usage status information in the third-level storage module is directly updated to unused, realizing global resource reclamation and avoiding first-level FIFO overflow.
[0082] In some embodiments, the pointer control logic module is specifically used to, when the number of null pointers in the first-level FIFO module is less than a preset threshold, preferentially write the currently released head pointer of the linked list as the target null pointer into the first-level FIFO module; if, after writing the currently released head pointer of the linked list into the first-level FIFO module, the number of null pointers in the first-level FIFO module is still less than the preset threshold, then further obtain the target null pointer according to the pointer usage status information stored in the second-level cache module, and write the target null pointer into the first-level FIFO module, until the number of null pointers in the first-level FIFO module is equal to the preset threshold.
[0083] Specifically, this embodiment proposes a priority-based replenishment strategy. The released pointer has the lowest acquisition latency and therefore has the highest replenishment priority. Read operations on the second-level cache module are only triggered when there is insufficient released resources, effectively reducing the system's average power consumption and the frequency of access to the second-level cache module.
[0084] In some embodiments, the pointer control logic module is specifically used to, upon receiving a write request, if the first-level FIFO module is empty and all first usage status information in the second-level cache module is used, then pause responding to the write request; otherwise, respond to the write request, obtain a null pointer from the first-level FIFO module and output it.
[0085] Specifically, this embodiment defines a backpressure mechanism for the pointer allocation device to protect the stability of the system under extreme resource scarcity conditions and prevent the risk of data overwriting or system deadlock when no pointers are available.
[0086] See Figure 2 Another embodiment of this application proposes a linked list structure product, the linked list structure including a head pointer entity, a tail pointer entity, a storage entity, a pointer entity, a read control logic module, and a pointer allocation device as described in the above embodiments of this application;
[0087] The head pointer entity is used to store the head pointer of the linked list;
[0088] Specifically, the head pointer entity is composed of registers that store the physical address of the first node of the current linked list. When the linked list is initialized, the head pointer is set to NULL. When data is written to the linked list and the linked list is empty, the head pointer entity is updated to the address of the new node. When the head node is read out, the head pointer entity is updated to the address of the next node after the original head node.
[0089] The tail pointer entity is used to store the tail pointer of the linked list;
[0090] Specifically, the tail pointer entity is also composed of registers, storing the physical address of the current last node of the linked list. During a write operation, a newly allocated null pointer is attached after the tail pointer, that is, the address of the new node is written into the pointer entity corresponding to the tail pointer, and then the tail pointer entity is updated to the address of the new node.
[0091] The storage entity is used to store the linked list data;
[0092] Specifically, the storage entity is the data storage medium, typically implemented using dual-port RAM or multi-port RAM to support simultaneous read and write access. The storage entity is divided into multiple fixed-length storage units, each storing one data node, and each unit is addressed by a pointer index. For example, after receiving write data and a write address (null pointer), the storage entity stores the data in the corresponding unit; upon receiving a read address (head pointer), it outputs the data from the corresponding unit.
[0093] The pointer entity is used to store the pointing relationship between pointers;
[0094] Specifically, the pointer entity records the successor relationship of the linked list nodes. Its structure is similar to that of the storage entity, which is usually a RAM array. The pointer units in the pointer entity correspond one-to-one with the storage units in the storage entity.
[0095] The read control logic module is used to receive a write request, write the data carried by the write request into the storage unit corresponding to the null pointer according to the null pointer output by the pointer allocation device in response to the write request, and update the pointing relationship between corresponding pointers in the pointer entity and the tail pointer of the linked list.
[0096] Specifically, the read control logic module is the scheduling center for linked list operations. During the write operation phase, its workflow is as follows: First, it initiates a null pointer request to the pointer allocation device; after receiving the allocated null pointer, it uses the null pointer as the write address and writes the data payload in the write request to the corresponding position of the storage entity; at the same time, it reads the current tail pointer register and writes the null pointer value to the tail pointer address of the pointer entity; finally, it updates the tail pointer register to the newly allocated null pointer value.
[0097] The read control logic module is also used to receive read requests, find the head pointer entity to obtain the head pointer according to the read request, read the data of the corresponding storage unit from the storage entity according to the head pointer, and update the head pointer of the linked list.
[0098] Specifically, during the read operation phase, the read control logic module performs a dequeue operation: it reads the value of the head pointer register as the current access address; it uses this address to read the data node from the storage entity; simultaneously, it uses this address to read the address of the next node from the pointer entity; and it updates the head pointer register with the read next node address, completing the head pointer shift. Furthermore, the control logic also needs to send a release signal to the pointer allocation device, informing it that the storage unit corresponding to the pointer is now free. The pointer allocation device then decides, based on the aforementioned logic, whether to return the pointer to the FIFO or update the state of the third-level storage module.
[0099] Another embodiment of this application provides a chip including a pointer allocation device as described in the above embodiments of this application, or a linked list structure product as described in the above embodiments of this application.
[0100] Specifically, the chip can be a Field-Programmable Gate Array (FPGA), an Application-Specific Integrated Circuit (ASIC), or a System-on-a-Chip. In the chip design, the pointer allocation device is integrated as an IP core within the chip's internal bus architecture. For example, in a network switching chip, this linked list structure manages the descriptor queue of the packet buffer, and the pointer allocation device is responsible for quickly allocating and reclaiming address pointers for the packet buffer. Similarly, in a Graphics Processing Unit (GPU), this linked list structure can be used to manage the task queue in video memory. Internally, the input / output interface of the pointer allocation device is connected to other functional modules, such as a Direct Memory Access Controller (DMA) or a Network Interface Controller (NIC), via top-level metal traces. Utilizing the low-latency, high-throughput pointer management capabilities provided in this application embodiment, the overall concurrent processing performance of the chip is improved. Simultaneously, due to the significantly reduced hardware resource consumption, the chip can integrate more functional units or increase queue depth on a limited silicon area, thereby enhancing product competitiveness.
[0101] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many updates and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. A pointer allocation device for a linked list, characterized in that, It includes a first-level FIFO module, a second-level cache module, a third-level storage module, and a pointer control logic module; The first-level FIFO module is used to store null pointers; wherein, the null pointer is the address of a free storage unit in the storage entity storing linked list data; the storage entity includes multiple storage units; The second-level cache module is used to store the first usage status information of pointers corresponding to some storage units of the storage entity; wherein, the first usage status information includes unused and used; The third-level storage module is used to store the second usage status information of the pointers corresponding to all storage units of the storage entity; wherein, the second usage status information includes unused and used, the storage capacity of the third-level storage module is greater than the storage capacity of the second-level cache module, and the storage capacity of the second-level cache module is greater than the storage capacity of the first-level FIFO module. The pointer control logic module is used to obtain a target null pointer based on the first usage status information stored in the second-level cache module when the number of null pointers in the first-level FIFO module is less than a preset threshold, write the target null pointer into the first-level FIFO module, and update the corresponding first usage status information in the second-level cache module. The pointer control logic module is further configured to, when detecting that the first usage status information in the second-level cache module meets the preset conditions, obtain a set of second usage status information based on the second usage status information stored in the third-level storage module, and write the set of second usage status information as a new set of first usage status information into the second-level cache module; wherein, the preset conditions indicate that a set of first usage status information needs to be added to the second-level cache module.
2. The pointer allocation device according to claim 1, characterized in that, In the second-level cache module, when the storage unit corresponding to any pointer is free and the pointer has been written to the first-level FIFO module, or when the storage unit corresponding to any pointer is not free, the first usage status information of the pointer is set to used; otherwise, the first usage status information of the pointer is set to unused. The pointer control logic module is specifically used to obtain a target null pointer based on the first usage status information of the pointers in the second-level cache module when the number of null pointers in the first-level FIFO module is less than a preset threshold, write the target null pointer into the first-level FIFO module, and update the first usage status information of the target null pointer in the second-level cache module to "used".
3. The pointer allocation device according to claim 2, characterized in that, The second-level cache module includes multiple cache lines, each cache line including multiple first usage status information; the third-level storage module includes multiple groups, each group including multiple second usage status information. In the third-level storage module, when the storage unit corresponding to any pointer is idle and the group to which any pointer belongs has not been prefetched to the second-level cache module, or when any pointer has been released and its status has been flushed, the second usage status information of any pointer is set to unused; when the group to which any pointer belongs has been prefetched to the second-level cache module and the first usage status information in the cache line corresponding to that group is all used, the second usage status information of any pointer is set to used. The pointer control logic module is specifically used to obtain a set of second usage status information based on the second usage status information in the third-level storage module when it is detected that the first usage status information of any cache line in the second-level cache module is used, and to flush the set of second usage status information as a new set of first usage status information to any cache line, wherein at least one of the second usage status information in the set of second usage status information is unused.
4. The pointer allocation device according to claim 3, characterized in that, The second-level cache module includes multiple first status bits, each of which is used to store a first usage status information; The pointer control logic module is specifically used to update the first mapping relationship between each first status bit and the pointer in any cache line after the set of second usage status information is written to any cache line as a new set of first usage status information. The pointer control logic module is specifically used to obtain the target null pointer based on the first usage status information of the pointer in the second-level cache module and the first mapping relationship.
5. The pointer allocation device according to claim 4, characterized in that, The pointer control logic module is further configured to update the second mapping relationship between the line number of any cache line and the group number corresponding to the set of second usage status information after the set of second usage status information is flushed to any cache line as a new set of first usage status information; The pointer control logic module is further configured to, when it is detected that all first usage status information of any cache line in the second-level cache module is used, obtain the corresponding target group number according to the line number of any cache line and the second mapping relationship, and update all second usage status information of a group corresponding to the target group number in the third-level storage module to be used.
6. The pointer allocation device according to claim 5, characterized in that, The first-level FIFO module includes multiple queue units, each queue unit is used to store a null pointer; each group of the third-level storage module includes multiple second status bits, each second status bit is used to store a second usage status information; The number of second status bits in each group of the third-level storage module is the same as the number of queue units in the first-level FIFO module and the number of first status bits in each cache line of the second-level cache module.
7. The pointer allocation device according to claim 3, characterized in that, The pointer control logic module is specifically used to determine whether the number of null pointers in the first-level FIFO module is less than the preset threshold when the data of the storage unit corresponding to the head pointer of the linked list is read out. If so, the head pointer is written into the first-level FIFO module; if not, a second usage status information corresponding to the head pointer in the third-level storage module is updated to unused.
8. The pointer allocation device according to claim 7, characterized in that, The pointer control logic module is specifically used to, when the number of null pointers in the first-level FIFO module is less than a preset threshold, preferentially write the currently released head pointer of the linked list as the target null pointer into the first-level FIFO module. If, after writing the currently released head pointer of the linked list into the first-level FIFO module, the number of null pointers in the first-level FIFO module is still less than the preset threshold, then the target null pointer is further obtained according to the pointer usage status information stored in the second-level cache module, and the target null pointer is written into the first-level FIFO module until the number of null pointers in the first-level FIFO module is equal to the preset threshold.
9. The pointer allocation device according to claim 1, characterized in that, The pointer control logic module is specifically used to, when receiving a write request, pause the response to the write request if the first-level FIFO module is empty and all first usage status information in the second-level cache module is used; otherwise, respond to the write request, obtain a null pointer from the first-level FIFO module and output it.
10. A linked list structure product, characterized in that, The linked list structure includes a head pointer entity, a tail pointer entity, a storage entity, a pointer entity, a read control logic module, and a pointer allocation device as described in any one of claims 1 to 9; The head pointer entity is used to store the head pointer of the linked list; The tail pointer entity is used to store the tail pointer of the linked list; The storage entity is used to store the linked list data; The pointer entity is used to store the pointing relationship between pointers; The read control logic module is used to receive write requests, write the data carried by the write request into the storage unit corresponding to the null pointer according to the null pointer output by the pointer allocation device in response to the write request, and update the pointing relationship between corresponding pointers in the pointer entity and the tail pointer of the linked list.
11. The linked list structure product according to claim 10, characterized in that, The read control logic module is also used to receive read requests, find the head pointer entity to obtain the head pointer according to the read request, read the data of the corresponding storage unit from the storage entity according to the head pointer, and update the head pointer of the linked list.
12. A chip, characterized in that, Includes the pointer assignment device as described in any one of claims 1 to 9, or the linked list structure product as described in claim 10 or 11.